| Murali Nalajala | 73c1333 | 2012-05-15 11:30:59 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2012, Code Aurora Forum. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <asm/hardware/cache-l2x0.h> |
| 14 | |
| 15 | /* Add 300 NOPs after 'wfi' for 8x25 target */ |
| 16 | .macro DELAY_8x25, rept |
| 17 | #ifdef CONFIG_ARCH_MSM8625 |
| 18 | .rept \rept |
| 19 | nop |
| 20 | .endr |
| 21 | #endif |
| 22 | .endm |
| 23 | |
| 24 | /* Switch between smp_to_amp/amp_to_smp configuration */ |
| 25 | .macro SET_SMP_COHERENCY, on = 0 |
| 26 | ldr r0, =target_type |
| 27 | ldr r0, [r0] |
| 28 | mov r1, #TARGET_IS_8625 |
| 29 | cmp r0, r1 |
| 30 | bne skip\@ |
| 31 | mrc p15, 0, r0, c1, c0, 1 /* read ACTLR register */ |
| 32 | .if \on |
| 33 | orr r0, r0, #(1 << 6) /* Set the SMP bit in ACTLR */ |
| 34 | .else |
| 35 | bic r0, r0, #(1 << 6) /* Clear the SMP bit */ |
| 36 | .endif |
| 37 | mcr p15, 0, r0, c1, c0, 1 /* write ACTLR register */ |
| 38 | isb |
| 39 | skip\@: |
| 40 | .endm |
| 41 | |
| 42 | /* |
| 43 | * Enable the "L2" cache, not require to restore the controller registers |
| 44 | */ |
| 45 | .macro ENABLE_8x25_L2 |
| 46 | ldr r0, =target_type |
| 47 | ldr r0, [r0] |
| 48 | mov r1, #TARGET_IS_8625 |
| 49 | cmp r0, r1 |
| 50 | bne skip_enable\@ |
| 51 | ldr r0, =apps_power_collapse |
| 52 | ldr r0, [r0] |
| 53 | cmp r0, #POWER_COLLAPSED |
| 54 | bne skip_enable\@ |
| 55 | ldr r0, =l2x0_base_addr |
| 56 | ldr r0, [r0] |
| 57 | mov r1, #0x1 |
| 58 | str r1, [r0, #L2X0_CTRL] |
| 59 | dmb |
| 60 | skip_enable\@: |
| 61 | .endm |
| 62 | |
| 63 | /* |
| 64 | * Perform the required operation |
| 65 | * operation: type of operation on l2 cache (e.g: clean&inv or inv) |
| 66 | * l2_enable: enable or disable |
| 67 | */ |
| 68 | .macro DO_CACHE_OPERATION, operation, l2_enable |
| 69 | ldr r2, =l2x0_base_addr |
| 70 | ldr r2, [r2] |
| 71 | ldr r0, =0xffff |
| 72 | str r0, [r2, #\operation] |
| 73 | wait\@: |
| 74 | ldr r0, [r2, #\operation] |
| 75 | ldr r1, =0xffff |
| 76 | ands r0, r0, r1 |
| 77 | bne wait\@ |
| 78 | l2x_sync\@: |
| 79 | mov r0, #0x0 |
| 80 | str r0, [r2, #L2X0_CACHE_SYNC] |
| 81 | sync\@: |
| 82 | ldr r0, [r2, #L2X0_CACHE_SYNC] |
| 83 | ands r0, r0, #0x1 |
| 84 | bne sync\@ |
| 85 | mov r1, #\l2_enable |
| 86 | str r1, [r2, #L2X0_CTRL] |
| 87 | .endm |
| 88 | |
| 89 | /* |
| 90 | * Clean and invalidate the L2 cache. |
| 91 | * 1. Check the target type |
| 92 | * 2. Check whether we are coming from PC are not |
| 93 | * 3. Save 'aux', 'data latency', & 'prefetch ctlr' registers |
| 94 | * 4. Start L2 clean & invalidation operation |
| 95 | * 5. Disable the L2 cache |
| 96 | */ |
| 97 | .macro SUSPEND_8x25_L2 |
| 98 | ldr r0, =target_type |
| 99 | ldr r0, [r0] |
| 100 | mov r1, #TARGET_IS_8625 |
| 101 | cmp r0, r1 |
| 102 | bne skip_suspend\@ |
| 103 | ldr r0, =apps_power_collapse |
| 104 | ldr r0, [r0] |
| 105 | cmp r0, #POWER_COLLAPSED |
| 106 | bne skip_suspend\@ |
| 107 | ldr r0, =l2x0_saved_ctrl_reg_val |
| 108 | ldr r1, =l2x0_base_addr |
| 109 | ldr r1, [r1] |
| 110 | ldr r2, [r1, #L2X0_AUX_CTRL] |
| 111 | str r2, [r0, #0x0] /* store aux_ctlr reg value */ |
| 112 | ldr r2, [r1, #L2X0_DATA_LATENCY_CTRL] |
| 113 | str r2, [r0, #0x4] /* store data latency reg value */ |
| 114 | ldr r2, [r1, #L2X0_PREFETCH_CTRL] |
| 115 | str r2, [r0, #0x8] /* store prefetch_ctlr reg value */ |
| 116 | DO_CACHE_OPERATION L2X0_CLEAN_INV_WAY OFF |
| 117 | dmb |
| 118 | skip_suspend\@: |
| 119 | .endm |
| 120 | |
| 121 | /* |
| 122 | * Coming back from a successful PC |
| 123 | * 1. Check the target type |
| 124 | * 2. Check whether we are going to PC are not |
| 125 | * 3. Disable the L2 cache |
| 126 | * 4. Restore 'aux', 'data latency', & 'prefetch ctlr' reg |
| 127 | * 5. Invalidate the cache |
| 128 | * 6. Enable the L2 cache |
| 129 | */ |
| 130 | .macro RESUME_8x25_L2 |
| 131 | ldr r0, =target_type |
| 132 | ldr r0, [r0] |
| 133 | mov r1, #TARGET_IS_8625 |
| 134 | cmp r0, r1 |
| 135 | bne skip_resume\@ |
| 136 | ldr r0, =apps_power_collapse |
| 137 | ldr r0, [r0] |
| 138 | cmp r0, #POWER_COLLAPSED |
| 139 | bne skip_resume\@ |
| 140 | ldr r1, =l2x0_base_addr |
| 141 | ldr r1, [r1] |
| 142 | mov r0, #0x0 |
| 143 | str r0, [r1, #L2X0_CTRL] |
| 144 | ldr r0, =l2x0_saved_ctrl_reg_val |
| 145 | ldr r2, [r0, #0x0] |
| 146 | str r2, [r1, #L2X0_AUX_CTRL] /* restore aux_ctlr reg value */ |
| 147 | ldr r2, [r0, #0x4] |
| 148 | str r2, [r1, #L2X0_DATA_LATENCY_CTRL] |
| 149 | ldr r2, [r0, #0x8] |
| 150 | str r2, [r1, #L2X0_PREFETCH_CTRL] |
| 151 | DO_CACHE_OPERATION L2X0_INV_WAY ON |
| 152 | skip_resume\@: |
| 153 | .endm |