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gerrit-public.fairphone.software / kernel / msm / a924db7c00655447c5228bd74da070c69b7cadbc / . / arch / blackfin / mach-bf548 / Kconfig
blob: 08d8dc83701c3e7cb3d279f757358155fba662f7 [file] [log] [blame]
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]1if (BF54x)
2
3menu "BF548 Specific Configuration"
4
Michael Hennericha924db72007-08-03 17:43:29 +0800[diff] [blame^]5config DEB_DMA_URGENT
6 bool "DMA has priority over core for ext. accesses"
7 depends on BF54x
8 default n
9 help
10 Treat any DEB1, DEB2 and DEB3 request as Urgent
11
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]12comment "Interrupt Priority Assignment"
13menu "Priority"
14
15config IRQ_PLL_WAKEUP
16 int "IRQ_PLL_WAKEUP"
17 default 7
18config IRQ_DMAC0_ERR
19 int "IRQ_DMAC0_ERR"
20 default 7
21config IRQ_EPPI0_ERR
22 int "IRQ_EPPI0_ERR"
23 default 7
24config IRQ_SPORT0_ERR
25 int "IRQ_SPORT0_ERR"
26 default 7
27config IRQ_SPORT1_ERR
28 int "IRQ_SPORT1_ERR"
29 default 7
30config IRQ_SPI0_ERR
31 int "IRQ_SPI0_ERR"
32 default 7
33config IRQ_UART0_ERR
34 int "IRQ_UART0_ERR"
35 default 7
36config IRQ_RTC
37 int "IRQ_RTC"
38 default 8
39config IRQ_EPPI0
40 int "IRQ_EPPI0"
41 default 8
42config IRQ_SPORT0_RX
43 int "IRQ_SPORT0_RX"
44 default 9
45config IRQ_SPORT0_TX
46 int "IRQ_SPORT0_TX"
47 default 9
48config IRQ_SPORT1_RX
49 int "IRQ_SPORT1_RX"
50 default 9
51config IRQ_SPORT1_TX
52 int "IRQ_SPORT1_TX"
53 default 9
54config IRQ_SPI0
55 int "IRQ_SPI0"
56 default 10
57config IRQ_UART0_RX
58 int "IRQ_UART0_RX"
59 default 10
60config IRQ_UART0_TX
61 int "IRQ_UART0_TX"
62 default 10
63config IRQ_TIMER8
64 int "IRQ_TIMER8"
65 default 11
66config IRQ_TIMER9
67 int "IRQ_TIMER9"
68 default 11
69config IRQ_TIMER10
70 int "IRQ_TIMER10"
71 default 11
72config IRQ_PINT0
73 int "IRQ_PINT0"
74 default 12
75config IRQ_PINT1
76 int "IRQ_PINT0"
77 default 12
78config IRQ_MDMAS0
79 int "IRQ_MDMAS0"
80 default 13
81config IRQ_MDMAS1
82 int "IRQ_DMDMAS1"
83 default 13
84config IRQ_WATCHDOG
85 int "IRQ_WATCHDOG"
86 default 13
87config IRQ_DMAC1_ERR
88 int "IRQ_DMAC1_ERR"
89 default 7
90config IRQ_SPORT2_ERR
91 int "IRQ_SPORT2_ERR"
92 default 7
93config IRQ_SPORT3_ERR
94 int "IRQ_SPORT3_ERR"
95 default 7
96config IRQ_MXVR_DATA
97 int "IRQ MXVR Data"
98 default 7
99config IRQ_SPI1_ERR
100 int "IRQ_SPI1_ERR"
101 default 7
102config IRQ_SPI2_ERR
103 int "IRQ_SPI2_ERR"
104 default 7
105config IRQ_UART1_ERR
106 int "IRQ_UART1_ERR"
107 default 7
108config IRQ_UART2_ERR
109 int "IRQ_UART2_ERR"
110 default 7
111config IRQ_CAN0_ERR
112 int "IRQ_CAN0_ERR"
113 default 7
114config IRQ_SPORT2_RX
115 int "IRQ_SPORT2_RX"
116 default 9
117config IRQ_SPORT2_TX
118 int "IRQ_SPORT2_TX"
119 default 9
120config IRQ_SPORT3_RX
121 int "IRQ_SPORT3_RX"
122 default 9
123config IRQ_SPORT3_TX
124 int "IRQ_SPORT3_TX"
125 default 9
126config IRQ_EPPI1
127 int "IRQ_EPPI1"
128 default 9
129config IRQ_EPPI2
130 int "IRQ_EPPI2"
131 default 9
132config IRQ_SPI1
133 int "IRQ_SPI1"
134 default 10
135config IRQ_SPI2
136 int "IRQ_SPI2"
137 default 10
138config IRQ_UART1_RX
139 int "IRQ_UART1_RX"
140 default 10
141config IRQ_UART1_TX
142 int "IRQ_UART1_TX"
143 default 10
144config IRQ_ATAPI_RX
145 int "IRQ_ATAPI_RX"
146 default 10
147config IRQ_ATAPI_TX
148 int "IRQ_ATAPI_TX"
149 default 10
150config IRQ_TWI0
151 int "IRQ_TWI0"
152 default 11
153config IRQ_TWI1
154 int "IRQ_TWI1"
155 default 11
156config IRQ_CAN0_RX
157 int "IRQ_CAN_RX"
158 default 11
159config IRQ_CAN0_TX
160 int "IRQ_CAN_TX"
161 default 11
162config IRQ_MDMAS2
163 int "IRQ_MDMAS2"
164 default 13
165config IRQ_MDMAS3
166 int "IRQ_DMMAS3"
167 default 13
168config IRQ_MXVR_ERR
169 int "IRQ_MXVR_ERR"
170 default 11
171config IRQ_MXVR_MSG
172 int "IRQ_MXVR_MSG"
173 default 11
174config IRQ_MXVR_PKT
175 int "IRQ_MXVR_PKT"
176 default 11
177config IRQ_EPPI1_ERR
178 int "IRQ_EPPI1_ERR"
179 default 7
180config IRQ_EPPI2_ERR
181 int "IRQ_EPPI2_ERR"
182 default 7
183config IRQ_UART3_ERR
184 int "IRQ_UART3_ERR"
185 default 7
186config IRQ_HOST_ERR
187 int "IRQ_HOST_ERR"
188 default 7
189config IRQ_PIXC_ERR
190 int "IRQ_PIXC_ERR"
191 default 7
192config IRQ_NFC_ERR
193 int "IRQ_NFC_ERR"
194 default 7
195config IRQ_ATAPI_ERR
196 int "IRQ_ATAPI_ERR"
197 default 7
198config IRQ_CAN1_ERR
199 int "IRQ_CAN1_ERR"
200 default 7
201config IRQ_HS_DMA_ERR
202 int "IRQ Handshake DMA Status"
203 default 7
204config IRQ_PIXC_IN0
205 int "IRQ PIXC IN0"
206 default 8
207config IRQ_PIXC_IN1
208 int "IRQ PIXC IN1"
209 default 8
210config IRQ_PIXC_OUT
211 int "IRQ PIXC OUT"
212 default 8
213config IRQ_SDH
214 int "IRQ SDH"
215 default 8
216config IRQ_CNT
217 int "IRQ CNT"
218 default 8
219config IRQ_KEY
220 int "IRQ KEY"
221 default 8
222config IRQ_CAN1_RX
223 int "IRQ CAN1 RX"
224 default 11
225config IRQ_CAN1_TX
226 int "IRQ_CAN1_TX"
227 default 11
228config IRQ_SDH_MASK0
229 int "IRQ_SDH_MASK0"
230 default 11
231config IRQ_SDH_MASK1
232 int "IRQ_SDH_MASK1"
233 default 11
234config IRQ_USB_INT0
235 int "IRQ USB INT0"
236 default 11
237config IRQ_USB_INT1
238 int "IRQ USB INT1"
239 default 11
240config IRQ_USB_INT2
241 int "IRQ USB INT2"
242 default 11
243config IRQ_USB_DMA
244 int "IRQ USB DMA"
245 default 11
246config IRQ_OTPSEC
247 int "IRQ OPTSEC"
248 default 11
249config IRQ_TIMER0
250 int "IRQ_TIMER0"
251 default 11
252config IRQ_TIMER1
253 int "IRQ_TIMER1"
254 default 11
255config IRQ_TIMER2
256 int "IRQ_TIMER2"
257 default 11
258config IRQ_TIMER3
259 int "IRQ_TIMER3"
260 default 11
261config IRQ_TIMER4
262 int "IRQ_TIMER4"
263 default 11
264config IRQ_TIMER5
265 int "IRQ_TIMER5"
266 default 11
267config IRQ_TIMER6
268 int "IRQ_TIMER6"
269 default 11
270config IRQ_TIMER7
271 int "IRQ_TIMER7"
272 default 11
273config IRQ_PINT2
274 int "IRQ_PIN2"
275 default 11
276config IRQ_PINT3
277 int "IRQ_PIN3"
278 default 11
279
280 help
281 Enter the priority numbers between 7-13 ONLY. Others are Reserved.
282 This applies to all the above. It is not recommended to assign the
283 highest priority number 7 to UART or any other device.
284
285endmenu
286
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800[diff] [blame]287comment "Pin Interrupt to Port Assignment"
288menu "Assignment"
289
290config PINTx_REASSIGN
291 bool "Reprogram PINT Assignment"
Michael Hennerich31430ba2007-07-24 16:27:25 +0800[diff] [blame]292 default y
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800[diff] [blame]293 help
294 The interrupt assignment registers controls the pin-to-interrupt
295 assignment in a byte-wide manner. Each option allows you to select
296 a set of pins (High/Low Byte) of an specific Port being mapped
297 to one of the four PIN Interrupts IRQ_PINTx.
298
299 You shouldn't change any of these unless you know exactly what you're doing.
300 Please consult the Blackfin BF54x Processor Hardware Reference Manual.
301
302config PINT0_ASSIGN
303 hex "PINT0_ASSIGN"
304 depends on PINTx_REASSIGN
305 default 0x00000101
306config PINT1_ASSIGN
307 hex "PINT1_ASSIGN"
308 depends on PINTx_REASSIGN
309 default 0x01010000
310config PINT2_ASSIGN
311 hex "PINT2_ASSIGN"
312 depends on PINTx_REASSIGN
Michael Hennerich31430ba2007-07-24 16:27:25 +0800[diff] [blame]313 default 0x07000101
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800[diff] [blame]314config PINT3_ASSIGN
315 hex "PINT3_ASSIGN"
316 depends on PINTx_REASSIGN
317 default 0x02020303
318
319endmenu
320
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]321endmenu
322
323endif