Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2011, Code Aurora Forum. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #define pr_fmt(fmt) "%s: " fmt, __func__ |
| 15 | |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/slab.h> |
| 18 | #include <linux/spinlock.h> |
Anirudh Ghayal | 8b8f189 | 2011-11-11 10:48:41 +0530 | [diff] [blame] | 19 | #include <linux/interrupt.h> |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/mfd/pm8xxx/core.h> |
| 22 | #include <linux/mfd/pm8xxx/misc.h> |
| 23 | |
| 24 | /* PON CTRL 1 register */ |
| 25 | #define REG_PM8058_PON_CTRL_1 0x01C |
| 26 | #define REG_PM8921_PON_CTRL_1 0x01C |
Jay Chokshi | 86580f2 | 2011-10-17 12:27:52 -0700 | [diff] [blame] | 27 | #define REG_PM8018_PON_CTRL_1 0x01C |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 28 | |
| 29 | #define PON_CTRL_1_PULL_UP_MASK 0xE0 |
| 30 | #define PON_CTRL_1_USB_PWR_EN 0x10 |
| 31 | |
| 32 | #define PON_CTRL_1_WD_EN_MASK 0x08 |
| 33 | #define PON_CTRL_1_WD_EN_RESET 0x08 |
| 34 | #define PON_CTRL_1_WD_EN_PWR_OFF 0x00 |
| 35 | |
Anirudh Ghayal | 9e1bd64 | 2011-11-01 13:57:40 +0530 | [diff] [blame] | 36 | /* Regulator master enable addresses */ |
| 37 | #define REG_PM8058_VREG_EN_MSM 0x018 |
| 38 | #define REG_PM8058_VREG_EN_GRP_5_4 0x1C8 |
| 39 | |
| 40 | /* Regulator control registers for shutdown/reset */ |
| 41 | #define REG_PM8058_S0_CTRL 0x004 |
| 42 | #define REG_PM8058_S1_CTRL 0x005 |
| 43 | #define REG_PM8058_S3_CTRL 0x111 |
| 44 | #define REG_PM8058_L21_CTRL 0x120 |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 45 | #define REG_PM8058_L22_CTRL 0x121 |
| 46 | |
Anirudh Ghayal | 9e1bd64 | 2011-11-01 13:57:40 +0530 | [diff] [blame] | 47 | #define PM8058_REGULATOR_ENABLE_MASK 0x80 |
| 48 | #define PM8058_REGULATOR_ENABLE 0x80 |
| 49 | #define PM8058_REGULATOR_DISABLE 0x00 |
| 50 | #define PM8058_REGULATOR_PULL_DOWN_MASK 0x40 |
| 51 | #define PM8058_REGULATOR_PULL_DOWN_EN 0x40 |
| 52 | |
| 53 | /* Buck CTRL register */ |
| 54 | #define PM8058_SMPS_LEGACY_VREF_SEL 0x20 |
| 55 | #define PM8058_SMPS_LEGACY_VPROG_MASK 0x1F |
| 56 | #define PM8058_SMPS_ADVANCED_BAND_MASK 0xC0 |
| 57 | #define PM8058_SMPS_ADVANCED_BAND_SHIFT 6 |
| 58 | #define PM8058_SMPS_ADVANCED_VPROG_MASK 0x3F |
| 59 | |
| 60 | /* Buck TEST2 registers for shutdown/reset */ |
| 61 | #define REG_PM8058_S0_TEST2 0x084 |
| 62 | #define REG_PM8058_S1_TEST2 0x085 |
| 63 | #define REG_PM8058_S3_TEST2 0x11A |
| 64 | |
| 65 | #define PM8058_REGULATOR_BANK_WRITE 0x80 |
| 66 | #define PM8058_REGULATOR_BANK_MASK 0x70 |
| 67 | #define PM8058_REGULATOR_BANK_SHIFT 4 |
| 68 | #define PM8058_REGULATOR_BANK_SEL(n) ((n) << PM8058_REGULATOR_BANK_SHIFT) |
| 69 | |
| 70 | /* Buck TEST2 register bank 1 */ |
| 71 | #define PM8058_SMPS_LEGACY_VLOW_SEL 0x01 |
| 72 | |
| 73 | /* Buck TEST2 register bank 7 */ |
| 74 | #define PM8058_SMPS_ADVANCED_MODE_MASK 0x02 |
| 75 | #define PM8058_SMPS_ADVANCED_MODE 0x02 |
| 76 | #define PM8058_SMPS_LEGACY_MODE 0x00 |
| 77 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 78 | /* SLEEP CTRL register */ |
| 79 | #define REG_PM8058_SLEEP_CTRL 0x02B |
| 80 | #define REG_PM8921_SLEEP_CTRL 0x10A |
Jay Chokshi | 86580f2 | 2011-10-17 12:27:52 -0700 | [diff] [blame] | 81 | #define REG_PM8018_SLEEP_CTRL 0x10A |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 82 | |
| 83 | #define SLEEP_CTRL_SMPL_EN_MASK 0x04 |
| 84 | #define SLEEP_CTRL_SMPL_EN_RESET 0x04 |
| 85 | #define SLEEP_CTRL_SMPL_EN_PWR_OFF 0x00 |
| 86 | |
Anirudh Ghayal | bfbaf82 | 2011-11-01 14:28:34 +0530 | [diff] [blame^] | 87 | #define SLEEP_CTRL_SMPL_SEL_MASK 0x03 |
| 88 | #define SLEEP_CTRL_SMPL_SEL_MIN 0 |
| 89 | #define SLEEP_CTRL_SMPL_SEL_MAX 3 |
| 90 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 91 | /* FTS regulator PMR registers */ |
| 92 | #define REG_PM8901_REGULATOR_S1_PMR 0xA7 |
| 93 | #define REG_PM8901_REGULATOR_S2_PMR 0xA8 |
| 94 | #define REG_PM8901_REGULATOR_S3_PMR 0xA9 |
| 95 | #define REG_PM8901_REGULATOR_S4_PMR 0xAA |
| 96 | |
| 97 | #define PM8901_REGULATOR_PMR_STATE_MASK 0x60 |
| 98 | #define PM8901_REGULATOR_PMR_STATE_OFF 0x20 |
| 99 | |
Anirudh Ghayal | 7b38229 | 2011-11-01 14:08:34 +0530 | [diff] [blame] | 100 | /* COINCELL CHG registers */ |
| 101 | #define REG_PM8058_COIN_CHG 0x02F |
| 102 | #define REG_PM8921_COIN_CHG 0x09C |
| 103 | #define REG_PM8018_COIN_CHG 0x09C |
| 104 | |
| 105 | #define COINCELL_RESISTOR_SHIFT 0x2 |
| 106 | |
Anirudh Ghayal | 5213eb8 | 2011-10-24 14:44:58 +0530 | [diff] [blame] | 107 | /* GPIO UART MUX CTRL registers */ |
| 108 | #define REG_PM8XXX_GPIO_MUX_CTRL 0x1CC |
| 109 | |
| 110 | #define UART_PATH_SEL_MASK 0x60 |
| 111 | #define UART_PATH_SEL_SHIFT 0x5 |
| 112 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 113 | struct pm8xxx_misc_chip { |
| 114 | struct list_head link; |
| 115 | struct pm8xxx_misc_platform_data pdata; |
| 116 | struct device *dev; |
| 117 | enum pm8xxx_version version; |
Anirudh Ghayal | 8b8f189 | 2011-11-11 10:48:41 +0530 | [diff] [blame] | 118 | u64 osc_halt_count; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 119 | }; |
| 120 | |
| 121 | static LIST_HEAD(pm8xxx_misc_chips); |
| 122 | static DEFINE_SPINLOCK(pm8xxx_misc_chips_lock); |
| 123 | |
| 124 | static int pm8xxx_misc_masked_write(struct pm8xxx_misc_chip *chip, u16 addr, |
| 125 | u8 mask, u8 val) |
| 126 | { |
| 127 | int rc; |
| 128 | u8 reg; |
| 129 | |
| 130 | rc = pm8xxx_readb(chip->dev->parent, addr, ®); |
| 131 | if (rc) { |
| 132 | pr_err("pm8xxx_readb(0x%03X) failed, rc=%d\n", addr, rc); |
| 133 | return rc; |
| 134 | } |
| 135 | reg &= ~mask; |
| 136 | reg |= val & mask; |
| 137 | rc = pm8xxx_writeb(chip->dev->parent, addr, reg); |
| 138 | if (rc) |
| 139 | pr_err("pm8xxx_writeb(0x%03X)=0x%02X failed, rc=%d\n", addr, |
| 140 | reg, rc); |
| 141 | return rc; |
| 142 | } |
| 143 | |
Anirudh Ghayal | 9e1bd64 | 2011-11-01 13:57:40 +0530 | [diff] [blame] | 144 | /* |
| 145 | * Set an SMPS regulator to be disabled in its CTRL register, but enabled |
| 146 | * in the master enable register. Also set it's pull down enable bit. |
| 147 | * Take care to make sure that the output voltage doesn't change if switching |
| 148 | * from advanced mode to legacy mode. |
| 149 | */ |
| 150 | static int |
| 151 | __pm8058_disable_smps_locally_set_pull_down(struct pm8xxx_misc_chip *chip, |
| 152 | u16 ctrl_addr, u16 test2_addr, u16 master_enable_addr, |
| 153 | u8 master_enable_bit) |
| 154 | { |
| 155 | int rc = 0; |
| 156 | u8 vref_sel, vlow_sel, band, vprog, bank, reg; |
| 157 | |
| 158 | bank = PM8058_REGULATOR_BANK_SEL(7); |
| 159 | rc = pm8xxx_writeb(chip->dev->parent, test2_addr, bank); |
| 160 | if (rc) { |
| 161 | pr_err("%s: pm8xxx_writeb(0x%03X) failed: rc=%d\n", __func__, |
| 162 | test2_addr, rc); |
| 163 | goto done; |
| 164 | } |
| 165 | |
| 166 | rc = pm8xxx_readb(chip->dev->parent, test2_addr, ®); |
| 167 | if (rc) { |
| 168 | pr_err("%s: FAIL pm8xxx_readb(0x%03X): rc=%d\n", |
| 169 | __func__, test2_addr, rc); |
| 170 | goto done; |
| 171 | } |
| 172 | |
| 173 | /* Check if in advanced mode. */ |
| 174 | if ((reg & PM8058_SMPS_ADVANCED_MODE_MASK) == |
| 175 | PM8058_SMPS_ADVANCED_MODE) { |
| 176 | /* Determine current output voltage. */ |
| 177 | rc = pm8xxx_readb(chip->dev->parent, ctrl_addr, ®); |
| 178 | if (rc) { |
| 179 | pr_err("%s: FAIL pm8xxx_readb(0x%03X): rc=%d\n", |
| 180 | __func__, ctrl_addr, rc); |
| 181 | goto done; |
| 182 | } |
| 183 | |
| 184 | band = (reg & PM8058_SMPS_ADVANCED_BAND_MASK) |
| 185 | >> PM8058_SMPS_ADVANCED_BAND_SHIFT; |
| 186 | switch (band) { |
| 187 | case 3: |
| 188 | vref_sel = 0; |
| 189 | vlow_sel = 0; |
| 190 | break; |
| 191 | case 2: |
| 192 | vref_sel = PM8058_SMPS_LEGACY_VREF_SEL; |
| 193 | vlow_sel = 0; |
| 194 | break; |
| 195 | case 1: |
| 196 | vref_sel = PM8058_SMPS_LEGACY_VREF_SEL; |
| 197 | vlow_sel = PM8058_SMPS_LEGACY_VLOW_SEL; |
| 198 | break; |
| 199 | default: |
| 200 | pr_err("%s: regulator already disabled\n", __func__); |
| 201 | return -EPERM; |
| 202 | } |
| 203 | vprog = (reg & PM8058_SMPS_ADVANCED_VPROG_MASK); |
| 204 | /* Round up if fine step is in use. */ |
| 205 | vprog = (vprog + 1) >> 1; |
| 206 | if (vprog > PM8058_SMPS_LEGACY_VPROG_MASK) |
| 207 | vprog = PM8058_SMPS_LEGACY_VPROG_MASK; |
| 208 | |
| 209 | /* Set VLOW_SEL bit. */ |
| 210 | bank = PM8058_REGULATOR_BANK_SEL(1); |
| 211 | rc = pm8xxx_writeb(chip->dev->parent, test2_addr, bank); |
| 212 | if (rc) { |
| 213 | pr_err("%s: FAIL pm8xxx_writeb(0x%03X): rc=%d\n", |
| 214 | __func__, test2_addr, rc); |
| 215 | goto done; |
| 216 | } |
| 217 | |
| 218 | rc = pm8xxx_misc_masked_write(chip, test2_addr, |
| 219 | PM8058_REGULATOR_BANK_WRITE | PM8058_REGULATOR_BANK_MASK |
| 220 | | PM8058_SMPS_LEGACY_VLOW_SEL, |
| 221 | PM8058_REGULATOR_BANK_WRITE | |
| 222 | PM8058_REGULATOR_BANK_SEL(1) | vlow_sel); |
| 223 | if (rc) |
| 224 | goto done; |
| 225 | |
| 226 | /* Switch to legacy mode */ |
| 227 | bank = PM8058_REGULATOR_BANK_SEL(7); |
| 228 | rc = pm8xxx_writeb(chip->dev->parent, test2_addr, bank); |
| 229 | if (rc) { |
| 230 | pr_err("%s: FAIL pm8xxx_writeb(0x%03X): rc=%d\n", |
| 231 | __func__, test2_addr, rc); |
| 232 | goto done; |
| 233 | } |
| 234 | rc = pm8xxx_misc_masked_write(chip, test2_addr, |
| 235 | PM8058_REGULATOR_BANK_WRITE | |
| 236 | PM8058_REGULATOR_BANK_MASK | |
| 237 | PM8058_SMPS_ADVANCED_MODE_MASK, |
| 238 | PM8058_REGULATOR_BANK_WRITE | |
| 239 | PM8058_REGULATOR_BANK_SEL(7) | |
| 240 | PM8058_SMPS_LEGACY_MODE); |
| 241 | if (rc) |
| 242 | goto done; |
| 243 | |
| 244 | /* Enable locally, enable pull down, keep voltage the same. */ |
| 245 | rc = pm8xxx_misc_masked_write(chip, ctrl_addr, |
| 246 | PM8058_REGULATOR_ENABLE_MASK | |
| 247 | PM8058_REGULATOR_PULL_DOWN_MASK | |
| 248 | PM8058_SMPS_LEGACY_VREF_SEL | |
| 249 | PM8058_SMPS_LEGACY_VPROG_MASK, |
| 250 | PM8058_REGULATOR_ENABLE | PM8058_REGULATOR_PULL_DOWN_EN |
| 251 | | vref_sel | vprog); |
| 252 | if (rc) |
| 253 | goto done; |
| 254 | } |
| 255 | |
| 256 | /* Enable in master control register. */ |
| 257 | rc = pm8xxx_misc_masked_write(chip, master_enable_addr, |
| 258 | master_enable_bit, master_enable_bit); |
| 259 | if (rc) |
| 260 | goto done; |
| 261 | |
| 262 | /* Disable locally and enable pull down. */ |
| 263 | rc = pm8xxx_misc_masked_write(chip, ctrl_addr, |
| 264 | PM8058_REGULATOR_ENABLE_MASK | PM8058_REGULATOR_PULL_DOWN_MASK, |
| 265 | PM8058_REGULATOR_DISABLE | PM8058_REGULATOR_PULL_DOWN_EN); |
| 266 | |
| 267 | done: |
| 268 | return rc; |
| 269 | } |
| 270 | |
| 271 | static int |
| 272 | __pm8058_disable_ldo_locally_set_pull_down(struct pm8xxx_misc_chip *chip, |
| 273 | u16 ctrl_addr, u16 master_enable_addr, u8 master_enable_bit) |
| 274 | { |
| 275 | int rc; |
| 276 | |
| 277 | /* Enable LDO in master control register. */ |
| 278 | rc = pm8xxx_misc_masked_write(chip, master_enable_addr, |
| 279 | master_enable_bit, master_enable_bit); |
| 280 | if (rc) |
| 281 | goto done; |
| 282 | |
| 283 | /* Disable LDO in CTRL register and set pull down */ |
| 284 | rc = pm8xxx_misc_masked_write(chip, ctrl_addr, |
| 285 | PM8058_REGULATOR_ENABLE_MASK | PM8058_REGULATOR_PULL_DOWN_MASK, |
| 286 | PM8058_REGULATOR_DISABLE | PM8058_REGULATOR_PULL_DOWN_EN); |
| 287 | |
| 288 | done: |
| 289 | return rc; |
| 290 | } |
| 291 | |
Jay Chokshi | 86580f2 | 2011-10-17 12:27:52 -0700 | [diff] [blame] | 292 | static int __pm8018_reset_pwr_off(struct pm8xxx_misc_chip *chip, int reset) |
| 293 | { |
| 294 | int rc; |
| 295 | |
| 296 | /* Enable SMPL if resetting is desired. */ |
| 297 | rc = pm8xxx_misc_masked_write(chip, REG_PM8018_SLEEP_CTRL, |
| 298 | SLEEP_CTRL_SMPL_EN_MASK, |
| 299 | (reset ? SLEEP_CTRL_SMPL_EN_RESET : SLEEP_CTRL_SMPL_EN_PWR_OFF)); |
| 300 | if (rc) { |
| 301 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 302 | return rc; |
| 303 | } |
| 304 | |
| 305 | /* |
| 306 | * Select action to perform (reset or shutdown) when PS_HOLD goes low. |
| 307 | * Also ensure that KPD, CBL0, and CBL1 pull ups are enabled and that |
| 308 | * USB charging is enabled. |
| 309 | */ |
| 310 | rc = pm8xxx_misc_masked_write(chip, REG_PM8018_PON_CTRL_1, |
| 311 | PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN |
| 312 | | PON_CTRL_1_WD_EN_MASK, |
| 313 | PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN |
| 314 | | (reset ? PON_CTRL_1_WD_EN_RESET : PON_CTRL_1_WD_EN_PWR_OFF)); |
| 315 | if (rc) |
| 316 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 317 | |
| 318 | return rc; |
| 319 | } |
| 320 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 321 | static int __pm8058_reset_pwr_off(struct pm8xxx_misc_chip *chip, int reset) |
| 322 | { |
| 323 | int rc; |
| 324 | |
Anirudh Ghayal | 9e1bd64 | 2011-11-01 13:57:40 +0530 | [diff] [blame] | 325 | /* When shutting down, enable active pulldowns on important rails. */ |
| 326 | if (!reset) { |
| 327 | /* Disable SMPS's 0,1,3 locally and set pulldown enable bits. */ |
| 328 | __pm8058_disable_smps_locally_set_pull_down(chip, |
| 329 | REG_PM8058_S0_CTRL, REG_PM8058_S0_TEST2, |
| 330 | REG_PM8058_VREG_EN_MSM, BIT(7)); |
| 331 | __pm8058_disable_smps_locally_set_pull_down(chip, |
| 332 | REG_PM8058_S1_CTRL, REG_PM8058_S1_TEST2, |
| 333 | REG_PM8058_VREG_EN_MSM, BIT(6)); |
| 334 | __pm8058_disable_smps_locally_set_pull_down(chip, |
| 335 | REG_PM8058_S3_CTRL, REG_PM8058_S3_TEST2, |
| 336 | REG_PM8058_VREG_EN_GRP_5_4, BIT(7) | BIT(4)); |
| 337 | /* Disable LDO 21 locally and set pulldown enable bit. */ |
| 338 | __pm8058_disable_ldo_locally_set_pull_down(chip, |
| 339 | REG_PM8058_L21_CTRL, REG_PM8058_VREG_EN_GRP_5_4, |
| 340 | BIT(1)); |
| 341 | } |
| 342 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 343 | /* |
| 344 | * Fix-up: Set regulator LDO22 to 1.225 V in high power mode. Leave its |
| 345 | * pull-down state intact. This ensures a safe shutdown. |
| 346 | */ |
| 347 | rc = pm8xxx_misc_masked_write(chip, REG_PM8058_L22_CTRL, 0xBF, 0x93); |
| 348 | if (rc) { |
| 349 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 350 | goto read_write_err; |
| 351 | } |
| 352 | |
| 353 | /* Enable SMPL if resetting is desired. */ |
| 354 | rc = pm8xxx_misc_masked_write(chip, REG_PM8058_SLEEP_CTRL, |
| 355 | SLEEP_CTRL_SMPL_EN_MASK, |
| 356 | (reset ? SLEEP_CTRL_SMPL_EN_RESET : SLEEP_CTRL_SMPL_EN_PWR_OFF)); |
| 357 | if (rc) { |
| 358 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 359 | goto read_write_err; |
| 360 | } |
| 361 | |
| 362 | /* |
| 363 | * Select action to perform (reset or shutdown) when PS_HOLD goes low. |
| 364 | * Also ensure that KPD, CBL0, and CBL1 pull ups are enabled and that |
| 365 | * USB charging is enabled. |
| 366 | */ |
| 367 | rc = pm8xxx_misc_masked_write(chip, REG_PM8058_PON_CTRL_1, |
| 368 | PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN |
| 369 | | PON_CTRL_1_WD_EN_MASK, |
| 370 | PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN |
| 371 | | (reset ? PON_CTRL_1_WD_EN_RESET : PON_CTRL_1_WD_EN_PWR_OFF)); |
| 372 | if (rc) { |
| 373 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 374 | goto read_write_err; |
| 375 | } |
| 376 | |
| 377 | read_write_err: |
| 378 | return rc; |
| 379 | } |
| 380 | |
| 381 | static int __pm8901_reset_pwr_off(struct pm8xxx_misc_chip *chip, int reset) |
| 382 | { |
| 383 | int rc = 0, i; |
| 384 | u8 pmr_addr[4] = { |
| 385 | REG_PM8901_REGULATOR_S2_PMR, |
| 386 | REG_PM8901_REGULATOR_S3_PMR, |
| 387 | REG_PM8901_REGULATOR_S4_PMR, |
| 388 | REG_PM8901_REGULATOR_S1_PMR, |
| 389 | }; |
| 390 | |
| 391 | /* Fix-up: Turn off regulators S1, S2, S3, S4 when shutting down. */ |
| 392 | if (!reset) { |
| 393 | for (i = 0; i < 4; i++) { |
| 394 | rc = pm8xxx_misc_masked_write(chip, pmr_addr[i], |
| 395 | PM8901_REGULATOR_PMR_STATE_MASK, |
| 396 | PM8901_REGULATOR_PMR_STATE_OFF); |
| 397 | if (rc) { |
| 398 | pr_err("pm8xxx_misc_masked_write failed, " |
| 399 | "rc=%d\n", rc); |
| 400 | goto read_write_err; |
| 401 | } |
| 402 | } |
| 403 | } |
| 404 | |
| 405 | read_write_err: |
| 406 | return rc; |
| 407 | } |
| 408 | |
| 409 | static int __pm8921_reset_pwr_off(struct pm8xxx_misc_chip *chip, int reset) |
| 410 | { |
| 411 | int rc; |
| 412 | |
| 413 | /* Enable SMPL if resetting is desired. */ |
| 414 | rc = pm8xxx_misc_masked_write(chip, REG_PM8921_SLEEP_CTRL, |
| 415 | SLEEP_CTRL_SMPL_EN_MASK, |
| 416 | (reset ? SLEEP_CTRL_SMPL_EN_RESET : SLEEP_CTRL_SMPL_EN_PWR_OFF)); |
| 417 | if (rc) { |
| 418 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 419 | goto read_write_err; |
| 420 | } |
| 421 | |
| 422 | /* |
| 423 | * Select action to perform (reset or shutdown) when PS_HOLD goes low. |
| 424 | * Also ensure that KPD, CBL0, and CBL1 pull ups are enabled and that |
| 425 | * USB charging is enabled. |
| 426 | */ |
| 427 | rc = pm8xxx_misc_masked_write(chip, REG_PM8921_PON_CTRL_1, |
| 428 | PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN |
| 429 | | PON_CTRL_1_WD_EN_MASK, |
| 430 | PON_CTRL_1_PULL_UP_MASK | PON_CTRL_1_USB_PWR_EN |
| 431 | | (reset ? PON_CTRL_1_WD_EN_RESET : PON_CTRL_1_WD_EN_PWR_OFF)); |
| 432 | if (rc) { |
| 433 | pr_err("pm8xxx_misc_masked_write failed, rc=%d\n", rc); |
| 434 | goto read_write_err; |
| 435 | } |
| 436 | |
| 437 | read_write_err: |
| 438 | return rc; |
| 439 | } |
| 440 | |
| 441 | /** |
| 442 | * pm8xxx_reset_pwr_off - switch all PM8XXX PMIC chips attached to the system to |
| 443 | * either reset or shutdown when they are turned off |
| 444 | * @reset: 0 = shudown the PMICs, 1 = shutdown and then restart the PMICs |
| 445 | * |
| 446 | * RETURNS: an appropriate -ERRNO error value on error, or zero for success. |
| 447 | */ |
| 448 | int pm8xxx_reset_pwr_off(int reset) |
| 449 | { |
| 450 | struct pm8xxx_misc_chip *chip; |
| 451 | unsigned long flags; |
| 452 | int rc = 0; |
| 453 | |
| 454 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 455 | |
| 456 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 457 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 458 | switch (chip->version) { |
Jay Chokshi | 86580f2 | 2011-10-17 12:27:52 -0700 | [diff] [blame] | 459 | case PM8XXX_VERSION_8018: |
| 460 | rc = __pm8018_reset_pwr_off(chip, reset); |
| 461 | break; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 462 | case PM8XXX_VERSION_8058: |
| 463 | rc = __pm8058_reset_pwr_off(chip, reset); |
| 464 | break; |
| 465 | case PM8XXX_VERSION_8901: |
| 466 | rc = __pm8901_reset_pwr_off(chip, reset); |
| 467 | break; |
| 468 | case PM8XXX_VERSION_8921: |
| 469 | rc = __pm8921_reset_pwr_off(chip, reset); |
| 470 | break; |
| 471 | default: |
| 472 | /* PMIC doesn't have reset_pwr_off; do nothing. */ |
| 473 | break; |
| 474 | } |
| 475 | if (rc) { |
| 476 | pr_err("reset_pwr_off failed, rc=%d\n", rc); |
| 477 | break; |
| 478 | } |
| 479 | } |
| 480 | |
| 481 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 482 | |
| 483 | return rc; |
| 484 | } |
| 485 | EXPORT_SYMBOL_GPL(pm8xxx_reset_pwr_off); |
| 486 | |
Anirudh Ghayal | 7b38229 | 2011-11-01 14:08:34 +0530 | [diff] [blame] | 487 | /** |
Anirudh Ghayal | bfbaf82 | 2011-11-01 14:28:34 +0530 | [diff] [blame^] | 488 | * pm8xxx_smpl_control - enables/disables SMPL detection |
| 489 | * @enable: 0 = shutdown PMIC on power loss, 1 = reset PMIC on power loss |
| 490 | * |
| 491 | * This function enables or disables the Sudden Momentary Power Loss detection |
| 492 | * module. If SMPL detection is enabled, then when a sufficiently long power |
| 493 | * loss event occurs, the PMIC will automatically reset itself. If SMPL |
| 494 | * detection is disabled, then the PMIC will shutdown when power loss occurs. |
| 495 | * |
| 496 | * RETURNS: an appropriate -ERRNO error value on error, or zero for success. |
| 497 | */ |
| 498 | int pm8xxx_smpl_control(int enable) |
| 499 | { |
| 500 | struct pm8xxx_misc_chip *chip; |
| 501 | unsigned long flags; |
| 502 | int rc = 0; |
| 503 | |
| 504 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 505 | |
| 506 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 507 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 508 | switch (chip->version) { |
| 509 | case PM8XXX_VERSION_8018: |
| 510 | rc = pm8xxx_misc_masked_write(chip, |
| 511 | REG_PM8018_SLEEP_CTRL, SLEEP_CTRL_SMPL_EN_MASK, |
| 512 | (enable ? SLEEP_CTRL_SMPL_EN_PWR_OFF |
| 513 | : SLEEP_CTRL_SMPL_EN_PWR_OFF)); |
| 514 | break; |
| 515 | case PM8XXX_VERSION_8058: |
| 516 | rc = pm8xxx_misc_masked_write(chip, |
| 517 | REG_PM8058_SLEEP_CTRL, SLEEP_CTRL_SMPL_EN_MASK, |
| 518 | (enable ? SLEEP_CTRL_SMPL_EN_RESET |
| 519 | : SLEEP_CTRL_SMPL_EN_PWR_OFF)); |
| 520 | break; |
| 521 | case PM8XXX_VERSION_8921: |
| 522 | rc = pm8xxx_misc_masked_write(chip, |
| 523 | REG_PM8921_SLEEP_CTRL, SLEEP_CTRL_SMPL_EN_MASK, |
| 524 | (enable ? SLEEP_CTRL_SMPL_EN_PWR_OFF |
| 525 | : SLEEP_CTRL_SMPL_EN_PWR_OFF)); |
| 526 | break; |
| 527 | default: |
| 528 | /* PMIC doesn't have reset_pwr_off; do nothing. */ |
| 529 | break; |
| 530 | } |
| 531 | if (rc) { |
| 532 | pr_err("setting smpl control failed, rc=%d\n", rc); |
| 533 | break; |
| 534 | } |
| 535 | } |
| 536 | |
| 537 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 538 | |
| 539 | return rc; |
| 540 | } |
| 541 | EXPORT_SYMBOL(pm8xxx_smpl_control); |
| 542 | |
| 543 | |
| 544 | /** |
| 545 | * pm8xxx_smpl_set_delay - sets the SMPL detection time delay |
| 546 | * @delay: enum value corresponding to delay time |
| 547 | * |
| 548 | * This function sets the time delay of the SMPL detection module. If power |
| 549 | * is reapplied within this interval, then the PMIC reset automatically. The |
| 550 | * SMPL detection module must be enabled for this delay time to take effect. |
| 551 | * |
| 552 | * RETURNS: an appropriate -ERRNO error value on error, or zero for success. |
| 553 | */ |
| 554 | int pm8xxx_smpl_set_delay(enum pm8xxx_smpl_delay delay) |
| 555 | { |
| 556 | struct pm8xxx_misc_chip *chip; |
| 557 | unsigned long flags; |
| 558 | int rc = 0; |
| 559 | |
| 560 | if (delay < SLEEP_CTRL_SMPL_SEL_MIN |
| 561 | || delay > SLEEP_CTRL_SMPL_SEL_MAX) { |
| 562 | pr_err("%s: invalid delay specified: %d\n", __func__, delay); |
| 563 | return -EINVAL; |
| 564 | } |
| 565 | |
| 566 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 567 | |
| 568 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 569 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 570 | switch (chip->version) { |
| 571 | case PM8XXX_VERSION_8018: |
| 572 | rc = pm8xxx_misc_masked_write(chip, |
| 573 | REG_PM8018_SLEEP_CTRL, SLEEP_CTRL_SMPL_SEL_MASK, |
| 574 | delay); |
| 575 | break; |
| 576 | case PM8XXX_VERSION_8058: |
| 577 | rc = pm8xxx_misc_masked_write(chip, |
| 578 | REG_PM8058_SLEEP_CTRL, SLEEP_CTRL_SMPL_SEL_MASK, |
| 579 | delay); |
| 580 | break; |
| 581 | case PM8XXX_VERSION_8921: |
| 582 | rc = pm8xxx_misc_masked_write(chip, |
| 583 | REG_PM8921_SLEEP_CTRL, SLEEP_CTRL_SMPL_SEL_MASK, |
| 584 | delay); |
| 585 | break; |
| 586 | default: |
| 587 | /* PMIC doesn't have reset_pwr_off; do nothing. */ |
| 588 | break; |
| 589 | } |
| 590 | if (rc) { |
| 591 | pr_err("setting smpl delay failed, rc=%d\n", rc); |
| 592 | break; |
| 593 | } |
| 594 | } |
| 595 | |
| 596 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 597 | |
| 598 | return rc; |
| 599 | } |
| 600 | EXPORT_SYMBOL(pm8xxx_smpl_set_delay); |
| 601 | |
| 602 | /** |
Anirudh Ghayal | 7b38229 | 2011-11-01 14:08:34 +0530 | [diff] [blame] | 603 | * pm8xxx_coincell_chg_config - Disables or enables the coincell charger, and |
| 604 | * configures its voltage and resistor settings. |
| 605 | * @chg_config: Holds both voltage and resistor values, and a |
| 606 | * switch to change the state of charger. |
| 607 | * If state is to disable the charger then |
| 608 | * both voltage and resistor are disregarded. |
| 609 | * |
| 610 | * RETURNS: an appropriate -ERRNO error value on error, or zero for success. |
| 611 | */ |
| 612 | int pm8xxx_coincell_chg_config(struct pm8xxx_coincell_chg *chg_config) |
| 613 | { |
| 614 | struct pm8xxx_misc_chip *chip; |
| 615 | unsigned long flags; |
| 616 | u8 reg = 0, voltage, resistor; |
| 617 | int rc = 0; |
| 618 | |
| 619 | if (chg_config == NULL) { |
| 620 | pr_err("chg_config is NULL\n"); |
| 621 | return -EINVAL; |
| 622 | } |
| 623 | |
| 624 | voltage = chg_config->voltage; |
| 625 | resistor = chg_config->resistor; |
| 626 | |
| 627 | if (resistor < PM8XXX_COINCELL_RESISTOR_2100_OHMS || |
| 628 | resistor > PM8XXX_COINCELL_RESISTOR_800_OHMS) { |
| 629 | pr_err("Invalid resistor value provided\n"); |
| 630 | return -EINVAL; |
| 631 | } |
| 632 | |
| 633 | if (voltage < PM8XXX_COINCELL_VOLTAGE_3p2V || |
| 634 | (voltage > PM8XXX_COINCELL_VOLTAGE_3p0V && |
| 635 | voltage != PM8XXX_COINCELL_VOLTAGE_2p5V)) { |
| 636 | pr_err("Invalid voltage value provided\n"); |
| 637 | return -EINVAL; |
| 638 | } |
| 639 | |
| 640 | if (chg_config->state == PM8XXX_COINCELL_CHG_DISABLE) { |
| 641 | reg = 0; |
| 642 | } else { |
| 643 | reg |= voltage; |
| 644 | reg |= (resistor << COINCELL_RESISTOR_SHIFT); |
| 645 | } |
| 646 | |
| 647 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 648 | |
| 649 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 650 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 651 | switch (chip->version) { |
| 652 | case PM8XXX_VERSION_8018: |
| 653 | rc = pm8xxx_writeb(chip->dev->parent, |
| 654 | REG_PM8018_COIN_CHG, reg); |
| 655 | break; |
| 656 | case PM8XXX_VERSION_8058: |
| 657 | rc = pm8xxx_writeb(chip->dev->parent, |
| 658 | REG_PM8058_COIN_CHG, reg); |
| 659 | break; |
| 660 | case PM8XXX_VERSION_8921: |
| 661 | rc = pm8xxx_writeb(chip->dev->parent, |
| 662 | REG_PM8921_COIN_CHG, reg); |
| 663 | break; |
| 664 | default: |
| 665 | /* PMIC doesn't have reset_pwr_off; do nothing. */ |
| 666 | break; |
| 667 | } |
| 668 | if (rc) { |
| 669 | pr_err("coincell chg. config failed, rc=%d\n", rc); |
| 670 | break; |
| 671 | } |
| 672 | } |
| 673 | |
| 674 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 675 | |
| 676 | return rc; |
| 677 | } |
| 678 | EXPORT_SYMBOL(pm8xxx_coincell_chg_config); |
| 679 | |
Anirudh Ghayal | 8b8f189 | 2011-11-11 10:48:41 +0530 | [diff] [blame] | 680 | /* Handle the OSC_HALT interrupt: 32 kHz XTAL oscillator has stopped. */ |
| 681 | static irqreturn_t pm8xxx_osc_halt_isr(int irq, void *data) |
| 682 | { |
| 683 | struct pm8xxx_misc_chip *chip = data; |
| 684 | u64 count = 0; |
| 685 | |
| 686 | if (chip) { |
| 687 | chip->osc_halt_count++; |
| 688 | count = chip->osc_halt_count; |
| 689 | } |
| 690 | |
| 691 | pr_crit("%s: OSC_HALT interrupt has triggered, 32 kHz XTAL oscillator" |
| 692 | " has halted (%llu)!\n", __func__, count); |
| 693 | |
| 694 | return IRQ_HANDLED; |
| 695 | } |
| 696 | |
Anirudh Ghayal | 5213eb8 | 2011-10-24 14:44:58 +0530 | [diff] [blame] | 697 | /** |
| 698 | * pm8xxx_uart_gpio_mux_ctrl - Mux configuration to select the UART |
| 699 | * |
| 700 | * @uart_path_sel: Input argument to select either UART1/2/3 |
| 701 | * |
| 702 | * RETURNS: an appropriate -ERRNO error value on error, or zero for success. |
| 703 | */ |
| 704 | int pm8xxx_uart_gpio_mux_ctrl(enum pm8xxx_uart_path_sel uart_path_sel) |
| 705 | { |
| 706 | struct pm8xxx_misc_chip *chip; |
| 707 | unsigned long flags; |
| 708 | int rc = 0; |
| 709 | |
| 710 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 711 | |
| 712 | /* Loop over all attached PMICs and call specific functions for them. */ |
| 713 | list_for_each_entry(chip, &pm8xxx_misc_chips, link) { |
| 714 | switch (chip->version) { |
| 715 | case PM8XXX_VERSION_8018: |
| 716 | case PM8XXX_VERSION_8058: |
| 717 | case PM8XXX_VERSION_8921: |
| 718 | rc = pm8xxx_misc_masked_write(chip, |
| 719 | REG_PM8XXX_GPIO_MUX_CTRL, UART_PATH_SEL_MASK, |
| 720 | uart_path_sel << UART_PATH_SEL_SHIFT); |
| 721 | break; |
| 722 | default: |
| 723 | /* Functionality not supported */ |
| 724 | break; |
| 725 | } |
| 726 | if (rc) { |
| 727 | pr_err("uart_gpio_mux_ctrl failed, rc=%d\n", rc); |
| 728 | break; |
| 729 | } |
| 730 | } |
| 731 | |
| 732 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 733 | |
| 734 | return rc; |
| 735 | } |
| 736 | EXPORT_SYMBOL(pm8xxx_uart_gpio_mux_ctrl); |
| 737 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 738 | static int __devinit pm8xxx_misc_probe(struct platform_device *pdev) |
| 739 | { |
| 740 | const struct pm8xxx_misc_platform_data *pdata = pdev->dev.platform_data; |
| 741 | struct pm8xxx_misc_chip *chip; |
| 742 | struct pm8xxx_misc_chip *sibling; |
| 743 | struct list_head *prev; |
| 744 | unsigned long flags; |
Anirudh Ghayal | 8b8f189 | 2011-11-11 10:48:41 +0530 | [diff] [blame] | 745 | int rc = 0, irq; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 746 | |
| 747 | if (!pdata) { |
| 748 | pr_err("missing platform data\n"); |
| 749 | return -EINVAL; |
| 750 | } |
| 751 | |
| 752 | chip = kzalloc(sizeof(struct pm8xxx_misc_chip), GFP_KERNEL); |
| 753 | if (!chip) { |
| 754 | pr_err("Cannot allocate %d bytes\n", |
| 755 | sizeof(struct pm8xxx_misc_chip)); |
| 756 | return -ENOMEM; |
| 757 | } |
| 758 | |
| 759 | chip->dev = &pdev->dev; |
| 760 | chip->version = pm8xxx_get_version(chip->dev->parent); |
| 761 | memcpy(&(chip->pdata), pdata, sizeof(struct pm8xxx_misc_platform_data)); |
| 762 | |
Anirudh Ghayal | 8b8f189 | 2011-11-11 10:48:41 +0530 | [diff] [blame] | 763 | irq = platform_get_irq_byname(pdev, "pm8xxx_osc_halt_irq"); |
| 764 | if (irq > 0) { |
| 765 | rc = request_any_context_irq(irq, pm8xxx_osc_halt_isr, |
| 766 | IRQF_TRIGGER_RISING | IRQF_DISABLED, |
| 767 | "pm8xxx_osc_halt_irq", chip); |
| 768 | if (rc < 0) { |
| 769 | pr_err("%s: request_any_context_irq(%d) FAIL: %d\n", |
| 770 | __func__, irq, rc); |
| 771 | goto fail_irq; |
| 772 | } |
| 773 | } |
| 774 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 775 | /* Insert PMICs in priority order (lowest value first). */ |
| 776 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 777 | prev = &pm8xxx_misc_chips; |
| 778 | list_for_each_entry(sibling, &pm8xxx_misc_chips, link) { |
| 779 | if (chip->pdata.priority < sibling->pdata.priority) |
| 780 | break; |
| 781 | else |
| 782 | prev = &sibling->link; |
| 783 | } |
| 784 | list_add(&chip->link, prev); |
| 785 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 786 | |
| 787 | platform_set_drvdata(pdev, chip); |
| 788 | |
| 789 | return rc; |
Anirudh Ghayal | 8b8f189 | 2011-11-11 10:48:41 +0530 | [diff] [blame] | 790 | |
| 791 | fail_irq: |
| 792 | platform_set_drvdata(pdev, NULL); |
| 793 | kfree(chip); |
| 794 | return rc; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 795 | } |
| 796 | |
| 797 | static int __devexit pm8xxx_misc_remove(struct platform_device *pdev) |
| 798 | { |
| 799 | struct pm8xxx_misc_chip *chip = platform_get_drvdata(pdev); |
| 800 | unsigned long flags; |
Anirudh Ghayal | 8b8f189 | 2011-11-11 10:48:41 +0530 | [diff] [blame] | 801 | int irq = platform_get_irq_byname(pdev, "pm8xxx_osc_halt_irq"); |
| 802 | if (irq > 0) |
| 803 | free_irq(irq, chip); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 804 | |
| 805 | spin_lock_irqsave(&pm8xxx_misc_chips_lock, flags); |
| 806 | list_del(&chip->link); |
| 807 | spin_unlock_irqrestore(&pm8xxx_misc_chips_lock, flags); |
| 808 | |
| 809 | platform_set_drvdata(pdev, NULL); |
| 810 | kfree(chip); |
| 811 | |
| 812 | return 0; |
| 813 | } |
| 814 | |
| 815 | static struct platform_driver pm8xxx_misc_driver = { |
| 816 | .probe = pm8xxx_misc_probe, |
| 817 | .remove = __devexit_p(pm8xxx_misc_remove), |
| 818 | .driver = { |
| 819 | .name = PM8XXX_MISC_DEV_NAME, |
| 820 | .owner = THIS_MODULE, |
| 821 | }, |
| 822 | }; |
| 823 | |
| 824 | static int __init pm8xxx_misc_init(void) |
| 825 | { |
| 826 | return platform_driver_register(&pm8xxx_misc_driver); |
| 827 | } |
| 828 | postcore_initcall(pm8xxx_misc_init); |
| 829 | |
| 830 | static void __exit pm8xxx_misc_exit(void) |
| 831 | { |
| 832 | platform_driver_unregister(&pm8xxx_misc_driver); |
| 833 | } |
| 834 | module_exit(pm8xxx_misc_exit); |
| 835 | |
| 836 | MODULE_LICENSE("GPL v2"); |
| 837 | MODULE_DESCRIPTION("PMIC 8XXX misc driver"); |
| 838 | MODULE_VERSION("1.0"); |
| 839 | MODULE_ALIAS("platform:" PM8XXX_MISC_DEV_NAME); |