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gerrit-public.fairphone.software / kernel / msm / c1986ee9bea3d880bcf0d3f1a31e055778f306c7 / . / arch / ppc / syslib / mpc85xx_devices.c
blob: 2ede677a0a53c37d24ad208a8a9447f7acb195b7 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
2 * arch/ppc/platforms/85xx/mpc85xx_devices.c
3 *
4 * MPC85xx Device descriptions
5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
7 *
8 * Copyright 2005 Freescale Semiconductor Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/device.h>
19#include <linux/serial_8250.h>
20#include <linux/fsl_devices.h>
21#include <asm/mpc85xx.h>
22#include <asm/irq.h>
23#include <asm/ppc_sys.h>
24
25/* We use offsets for IORESOURCE_MEM since we do not know at compile time
26 * what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup
27 */
Andy Flemingb37665e2005-10-28 17:46:27 -0700[diff] [blame]28struct gianfar_mdio_data mpc85xx_mdio_pdata = {
29 .paddr = MPC85xx_MIIM_OFFSET,
30};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]31
32static struct gianfar_platform_data mpc85xx_tsec1_pdata = {
33 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
34 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
35 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]36};
37
38static struct gianfar_platform_data mpc85xx_tsec2_pdata = {
39 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
40 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
41 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]42};
43
Kumar Gala5b37b702005-06-21 17:15:18 -0700[diff] [blame]44static struct gianfar_platform_data mpc85xx_etsec1_pdata = {
45 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
46 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
47 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
48 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
49 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
Kumar Gala5b37b702005-06-21 17:15:18 -0700[diff] [blame]50};
51
52static struct gianfar_platform_data mpc85xx_etsec2_pdata = {
53 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
54 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
55 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
56 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
57 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
Kumar Gala5b37b702005-06-21 17:15:18 -0700[diff] [blame]58};
59
60static struct gianfar_platform_data mpc85xx_etsec3_pdata = {
61 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
62 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
63 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
64 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
65 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
Kumar Gala5b37b702005-06-21 17:15:18 -0700[diff] [blame]66};
67
68static struct gianfar_platform_data mpc85xx_etsec4_pdata = {
69 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
70 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
71 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
72 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
73 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
Kumar Gala5b37b702005-06-21 17:15:18 -0700[diff] [blame]74};
75
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]76static struct gianfar_platform_data mpc85xx_fec_pdata = {
Andy Flemingb37665e2005-10-28 17:46:27 -0700[diff] [blame]77 .device_flags = 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]78};
79
80static struct fsl_i2c_platform_data mpc85xx_fsl_i2c_pdata = {
81 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
82};
83
Kumar Gala5b37b702005-06-21 17:15:18 -0700[diff] [blame]84static struct fsl_i2c_platform_data mpc85xx_fsl_i2c2_pdata = {
85 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
86};
87
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]88static struct plat_serial8250_port serial_platform_data[] = {
89 [0] = {
90 .mapbase = 0x4500,
91 .irq = MPC85xx_IRQ_DUART,
92 .iotype = UPIO_MEM,
93 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
94 },
95 [1] = {
96 .mapbase = 0x4600,
97 .irq = MPC85xx_IRQ_DUART,
98 .iotype = UPIO_MEM,
99 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
100 },
Kumar Gala7f8cd802005-05-20 13:59:13 -0700[diff] [blame]101 { },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]102};
103
104struct platform_device ppc_sys_platform_devices[] = {
105 [MPC85xx_TSEC1] = {
106 .name = "fsl-gianfar",
107 .id = 1,
108 .dev.platform_data = &mpc85xx_tsec1_pdata,
109 .num_resources = 4,
110 .resource = (struct resource[]) {
111 {
112 .start = MPC85xx_ENET1_OFFSET,
113 .end = MPC85xx_ENET1_OFFSET +
114 MPC85xx_ENET1_SIZE - 1,
115 .flags = IORESOURCE_MEM,
116 },
117 {
118 .name = "tx",
119 .start = MPC85xx_IRQ_TSEC1_TX,
120 .end = MPC85xx_IRQ_TSEC1_TX,
121 .flags = IORESOURCE_IRQ,
122 },
123 {
124 .name = "rx",
125 .start = MPC85xx_IRQ_TSEC1_RX,
126 .end = MPC85xx_IRQ_TSEC1_RX,
127 .flags = IORESOURCE_IRQ,
128 },
129 {
130 .name = "error",
131 .start = MPC85xx_IRQ_TSEC1_ERROR,
132 .end = MPC85xx_IRQ_TSEC1_ERROR,
133 .flags = IORESOURCE_IRQ,
134 },
135 },
136 },
137 [MPC85xx_TSEC2] = {
138 .name = "fsl-gianfar",
139 .id = 2,
140 .dev.platform_data = &mpc85xx_tsec2_pdata,
141 .num_resources = 4,
142 .resource = (struct resource[]) {
143 {
144 .start = MPC85xx_ENET2_OFFSET,
145 .end = MPC85xx_ENET2_OFFSET +
146 MPC85xx_ENET2_SIZE - 1,
147 .flags = IORESOURCE_MEM,
148 },
149 {
150 .name = "tx",
151 .start = MPC85xx_IRQ_TSEC2_TX,
152 .end = MPC85xx_IRQ_TSEC2_TX,
153 .flags = IORESOURCE_IRQ,
154 },
155 {
156 .name = "rx",
157 .start = MPC85xx_IRQ_TSEC2_RX,
158 .end = MPC85xx_IRQ_TSEC2_RX,
159 .flags = IORESOURCE_IRQ,
160 },
161 {
162 .name = "error",
163 .start = MPC85xx_IRQ_TSEC2_ERROR,
164 .end = MPC85xx_IRQ_TSEC2_ERROR,
165 .flags = IORESOURCE_IRQ,
166 },
167 },
168 },
169 [MPC85xx_FEC] = {
170 .name = "fsl-gianfar",
171 .id = 3,
172 .dev.platform_data = &mpc85xx_fec_pdata,
173 .num_resources = 2,
174 .resource = (struct resource[]) {
175 {
176 .start = MPC85xx_ENET3_OFFSET,
177 .end = MPC85xx_ENET3_OFFSET +
178 MPC85xx_ENET3_SIZE - 1,
179 .flags = IORESOURCE_MEM,
180
181 },
182 {
183 .start = MPC85xx_IRQ_FEC,
184 .end = MPC85xx_IRQ_FEC,
185 .flags = IORESOURCE_IRQ,
186 },
187 },
188 },
189 [MPC85xx_IIC1] = {
190 .name = "fsl-i2c",
191 .id = 1,
192 .dev.platform_data = &mpc85xx_fsl_i2c_pdata,
193 .num_resources = 2,
194 .resource = (struct resource[]) {
195 {
196 .start = MPC85xx_IIC1_OFFSET,
197 .end = MPC85xx_IIC1_OFFSET +
198 MPC85xx_IIC1_SIZE - 1,
199 .flags = IORESOURCE_MEM,
200 },
201 {
202 .start = MPC85xx_IRQ_IIC1,
203 .end = MPC85xx_IRQ_IIC1,
204 .flags = IORESOURCE_IRQ,
205 },
206 },
207 },
208 [MPC85xx_DMA0] = {
209 .name = "fsl-dma",
210 .id = 0,
211 .num_resources = 2,
212 .resource = (struct resource[]) {
213 {
214 .start = MPC85xx_DMA0_OFFSET,
215 .end = MPC85xx_DMA0_OFFSET +
216 MPC85xx_DMA0_SIZE - 1,
217 .flags = IORESOURCE_MEM,
218 },
219 {
220 .start = MPC85xx_IRQ_DMA0,
221 .end = MPC85xx_IRQ_DMA0,
222 .flags = IORESOURCE_IRQ,
223 },
224 },
225 },
226 [MPC85xx_DMA1] = {
227 .name = "fsl-dma",
228 .id = 1,
229 .num_resources = 2,
230 .resource = (struct resource[]) {
231 {
232 .start = MPC85xx_DMA1_OFFSET,
233 .end = MPC85xx_DMA1_OFFSET +
234 MPC85xx_DMA1_SIZE - 1,
235 .flags = IORESOURCE_MEM,
236 },
237 {
238 .start = MPC85xx_IRQ_DMA1,
239 .end = MPC85xx_IRQ_DMA1,
240 .flags = IORESOURCE_IRQ,
241 },
242 },
243 },
244 [MPC85xx_DMA2] = {
245 .name = "fsl-dma",
246 .id = 2,
247 .num_resources = 2,
248 .resource = (struct resource[]) {
249 {
250 .start = MPC85xx_DMA2_OFFSET,
251 .end = MPC85xx_DMA2_OFFSET +
252 MPC85xx_DMA2_SIZE - 1,
253 .flags = IORESOURCE_MEM,
254 },
255 {
256 .start = MPC85xx_IRQ_DMA2,
257 .end = MPC85xx_IRQ_DMA2,
258 .flags = IORESOURCE_IRQ,
259 },
260 },
261 },
262 [MPC85xx_DMA3] = {
263 .name = "fsl-dma",
264 .id = 3,
265 .num_resources = 2,
266 .resource = (struct resource[]) {
267 {
268 .start = MPC85xx_DMA3_OFFSET,
269 .end = MPC85xx_DMA3_OFFSET +
270 MPC85xx_DMA3_SIZE - 1,
271 .flags = IORESOURCE_MEM,
272 },
273 {
274 .start = MPC85xx_IRQ_DMA3,
275 .end = MPC85xx_IRQ_DMA3,
276 .flags = IORESOURCE_IRQ,
277 },
278 },
279 },
280 [MPC85xx_DUART] = {
281 .name = "serial8250",
Russell King6df29de2005-09-08 16:04:41 +0100[diff] [blame]282 .id = PLAT8250_DEV_PLATFORM,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]283 .dev.platform_data = serial_platform_data,
284 },
285 [MPC85xx_PERFMON] = {
286 .name = "fsl-perfmon",
287 .id = 1,
288 .num_resources = 2,
289 .resource = (struct resource[]) {
290 {
291 .start = MPC85xx_PERFMON_OFFSET,
292 .end = MPC85xx_PERFMON_OFFSET +
293 MPC85xx_PERFMON_SIZE - 1,
294 .flags = IORESOURCE_MEM,
295 },
296 {
297 .start = MPC85xx_IRQ_PERFMON,
298 .end = MPC85xx_IRQ_PERFMON,
299 .flags = IORESOURCE_IRQ,
300 },
301 },
302 },
303 [MPC85xx_SEC2] = {
304 .name = "fsl-sec2",
305 .id = 1,
306 .num_resources = 2,
307 .resource = (struct resource[]) {
308 {
309 .start = MPC85xx_SEC2_OFFSET,
310 .end = MPC85xx_SEC2_OFFSET +
311 MPC85xx_SEC2_SIZE - 1,
312 .flags = IORESOURCE_MEM,
313 },
314 {
315 .start = MPC85xx_IRQ_SEC2,
316 .end = MPC85xx_IRQ_SEC2,
317 .flags = IORESOURCE_IRQ,
318 },
319 },
320 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]321 [MPC85xx_CPM_FCC1] = {
322 .name = "fsl-cpm-fcc",
323 .id = 1,
324 .num_resources = 3,
325 .resource = (struct resource[]) {
326 {
327 .start = 0x91300,
328 .end = 0x9131F,
329 .flags = IORESOURCE_MEM,
330 },
331 {
332 .start = 0x91380,
333 .end = 0x9139F,
334 .flags = IORESOURCE_MEM,
335 },
336 {
337 .start = SIU_INT_FCC1,
338 .end = SIU_INT_FCC1,
339 .flags = IORESOURCE_IRQ,
340 },
341 },
342 },
343 [MPC85xx_CPM_FCC2] = {
344 .name = "fsl-cpm-fcc",
345 .id = 2,
346 .num_resources = 3,
347 .resource = (struct resource[]) {
348 {
349 .start = 0x91320,
350 .end = 0x9133F,
351 .flags = IORESOURCE_MEM,
352 },
353 {
354 .start = 0x913A0,
355 .end = 0x913CF,
356 .flags = IORESOURCE_MEM,
357 },
358 {
359 .start = SIU_INT_FCC2,
360 .end = SIU_INT_FCC2,
361 .flags = IORESOURCE_IRQ,
362 },
363 },
364 },
365 [MPC85xx_CPM_FCC3] = {
366 .name = "fsl-cpm-fcc",
367 .id = 3,
368 .num_resources = 3,
369 .resource = (struct resource[]) {
370 {
371 .start = 0x91340,
372 .end = 0x9135F,
373 .flags = IORESOURCE_MEM,
374 },
375 {
376 .start = 0x913D0,
377 .end = 0x913FF,
378 .flags = IORESOURCE_MEM,
379 },
380 {
381 .start = SIU_INT_FCC3,
382 .end = SIU_INT_FCC3,
383 .flags = IORESOURCE_IRQ,
384 },
385 },
386 },
387 [MPC85xx_CPM_I2C] = {
388 .name = "fsl-cpm-i2c",
389 .id = 1,
390 .num_resources = 2,
391 .resource = (struct resource[]) {
392 {
393 .start = 0x91860,
394 .end = 0x918BF,
395 .flags = IORESOURCE_MEM,
396 },
397 {
398 .start = SIU_INT_I2C,
399 .end = SIU_INT_I2C,
400 .flags = IORESOURCE_IRQ,
401 },
402 },
403 },
404 [MPC85xx_CPM_SCC1] = {
405 .name = "fsl-cpm-scc",
406 .id = 1,
407 .num_resources = 2,
408 .resource = (struct resource[]) {
409 {
410 .start = 0x91A00,
411 .end = 0x91A1F,
412 .flags = IORESOURCE_MEM,
413 },
414 {
415 .start = SIU_INT_SCC1,
416 .end = SIU_INT_SCC1,
417 .flags = IORESOURCE_IRQ,
418 },
419 },
420 },
421 [MPC85xx_CPM_SCC2] = {
422 .name = "fsl-cpm-scc",
423 .id = 2,
424 .num_resources = 2,
425 .resource = (struct resource[]) {
426 {
427 .start = 0x91A20,
428 .end = 0x91A3F,
429 .flags = IORESOURCE_MEM,
430 },
431 {
432 .start = SIU_INT_SCC2,
433 .end = SIU_INT_SCC2,
434 .flags = IORESOURCE_IRQ,
435 },
436 },
437 },
438 [MPC85xx_CPM_SCC3] = {
439 .name = "fsl-cpm-scc",
440 .id = 3,
441 .num_resources = 2,
442 .resource = (struct resource[]) {
443 {
444 .start = 0x91A40,
445 .end = 0x91A5F,
446 .flags = IORESOURCE_MEM,
447 },
448 {
449 .start = SIU_INT_SCC3,
450 .end = SIU_INT_SCC3,
451 .flags = IORESOURCE_IRQ,
452 },
453 },
454 },
455 [MPC85xx_CPM_SCC4] = {
456 .name = "fsl-cpm-scc",
457 .id = 4,
458 .num_resources = 2,
459 .resource = (struct resource[]) {
460 {
461 .start = 0x91A60,
462 .end = 0x91A7F,
463 .flags = IORESOURCE_MEM,
464 },
465 {
466 .start = SIU_INT_SCC4,
467 .end = SIU_INT_SCC4,
468 .flags = IORESOURCE_IRQ,
469 },
470 },
471 },
472 [MPC85xx_CPM_SPI] = {
473 .name = "fsl-cpm-spi",
474 .id = 1,
475 .num_resources = 2,
476 .resource = (struct resource[]) {
477 {
478 .start = 0x91AA0,
479 .end = 0x91AFF,
480 .flags = IORESOURCE_MEM,
481 },
482 {
483 .start = SIU_INT_SPI,
484 .end = SIU_INT_SPI,
485 .flags = IORESOURCE_IRQ,
486 },
487 },
488 },
489 [MPC85xx_CPM_MCC1] = {
490 .name = "fsl-cpm-mcc",
491 .id = 1,
492 .num_resources = 2,
493 .resource = (struct resource[]) {
494 {
495 .start = 0x91B30,
496 .end = 0x91B3F,
497 .flags = IORESOURCE_MEM,
498 },
499 {
500 .start = SIU_INT_MCC1,
501 .end = SIU_INT_MCC1,
502 .flags = IORESOURCE_IRQ,
503 },
504 },
505 },
506 [MPC85xx_CPM_MCC2] = {
507 .name = "fsl-cpm-mcc",
508 .id = 2,
509 .num_resources = 2,
510 .resource = (struct resource[]) {
511 {
512 .start = 0x91B50,
513 .end = 0x91B5F,
514 .flags = IORESOURCE_MEM,
515 },
516 {
517 .start = SIU_INT_MCC2,
518 .end = SIU_INT_MCC2,
519 .flags = IORESOURCE_IRQ,
520 },
521 },
522 },
523 [MPC85xx_CPM_SMC1] = {
524 .name = "fsl-cpm-smc",
525 .id = 1,
526 .num_resources = 2,
527 .resource = (struct resource[]) {
528 {
529 .start = 0x91A80,
530 .end = 0x91A8F,
531 .flags = IORESOURCE_MEM,
532 },
533 {
534 .start = SIU_INT_SMC1,
535 .end = SIU_INT_SMC1,
536 .flags = IORESOURCE_IRQ,
537 },
538 },
539 },
540 [MPC85xx_CPM_SMC2] = {
541 .name = "fsl-cpm-smc",
542 .id = 2,
543 .num_resources = 2,
544 .resource = (struct resource[]) {
545 {
546 .start = 0x91A90,
547 .end = 0x91A9F,
548 .flags = IORESOURCE_MEM,
549 },
550 {
551 .start = SIU_INT_SMC2,
552 .end = SIU_INT_SMC2,
553 .flags = IORESOURCE_IRQ,
554 },
555 },
556 },
557 [MPC85xx_CPM_USB] = {
558 .name = "fsl-cpm-usb",
559 .id = 2,
560 .num_resources = 2,
561 .resource = (struct resource[]) {
562 {
563 .start = 0x91B60,
564 .end = 0x91B7F,
565 .flags = IORESOURCE_MEM,
566 },
567 {
568 .start = SIU_INT_USB,
569 .end = SIU_INT_USB,
570 .flags = IORESOURCE_IRQ,
571 },
572 },
573 },
Kumar Gala5b37b702005-06-21 17:15:18 -0700[diff] [blame]574 [MPC85xx_eTSEC1] = {
575 .name = "fsl-gianfar",
576 .id = 1,
577 .dev.platform_data = &mpc85xx_etsec1_pdata,
578 .num_resources = 4,
579 .resource = (struct resource[]) {
580 {
581 .start = MPC85xx_ENET1_OFFSET,
582 .end = MPC85xx_ENET1_OFFSET +
583 MPC85xx_ENET1_SIZE - 1,
584 .flags = IORESOURCE_MEM,
585 },
586 {
587 .name = "tx",
588 .start = MPC85xx_IRQ_TSEC1_TX,
589 .end = MPC85xx_IRQ_TSEC1_TX,
590 .flags = IORESOURCE_IRQ,
591 },
592 {
593 .name = "rx",
594 .start = MPC85xx_IRQ_TSEC1_RX,
595 .end = MPC85xx_IRQ_TSEC1_RX,
596 .flags = IORESOURCE_IRQ,
597 },
598 {
599 .name = "error",
600 .start = MPC85xx_IRQ_TSEC1_ERROR,
601 .end = MPC85xx_IRQ_TSEC1_ERROR,
602 .flags = IORESOURCE_IRQ,
603 },
604 },
605 },
606 [MPC85xx_eTSEC2] = {
607 .name = "fsl-gianfar",
608 .id = 2,
609 .dev.platform_data = &mpc85xx_etsec2_pdata,
610 .num_resources = 4,
611 .resource = (struct resource[]) {
612 {
613 .start = MPC85xx_ENET2_OFFSET,
614 .end = MPC85xx_ENET2_OFFSET +
615 MPC85xx_ENET2_SIZE - 1,
616 .flags = IORESOURCE_MEM,
617 },
618 {
619 .name = "tx",
620 .start = MPC85xx_IRQ_TSEC2_TX,
621 .end = MPC85xx_IRQ_TSEC2_TX,
622 .flags = IORESOURCE_IRQ,
623 },
624 {
625 .name = "rx",
626 .start = MPC85xx_IRQ_TSEC2_RX,
627 .end = MPC85xx_IRQ_TSEC2_RX,
628 .flags = IORESOURCE_IRQ,
629 },
630 {
631 .name = "error",
632 .start = MPC85xx_IRQ_TSEC2_ERROR,
633 .end = MPC85xx_IRQ_TSEC2_ERROR,
634 .flags = IORESOURCE_IRQ,
635 },
636 },
637 },
638 [MPC85xx_eTSEC3] = {
639 .name = "fsl-gianfar",
640 .id = 3,
641 .dev.platform_data = &mpc85xx_etsec3_pdata,
642 .num_resources = 4,
643 .resource = (struct resource[]) {
644 {
645 .start = MPC85xx_ENET3_OFFSET,
646 .end = MPC85xx_ENET3_OFFSET +
647 MPC85xx_ENET3_SIZE - 1,
648 .flags = IORESOURCE_MEM,
649 },
650 {
651 .name = "tx",
652 .start = MPC85xx_IRQ_TSEC3_TX,
653 .end = MPC85xx_IRQ_TSEC3_TX,
654 .flags = IORESOURCE_IRQ,
655 },
656 {
657 .name = "rx",
658 .start = MPC85xx_IRQ_TSEC3_RX,
659 .end = MPC85xx_IRQ_TSEC3_RX,
660 .flags = IORESOURCE_IRQ,
661 },
662 {
663 .name = "error",
664 .start = MPC85xx_IRQ_TSEC3_ERROR,
665 .end = MPC85xx_IRQ_TSEC3_ERROR,
666 .flags = IORESOURCE_IRQ,
667 },
668 },
669 },
670 [MPC85xx_eTSEC4] = {
671 .name = "fsl-gianfar",
672 .id = 4,
673 .dev.platform_data = &mpc85xx_etsec4_pdata,
674 .num_resources = 4,
675 .resource = (struct resource[]) {
676 {
677 .start = 0x27000,
678 .end = 0x27fff,
679 .flags = IORESOURCE_MEM,
680 },
681 {
682 .name = "tx",
683 .start = MPC85xx_IRQ_TSEC4_TX,
684 .end = MPC85xx_IRQ_TSEC4_TX,
685 .flags = IORESOURCE_IRQ,
686 },
687 {
688 .name = "rx",
689 .start = MPC85xx_IRQ_TSEC4_RX,
690 .end = MPC85xx_IRQ_TSEC4_RX,
691 .flags = IORESOURCE_IRQ,
692 },
693 {
694 .name = "error",
695 .start = MPC85xx_IRQ_TSEC4_ERROR,
696 .end = MPC85xx_IRQ_TSEC4_ERROR,
697 .flags = IORESOURCE_IRQ,
698 },
699 },
700 },
701 [MPC85xx_IIC2] = {
702 .name = "fsl-i2c",
703 .id = 2,
704 .dev.platform_data = &mpc85xx_fsl_i2c2_pdata,
705 .num_resources = 2,
706 .resource = (struct resource[]) {
707 {
708 .start = 0x03100,
709 .end = 0x031ff,
710 .flags = IORESOURCE_MEM,
711 },
712 {
713 .start = MPC85xx_IRQ_IIC1,
714 .end = MPC85xx_IRQ_IIC1,
715 .flags = IORESOURCE_IRQ,
716 },
717 },
718 },
Andy Flemingb37665e2005-10-28 17:46:27 -0700[diff] [blame]719 [MPC85xx_MDIO] = {
720 .name = "fsl-gianfar_mdio",
721 .id = 0,
722 .dev.platform_data = &mpc85xx_mdio_pdata,
723 .num_resources = 0,
724 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]725};
726
727static int __init mach_mpc85xx_fixup(struct platform_device *pdev)
728{
729 ppc_sys_fixup_mem_resource(pdev, CCSRBAR);
730 return 0;
731}
732
733static int __init mach_mpc85xx_init(void)
734{
735 ppc_sys_device_fixup = mach_mpc85xx_fixup;
736 return 0;
737}
738
739postcore_initcall(mach_mpc85xx_init);