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Felipe Balbi72246da2011-08-19 18:10:58 +03001/**
2 * core.h - DesignWare USB3 DRD Core Header
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
Felipe Balbi72246da2011-08-19 18:10:58 +03005 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#ifndef __DRIVERS_USB_DWC3_CORE_H
40#define __DRIVERS_USB_DWC3_CORE_H
41
42#include <linux/device.h>
43#include <linux/spinlock.h>
Felipe Balbid07e8812011-10-12 14:08:26 +030044#include <linux/ioport.h>
Felipe Balbi72246da2011-08-19 18:10:58 +030045#include <linux/list.h>
46#include <linux/dma-mapping.h>
47#include <linux/mm.h>
48#include <linux/debugfs.h>
49
50#include <linux/usb/ch9.h>
51#include <linux/usb/gadget.h>
52
Ido Shayevitzcdeef4c2012-05-29 13:17:41 +020053#include "dwc3_otg.h"
54
Felipe Balbi72246da2011-08-19 18:10:58 +030055/* Global constants */
Felipe Balbib0791fb2012-05-04 12:58:14 +030056#define DWC3_EP0_BOUNCE_SIZE 512
Felipe Balbi72246da2011-08-19 18:10:58 +030057#define DWC3_ENDPOINTS_NUM 32
Ido Shayevitz4a187332012-04-23 14:53:37 +020058#define DWC3_XHCI_RESOURCES_NUM 2
Felipe Balbi72246da2011-08-19 18:10:58 +030059
Pavankumar Kondetid393e172012-06-12 16:07:29 +053060#define DWC3_EVENT_BUFFERS_SIZE (2 * PAGE_SIZE)
Felipe Balbi72246da2011-08-19 18:10:58 +030061#define DWC3_EVENT_TYPE_MASK 0xfe
62
63#define DWC3_EVENT_TYPE_DEV 0
64#define DWC3_EVENT_TYPE_CARKIT 3
65#define DWC3_EVENT_TYPE_I2C 4
66
67#define DWC3_DEVICE_EVENT_DISCONNECT 0
68#define DWC3_DEVICE_EVENT_RESET 1
69#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
70#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
71#define DWC3_DEVICE_EVENT_WAKEUP 4
Paul Zimmerman394c74f2012-02-15 18:56:58 -080072#define DWC3_DEVICE_EVENT_HIBER_REQ 5
Felipe Balbi72246da2011-08-19 18:10:58 +030073#define DWC3_DEVICE_EVENT_EOPF 6
74#define DWC3_DEVICE_EVENT_SOF 7
75#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
76#define DWC3_DEVICE_EVENT_CMD_CMPL 10
77#define DWC3_DEVICE_EVENT_OVERFLOW 11
Pavankumar Kondeti33fe6f12012-06-12 16:21:46 +053078#define DWC3_DEVICE_EVENT_VENDOR_DEV_TEST_LMP 12
Felipe Balbi72246da2011-08-19 18:10:58 +030079
80#define DWC3_GEVNTCOUNT_MASK 0xfffc
81#define DWC3_GSNPSID_MASK 0xffff0000
82#define DWC3_GSNPSREV_MASK 0xffff
83
Ido Shayevitz4a187332012-04-23 14:53:37 +020084/* DWC3 registers memory space boundries */
85#define DWC3_XHCI_REGS_START 0x0
86#define DWC3_XHCI_REGS_END 0x7fff
87#define DWC3_GLOBALS_REGS_START 0xc100
88#define DWC3_GLOBALS_REGS_END 0xc6ff
89#define DWC3_DEVICE_REGS_START 0xc700
90#define DWC3_DEVICE_REGS_END 0xcbff
91#define DWC3_OTG_REGS_START 0xcc00
92#define DWC3_OTG_REGS_END 0xccff
93
Felipe Balbi72246da2011-08-19 18:10:58 +030094/* Global Registers */
95#define DWC3_GSBUSCFG0 0xc100
96#define DWC3_GSBUSCFG1 0xc104
97#define DWC3_GTXTHRCFG 0xc108
98#define DWC3_GRXTHRCFG 0xc10c
99#define DWC3_GCTL 0xc110
100#define DWC3_GEVTEN 0xc114
101#define DWC3_GSTS 0xc118
102#define DWC3_GSNPSID 0xc120
103#define DWC3_GGPIO 0xc124
104#define DWC3_GUID 0xc128
105#define DWC3_GUCTL 0xc12c
106#define DWC3_GBUSERRADDR0 0xc130
107#define DWC3_GBUSERRADDR1 0xc134
108#define DWC3_GPRTBIMAP0 0xc138
109#define DWC3_GPRTBIMAP1 0xc13c
110#define DWC3_GHWPARAMS0 0xc140
111#define DWC3_GHWPARAMS1 0xc144
112#define DWC3_GHWPARAMS2 0xc148
113#define DWC3_GHWPARAMS3 0xc14c
114#define DWC3_GHWPARAMS4 0xc150
115#define DWC3_GHWPARAMS5 0xc154
116#define DWC3_GHWPARAMS6 0xc158
117#define DWC3_GHWPARAMS7 0xc15c
118#define DWC3_GDBGFIFOSPACE 0xc160
119#define DWC3_GDBGLTSSM 0xc164
120#define DWC3_GPRTBIMAP_HS0 0xc180
121#define DWC3_GPRTBIMAP_HS1 0xc184
122#define DWC3_GPRTBIMAP_FS0 0xc188
123#define DWC3_GPRTBIMAP_FS1 0xc18c
124
125#define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
126#define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
127
128#define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
129
130#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
131
132#define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
133#define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
134
135#define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
136#define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
137#define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
138#define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
139
140#define DWC3_GHWPARAMS8 0xc600
141
142/* Device Registers */
143#define DWC3_DCFG 0xc700
144#define DWC3_DCTL 0xc704
145#define DWC3_DEVTEN 0xc708
146#define DWC3_DSTS 0xc70c
147#define DWC3_DGCMDPAR 0xc710
148#define DWC3_DGCMD 0xc714
149#define DWC3_DALEPENA 0xc720
150#define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
151#define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
152#define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
153#define DWC3_DEPCMD(n) (0xc80c + (n * 0x10))
154
155/* OTG Registers */
156#define DWC3_OCFG 0xcc00
157#define DWC3_OCTL 0xcc04
Ido Shayevitzcdeef4c2012-05-29 13:17:41 +0200158#define DWC3_OEVT 0xcc08
159#define DWC3_OEVTEN 0xcc0c
160#define DWC3_OSTS 0xcc10
Felipe Balbi72246da2011-08-19 18:10:58 +0300161
162/* Bit fields */
163
164/* Global Configuration Register */
Paul Zimmerman1d046792012-02-15 18:56:56 -0800165#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
Felipe Balbif4aadbe2011-09-08 17:39:59 +0300166#define DWC3_GCTL_U2RSTECN (1 << 16)
Paul Zimmerman1d046792012-02-15 18:56:56 -0800167#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
Felipe Balbi72246da2011-08-19 18:10:58 +0300168#define DWC3_GCTL_CLK_BUS (0)
169#define DWC3_GCTL_CLK_PIPE (1)
170#define DWC3_GCTL_CLK_PIPEHALF (2)
171#define DWC3_GCTL_CLK_MASK (3)
172
Felipe Balbi0b9fe322011-10-17 08:50:39 +0300173#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
Paul Zimmerman1d046792012-02-15 18:56:56 -0800174#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
Felipe Balbi72246da2011-08-19 18:10:58 +0300175#define DWC3_GCTL_PRTCAP_HOST 1
176#define DWC3_GCTL_PRTCAP_DEVICE 2
177#define DWC3_GCTL_PRTCAP_OTG 3
178
Paul Zimmerman394c74f2012-02-15 18:56:58 -0800179#define DWC3_GCTL_CORESOFTRESET (1 << 11)
180#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
181#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
182#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
183#define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
184#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
Felipe Balbi72246da2011-08-19 18:10:58 +0300185
Pavankumar Kondetic6e15aa2012-07-16 11:37:15 +0530186/* Global User Control Register */
187#define DWC3_GUCTL_REFCLKPER (0x3FF << 22)
188
Felipe Balbi72246da2011-08-19 18:10:58 +0300189/* Global USB2 PHY Configuration Register */
Paul Zimmerman394c74f2012-02-15 18:56:58 -0800190#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
191#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
Felipe Balbi72246da2011-08-19 18:10:58 +0300192
193/* Global USB3 PIPE Control Register */
Paul Zimmerman394c74f2012-02-15 18:56:58 -0800194#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
195#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
196#define DWC3_GUSB3PIPECTL_DELAY_P1P2P3 (7 << 19)
197#define DWC3_GUSB3PIPECTL_DIS_RXDET_U3_RXDET (1 << 22)
Vijayavardhan Vennapusad0136a72013-06-07 13:22:18 +0530198#define DWC3_GUSB3PIPECTL_ELASTIC_BUF_MODE (1 << 0)
Felipe Balbi72246da2011-08-19 18:10:58 +0300199
Felipe Balbi457e84b2012-01-18 18:04:09 +0200200/* Global TX Fifo Size Register */
Paul Zimmerman394c74f2012-02-15 18:56:58 -0800201#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
202#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
Felipe Balbi457e84b2012-01-18 18:04:09 +0200203
Felipe Balbiaabb7072011-09-30 10:58:50 +0300204/* Global HWPARAMS1 Register */
Paul Zimmerman1d046792012-02-15 18:56:56 -0800205#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
Felipe Balbiaabb7072011-09-30 10:58:50 +0300206#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
207#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
Paul Zimmerman394c74f2012-02-15 18:56:58 -0800208#define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
209#define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
210#define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
211
212/* Global HWPARAMS4 Register */
213#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
214#define DWC3_MAX_HIBER_SCRATCHBUFS 15
Felipe Balbiaabb7072011-09-30 10:58:50 +0300215
Ido Shayevitzcdeef4c2012-05-29 13:17:41 +0200216/* Global HWPARAMS6 Register */
217#define DWC3_GHWPARAMS6_SRP_SUPPORT (1 << 10)
218
Felipe Balbi72246da2011-08-19 18:10:58 +0300219/* Device Configuration Register */
Sebastian Andrzej Siewiorbb8b8a32011-09-13 17:54:39 +0200220#define DWC3_DCFG_LPM_CAP (1 << 22)
Felipe Balbi72246da2011-08-19 18:10:58 +0300221#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
222#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
223
224#define DWC3_DCFG_SPEED_MASK (7 << 0)
225#define DWC3_DCFG_SUPERSPEED (4 << 0)
226#define DWC3_DCFG_HIGHSPEED (0 << 0)
227#define DWC3_DCFG_FULLSPEED2 (1 << 0)
228#define DWC3_DCFG_LOWSPEED (2 << 0)
229#define DWC3_DCFG_FULLSPEED1 (3 << 0)
230
Paul Zimmerman394c74f2012-02-15 18:56:58 -0800231#define DWC3_DCFG_LPM_CAP (1 << 22)
232
Felipe Balbi72246da2011-08-19 18:10:58 +0300233/* Device Control Register */
234#define DWC3_DCTL_RUN_STOP (1 << 31)
235#define DWC3_DCTL_CSFTRST (1 << 30)
236#define DWC3_DCTL_LSFTRST (1 << 29)
237
238#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
Pratyush Anandb403c112012-06-06 19:18:29 +0530239#define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
Felipe Balbi72246da2011-08-19 18:10:58 +0300240
241#define DWC3_DCTL_APPL1RES (1 << 23)
242
Paul Zimmerman394c74f2012-02-15 18:56:58 -0800243/* These apply for core versions 1.87a and earlier */
244#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
245#define DWC3_DCTL_TRGTULST(n) ((n) << 17)
246#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
247#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
248#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
249#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
250#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
Felipe Balbi8db7ed12012-01-18 18:32:29 +0200251
Paul Zimmerman394c74f2012-02-15 18:56:58 -0800252/* These apply for core versions 1.94a and later */
253#define DWC3_DCTL_KEEP_CONNECT (1 << 19)
254#define DWC3_DCTL_L1_HIBER_EN (1 << 18)
255#define DWC3_DCTL_CRS (1 << 17)
256#define DWC3_DCTL_CSS (1 << 16)
Felipe Balbi8db7ed12012-01-18 18:32:29 +0200257
Felipe Balbi72246da2011-08-19 18:10:58 +0300258#define DWC3_DCTL_INITU2ENA (1 << 12)
259#define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
260#define DWC3_DCTL_INITU1ENA (1 << 10)
261#define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
262#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
263
264#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
265#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
266
267#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
268#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
269#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
270#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
271#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
272#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
273#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
274
275/* Device Event Enable Register */
276#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
277#define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
278#define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
279#define DWC3_DEVTEN_ERRTICERREN (1 << 9)
280#define DWC3_DEVTEN_SOFEN (1 << 7)
281#define DWC3_DEVTEN_EOPFEN (1 << 6)
Paul Zimmerman394c74f2012-02-15 18:56:58 -0800282#define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
Felipe Balbi72246da2011-08-19 18:10:58 +0300283#define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
284#define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
285#define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
286#define DWC3_DEVTEN_USBRSTEN (1 << 1)
287#define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
288
289/* Device Status Register */
Paul Zimmerman394c74f2012-02-15 18:56:58 -0800290#define DWC3_DSTS_DCNRD (1 << 29)
291
292/* This applies for core versions 1.87a and earlier */
Felipe Balbi72246da2011-08-19 18:10:58 +0300293#define DWC3_DSTS_PWRUPREQ (1 << 24)
Paul Zimmerman394c74f2012-02-15 18:56:58 -0800294
295/* These apply for core versions 1.94a and later */
296#define DWC3_DSTS_RSS (1 << 25)
297#define DWC3_DSTS_SSS (1 << 24)
298
Felipe Balbi72246da2011-08-19 18:10:58 +0300299#define DWC3_DSTS_COREIDLE (1 << 23)
300#define DWC3_DSTS_DEVCTRLHLT (1 << 22)
301
302#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
303#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
304
305#define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
306
Pratyush Anande8478e62012-05-21 14:51:30 +0530307#define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
Felipe Balbi72246da2011-08-19 18:10:58 +0300308#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
309
310#define DWC3_DSTS_CONNECTSPD (7 << 0)
311
312#define DWC3_DSTS_SUPERSPEED (4 << 0)
313#define DWC3_DSTS_HIGHSPEED (0 << 0)
314#define DWC3_DSTS_FULLSPEED2 (1 << 0)
315#define DWC3_DSTS_LOWSPEED (2 << 0)
316#define DWC3_DSTS_FULLSPEED1 (3 << 0)
317
318/* Device Generic Command Register */
319#define DWC3_DGCMD_SET_LMP 0x01
320#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
321#define DWC3_DGCMD_XMIT_FUNCTION 0x03
Paul Zimmerman394c74f2012-02-15 18:56:58 -0800322
323/* These apply for core versions 1.94a and later */
324#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
325#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
326
Felipe Balbi72246da2011-08-19 18:10:58 +0300327#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
328#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
329#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
330#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
331
Felipe Balbi573c2762012-04-24 16:19:11 +0300332#define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1)
333#define DWC3_DGCMD_CMDACT (1 << 10)
Paul Zimmerman394c74f2012-02-15 18:56:58 -0800334#define DWC3_DGCMD_CMDIOC (1 << 8)
335
336/* Device Generic Command Parameter Register */
337#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)
338#define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
339#define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
340#define DWC3_DGCMDPAR_TX_FIFO (1 << 5)
341#define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
342#define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0)
Felipe Balbi573c2762012-04-24 16:19:11 +0300343
Felipe Balbi72246da2011-08-19 18:10:58 +0300344/* Device Endpoint Command Register */
345#define DWC3_DEPCMD_PARAM_SHIFT 16
Paul Zimmerman1d046792012-02-15 18:56:56 -0800346#define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
347#define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
Felipe Balbi573c2762012-04-24 16:19:11 +0300348#define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1)
Felipe Balbi72246da2011-08-19 18:10:58 +0300349#define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
350#define DWC3_DEPCMD_CMDACT (1 << 10)
351#define DWC3_DEPCMD_CMDIOC (1 << 8)
352
353#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
354#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
355#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
356#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
357#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
358#define DWC3_DEPCMD_SETSTALL (0x04 << 0)
Paul Zimmerman394c74f2012-02-15 18:56:58 -0800359/* This applies for core versions 1.90a and earlier */
Felipe Balbi72246da2011-08-19 18:10:58 +0300360#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
Paul Zimmerman394c74f2012-02-15 18:56:58 -0800361/* This applies for core versions 1.94a and later */
362#define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
Felipe Balbi72246da2011-08-19 18:10:58 +0300363#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
364#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
365
366/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
367#define DWC3_DALEPENA_EP(n) (1 << n)
368
369#define DWC3_DEPCMD_TYPE_CONTROL 0
370#define DWC3_DEPCMD_TYPE_ISOC 1
371#define DWC3_DEPCMD_TYPE_BULK 2
372#define DWC3_DEPCMD_TYPE_INTR 3
373
Ido Shayevitzcdeef4c2012-05-29 13:17:41 +0200374/* OTG Events Register */
375#define DWC3_OEVT_DEVICEMODE (1 << 31)
376#define DWC3_OEVTEN_OTGCONIDSTSCHNGEVNT (1 << 24)
377#define DWC3_OEVTEN_OTGADEVBHOSTENDEVNT (1 << 20)
378#define DWC3_OEVTEN_OTGADEVHOSTEVNT (1 << 19)
379#define DWC3_OEVTEN_OTGADEVHNPCHNGEVNT (1 << 18)
380#define DWC3_OEVTEN_OTGADEVSRPDETEVNT (1 << 17)
381#define DWC3_OEVTEN_OTGADEVSESSENDDETEVNT (1 << 16)
382#define DWC3_OEVTEN_OTGBDEVBHOSTENDEVNT (1 << 11)
383#define DWC3_OEVTEN_OTGBDEVHNPCHNGEVNT (1 << 10)
384#define DWC3_OEVTEN_OTGBDEVSESSVLDDETEVNT (1 << 9)
385#define DWC3_OEVTEN_OTGBDEVVBUSCHNGEVNT (1 << 8)
386
387/* OTG OSTS register */
388#define DWC3_OTG_OSTS_OTGSTATE_SHIFT (8)
389#define DWC3_OTG_OSTS_OTGSTATE (0xF << DWC3_OTG_OSTS_OTGSTATE_SHIFT)
390#define DWC3_OTG_OSTS_PERIPHERALSTATE (1 << 4)
391#define DWC3_OTG_OSTS_XHCIPRTPOWER (1 << 3)
392#define DWC3_OTG_OSTS_BSESVALID (1 << 2)
393#define DWC3_OTG_OSTS_VBUSVALID (1 << 1)
394#define DWC3_OTG_OSTS_CONIDSTS (1 << 0)
395
396/* OTG OSTS register */
397#define DWC3_OTG_OCTL_PERIMODE (1 << 6)
398#define DWC3_OTG_OCTL_PRTPWRCTL (1 << 5)
399#define DWC3_OTG_OCTL_HNPREQ (1 << 4)
400#define DWC3_OTG_OCTL_SESREQ (1 << 3)
401#define DWC3_OTG_OCTL_TERMSELDLPULSE (1 << 2)
402#define DWC3_OTG_OCTL_DEVSETHNPEN (1 << 1)
403#define DWC3_OTG_OCTL_HSTSETHNPEN (1 << 0)
404
Felipe Balbi72246da2011-08-19 18:10:58 +0300405/* Structures */
406
Felipe Balbif6bafc62012-02-06 11:04:53 +0200407struct dwc3_trb;
Felipe Balbi72246da2011-08-19 18:10:58 +0300408
409/**
410 * struct dwc3_event_buffer - Software event buffer representation
411 * @list: a list of event buffers
412 * @buf: _THE_ buffer
413 * @length: size of this buffer
414 * @dma: dma_addr_t
415 * @dwc: pointer to DWC controller
416 */
417struct dwc3_event_buffer {
418 void *buf;
419 unsigned length;
420 unsigned int lpos;
421
422 dma_addr_t dma;
423
424 struct dwc3 *dwc;
425};
426
427#define DWC3_EP_FLAG_STALLED (1 << 0)
428#define DWC3_EP_FLAG_WEDGED (1 << 1)
429
430#define DWC3_EP_DIRECTION_TX true
431#define DWC3_EP_DIRECTION_RX false
432
433#define DWC3_TRB_NUM 32
434#define DWC3_TRB_MASK (DWC3_TRB_NUM - 1)
435
436/**
437 * struct dwc3_ep - device side endpoint representation
438 * @endpoint: usb endpoint
439 * @request_list: list of requests for this endpoint
440 * @req_queued: list of requests on this ep which have TRBs setup
441 * @trb_pool: array of transaction buffers
442 * @trb_pool_dma: dma address of @trb_pool
443 * @free_slot: next slot which is going to be used
444 * @busy_slot: first slot which is owned by HW
445 * @desc: usb_endpoint_descriptor pointer
446 * @dwc: pointer to DWC controller
447 * @flags: endpoint flags (wedged, stalled, ...)
448 * @current_trb: index of current used trb
449 * @number: endpoint number (1 - 15)
450 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
Felipe Balbi4959cfc2012-06-06 12:04:13 +0300451 * @resource_index: Resource transfer index
Pratyush Anand73939b02012-05-25 18:54:56 +0530452 * @current_uf: Current uf received through last event parameter
Felipe Balbi72246da2011-08-19 18:10:58 +0300453 * @interval: the intervall on which the ISOC transfer is started
454 * @name: a human readable name e.g. ep1out-bulk
455 * @direction: true for TX, false for RX
Felipe Balbi879631a2011-09-30 10:58:47 +0300456 * @stream_capable: true when streams are enabled
Felipe Balbi72246da2011-08-19 18:10:58 +0300457 */
458struct dwc3_ep {
459 struct usb_ep endpoint;
460 struct list_head request_list;
461 struct list_head req_queued;
462
Felipe Balbif6bafc62012-02-06 11:04:53 +0200463 struct dwc3_trb *trb_pool;
Felipe Balbi72246da2011-08-19 18:10:58 +0300464 dma_addr_t trb_pool_dma;
465 u32 free_slot;
466 u32 busy_slot;
Felipe Balbic90bfae2011-11-29 13:11:21 +0200467 const struct usb_ss_ep_comp_descriptor *comp_desc;
Felipe Balbi72246da2011-08-19 18:10:58 +0300468 struct dwc3 *dwc;
469
470 unsigned flags;
471#define DWC3_EP_ENABLED (1 << 0)
472#define DWC3_EP_STALL (1 << 1)
473#define DWC3_EP_WEDGE (1 << 2)
474#define DWC3_EP_BUSY (1 << 4)
475#define DWC3_EP_PENDING_REQUEST (1 << 5)
Pratyush Anand73939b02012-05-25 18:54:56 +0530476#define DWC3_EP_MISSED_ISOC (1 << 6)
Felipe Balbi72246da2011-08-19 18:10:58 +0300477
Felipe Balbi984f66a2011-08-27 22:26:00 +0300478 /* This last one is specific to EP0 */
479#define DWC3_EP0_DIR_IN (1 << 31)
480
Felipe Balbi72246da2011-08-19 18:10:58 +0300481 unsigned current_trb;
482
483 u8 number;
484 u8 type;
Felipe Balbi4959cfc2012-06-06 12:04:13 +0300485 u8 resource_index;
Pratyush Anand73939b02012-05-25 18:54:56 +0530486 u16 current_uf;
Felipe Balbi72246da2011-08-19 18:10:58 +0300487 u32 interval;
488
489 char name[20];
490
491 unsigned direction:1;
Felipe Balbi879631a2011-09-30 10:58:47 +0300492 unsigned stream_capable:1;
Felipe Balbi72246da2011-08-19 18:10:58 +0300493};
494
495enum dwc3_phy {
496 DWC3_PHY_UNKNOWN = 0,
497 DWC3_PHY_USB3,
498 DWC3_PHY_USB2,
499};
500
Felipe Balbib53c7722011-08-30 15:50:40 +0300501enum dwc3_ep0_next {
502 DWC3_EP0_UNKNOWN = 0,
503 DWC3_EP0_COMPLETE,
Felipe Balbib53c7722011-08-30 15:50:40 +0300504 DWC3_EP0_NRDY_DATA,
505 DWC3_EP0_NRDY_STATUS,
506};
507
Felipe Balbi72246da2011-08-19 18:10:58 +0300508enum dwc3_ep0_state {
509 EP0_UNCONNECTED = 0,
Felipe Balbic7fcdeb2011-08-27 22:28:36 +0300510 EP0_SETUP_PHASE,
511 EP0_DATA_PHASE,
512 EP0_STATUS_PHASE,
Felipe Balbi72246da2011-08-19 18:10:58 +0300513};
514
515enum dwc3_link_state {
516 /* In SuperSpeed */
517 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
518 DWC3_LINK_STATE_U1 = 0x01,
519 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
520 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
521 DWC3_LINK_STATE_SS_DIS = 0x04,
522 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
523 DWC3_LINK_STATE_SS_INACT = 0x06,
524 DWC3_LINK_STATE_POLL = 0x07,
525 DWC3_LINK_STATE_RECOV = 0x08,
526 DWC3_LINK_STATE_HRESET = 0x09,
527 DWC3_LINK_STATE_CMPLY = 0x0a,
528 DWC3_LINK_STATE_LPBK = 0x0b,
Paul Zimmerman394c74f2012-02-15 18:56:58 -0800529 DWC3_LINK_STATE_RESET = 0x0e,
530 DWC3_LINK_STATE_RESUME = 0x0f,
Felipe Balbi72246da2011-08-19 18:10:58 +0300531 DWC3_LINK_STATE_MASK = 0x0f,
532};
533
534enum dwc3_device_state {
535 DWC3_DEFAULT_STATE,
536 DWC3_ADDRESS_STATE,
537 DWC3_CONFIGURED_STATE,
538};
539
Felipe Balbif6bafc62012-02-06 11:04:53 +0200540/* TRB Length, PCM and Status */
541#define DWC3_TRB_SIZE_MASK (0x00ffffff)
542#define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
543#define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
Pratyush Anand8379bef2012-05-21 12:46:26 +0530544#define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
Felipe Balbi72246da2011-08-19 18:10:58 +0300545
Felipe Balbif6bafc62012-02-06 11:04:53 +0200546#define DWC3_TRBSTS_OK 0
547#define DWC3_TRBSTS_MISSED_ISOC 1
548#define DWC3_TRBSTS_SETUP_PENDING 2
Paul Zimmerman394c74f2012-02-15 18:56:58 -0800549#define DWC3_TRB_STS_XFER_IN_PROG 4
Felipe Balbi72246da2011-08-19 18:10:58 +0300550
Felipe Balbif6bafc62012-02-06 11:04:53 +0200551/* TRB Control */
552#define DWC3_TRB_CTRL_HWO (1 << 0)
553#define DWC3_TRB_CTRL_LST (1 << 1)
554#define DWC3_TRB_CTRL_CHN (1 << 2)
555#define DWC3_TRB_CTRL_CSP (1 << 3)
556#define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
557#define DWC3_TRB_CTRL_ISP_IMI (1 << 10)
558#define DWC3_TRB_CTRL_IOC (1 << 11)
559#define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
560
561#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
562#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
563#define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
564#define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
565#define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
566#define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
567#define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
568#define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
Felipe Balbi72246da2011-08-19 18:10:58 +0300569
570/**
Felipe Balbif6bafc62012-02-06 11:04:53 +0200571 * struct dwc3_trb - transfer request block (hw format)
Felipe Balbi72246da2011-08-19 18:10:58 +0300572 * @bpl: DW0-3
573 * @bph: DW4-7
574 * @size: DW8-B
575 * @trl: DWC-F
576 */
Felipe Balbif6bafc62012-02-06 11:04:53 +0200577struct dwc3_trb {
578 u32 bpl;
579 u32 bph;
580 u32 size;
581 u32 ctrl;
Felipe Balbi72246da2011-08-19 18:10:58 +0300582} __packed;
583
Felipe Balbi72246da2011-08-19 18:10:58 +0300584/**
Felipe Balbia3299492011-09-30 10:58:48 +0300585 * dwc3_hwparams - copy of HWPARAMS registers
586 * @hwparams0 - GHWPARAMS0
587 * @hwparams1 - GHWPARAMS1
588 * @hwparams2 - GHWPARAMS2
589 * @hwparams3 - GHWPARAMS3
590 * @hwparams4 - GHWPARAMS4
591 * @hwparams5 - GHWPARAMS5
592 * @hwparams6 - GHWPARAMS6
593 * @hwparams7 - GHWPARAMS7
594 * @hwparams8 - GHWPARAMS8
595 */
596struct dwc3_hwparams {
597 u32 hwparams0;
598 u32 hwparams1;
599 u32 hwparams2;
600 u32 hwparams3;
601 u32 hwparams4;
602 u32 hwparams5;
603 u32 hwparams6;
604 u32 hwparams7;
605 u32 hwparams8;
606};
607
Felipe Balbi0949e992011-10-12 10:44:56 +0300608/* HWPARAMS0 */
609#define DWC3_MODE(n) ((n) & 0x7)
610
611#define DWC3_MODE_DEVICE 0
612#define DWC3_MODE_HOST 1
613#define DWC3_MODE_DRD 2
614#define DWC3_MODE_HUB 3
615
Felipe Balbi457e84b2012-01-18 18:04:09 +0200616#define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
617
Felipe Balbi0949e992011-10-12 10:44:56 +0300618/* HWPARAMS1 */
Felipe Balbi457e84b2012-01-18 18:04:09 +0200619#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
620
621/* HWPARAMS7 */
622#define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
Felipe Balbi9f622b22011-10-12 10:31:04 +0300623
Sebastian Andrzej Siewiore0ce0b02011-11-25 12:03:46 +0100624struct dwc3_request {
625 struct usb_request request;
626 struct list_head list;
627 struct dwc3_ep *dep;
628
629 u8 epnum;
Felipe Balbif6bafc62012-02-06 11:04:53 +0200630 struct dwc3_trb *trb;
Sebastian Andrzej Siewiore0ce0b02011-11-25 12:03:46 +0100631 dma_addr_t trb_dma;
632
633 unsigned direction:1;
634 unsigned mapped:1;
635 unsigned queued:1;
636};
637
Paul Zimmerman394c74f2012-02-15 18:56:58 -0800638/*
639 * struct dwc3_scratchpad_array - hibernation scratchpad array
640 * (format defined by hw)
641 */
642struct dwc3_scratchpad_array {
643 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
644};
645
Felipe Balbia3299492011-09-30 10:58:48 +0300646/**
Felipe Balbi72246da2011-08-19 18:10:58 +0300647 * struct dwc3 - representation of our controller
Felipe Balbi91db07d2011-08-27 01:40:52 +0300648 * @ctrl_req: usb control request which is used for ep0
649 * @ep0_trb: trb which is used for the ctrl_req
Felipe Balbi5812b1c2011-08-27 22:07:53 +0300650 * @ep0_bounce: bounce buffer for ep0
Felipe Balbi91db07d2011-08-27 01:40:52 +0300651 * @setup_buf: used while precessing STD USB requests
652 * @ctrl_req_addr: dma address of ctrl_req
653 * @ep0_trb: dma address of ep0_trb
654 * @ep0_usb_req: dummy req used while handling STD USB requests
Felipe Balbi5812b1c2011-08-27 22:07:53 +0300655 * @ep0_bounce_addr: dma address of ep0_bounce
Felipe Balbi72246da2011-08-19 18:10:58 +0300656 * @lock: for synchronizing
657 * @dev: pointer to our struct device
Felipe Balbid07e8812011-10-12 14:08:26 +0300658 * @xhci: pointer to our xHCI child
Felipe Balbi72246da2011-08-19 18:10:58 +0300659 * @event_buffer_list: a list of event buffers
660 * @gadget: device side representation of the peripheral controller
661 * @gadget_driver: pointer to the gadget driver
662 * @regs: base address for our registers
663 * @regs_size: address space size
664 * @irq: IRQ number
Felipe Balbi9f622b22011-10-12 10:31:04 +0300665 * @num_event_buffers: calculated number of event buffers
Felipe Balbifae2b902011-10-14 13:00:30 +0300666 * @u1u2: only used on revisions <1.83a for workaround
Felipe Balbi6c167fc2011-10-07 22:55:04 +0300667 * @maximum_speed: maximum speed requested (mainly for testing purposes)
Felipe Balbi72246da2011-08-19 18:10:58 +0300668 * @revision: revision register contents
Felipe Balbi0949e992011-10-12 10:44:56 +0300669 * @mode: mode of operation
Felipe Balbi72246da2011-08-19 18:10:58 +0300670 * @is_selfpowered: true when we are selfpowered
671 * @three_stage_setup: set if we perform a three phase setup
Felipe Balbi5812b1c2011-08-27 22:07:53 +0300672 * @ep0_bounced: true when we used bounce buffer
Felipe Balbi55f3fba2011-09-08 18:27:33 +0300673 * @ep0_expect_in: true when we expect a DATA IN transfer
Paul Zimmermanb23c8432011-09-30 10:58:42 +0300674 * @start_config_issued: true when StartConfig command has been issued
Felipe Balbidf62df52011-10-14 15:11:49 +0300675 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
Felipe Balbi457e84b2012-01-18 18:04:09 +0200676 * @needs_fifo_resize: not all users might want fifo resizing, flag it
677 * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes.
Felipe Balbi395c3492012-04-25 10:45:05 +0300678 * @isoch_delay: wValue from Set Isochronous Delay request;
Felipe Balbi9e788d62012-04-24 16:19:49 +0300679 * @u2sel: parameter from Set SEL request.
680 * @u2pel: parameter from Set SEL request.
681 * @u1sel: parameter from Set SEL request.
682 * @u1pel: parameter from Set SEL request.
Felipe Balbib53c7722011-08-30 15:50:40 +0300683 * @ep0_next_event: hold the next expected event
Felipe Balbi72246da2011-08-19 18:10:58 +0300684 * @ep0state: state of endpoint zero
685 * @link_state: link state
686 * @speed: device speed (super, high, full, low)
687 * @mem: points to start of memory which is used for this struct.
Felipe Balbia3299492011-09-30 10:58:48 +0300688 * @hwparams: copy of hwparams registers
Felipe Balbi72246da2011-08-19 18:10:58 +0300689 * @root: debugfs root folder pointer
690 */
691struct dwc3 {
692 struct usb_ctrlrequest *ctrl_req;
Felipe Balbif6bafc62012-02-06 11:04:53 +0200693 struct dwc3_trb *ep0_trb;
Felipe Balbi5812b1c2011-08-27 22:07:53 +0300694 void *ep0_bounce;
Felipe Balbi72246da2011-08-19 18:10:58 +0300695 u8 *setup_buf;
696 dma_addr_t ctrl_req_addr;
697 dma_addr_t ep0_trb_addr;
Felipe Balbi5812b1c2011-08-27 22:07:53 +0300698 dma_addr_t ep0_bounce_addr;
Sebastian Andrzej Siewiore0ce0b02011-11-25 12:03:46 +0100699 struct dwc3_request ep0_usb_req;
Felipe Balbi72246da2011-08-19 18:10:58 +0300700 /* device lock */
701 spinlock_t lock;
702 struct device *dev;
703
Ido Shayevitzcdeef4c2012-05-29 13:17:41 +0200704 struct dwc3_otg *dotg;
Felipe Balbid07e8812011-10-12 14:08:26 +0300705 struct platform_device *xhci;
Ido Shayevitz4a187332012-04-23 14:53:37 +0200706 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
Felipe Balbid07e8812011-10-12 14:08:26 +0300707
Felipe Balbi457d3f22011-10-24 12:03:13 +0300708 struct dwc3_event_buffer **ev_buffs;
Felipe Balbi72246da2011-08-19 18:10:58 +0300709 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
710
711 struct usb_gadget gadget;
712 struct usb_gadget_driver *gadget_driver;
713
714 void __iomem *regs;
715 size_t regs_size;
716
Felipe Balbi9f622b22011-10-12 10:31:04 +0300717 u32 num_event_buffers;
Felipe Balbifae2b902011-10-14 13:00:30 +0300718 u32 u1u2;
Felipe Balbi6c167fc2011-10-07 22:55:04 +0300719 u32 maximum_speed;
Felipe Balbi72246da2011-08-19 18:10:58 +0300720 u32 revision;
Felipe Balbi0949e992011-10-12 10:44:56 +0300721 u32 mode;
Felipe Balbi72246da2011-08-19 18:10:58 +0300722
723#define DWC3_REVISION_173A 0x5533173a
724#define DWC3_REVISION_175A 0x5533175a
725#define DWC3_REVISION_180A 0x5533180a
726#define DWC3_REVISION_183A 0x5533183a
727#define DWC3_REVISION_185A 0x5533185a
Paul Zimmerman394c74f2012-02-15 18:56:58 -0800728#define DWC3_REVISION_187A 0x5533187a
Felipe Balbi72246da2011-08-19 18:10:58 +0300729#define DWC3_REVISION_188A 0x5533188a
730#define DWC3_REVISION_190A 0x5533190a
Paul Zimmerman394c74f2012-02-15 18:56:58 -0800731#define DWC3_REVISION_194A 0x5533194a
Felipe Balbic712cf82012-03-23 12:10:48 +0200732#define DWC3_REVISION_200A 0x5533200a
733#define DWC3_REVISION_202A 0x5533202a
734#define DWC3_REVISION_210A 0x5533210a
735#define DWC3_REVISION_220A 0x5533220a
Pavankumar Kondetife2c0632012-06-12 15:21:13 +0530736#define DWC3_REVISION_230A 0x5533230a
Felipe Balbi72246da2011-08-19 18:10:58 +0300737
738 unsigned is_selfpowered:1;
739 unsigned three_stage_setup:1;
Felipe Balbi5812b1c2011-08-27 22:07:53 +0300740 unsigned ep0_bounced:1;
Felipe Balbi55f3fba2011-09-08 18:27:33 +0300741 unsigned ep0_expect_in:1;
Paul Zimmermanb23c8432011-09-30 10:58:42 +0300742 unsigned start_config_issued:1;
Felipe Balbidf62df52011-10-14 15:11:49 +0300743 unsigned setup_packet_pending:1;
Sebastian Andrzej Siewior5bdb1dc2011-11-02 13:30:45 +0100744 unsigned delayed_status:1;
Felipe Balbi457e84b2012-01-18 18:04:09 +0200745 unsigned needs_fifo_resize:1;
746 unsigned resize_fifos:1;
Felipe Balbi72246da2011-08-19 18:10:58 +0300747
Felipe Balbib53c7722011-08-30 15:50:40 +0300748 enum dwc3_ep0_next ep0_next_event;
Felipe Balbi72246da2011-08-19 18:10:58 +0300749 enum dwc3_ep0_state ep0state;
750 enum dwc3_link_state link_state;
751 enum dwc3_device_state dev_state;
752
Felipe Balbi395c3492012-04-25 10:45:05 +0300753 u16 isoch_delay;
Felipe Balbi9e788d62012-04-24 16:19:49 +0300754 u16 u2sel;
755 u16 u2pel;
756 u8 u1sel;
757 u8 u1pel;
758
Felipe Balbi72246da2011-08-19 18:10:58 +0300759 u8 speed;
Felipe Balbi9e788d62012-04-24 16:19:49 +0300760
Felipe Balbi72246da2011-08-19 18:10:58 +0300761 void *mem;
762
Felipe Balbia3299492011-09-30 10:58:48 +0300763 struct dwc3_hwparams hwparams;
Felipe Balbi72246da2011-08-19 18:10:58 +0300764 struct dentry *root;
Gerard Cauvy3b637362012-02-10 12:21:18 +0200765
766 u8 test_mode;
767 u8 test_mode_nr;
Ido Shayevitzcdeef4c2012-05-29 13:17:41 +0200768
769 /* Indicate if the gadget was powered by the otg driver */
770 bool vbus_active;
771
772 /* Indicate if software connect was issued by the usb_gadget_driver */
773 bool softconnect;
Felipe Balbi72246da2011-08-19 18:10:58 +0300774};
775
776/* -------------------------------------------------------------------------- */
777
Felipe Balbi72246da2011-08-19 18:10:58 +0300778/* -------------------------------------------------------------------------- */
779
780struct dwc3_event_type {
781 u32 is_devspec:1;
782 u32 type:6;
783 u32 reserved8_31:25;
784} __packed;
785
786#define DWC3_DEPEVT_XFERCOMPLETE 0x01
787#define DWC3_DEPEVT_XFERINPROGRESS 0x02
788#define DWC3_DEPEVT_XFERNOTREADY 0x03
789#define DWC3_DEPEVT_RXTXFIFOEVT 0x04
790#define DWC3_DEPEVT_STREAMEVT 0x06
791#define DWC3_DEPEVT_EPCMDCMPLT 0x07
792
793/**
794 * struct dwc3_event_depvt - Device Endpoint Events
795 * @one_bit: indicates this is an endpoint event (not used)
796 * @endpoint_number: number of the endpoint
797 * @endpoint_event: The event we have:
798 * 0x00 - Reserved
799 * 0x01 - XferComplete
800 * 0x02 - XferInProgress
801 * 0x03 - XferNotReady
802 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
803 * 0x05 - Reserved
804 * 0x06 - StreamEvt
805 * 0x07 - EPCmdCmplt
806 * @reserved11_10: Reserved, don't use.
807 * @status: Indicates the status of the event. Refer to databook for
808 * more information.
809 * @parameters: Parameters of the current event. Refer to databook for
810 * more information.
811 */
812struct dwc3_event_depevt {
813 u32 one_bit:1;
814 u32 endpoint_number:5;
815 u32 endpoint_event:4;
816 u32 reserved11_10:2;
817 u32 status:4;
Felipe Balbi40aa41f2012-01-18 17:06:03 +0200818
819/* Within XferNotReady */
820#define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
821
822/* Within XferComplete */
Paul Zimmerman1d046792012-02-15 18:56:56 -0800823#define DEPEVT_STATUS_BUSERR (1 << 0)
824#define DEPEVT_STATUS_SHORT (1 << 1)
825#define DEPEVT_STATUS_IOC (1 << 2)
Felipe Balbi72246da2011-08-19 18:10:58 +0300826#define DEPEVT_STATUS_LST (1 << 3)
Felipe Balbidc137f02011-08-27 22:04:32 +0300827
Felipe Balbi879631a2011-09-30 10:58:47 +0300828/* Stream event only */
829#define DEPEVT_STREAMEVT_FOUND 1
830#define DEPEVT_STREAMEVT_NOTFOUND 2
831
Felipe Balbidc137f02011-08-27 22:04:32 +0300832/* Control-only Status */
Felipe Balbidc137f02011-08-27 22:04:32 +0300833#define DEPEVT_STATUS_CONTROL_DATA 1
834#define DEPEVT_STATUS_CONTROL_STATUS 2
835
Felipe Balbi72246da2011-08-19 18:10:58 +0300836 u32 parameters:16;
837} __packed;
838
839/**
840 * struct dwc3_event_devt - Device Events
841 * @one_bit: indicates this is a non-endpoint event (not used)
842 * @device_event: indicates it's a device event. Should read as 0x00
843 * @type: indicates the type of device event.
844 * 0 - DisconnEvt
845 * 1 - USBRst
846 * 2 - ConnectDone
847 * 3 - ULStChng
848 * 4 - WkUpEvt
849 * 5 - Reserved
850 * 6 - EOPF
851 * 7 - SOF
852 * 8 - Reserved
853 * 9 - ErrticErr
854 * 10 - CmdCmplt
855 * 11 - EvntOverflow
856 * 12 - VndrDevTstRcved
857 * @reserved15_12: Reserved, not used
858 * @event_info: Information about this event
859 * @reserved31_24: Reserved, not used
860 */
861struct dwc3_event_devt {
862 u32 one_bit:1;
863 u32 device_event:7;
864 u32 type:4;
865 u32 reserved15_12:4;
866 u32 event_info:8;
867 u32 reserved31_24:8;
868} __packed;
869
870/**
871 * struct dwc3_event_gevt - Other Core Events
872 * @one_bit: indicates this is a non-endpoint event (not used)
873 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
874 * @phy_port_number: self-explanatory
875 * @reserved31_12: Reserved, not used.
876 */
877struct dwc3_event_gevt {
878 u32 one_bit:1;
879 u32 device_event:7;
880 u32 phy_port_number:4;
881 u32 reserved31_12:20;
882} __packed;
883
884/**
885 * union dwc3_event - representation of Event Buffer contents
886 * @raw: raw 32-bit event
887 * @type: the type of the event
888 * @depevt: Device Endpoint Event
889 * @devt: Device Event
890 * @gevt: Global Event
891 */
892union dwc3_event {
893 u32 raw;
894 struct dwc3_event_type type;
895 struct dwc3_event_depevt depevt;
896 struct dwc3_event_devt devt;
897 struct dwc3_event_gevt gevt;
898};
899
900/*
901 * DWC3 Features to be used as Driver Data
902 */
903
904#define DWC3_HAS_PERIPHERAL BIT(0)
905#define DWC3_HAS_XHCI BIT(1)
906#define DWC3_HAS_OTG BIT(3)
907
Felipe Balbid07e8812011-10-12 14:08:26 +0300908/* prototypes */
Sebastian Andrzej Siewior3140e8c2011-10-31 22:25:40 +0100909void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
Felipe Balbi457e84b2012-01-18 18:04:09 +0200910int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
Sebastian Andrzej Siewior3140e8c2011-10-31 22:25:40 +0100911
Ido Shayevitzcdeef4c2012-05-29 13:17:41 +0200912int dwc3_otg_init(struct dwc3 *dwc);
913void dwc3_otg_exit(struct dwc3 *dwc);
914
Felipe Balbid07e8812011-10-12 14:08:26 +0300915int dwc3_host_init(struct dwc3 *dwc);
916void dwc3_host_exit(struct dwc3 *dwc);
917
Felipe Balbif80b45e2011-10-12 14:15:49 +0300918int dwc3_gadget_init(struct dwc3 *dwc);
919void dwc3_gadget_exit(struct dwc3 *dwc);
920
Manu Gautamf1fceddf2012-10-12 14:02:50 +0530921void dwc3_gadget_restart(struct dwc3 *dwc);
922void dwc3_post_host_reset_core_init(struct dwc3 *dwc);
923
Felipe Balbi8300dd22011-10-18 13:54:01 +0300924extern int dwc3_get_device_id(void);
925extern void dwc3_put_device_id(int id);
926
Felipe Balbi72246da2011-08-19 18:10:58 +0300927#endif /* __DRIVERS_USB_DWC3_CORE_H */