Bhupesh Sharma | 881ff67 | 2011-02-13 22:51:44 -0800 | [diff] [blame] | 1 | /* |
| 2 | * CAN bus driver for Bosch C_CAN controller |
| 3 | * |
| 4 | * Copyright (C) 2010 ST Microelectronics |
| 5 | * Bhupesh Sharma <bhupesh.sharma@st.com> |
| 6 | * |
| 7 | * Borrowed heavily from the C_CAN driver originally written by: |
| 8 | * Copyright (C) 2007 |
| 9 | * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> |
| 10 | * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> |
| 11 | * |
| 12 | * TX and RX NAPI implementation has been borrowed from at91 CAN driver |
| 13 | * written by: |
| 14 | * Copyright |
| 15 | * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> |
| 16 | * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> |
| 17 | * |
| 18 | * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. |
| 19 | * Bosch C_CAN user manual can be obtained from: |
| 20 | * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ |
| 21 | * users_manual_c_can.pdf |
| 22 | * |
| 23 | * This file is licensed under the terms of the GNU General Public |
| 24 | * License version 2. This program is licensed "as is" without any |
| 25 | * warranty of any kind, whether express or implied. |
| 26 | */ |
| 27 | |
| 28 | #include <linux/kernel.h> |
Bhupesh Sharma | 881ff67 | 2011-02-13 22:51:44 -0800 | [diff] [blame] | 29 | #include <linux/module.h> |
| 30 | #include <linux/interrupt.h> |
| 31 | #include <linux/delay.h> |
| 32 | #include <linux/netdevice.h> |
| 33 | #include <linux/if_arp.h> |
| 34 | #include <linux/if_ether.h> |
| 35 | #include <linux/list.h> |
| 36 | #include <linux/delay.h> |
| 37 | #include <linux/io.h> |
| 38 | |
| 39 | #include <linux/can.h> |
| 40 | #include <linux/can/dev.h> |
| 41 | #include <linux/can/error.h> |
| 42 | |
| 43 | #include "c_can.h" |
| 44 | |
| 45 | /* control register */ |
| 46 | #define CONTROL_TEST BIT(7) |
| 47 | #define CONTROL_CCE BIT(6) |
| 48 | #define CONTROL_DISABLE_AR BIT(5) |
| 49 | #define CONTROL_ENABLE_AR (0 << 5) |
| 50 | #define CONTROL_EIE BIT(3) |
| 51 | #define CONTROL_SIE BIT(2) |
| 52 | #define CONTROL_IE BIT(1) |
| 53 | #define CONTROL_INIT BIT(0) |
| 54 | |
| 55 | /* test register */ |
| 56 | #define TEST_RX BIT(7) |
| 57 | #define TEST_TX1 BIT(6) |
| 58 | #define TEST_TX2 BIT(5) |
| 59 | #define TEST_LBACK BIT(4) |
| 60 | #define TEST_SILENT BIT(3) |
| 61 | #define TEST_BASIC BIT(2) |
| 62 | |
| 63 | /* status register */ |
| 64 | #define STATUS_BOFF BIT(7) |
| 65 | #define STATUS_EWARN BIT(6) |
| 66 | #define STATUS_EPASS BIT(5) |
| 67 | #define STATUS_RXOK BIT(4) |
| 68 | #define STATUS_TXOK BIT(3) |
| 69 | |
| 70 | /* error counter register */ |
| 71 | #define ERR_CNT_TEC_MASK 0xff |
| 72 | #define ERR_CNT_TEC_SHIFT 0 |
| 73 | #define ERR_CNT_REC_SHIFT 8 |
| 74 | #define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) |
| 75 | #define ERR_CNT_RP_SHIFT 15 |
| 76 | #define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) |
| 77 | |
| 78 | /* bit-timing register */ |
| 79 | #define BTR_BRP_MASK 0x3f |
| 80 | #define BTR_BRP_SHIFT 0 |
| 81 | #define BTR_SJW_SHIFT 6 |
| 82 | #define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) |
| 83 | #define BTR_TSEG1_SHIFT 8 |
| 84 | #define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) |
| 85 | #define BTR_TSEG2_SHIFT 12 |
| 86 | #define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) |
| 87 | |
| 88 | /* brp extension register */ |
| 89 | #define BRP_EXT_BRPE_MASK 0x0f |
| 90 | #define BRP_EXT_BRPE_SHIFT 0 |
| 91 | |
| 92 | /* IFx command request */ |
| 93 | #define IF_COMR_BUSY BIT(15) |
| 94 | |
| 95 | /* IFx command mask */ |
| 96 | #define IF_COMM_WR BIT(7) |
| 97 | #define IF_COMM_MASK BIT(6) |
| 98 | #define IF_COMM_ARB BIT(5) |
| 99 | #define IF_COMM_CONTROL BIT(4) |
| 100 | #define IF_COMM_CLR_INT_PND BIT(3) |
| 101 | #define IF_COMM_TXRQST BIT(2) |
| 102 | #define IF_COMM_DATAA BIT(1) |
| 103 | #define IF_COMM_DATAB BIT(0) |
| 104 | #define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \ |
| 105 | IF_COMM_CONTROL | IF_COMM_TXRQST | \ |
| 106 | IF_COMM_DATAA | IF_COMM_DATAB) |
| 107 | |
| 108 | /* IFx arbitration */ |
| 109 | #define IF_ARB_MSGVAL BIT(15) |
| 110 | #define IF_ARB_MSGXTD BIT(14) |
| 111 | #define IF_ARB_TRANSMIT BIT(13) |
| 112 | |
| 113 | /* IFx message control */ |
| 114 | #define IF_MCONT_NEWDAT BIT(15) |
| 115 | #define IF_MCONT_MSGLST BIT(14) |
| 116 | #define IF_MCONT_CLR_MSGLST (0 << 14) |
| 117 | #define IF_MCONT_INTPND BIT(13) |
| 118 | #define IF_MCONT_UMASK BIT(12) |
| 119 | #define IF_MCONT_TXIE BIT(11) |
| 120 | #define IF_MCONT_RXIE BIT(10) |
| 121 | #define IF_MCONT_RMTEN BIT(9) |
| 122 | #define IF_MCONT_TXRQST BIT(8) |
| 123 | #define IF_MCONT_EOB BIT(7) |
| 124 | #define IF_MCONT_DLC_MASK 0xf |
| 125 | |
| 126 | /* |
| 127 | * IFx register masks: |
| 128 | * allow easy operation on 16-bit registers when the |
| 129 | * argument is 32-bit instead |
| 130 | */ |
| 131 | #define IFX_WRITE_LOW_16BIT(x) ((x) & 0xFFFF) |
| 132 | #define IFX_WRITE_HIGH_16BIT(x) (((x) & 0xFFFF0000) >> 16) |
| 133 | |
| 134 | /* message object split */ |
| 135 | #define C_CAN_NO_OF_OBJECTS 32 |
| 136 | #define C_CAN_MSG_OBJ_RX_NUM 16 |
| 137 | #define C_CAN_MSG_OBJ_TX_NUM 16 |
| 138 | |
| 139 | #define C_CAN_MSG_OBJ_RX_FIRST 1 |
| 140 | #define C_CAN_MSG_OBJ_RX_LAST (C_CAN_MSG_OBJ_RX_FIRST + \ |
| 141 | C_CAN_MSG_OBJ_RX_NUM - 1) |
| 142 | |
| 143 | #define C_CAN_MSG_OBJ_TX_FIRST (C_CAN_MSG_OBJ_RX_LAST + 1) |
| 144 | #define C_CAN_MSG_OBJ_TX_LAST (C_CAN_MSG_OBJ_TX_FIRST + \ |
| 145 | C_CAN_MSG_OBJ_TX_NUM - 1) |
| 146 | |
| 147 | #define C_CAN_MSG_OBJ_RX_SPLIT 9 |
| 148 | #define C_CAN_MSG_RX_LOW_LAST (C_CAN_MSG_OBJ_RX_SPLIT - 1) |
| 149 | |
| 150 | #define C_CAN_NEXT_MSG_OBJ_MASK (C_CAN_MSG_OBJ_TX_NUM - 1) |
| 151 | #define RECEIVE_OBJECT_BITS 0x0000ffff |
| 152 | |
| 153 | /* status interrupt */ |
| 154 | #define STATUS_INTERRUPT 0x8000 |
| 155 | |
| 156 | /* global interrupt masks */ |
| 157 | #define ENABLE_ALL_INTERRUPTS 1 |
| 158 | #define DISABLE_ALL_INTERRUPTS 0 |
| 159 | |
| 160 | /* minimum timeout for checking BUSY status */ |
| 161 | #define MIN_TIMEOUT_VALUE 6 |
| 162 | |
| 163 | /* napi related */ |
| 164 | #define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM |
| 165 | |
| 166 | /* c_can lec values */ |
| 167 | enum c_can_lec_type { |
| 168 | LEC_NO_ERROR = 0, |
| 169 | LEC_STUFF_ERROR, |
| 170 | LEC_FORM_ERROR, |
| 171 | LEC_ACK_ERROR, |
| 172 | LEC_BIT1_ERROR, |
| 173 | LEC_BIT0_ERROR, |
| 174 | LEC_CRC_ERROR, |
| 175 | LEC_UNUSED, |
| 176 | }; |
| 177 | |
| 178 | /* |
| 179 | * c_can error types: |
| 180 | * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported |
| 181 | */ |
| 182 | enum c_can_bus_error_types { |
| 183 | C_CAN_NO_ERROR = 0, |
| 184 | C_CAN_BUS_OFF, |
| 185 | C_CAN_ERROR_WARNING, |
| 186 | C_CAN_ERROR_PASSIVE, |
| 187 | }; |
| 188 | |
| 189 | static struct can_bittiming_const c_can_bittiming_const = { |
| 190 | .name = KBUILD_MODNAME, |
| 191 | .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ |
| 192 | .tseg1_max = 16, |
| 193 | .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ |
| 194 | .tseg2_max = 8, |
| 195 | .sjw_max = 4, |
| 196 | .brp_min = 1, |
| 197 | .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ |
| 198 | .brp_inc = 1, |
| 199 | }; |
| 200 | |
| 201 | static inline int get_tx_next_msg_obj(const struct c_can_priv *priv) |
| 202 | { |
| 203 | return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) + |
| 204 | C_CAN_MSG_OBJ_TX_FIRST; |
| 205 | } |
| 206 | |
| 207 | static inline int get_tx_echo_msg_obj(const struct c_can_priv *priv) |
| 208 | { |
| 209 | return (priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) + |
| 210 | C_CAN_MSG_OBJ_TX_FIRST; |
| 211 | } |
| 212 | |
| 213 | static u32 c_can_read_reg32(struct c_can_priv *priv, void *reg) |
| 214 | { |
| 215 | u32 val = priv->read_reg(priv, reg); |
| 216 | val |= ((u32) priv->read_reg(priv, reg + 2)) << 16; |
| 217 | return val; |
| 218 | } |
| 219 | |
| 220 | static void c_can_enable_all_interrupts(struct c_can_priv *priv, |
| 221 | int enable) |
| 222 | { |
| 223 | unsigned int cntrl_save = priv->read_reg(priv, |
| 224 | &priv->regs->control); |
| 225 | |
| 226 | if (enable) |
| 227 | cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE); |
| 228 | else |
| 229 | cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE); |
| 230 | |
| 231 | priv->write_reg(priv, &priv->regs->control, cntrl_save); |
| 232 | } |
| 233 | |
| 234 | static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface) |
| 235 | { |
| 236 | int count = MIN_TIMEOUT_VALUE; |
| 237 | |
| 238 | while (count && priv->read_reg(priv, |
| 239 | &priv->regs->ifregs[iface].com_req) & |
| 240 | IF_COMR_BUSY) { |
| 241 | count--; |
| 242 | udelay(1); |
| 243 | } |
| 244 | |
| 245 | if (!count) |
| 246 | return 1; |
| 247 | |
| 248 | return 0; |
| 249 | } |
| 250 | |
| 251 | static inline void c_can_object_get(struct net_device *dev, |
| 252 | int iface, int objno, int mask) |
| 253 | { |
| 254 | struct c_can_priv *priv = netdev_priv(dev); |
| 255 | |
| 256 | /* |
| 257 | * As per specs, after writting the message object number in the |
| 258 | * IF command request register the transfer b/w interface |
| 259 | * register and message RAM must be complete in 6 CAN-CLK |
| 260 | * period. |
| 261 | */ |
| 262 | priv->write_reg(priv, &priv->regs->ifregs[iface].com_mask, |
| 263 | IFX_WRITE_LOW_16BIT(mask)); |
| 264 | priv->write_reg(priv, &priv->regs->ifregs[iface].com_req, |
| 265 | IFX_WRITE_LOW_16BIT(objno)); |
| 266 | |
| 267 | if (c_can_msg_obj_is_busy(priv, iface)) |
| 268 | netdev_err(dev, "timed out in object get\n"); |
| 269 | } |
| 270 | |
| 271 | static inline void c_can_object_put(struct net_device *dev, |
| 272 | int iface, int objno, int mask) |
| 273 | { |
| 274 | struct c_can_priv *priv = netdev_priv(dev); |
| 275 | |
| 276 | /* |
| 277 | * As per specs, after writting the message object number in the |
| 278 | * IF command request register the transfer b/w interface |
| 279 | * register and message RAM must be complete in 6 CAN-CLK |
| 280 | * period. |
| 281 | */ |
| 282 | priv->write_reg(priv, &priv->regs->ifregs[iface].com_mask, |
| 283 | (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask))); |
| 284 | priv->write_reg(priv, &priv->regs->ifregs[iface].com_req, |
| 285 | IFX_WRITE_LOW_16BIT(objno)); |
| 286 | |
| 287 | if (c_can_msg_obj_is_busy(priv, iface)) |
| 288 | netdev_err(dev, "timed out in object put\n"); |
| 289 | } |
| 290 | |
| 291 | static void c_can_write_msg_object(struct net_device *dev, |
| 292 | int iface, struct can_frame *frame, int objno) |
| 293 | { |
| 294 | int i; |
| 295 | u16 flags = 0; |
| 296 | unsigned int id; |
| 297 | struct c_can_priv *priv = netdev_priv(dev); |
| 298 | |
| 299 | if (!(frame->can_id & CAN_RTR_FLAG)) |
| 300 | flags |= IF_ARB_TRANSMIT; |
| 301 | |
| 302 | if (frame->can_id & CAN_EFF_FLAG) { |
| 303 | id = frame->can_id & CAN_EFF_MASK; |
| 304 | flags |= IF_ARB_MSGXTD; |
| 305 | } else |
| 306 | id = ((frame->can_id & CAN_SFF_MASK) << 18); |
| 307 | |
| 308 | flags |= IF_ARB_MSGVAL; |
| 309 | |
| 310 | priv->write_reg(priv, &priv->regs->ifregs[iface].arb1, |
| 311 | IFX_WRITE_LOW_16BIT(id)); |
| 312 | priv->write_reg(priv, &priv->regs->ifregs[iface].arb2, flags | |
| 313 | IFX_WRITE_HIGH_16BIT(id)); |
| 314 | |
| 315 | for (i = 0; i < frame->can_dlc; i += 2) { |
| 316 | priv->write_reg(priv, &priv->regs->ifregs[iface].data[i / 2], |
| 317 | frame->data[i] | (frame->data[i + 1] << 8)); |
| 318 | } |
| 319 | |
| 320 | /* enable interrupt for this message object */ |
| 321 | priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl, |
| 322 | IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB | |
| 323 | frame->can_dlc); |
| 324 | c_can_object_put(dev, iface, objno, IF_COMM_ALL); |
| 325 | } |
| 326 | |
| 327 | static inline void c_can_mark_rx_msg_obj(struct net_device *dev, |
| 328 | int iface, int ctrl_mask, |
| 329 | int obj) |
| 330 | { |
| 331 | struct c_can_priv *priv = netdev_priv(dev); |
| 332 | |
| 333 | priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl, |
| 334 | ctrl_mask & ~(IF_MCONT_MSGLST | IF_MCONT_INTPND)); |
| 335 | c_can_object_put(dev, iface, obj, IF_COMM_CONTROL); |
| 336 | |
| 337 | } |
| 338 | |
| 339 | static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev, |
| 340 | int iface, |
| 341 | int ctrl_mask) |
| 342 | { |
| 343 | int i; |
| 344 | struct c_can_priv *priv = netdev_priv(dev); |
| 345 | |
| 346 | for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) { |
| 347 | priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl, |
| 348 | ctrl_mask & ~(IF_MCONT_MSGLST | |
| 349 | IF_MCONT_INTPND | IF_MCONT_NEWDAT)); |
| 350 | c_can_object_put(dev, iface, i, IF_COMM_CONTROL); |
| 351 | } |
| 352 | } |
| 353 | |
| 354 | static inline void c_can_activate_rx_msg_obj(struct net_device *dev, |
| 355 | int iface, int ctrl_mask, |
| 356 | int obj) |
| 357 | { |
| 358 | struct c_can_priv *priv = netdev_priv(dev); |
| 359 | |
| 360 | priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl, |
| 361 | ctrl_mask & ~(IF_MCONT_MSGLST | |
| 362 | IF_MCONT_INTPND | IF_MCONT_NEWDAT)); |
| 363 | c_can_object_put(dev, iface, obj, IF_COMM_CONTROL); |
| 364 | } |
| 365 | |
| 366 | static void c_can_handle_lost_msg_obj(struct net_device *dev, |
| 367 | int iface, int objno) |
| 368 | { |
| 369 | struct c_can_priv *priv = netdev_priv(dev); |
| 370 | struct net_device_stats *stats = &dev->stats; |
| 371 | struct sk_buff *skb; |
| 372 | struct can_frame *frame; |
| 373 | |
| 374 | netdev_err(dev, "msg lost in buffer %d\n", objno); |
| 375 | |
| 376 | c_can_object_get(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); |
| 377 | |
| 378 | priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl, |
| 379 | IF_MCONT_CLR_MSGLST); |
| 380 | |
| 381 | c_can_object_put(dev, 0, objno, IF_COMM_CONTROL); |
| 382 | |
| 383 | /* create an error msg */ |
| 384 | skb = alloc_can_err_skb(dev, &frame); |
| 385 | if (unlikely(!skb)) |
| 386 | return; |
| 387 | |
| 388 | frame->can_id |= CAN_ERR_CRTL; |
| 389 | frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; |
| 390 | stats->rx_errors++; |
| 391 | stats->rx_over_errors++; |
| 392 | |
| 393 | netif_receive_skb(skb); |
| 394 | } |
| 395 | |
| 396 | static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl) |
| 397 | { |
| 398 | u16 flags, data; |
| 399 | int i; |
| 400 | unsigned int val; |
| 401 | struct c_can_priv *priv = netdev_priv(dev); |
| 402 | struct net_device_stats *stats = &dev->stats; |
| 403 | struct sk_buff *skb; |
| 404 | struct can_frame *frame; |
| 405 | |
| 406 | skb = alloc_can_skb(dev, &frame); |
| 407 | if (!skb) { |
| 408 | stats->rx_dropped++; |
| 409 | return -ENOMEM; |
| 410 | } |
| 411 | |
| 412 | frame->can_dlc = get_can_dlc(ctrl & 0x0F); |
| 413 | |
| 414 | flags = priv->read_reg(priv, &priv->regs->ifregs[iface].arb2); |
| 415 | val = priv->read_reg(priv, &priv->regs->ifregs[iface].arb1) | |
| 416 | (flags << 16); |
| 417 | |
| 418 | if (flags & IF_ARB_MSGXTD) |
| 419 | frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG; |
| 420 | else |
| 421 | frame->can_id = (val >> 18) & CAN_SFF_MASK; |
| 422 | |
| 423 | if (flags & IF_ARB_TRANSMIT) |
| 424 | frame->can_id |= CAN_RTR_FLAG; |
| 425 | else { |
| 426 | for (i = 0; i < frame->can_dlc; i += 2) { |
| 427 | data = priv->read_reg(priv, |
| 428 | &priv->regs->ifregs[iface].data[i / 2]); |
| 429 | frame->data[i] = data; |
| 430 | frame->data[i + 1] = data >> 8; |
| 431 | } |
| 432 | } |
| 433 | |
| 434 | netif_receive_skb(skb); |
| 435 | |
| 436 | stats->rx_packets++; |
| 437 | stats->rx_bytes += frame->can_dlc; |
| 438 | |
| 439 | return 0; |
| 440 | } |
| 441 | |
| 442 | static void c_can_setup_receive_object(struct net_device *dev, int iface, |
| 443 | int objno, unsigned int mask, |
| 444 | unsigned int id, unsigned int mcont) |
| 445 | { |
| 446 | struct c_can_priv *priv = netdev_priv(dev); |
| 447 | |
| 448 | priv->write_reg(priv, &priv->regs->ifregs[iface].mask1, |
| 449 | IFX_WRITE_LOW_16BIT(mask)); |
| 450 | priv->write_reg(priv, &priv->regs->ifregs[iface].mask2, |
| 451 | IFX_WRITE_HIGH_16BIT(mask)); |
| 452 | |
| 453 | priv->write_reg(priv, &priv->regs->ifregs[iface].arb1, |
| 454 | IFX_WRITE_LOW_16BIT(id)); |
| 455 | priv->write_reg(priv, &priv->regs->ifregs[iface].arb2, |
| 456 | (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id))); |
| 457 | |
| 458 | priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl, mcont); |
| 459 | c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); |
| 460 | |
| 461 | netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, |
| 462 | c_can_read_reg32(priv, &priv->regs->msgval1)); |
| 463 | } |
| 464 | |
| 465 | static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno) |
| 466 | { |
| 467 | struct c_can_priv *priv = netdev_priv(dev); |
| 468 | |
| 469 | priv->write_reg(priv, &priv->regs->ifregs[iface].arb1, 0); |
| 470 | priv->write_reg(priv, &priv->regs->ifregs[iface].arb2, 0); |
| 471 | priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl, 0); |
| 472 | |
| 473 | c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL); |
| 474 | |
| 475 | netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, |
| 476 | c_can_read_reg32(priv, &priv->regs->msgval1)); |
| 477 | } |
| 478 | |
| 479 | static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno) |
| 480 | { |
| 481 | int val = c_can_read_reg32(priv, &priv->regs->txrqst1); |
| 482 | |
| 483 | /* |
| 484 | * as transmission request register's bit n-1 corresponds to |
| 485 | * message object n, we need to handle the same properly. |
| 486 | */ |
| 487 | if (val & (1 << (objno - 1))) |
| 488 | return 1; |
| 489 | |
| 490 | return 0; |
| 491 | } |
| 492 | |
| 493 | static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, |
| 494 | struct net_device *dev) |
| 495 | { |
| 496 | u32 msg_obj_no; |
| 497 | struct c_can_priv *priv = netdev_priv(dev); |
| 498 | struct can_frame *frame = (struct can_frame *)skb->data; |
| 499 | |
| 500 | if (can_dropped_invalid_skb(dev, skb)) |
| 501 | return NETDEV_TX_OK; |
| 502 | |
| 503 | msg_obj_no = get_tx_next_msg_obj(priv); |
| 504 | |
| 505 | /* prepare message object for transmission */ |
| 506 | c_can_write_msg_object(dev, 0, frame, msg_obj_no); |
| 507 | can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); |
| 508 | |
| 509 | /* |
| 510 | * we have to stop the queue in case of a wrap around or |
| 511 | * if the next TX message object is still in use |
| 512 | */ |
| 513 | priv->tx_next++; |
| 514 | if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) || |
| 515 | (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0) |
| 516 | netif_stop_queue(dev); |
| 517 | |
| 518 | return NETDEV_TX_OK; |
| 519 | } |
| 520 | |
| 521 | static int c_can_set_bittiming(struct net_device *dev) |
| 522 | { |
| 523 | unsigned int reg_btr, reg_brpe, ctrl_save; |
| 524 | u8 brp, brpe, sjw, tseg1, tseg2; |
| 525 | u32 ten_bit_brp; |
| 526 | struct c_can_priv *priv = netdev_priv(dev); |
| 527 | const struct can_bittiming *bt = &priv->can.bittiming; |
| 528 | |
| 529 | /* c_can provides a 6-bit brp and 4-bit brpe fields */ |
| 530 | ten_bit_brp = bt->brp - 1; |
| 531 | brp = ten_bit_brp & BTR_BRP_MASK; |
| 532 | brpe = ten_bit_brp >> 6; |
| 533 | |
| 534 | sjw = bt->sjw - 1; |
| 535 | tseg1 = bt->prop_seg + bt->phase_seg1 - 1; |
| 536 | tseg2 = bt->phase_seg2 - 1; |
| 537 | reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | |
| 538 | (tseg2 << BTR_TSEG2_SHIFT); |
| 539 | reg_brpe = brpe & BRP_EXT_BRPE_MASK; |
| 540 | |
| 541 | netdev_info(dev, |
| 542 | "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); |
| 543 | |
| 544 | ctrl_save = priv->read_reg(priv, &priv->regs->control); |
| 545 | priv->write_reg(priv, &priv->regs->control, |
| 546 | ctrl_save | CONTROL_CCE | CONTROL_INIT); |
| 547 | priv->write_reg(priv, &priv->regs->btr, reg_btr); |
| 548 | priv->write_reg(priv, &priv->regs->brp_ext, reg_brpe); |
| 549 | priv->write_reg(priv, &priv->regs->control, ctrl_save); |
| 550 | |
| 551 | return 0; |
| 552 | } |
| 553 | |
| 554 | /* |
| 555 | * Configure C_CAN message objects for Tx and Rx purposes: |
| 556 | * C_CAN provides a total of 32 message objects that can be configured |
| 557 | * either for Tx or Rx purposes. Here the first 16 message objects are used as |
| 558 | * a reception FIFO. The end of reception FIFO is signified by the EoB bit |
| 559 | * being SET. The remaining 16 message objects are kept aside for Tx purposes. |
| 560 | * See user guide document for further details on configuring message |
| 561 | * objects. |
| 562 | */ |
| 563 | static void c_can_configure_msg_objects(struct net_device *dev) |
| 564 | { |
| 565 | int i; |
| 566 | |
| 567 | /* first invalidate all message objects */ |
| 568 | for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++) |
| 569 | c_can_inval_msg_object(dev, 0, i); |
| 570 | |
| 571 | /* setup receive message objects */ |
| 572 | for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++) |
| 573 | c_can_setup_receive_object(dev, 0, i, 0, 0, |
| 574 | (IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB); |
| 575 | |
| 576 | c_can_setup_receive_object(dev, 0, C_CAN_MSG_OBJ_RX_LAST, 0, 0, |
| 577 | IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK); |
| 578 | } |
| 579 | |
| 580 | /* |
| 581 | * Configure C_CAN chip: |
| 582 | * - enable/disable auto-retransmission |
| 583 | * - set operating mode |
| 584 | * - configure message objects |
| 585 | */ |
| 586 | static void c_can_chip_config(struct net_device *dev) |
| 587 | { |
| 588 | struct c_can_priv *priv = netdev_priv(dev); |
| 589 | |
Marc Kleine-Budde | ee6f098 | 2011-03-24 02:34:32 +0000 | [diff] [blame] | 590 | /* enable automatic retransmission */ |
| 591 | priv->write_reg(priv, &priv->regs->control, |
| 592 | CONTROL_ENABLE_AR); |
Bhupesh Sharma | 881ff67 | 2011-02-13 22:51:44 -0800 | [diff] [blame] | 593 | |
| 594 | if (priv->can.ctrlmode & (CAN_CTRLMODE_LISTENONLY & |
| 595 | CAN_CTRLMODE_LOOPBACK)) { |
| 596 | /* loopback + silent mode : useful for hot self-test */ |
| 597 | priv->write_reg(priv, &priv->regs->control, CONTROL_EIE | |
| 598 | CONTROL_SIE | CONTROL_IE | CONTROL_TEST); |
| 599 | priv->write_reg(priv, &priv->regs->test, |
| 600 | TEST_LBACK | TEST_SILENT); |
| 601 | } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { |
| 602 | /* loopback mode : useful for self-test function */ |
| 603 | priv->write_reg(priv, &priv->regs->control, CONTROL_EIE | |
| 604 | CONTROL_SIE | CONTROL_IE | CONTROL_TEST); |
| 605 | priv->write_reg(priv, &priv->regs->test, TEST_LBACK); |
| 606 | } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { |
| 607 | /* silent mode : bus-monitoring mode */ |
| 608 | priv->write_reg(priv, &priv->regs->control, CONTROL_EIE | |
| 609 | CONTROL_SIE | CONTROL_IE | CONTROL_TEST); |
| 610 | priv->write_reg(priv, &priv->regs->test, TEST_SILENT); |
| 611 | } else |
| 612 | /* normal mode*/ |
| 613 | priv->write_reg(priv, &priv->regs->control, |
| 614 | CONTROL_EIE | CONTROL_SIE | CONTROL_IE); |
| 615 | |
| 616 | /* configure message objects */ |
| 617 | c_can_configure_msg_objects(dev); |
| 618 | |
| 619 | /* set a `lec` value so that we can check for updates later */ |
| 620 | priv->write_reg(priv, &priv->regs->status, LEC_UNUSED); |
| 621 | |
| 622 | /* set bittiming params */ |
| 623 | c_can_set_bittiming(dev); |
| 624 | } |
| 625 | |
| 626 | static void c_can_start(struct net_device *dev) |
| 627 | { |
| 628 | struct c_can_priv *priv = netdev_priv(dev); |
| 629 | |
Bhupesh Sharma | 881ff67 | 2011-02-13 22:51:44 -0800 | [diff] [blame] | 630 | /* basic c_can configuration */ |
| 631 | c_can_chip_config(dev); |
| 632 | |
| 633 | priv->can.state = CAN_STATE_ERROR_ACTIVE; |
| 634 | |
| 635 | /* reset tx helper pointers */ |
| 636 | priv->tx_next = priv->tx_echo = 0; |
Jan Altenberg | 4f2d56c | 2011-03-21 18:19:26 -0700 | [diff] [blame] | 637 | |
| 638 | /* enable status change, error and module interrupts */ |
| 639 | c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); |
Bhupesh Sharma | 881ff67 | 2011-02-13 22:51:44 -0800 | [diff] [blame] | 640 | } |
| 641 | |
| 642 | static void c_can_stop(struct net_device *dev) |
| 643 | { |
| 644 | struct c_can_priv *priv = netdev_priv(dev); |
| 645 | |
| 646 | /* disable all interrupts */ |
| 647 | c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); |
| 648 | |
| 649 | /* set the state as STOPPED */ |
| 650 | priv->can.state = CAN_STATE_STOPPED; |
| 651 | } |
| 652 | |
| 653 | static int c_can_set_mode(struct net_device *dev, enum can_mode mode) |
| 654 | { |
| 655 | switch (mode) { |
| 656 | case CAN_MODE_START: |
| 657 | c_can_start(dev); |
| 658 | netif_wake_queue(dev); |
| 659 | break; |
| 660 | default: |
| 661 | return -EOPNOTSUPP; |
| 662 | } |
| 663 | |
| 664 | return 0; |
| 665 | } |
| 666 | |
| 667 | static int c_can_get_berr_counter(const struct net_device *dev, |
| 668 | struct can_berr_counter *bec) |
| 669 | { |
| 670 | unsigned int reg_err_counter; |
| 671 | struct c_can_priv *priv = netdev_priv(dev); |
| 672 | |
| 673 | reg_err_counter = priv->read_reg(priv, &priv->regs->err_cnt); |
| 674 | bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> |
| 675 | ERR_CNT_REC_SHIFT; |
| 676 | bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; |
| 677 | |
| 678 | return 0; |
| 679 | } |
| 680 | |
| 681 | /* |
| 682 | * theory of operation: |
| 683 | * |
| 684 | * priv->tx_echo holds the number of the oldest can_frame put for |
| 685 | * transmission into the hardware, but not yet ACKed by the CAN tx |
| 686 | * complete IRQ. |
| 687 | * |
| 688 | * We iterate from priv->tx_echo to priv->tx_next and check if the |
| 689 | * packet has been transmitted, echo it back to the CAN framework. |
| 690 | * If we discover a not yet transmitted package, stop looking for more. |
| 691 | */ |
| 692 | static void c_can_do_tx(struct net_device *dev) |
| 693 | { |
| 694 | u32 val; |
| 695 | u32 msg_obj_no; |
| 696 | struct c_can_priv *priv = netdev_priv(dev); |
| 697 | struct net_device_stats *stats = &dev->stats; |
| 698 | |
| 699 | for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { |
| 700 | msg_obj_no = get_tx_echo_msg_obj(priv); |
Bhupesh Sharma | 881ff67 | 2011-02-13 22:51:44 -0800 | [diff] [blame] | 701 | val = c_can_read_reg32(priv, &priv->regs->txrqst1); |
| 702 | if (!(val & (1 << msg_obj_no))) { |
| 703 | can_get_echo_skb(dev, |
| 704 | msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); |
| 705 | stats->tx_bytes += priv->read_reg(priv, |
| 706 | &priv->regs->ifregs[0].msg_cntrl) |
| 707 | & IF_MCONT_DLC_MASK; |
| 708 | stats->tx_packets++; |
Jan Altenberg | dc760b3 | 2011-03-27 18:24:10 -0700 | [diff] [blame] | 709 | c_can_inval_msg_object(dev, 0, msg_obj_no); |
Bhupesh Sharma | 881ff67 | 2011-02-13 22:51:44 -0800 | [diff] [blame] | 710 | } |
| 711 | } |
| 712 | |
| 713 | /* restart queue if wrap-up or if queue stalled on last pkt */ |
| 714 | if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) || |
| 715 | ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0)) |
| 716 | netif_wake_queue(dev); |
| 717 | } |
| 718 | |
| 719 | /* |
| 720 | * theory of operation: |
| 721 | * |
| 722 | * c_can core saves a received CAN message into the first free message |
| 723 | * object it finds free (starting with the lowest). Bits NEWDAT and |
| 724 | * INTPND are set for this message object indicating that a new message |
| 725 | * has arrived. To work-around this issue, we keep two groups of message |
| 726 | * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT. |
| 727 | * |
| 728 | * To ensure in-order frame reception we use the following |
| 729 | * approach while re-activating a message object to receive further |
| 730 | * frames: |
| 731 | * - if the current message object number is lower than |
| 732 | * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing |
| 733 | * the INTPND bit. |
| 734 | * - if the current message object number is equal to |
| 735 | * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower |
| 736 | * receive message objects. |
| 737 | * - if the current message object number is greater than |
| 738 | * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of |
| 739 | * only this message object. |
| 740 | */ |
| 741 | static int c_can_do_rx_poll(struct net_device *dev, int quota) |
| 742 | { |
| 743 | u32 num_rx_pkts = 0; |
| 744 | unsigned int msg_obj, msg_ctrl_save; |
| 745 | struct c_can_priv *priv = netdev_priv(dev); |
| 746 | u32 val = c_can_read_reg32(priv, &priv->regs->intpnd1); |
| 747 | |
| 748 | for (msg_obj = C_CAN_MSG_OBJ_RX_FIRST; |
| 749 | msg_obj <= C_CAN_MSG_OBJ_RX_LAST && quota > 0; |
| 750 | val = c_can_read_reg32(priv, &priv->regs->intpnd1), |
| 751 | msg_obj++) { |
| 752 | /* |
| 753 | * as interrupt pending register's bit n-1 corresponds to |
| 754 | * message object n, we need to handle the same properly. |
| 755 | */ |
| 756 | if (val & (1 << (msg_obj - 1))) { |
| 757 | c_can_object_get(dev, 0, msg_obj, IF_COMM_ALL & |
| 758 | ~IF_COMM_TXRQST); |
| 759 | msg_ctrl_save = priv->read_reg(priv, |
| 760 | &priv->regs->ifregs[0].msg_cntrl); |
| 761 | |
| 762 | if (msg_ctrl_save & IF_MCONT_EOB) |
| 763 | return num_rx_pkts; |
| 764 | |
| 765 | if (msg_ctrl_save & IF_MCONT_MSGLST) { |
| 766 | c_can_handle_lost_msg_obj(dev, 0, msg_obj); |
| 767 | num_rx_pkts++; |
| 768 | quota--; |
| 769 | continue; |
| 770 | } |
| 771 | |
| 772 | if (!(msg_ctrl_save & IF_MCONT_NEWDAT)) |
| 773 | continue; |
| 774 | |
| 775 | /* read the data from the message object */ |
| 776 | c_can_read_msg_object(dev, 0, msg_ctrl_save); |
| 777 | |
| 778 | if (msg_obj < C_CAN_MSG_RX_LOW_LAST) |
| 779 | c_can_mark_rx_msg_obj(dev, 0, |
| 780 | msg_ctrl_save, msg_obj); |
| 781 | else if (msg_obj > C_CAN_MSG_RX_LOW_LAST) |
| 782 | /* activate this msg obj */ |
| 783 | c_can_activate_rx_msg_obj(dev, 0, |
| 784 | msg_ctrl_save, msg_obj); |
| 785 | else if (msg_obj == C_CAN_MSG_RX_LOW_LAST) |
| 786 | /* activate all lower message objects */ |
| 787 | c_can_activate_all_lower_rx_msg_obj(dev, |
| 788 | 0, msg_ctrl_save); |
| 789 | |
| 790 | num_rx_pkts++; |
| 791 | quota--; |
| 792 | } |
| 793 | } |
| 794 | |
| 795 | return num_rx_pkts; |
| 796 | } |
| 797 | |
| 798 | static inline int c_can_has_and_handle_berr(struct c_can_priv *priv) |
| 799 | { |
| 800 | return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && |
| 801 | (priv->current_status & LEC_UNUSED); |
| 802 | } |
| 803 | |
| 804 | static int c_can_handle_state_change(struct net_device *dev, |
| 805 | enum c_can_bus_error_types error_type) |
| 806 | { |
| 807 | unsigned int reg_err_counter; |
| 808 | unsigned int rx_err_passive; |
| 809 | struct c_can_priv *priv = netdev_priv(dev); |
| 810 | struct net_device_stats *stats = &dev->stats; |
| 811 | struct can_frame *cf; |
| 812 | struct sk_buff *skb; |
| 813 | struct can_berr_counter bec; |
| 814 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 815 | /* propagate the error condition to the CAN stack */ |
Bhupesh Sharma | 881ff67 | 2011-02-13 22:51:44 -0800 | [diff] [blame] | 816 | skb = alloc_can_err_skb(dev, &cf); |
| 817 | if (unlikely(!skb)) |
| 818 | return 0; |
| 819 | |
| 820 | c_can_get_berr_counter(dev, &bec); |
| 821 | reg_err_counter = priv->read_reg(priv, &priv->regs->err_cnt); |
| 822 | rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> |
| 823 | ERR_CNT_RP_SHIFT; |
| 824 | |
| 825 | switch (error_type) { |
| 826 | case C_CAN_ERROR_WARNING: |
| 827 | /* error warning state */ |
| 828 | priv->can.can_stats.error_warning++; |
| 829 | priv->can.state = CAN_STATE_ERROR_WARNING; |
| 830 | cf->can_id |= CAN_ERR_CRTL; |
| 831 | cf->data[1] = (bec.txerr > bec.rxerr) ? |
| 832 | CAN_ERR_CRTL_TX_WARNING : |
| 833 | CAN_ERR_CRTL_RX_WARNING; |
| 834 | cf->data[6] = bec.txerr; |
| 835 | cf->data[7] = bec.rxerr; |
| 836 | |
| 837 | break; |
| 838 | case C_CAN_ERROR_PASSIVE: |
| 839 | /* error passive state */ |
| 840 | priv->can.can_stats.error_passive++; |
| 841 | priv->can.state = CAN_STATE_ERROR_PASSIVE; |
| 842 | cf->can_id |= CAN_ERR_CRTL; |
| 843 | if (rx_err_passive) |
| 844 | cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; |
| 845 | if (bec.txerr > 127) |
| 846 | cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; |
| 847 | |
| 848 | cf->data[6] = bec.txerr; |
| 849 | cf->data[7] = bec.rxerr; |
| 850 | break; |
| 851 | case C_CAN_BUS_OFF: |
| 852 | /* bus-off state */ |
| 853 | priv->can.state = CAN_STATE_BUS_OFF; |
| 854 | cf->can_id |= CAN_ERR_BUSOFF; |
| 855 | /* |
| 856 | * disable all interrupts in bus-off mode to ensure that |
| 857 | * the CPU is not hogged down |
| 858 | */ |
| 859 | c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); |
| 860 | can_bus_off(dev); |
| 861 | break; |
| 862 | default: |
| 863 | break; |
| 864 | } |
| 865 | |
| 866 | netif_receive_skb(skb); |
| 867 | stats->rx_packets++; |
| 868 | stats->rx_bytes += cf->can_dlc; |
| 869 | |
| 870 | return 1; |
| 871 | } |
| 872 | |
| 873 | static int c_can_handle_bus_err(struct net_device *dev, |
| 874 | enum c_can_lec_type lec_type) |
| 875 | { |
| 876 | struct c_can_priv *priv = netdev_priv(dev); |
| 877 | struct net_device_stats *stats = &dev->stats; |
| 878 | struct can_frame *cf; |
| 879 | struct sk_buff *skb; |
| 880 | |
| 881 | /* |
| 882 | * early exit if no lec update or no error. |
| 883 | * no lec update means that no CAN bus event has been detected |
| 884 | * since CPU wrote 0x7 value to status reg. |
| 885 | */ |
| 886 | if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) |
| 887 | return 0; |
| 888 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 889 | /* propagate the error condition to the CAN stack */ |
Bhupesh Sharma | 881ff67 | 2011-02-13 22:51:44 -0800 | [diff] [blame] | 890 | skb = alloc_can_err_skb(dev, &cf); |
| 891 | if (unlikely(!skb)) |
| 892 | return 0; |
| 893 | |
| 894 | /* |
| 895 | * check for 'last error code' which tells us the |
| 896 | * type of the last error to occur on the CAN bus |
| 897 | */ |
| 898 | |
| 899 | /* common for all type of bus errors */ |
| 900 | priv->can.can_stats.bus_error++; |
| 901 | stats->rx_errors++; |
| 902 | cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; |
| 903 | cf->data[2] |= CAN_ERR_PROT_UNSPEC; |
| 904 | |
| 905 | switch (lec_type) { |
| 906 | case LEC_STUFF_ERROR: |
| 907 | netdev_dbg(dev, "stuff error\n"); |
| 908 | cf->data[2] |= CAN_ERR_PROT_STUFF; |
| 909 | break; |
| 910 | case LEC_FORM_ERROR: |
| 911 | netdev_dbg(dev, "form error\n"); |
| 912 | cf->data[2] |= CAN_ERR_PROT_FORM; |
| 913 | break; |
| 914 | case LEC_ACK_ERROR: |
| 915 | netdev_dbg(dev, "ack error\n"); |
| 916 | cf->data[2] |= (CAN_ERR_PROT_LOC_ACK | |
| 917 | CAN_ERR_PROT_LOC_ACK_DEL); |
| 918 | break; |
| 919 | case LEC_BIT1_ERROR: |
| 920 | netdev_dbg(dev, "bit1 error\n"); |
| 921 | cf->data[2] |= CAN_ERR_PROT_BIT1; |
| 922 | break; |
| 923 | case LEC_BIT0_ERROR: |
| 924 | netdev_dbg(dev, "bit0 error\n"); |
| 925 | cf->data[2] |= CAN_ERR_PROT_BIT0; |
| 926 | break; |
| 927 | case LEC_CRC_ERROR: |
| 928 | netdev_dbg(dev, "CRC error\n"); |
| 929 | cf->data[2] |= (CAN_ERR_PROT_LOC_CRC_SEQ | |
| 930 | CAN_ERR_PROT_LOC_CRC_DEL); |
| 931 | break; |
| 932 | default: |
| 933 | break; |
| 934 | } |
| 935 | |
| 936 | /* set a `lec` value so that we can check for updates later */ |
| 937 | priv->write_reg(priv, &priv->regs->status, LEC_UNUSED); |
| 938 | |
| 939 | netif_receive_skb(skb); |
| 940 | stats->rx_packets++; |
| 941 | stats->rx_bytes += cf->can_dlc; |
| 942 | |
| 943 | return 1; |
| 944 | } |
| 945 | |
| 946 | static int c_can_poll(struct napi_struct *napi, int quota) |
| 947 | { |
| 948 | u16 irqstatus; |
| 949 | int lec_type = 0; |
| 950 | int work_done = 0; |
| 951 | struct net_device *dev = napi->dev; |
| 952 | struct c_can_priv *priv = netdev_priv(dev); |
| 953 | |
| 954 | irqstatus = priv->read_reg(priv, &priv->regs->interrupt); |
| 955 | if (!irqstatus) |
| 956 | goto end; |
| 957 | |
| 958 | /* status events have the highest priority */ |
| 959 | if (irqstatus == STATUS_INTERRUPT) { |
| 960 | priv->current_status = priv->read_reg(priv, |
| 961 | &priv->regs->status); |
| 962 | |
| 963 | /* handle Tx/Rx events */ |
| 964 | if (priv->current_status & STATUS_TXOK) |
| 965 | priv->write_reg(priv, &priv->regs->status, |
| 966 | priv->current_status & ~STATUS_TXOK); |
| 967 | |
| 968 | if (priv->current_status & STATUS_RXOK) |
| 969 | priv->write_reg(priv, &priv->regs->status, |
| 970 | priv->current_status & ~STATUS_RXOK); |
| 971 | |
| 972 | /* handle state changes */ |
| 973 | if ((priv->current_status & STATUS_EWARN) && |
| 974 | (!(priv->last_status & STATUS_EWARN))) { |
| 975 | netdev_dbg(dev, "entered error warning state\n"); |
| 976 | work_done += c_can_handle_state_change(dev, |
| 977 | C_CAN_ERROR_WARNING); |
| 978 | } |
| 979 | if ((priv->current_status & STATUS_EPASS) && |
| 980 | (!(priv->last_status & STATUS_EPASS))) { |
| 981 | netdev_dbg(dev, "entered error passive state\n"); |
| 982 | work_done += c_can_handle_state_change(dev, |
| 983 | C_CAN_ERROR_PASSIVE); |
| 984 | } |
| 985 | if ((priv->current_status & STATUS_BOFF) && |
| 986 | (!(priv->last_status & STATUS_BOFF))) { |
| 987 | netdev_dbg(dev, "entered bus off state\n"); |
| 988 | work_done += c_can_handle_state_change(dev, |
| 989 | C_CAN_BUS_OFF); |
| 990 | } |
| 991 | |
| 992 | /* handle bus recovery events */ |
| 993 | if ((!(priv->current_status & STATUS_BOFF)) && |
| 994 | (priv->last_status & STATUS_BOFF)) { |
| 995 | netdev_dbg(dev, "left bus off state\n"); |
| 996 | priv->can.state = CAN_STATE_ERROR_ACTIVE; |
| 997 | } |
| 998 | if ((!(priv->current_status & STATUS_EPASS)) && |
| 999 | (priv->last_status & STATUS_EPASS)) { |
| 1000 | netdev_dbg(dev, "left error passive state\n"); |
| 1001 | priv->can.state = CAN_STATE_ERROR_ACTIVE; |
| 1002 | } |
| 1003 | |
| 1004 | priv->last_status = priv->current_status; |
| 1005 | |
| 1006 | /* handle lec errors on the bus */ |
| 1007 | lec_type = c_can_has_and_handle_berr(priv); |
| 1008 | if (lec_type) |
| 1009 | work_done += c_can_handle_bus_err(dev, lec_type); |
| 1010 | } else if ((irqstatus >= C_CAN_MSG_OBJ_RX_FIRST) && |
| 1011 | (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) { |
| 1012 | /* handle events corresponding to receive message objects */ |
| 1013 | work_done += c_can_do_rx_poll(dev, (quota - work_done)); |
| 1014 | } else if ((irqstatus >= C_CAN_MSG_OBJ_TX_FIRST) && |
| 1015 | (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) { |
| 1016 | /* handle events corresponding to transmit message objects */ |
| 1017 | c_can_do_tx(dev); |
| 1018 | } |
| 1019 | |
| 1020 | end: |
| 1021 | if (work_done < quota) { |
| 1022 | napi_complete(napi); |
| 1023 | /* enable all IRQs */ |
| 1024 | c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); |
| 1025 | } |
| 1026 | |
| 1027 | return work_done; |
| 1028 | } |
| 1029 | |
| 1030 | static irqreturn_t c_can_isr(int irq, void *dev_id) |
| 1031 | { |
| 1032 | u16 irqstatus; |
| 1033 | struct net_device *dev = (struct net_device *)dev_id; |
| 1034 | struct c_can_priv *priv = netdev_priv(dev); |
| 1035 | |
| 1036 | irqstatus = priv->read_reg(priv, &priv->regs->interrupt); |
| 1037 | if (!irqstatus) |
| 1038 | return IRQ_NONE; |
| 1039 | |
| 1040 | /* disable all interrupts and schedule the NAPI */ |
| 1041 | c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); |
| 1042 | napi_schedule(&priv->napi); |
| 1043 | |
| 1044 | return IRQ_HANDLED; |
| 1045 | } |
| 1046 | |
| 1047 | static int c_can_open(struct net_device *dev) |
| 1048 | { |
| 1049 | int err; |
| 1050 | struct c_can_priv *priv = netdev_priv(dev); |
| 1051 | |
| 1052 | /* open the can device */ |
| 1053 | err = open_candev(dev); |
| 1054 | if (err) { |
| 1055 | netdev_err(dev, "failed to open can device\n"); |
| 1056 | return err; |
| 1057 | } |
| 1058 | |
| 1059 | /* register interrupt handler */ |
| 1060 | err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, |
| 1061 | dev); |
| 1062 | if (err < 0) { |
| 1063 | netdev_err(dev, "failed to request interrupt\n"); |
| 1064 | goto exit_irq_fail; |
| 1065 | } |
| 1066 | |
| 1067 | /* start the c_can controller */ |
| 1068 | c_can_start(dev); |
| 1069 | |
| 1070 | napi_enable(&priv->napi); |
| 1071 | netif_start_queue(dev); |
| 1072 | |
| 1073 | return 0; |
| 1074 | |
| 1075 | exit_irq_fail: |
| 1076 | close_candev(dev); |
| 1077 | return err; |
| 1078 | } |
| 1079 | |
| 1080 | static int c_can_close(struct net_device *dev) |
| 1081 | { |
| 1082 | struct c_can_priv *priv = netdev_priv(dev); |
| 1083 | |
| 1084 | netif_stop_queue(dev); |
| 1085 | napi_disable(&priv->napi); |
| 1086 | c_can_stop(dev); |
| 1087 | free_irq(dev->irq, dev); |
| 1088 | close_candev(dev); |
| 1089 | |
| 1090 | return 0; |
| 1091 | } |
| 1092 | |
| 1093 | struct net_device *alloc_c_can_dev(void) |
| 1094 | { |
| 1095 | struct net_device *dev; |
| 1096 | struct c_can_priv *priv; |
| 1097 | |
| 1098 | dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM); |
| 1099 | if (!dev) |
| 1100 | return NULL; |
| 1101 | |
| 1102 | priv = netdev_priv(dev); |
| 1103 | netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT); |
| 1104 | |
| 1105 | priv->dev = dev; |
| 1106 | priv->can.bittiming_const = &c_can_bittiming_const; |
| 1107 | priv->can.do_set_mode = c_can_set_mode; |
| 1108 | priv->can.do_get_berr_counter = c_can_get_berr_counter; |
Marc Kleine-Budde | ee6f098 | 2011-03-24 02:34:32 +0000 | [diff] [blame] | 1109 | priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | |
Bhupesh Sharma | 881ff67 | 2011-02-13 22:51:44 -0800 | [diff] [blame] | 1110 | CAN_CTRLMODE_LISTENONLY | |
| 1111 | CAN_CTRLMODE_BERR_REPORTING; |
| 1112 | |
| 1113 | return dev; |
| 1114 | } |
| 1115 | EXPORT_SYMBOL_GPL(alloc_c_can_dev); |
| 1116 | |
| 1117 | void free_c_can_dev(struct net_device *dev) |
| 1118 | { |
| 1119 | free_candev(dev); |
| 1120 | } |
| 1121 | EXPORT_SYMBOL_GPL(free_c_can_dev); |
| 1122 | |
| 1123 | static const struct net_device_ops c_can_netdev_ops = { |
| 1124 | .ndo_open = c_can_open, |
| 1125 | .ndo_stop = c_can_close, |
| 1126 | .ndo_start_xmit = c_can_start_xmit, |
| 1127 | }; |
| 1128 | |
| 1129 | int register_c_can_dev(struct net_device *dev) |
| 1130 | { |
| 1131 | dev->flags |= IFF_ECHO; /* we support local echo */ |
| 1132 | dev->netdev_ops = &c_can_netdev_ops; |
| 1133 | |
| 1134 | return register_candev(dev); |
| 1135 | } |
| 1136 | EXPORT_SYMBOL_GPL(register_c_can_dev); |
| 1137 | |
| 1138 | void unregister_c_can_dev(struct net_device *dev) |
| 1139 | { |
| 1140 | struct c_can_priv *priv = netdev_priv(dev); |
| 1141 | |
| 1142 | /* disable all interrupts */ |
| 1143 | c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); |
| 1144 | |
| 1145 | unregister_candev(dev); |
| 1146 | } |
| 1147 | EXPORT_SYMBOL_GPL(unregister_c_can_dev); |
| 1148 | |
| 1149 | MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); |
| 1150 | MODULE_LICENSE("GPL v2"); |
| 1151 | MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); |