Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be included in |
| 13 | * all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: Dave Airlie |
| 24 | * Alex Deucher |
| 25 | */ |
| 26 | #include <drm/drmP.h> |
| 27 | #include <drm/drm_crtc_helper.h> |
| 28 | #include <drm/radeon_drm.h> |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 29 | #include <drm/drm_fixed.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 30 | #include "radeon.h" |
| 31 | #include "atom.h" |
| 32 | #include "atom-bits.h" |
| 33 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 34 | static void atombios_overscan_setup(struct drm_crtc *crtc, |
| 35 | struct drm_display_mode *mode, |
| 36 | struct drm_display_mode *adjusted_mode) |
| 37 | { |
| 38 | struct drm_device *dev = crtc->dev; |
| 39 | struct radeon_device *rdev = dev->dev_private; |
| 40 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 41 | SET_CRTC_OVERSCAN_PS_ALLOCATION args; |
| 42 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); |
| 43 | int a1, a2; |
| 44 | |
| 45 | memset(&args, 0, sizeof(args)); |
| 46 | |
| 47 | args.usOverscanRight = 0; |
| 48 | args.usOverscanLeft = 0; |
| 49 | args.usOverscanBottom = 0; |
| 50 | args.usOverscanTop = 0; |
| 51 | args.ucCRTC = radeon_crtc->crtc_id; |
| 52 | |
| 53 | switch (radeon_crtc->rmx_type) { |
| 54 | case RMX_CENTER: |
| 55 | args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; |
| 56 | args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; |
| 57 | args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; |
| 58 | args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; |
| 59 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 60 | break; |
| 61 | case RMX_ASPECT: |
| 62 | a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; |
| 63 | a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; |
| 64 | |
| 65 | if (a1 > a2) { |
| 66 | args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; |
| 67 | args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; |
| 68 | } else if (a2 > a1) { |
| 69 | args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; |
| 70 | args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; |
| 71 | } |
| 72 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 73 | break; |
| 74 | case RMX_FULL: |
| 75 | default: |
| 76 | args.usOverscanRight = 0; |
| 77 | args.usOverscanLeft = 0; |
| 78 | args.usOverscanBottom = 0; |
| 79 | args.usOverscanTop = 0; |
| 80 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 81 | break; |
| 82 | } |
| 83 | } |
| 84 | |
| 85 | static void atombios_scaler_setup(struct drm_crtc *crtc) |
| 86 | { |
| 87 | struct drm_device *dev = crtc->dev; |
| 88 | struct radeon_device *rdev = dev->dev_private; |
| 89 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 90 | ENABLE_SCALER_PS_ALLOCATION args; |
| 91 | int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 92 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 93 | /* fixme - fill in enc_priv for atom dac */ |
| 94 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 95 | bool is_tv = false, is_cv = false; |
| 96 | struct drm_encoder *encoder; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 97 | |
| 98 | if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) |
| 99 | return; |
| 100 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 101 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 102 | /* find tv std */ |
| 103 | if (encoder->crtc == crtc) { |
| 104 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 105 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
| 106 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
| 107 | tv_std = tv_dac->tv_std; |
| 108 | is_tv = true; |
| 109 | } |
| 110 | } |
| 111 | } |
| 112 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 113 | memset(&args, 0, sizeof(args)); |
| 114 | |
| 115 | args.ucScaler = radeon_crtc->crtc_id; |
| 116 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 117 | if (is_tv) { |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 118 | switch (tv_std) { |
| 119 | case TV_STD_NTSC: |
| 120 | default: |
| 121 | args.ucTVStandard = ATOM_TV_NTSC; |
| 122 | break; |
| 123 | case TV_STD_PAL: |
| 124 | args.ucTVStandard = ATOM_TV_PAL; |
| 125 | break; |
| 126 | case TV_STD_PAL_M: |
| 127 | args.ucTVStandard = ATOM_TV_PALM; |
| 128 | break; |
| 129 | case TV_STD_PAL_60: |
| 130 | args.ucTVStandard = ATOM_TV_PAL60; |
| 131 | break; |
| 132 | case TV_STD_NTSC_J: |
| 133 | args.ucTVStandard = ATOM_TV_NTSCJ; |
| 134 | break; |
| 135 | case TV_STD_SCART_PAL: |
| 136 | args.ucTVStandard = ATOM_TV_PAL; /* ??? */ |
| 137 | break; |
| 138 | case TV_STD_SECAM: |
| 139 | args.ucTVStandard = ATOM_TV_SECAM; |
| 140 | break; |
| 141 | case TV_STD_PAL_CN: |
| 142 | args.ucTVStandard = ATOM_TV_PALCN; |
| 143 | break; |
| 144 | } |
| 145 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 146 | } else if (is_cv) { |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 147 | args.ucTVStandard = ATOM_TV_CV; |
| 148 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
| 149 | } else { |
| 150 | switch (radeon_crtc->rmx_type) { |
| 151 | case RMX_FULL: |
| 152 | args.ucEnable = ATOM_SCALER_EXPANSION; |
| 153 | break; |
| 154 | case RMX_CENTER: |
| 155 | args.ucEnable = ATOM_SCALER_CENTER; |
| 156 | break; |
| 157 | case RMX_ASPECT: |
| 158 | args.ucEnable = ATOM_SCALER_EXPANSION; |
| 159 | break; |
| 160 | default: |
| 161 | if (ASIC_IS_AVIVO(rdev)) |
| 162 | args.ucEnable = ATOM_SCALER_DISABLE; |
| 163 | else |
| 164 | args.ucEnable = ATOM_SCALER_CENTER; |
| 165 | break; |
| 166 | } |
| 167 | } |
| 168 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 169 | if ((is_tv || is_cv) |
| 170 | && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { |
| 171 | atom_rv515_force_tv_scaler(rdev, radeon_crtc); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 172 | } |
| 173 | } |
| 174 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 175 | static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) |
| 176 | { |
| 177 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 178 | struct drm_device *dev = crtc->dev; |
| 179 | struct radeon_device *rdev = dev->dev_private; |
| 180 | int index = |
| 181 | GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); |
| 182 | ENABLE_CRTC_PS_ALLOCATION args; |
| 183 | |
| 184 | memset(&args, 0, sizeof(args)); |
| 185 | |
| 186 | args.ucCRTC = radeon_crtc->crtc_id; |
| 187 | args.ucEnable = lock; |
| 188 | |
| 189 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 190 | } |
| 191 | |
| 192 | static void atombios_enable_crtc(struct drm_crtc *crtc, int state) |
| 193 | { |
| 194 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 195 | struct drm_device *dev = crtc->dev; |
| 196 | struct radeon_device *rdev = dev->dev_private; |
| 197 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); |
| 198 | ENABLE_CRTC_PS_ALLOCATION args; |
| 199 | |
| 200 | memset(&args, 0, sizeof(args)); |
| 201 | |
| 202 | args.ucCRTC = radeon_crtc->crtc_id; |
| 203 | args.ucEnable = state; |
| 204 | |
| 205 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 206 | } |
| 207 | |
| 208 | static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) |
| 209 | { |
| 210 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 211 | struct drm_device *dev = crtc->dev; |
| 212 | struct radeon_device *rdev = dev->dev_private; |
| 213 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); |
| 214 | ENABLE_CRTC_PS_ALLOCATION args; |
| 215 | |
| 216 | memset(&args, 0, sizeof(args)); |
| 217 | |
| 218 | args.ucCRTC = radeon_crtc->crtc_id; |
| 219 | args.ucEnable = state; |
| 220 | |
| 221 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 222 | } |
| 223 | |
| 224 | static void atombios_blank_crtc(struct drm_crtc *crtc, int state) |
| 225 | { |
| 226 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 227 | struct drm_device *dev = crtc->dev; |
| 228 | struct radeon_device *rdev = dev->dev_private; |
| 229 | int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); |
| 230 | BLANK_CRTC_PS_ALLOCATION args; |
| 231 | |
| 232 | memset(&args, 0, sizeof(args)); |
| 233 | |
| 234 | args.ucCRTC = radeon_crtc->crtc_id; |
| 235 | args.ucBlanking = state; |
| 236 | |
| 237 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 238 | } |
| 239 | |
| 240 | void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) |
| 241 | { |
| 242 | struct drm_device *dev = crtc->dev; |
| 243 | struct radeon_device *rdev = dev->dev_private; |
Alex Deucher | 500b758 | 2009-12-02 11:46:52 -0500 | [diff] [blame] | 244 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 245 | |
| 246 | switch (mode) { |
| 247 | case DRM_MODE_DPMS_ON: |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 248 | radeon_crtc->enabled = true; |
| 249 | /* adjust pm to dpms changes BEFORE enabling crtcs */ |
| 250 | radeon_pm_compute_clocks(rdev); |
Alex Deucher | 37b4390 | 2010-02-09 12:04:43 -0500 | [diff] [blame] | 251 | atombios_enable_crtc(crtc, ATOM_ENABLE); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 252 | if (ASIC_IS_DCE3(rdev)) |
Alex Deucher | 37b4390 | 2010-02-09 12:04:43 -0500 | [diff] [blame] | 253 | atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); |
| 254 | atombios_blank_crtc(crtc, ATOM_DISABLE); |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 255 | drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); |
Alex Deucher | 500b758 | 2009-12-02 11:46:52 -0500 | [diff] [blame] | 256 | radeon_crtc_load_lut(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 257 | break; |
| 258 | case DRM_MODE_DPMS_STANDBY: |
| 259 | case DRM_MODE_DPMS_SUSPEND: |
| 260 | case DRM_MODE_DPMS_OFF: |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 261 | drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); |
Alex Deucher | 37b4390 | 2010-02-09 12:04:43 -0500 | [diff] [blame] | 262 | atombios_blank_crtc(crtc, ATOM_ENABLE); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 263 | if (ASIC_IS_DCE3(rdev)) |
Alex Deucher | 37b4390 | 2010-02-09 12:04:43 -0500 | [diff] [blame] | 264 | atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); |
| 265 | atombios_enable_crtc(crtc, ATOM_DISABLE); |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 266 | radeon_crtc->enabled = false; |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 267 | /* adjust pm to dpms changes AFTER disabling crtcs */ |
| 268 | radeon_pm_compute_clocks(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 269 | break; |
| 270 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 271 | } |
| 272 | |
| 273 | static void |
| 274 | atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 275 | struct drm_display_mode *mode) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 276 | { |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 277 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 278 | struct drm_device *dev = crtc->dev; |
| 279 | struct radeon_device *rdev = dev->dev_private; |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 280 | SET_CRTC_USING_DTD_TIMING_PARAMETERS args; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 281 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 282 | u16 misc = 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 283 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 284 | memset(&args, 0, sizeof(args)); |
| 285 | args.usH_Size = cpu_to_le16(mode->crtc_hdisplay); |
| 286 | args.usH_Blanking_Time = |
| 287 | cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay); |
| 288 | args.usV_Size = cpu_to_le16(mode->crtc_vdisplay); |
| 289 | args.usV_Blanking_Time = |
| 290 | cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay); |
| 291 | args.usH_SyncOffset = |
| 292 | cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay); |
| 293 | args.usH_SyncWidth = |
| 294 | cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); |
| 295 | args.usV_SyncOffset = |
| 296 | cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay); |
| 297 | args.usV_SyncWidth = |
| 298 | cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); |
| 299 | /*args.ucH_Border = mode->hborder;*/ |
| 300 | /*args.ucV_Border = mode->vborder;*/ |
| 301 | |
| 302 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 303 | misc |= ATOM_VSYNC_POLARITY; |
| 304 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 305 | misc |= ATOM_HSYNC_POLARITY; |
| 306 | if (mode->flags & DRM_MODE_FLAG_CSYNC) |
| 307 | misc |= ATOM_COMPOSITESYNC; |
| 308 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 309 | misc |= ATOM_INTERLACE; |
| 310 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 311 | misc |= ATOM_DOUBLE_CLOCK_MODE; |
| 312 | |
| 313 | args.susModeMiscInfo.usAccess = cpu_to_le16(misc); |
| 314 | args.ucCRTC = radeon_crtc->crtc_id; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 315 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 316 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 317 | } |
| 318 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 319 | static void atombios_crtc_set_timing(struct drm_crtc *crtc, |
| 320 | struct drm_display_mode *mode) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 321 | { |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 322 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 323 | struct drm_device *dev = crtc->dev; |
| 324 | struct radeon_device *rdev = dev->dev_private; |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 325 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 326 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 327 | u16 misc = 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 328 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 329 | memset(&args, 0, sizeof(args)); |
| 330 | args.usH_Total = cpu_to_le16(mode->crtc_htotal); |
| 331 | args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); |
| 332 | args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); |
| 333 | args.usH_SyncWidth = |
| 334 | cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); |
| 335 | args.usV_Total = cpu_to_le16(mode->crtc_vtotal); |
| 336 | args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); |
| 337 | args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); |
| 338 | args.usV_SyncWidth = |
| 339 | cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); |
| 340 | |
| 341 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 342 | misc |= ATOM_VSYNC_POLARITY; |
| 343 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 344 | misc |= ATOM_HSYNC_POLARITY; |
| 345 | if (mode->flags & DRM_MODE_FLAG_CSYNC) |
| 346 | misc |= ATOM_COMPOSITESYNC; |
| 347 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 348 | misc |= ATOM_INTERLACE; |
| 349 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 350 | misc |= ATOM_DOUBLE_CLOCK_MODE; |
| 351 | |
| 352 | args.susModeMiscInfo.usAccess = cpu_to_le16(misc); |
| 353 | args.ucCRTC = radeon_crtc->crtc_id; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 354 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 355 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 356 | } |
| 357 | |
Alex Deucher | b792210 | 2010-03-06 10:57:30 -0500 | [diff] [blame] | 358 | static void atombios_disable_ss(struct drm_crtc *crtc) |
| 359 | { |
| 360 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 361 | struct drm_device *dev = crtc->dev; |
| 362 | struct radeon_device *rdev = dev->dev_private; |
| 363 | u32 ss_cntl; |
| 364 | |
| 365 | if (ASIC_IS_DCE4(rdev)) { |
| 366 | switch (radeon_crtc->pll_id) { |
| 367 | case ATOM_PPLL1: |
| 368 | ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); |
| 369 | ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; |
| 370 | WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); |
| 371 | break; |
| 372 | case ATOM_PPLL2: |
| 373 | ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); |
| 374 | ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; |
| 375 | WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); |
| 376 | break; |
| 377 | case ATOM_DCPLL: |
| 378 | case ATOM_PPLL_INVALID: |
| 379 | return; |
| 380 | } |
| 381 | } else if (ASIC_IS_AVIVO(rdev)) { |
| 382 | switch (radeon_crtc->pll_id) { |
| 383 | case ATOM_PPLL1: |
| 384 | ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); |
| 385 | ss_cntl &= ~1; |
| 386 | WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); |
| 387 | break; |
| 388 | case ATOM_PPLL2: |
| 389 | ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); |
| 390 | ss_cntl &= ~1; |
| 391 | WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); |
| 392 | break; |
| 393 | case ATOM_DCPLL: |
| 394 | case ATOM_PPLL_INVALID: |
| 395 | return; |
| 396 | } |
| 397 | } |
| 398 | } |
| 399 | |
| 400 | |
Alex Deucher | 26b9fc3 | 2010-02-01 16:39:11 -0500 | [diff] [blame] | 401 | union atom_enable_ss { |
| 402 | ENABLE_LVDS_SS_PARAMETERS legacy; |
| 403 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; |
| 404 | }; |
| 405 | |
Alex Deucher | b792210 | 2010-03-06 10:57:30 -0500 | [diff] [blame] | 406 | static void atombios_enable_ss(struct drm_crtc *crtc) |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 407 | { |
| 408 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 409 | struct drm_device *dev = crtc->dev; |
| 410 | struct radeon_device *rdev = dev->dev_private; |
| 411 | struct drm_encoder *encoder = NULL; |
| 412 | struct radeon_encoder *radeon_encoder = NULL; |
| 413 | struct radeon_encoder_atom_dig *dig = NULL; |
| 414 | int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); |
Alex Deucher | 26b9fc3 | 2010-02-01 16:39:11 -0500 | [diff] [blame] | 415 | union atom_enable_ss args; |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 416 | uint16_t percentage = 0; |
| 417 | uint8_t type = 0, step = 0, delay = 0, range = 0; |
| 418 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 419 | /* XXX add ss support for DCE4 */ |
| 420 | if (ASIC_IS_DCE4(rdev)) |
| 421 | return; |
| 422 | |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 423 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 424 | if (encoder->crtc == crtc) { |
| 425 | radeon_encoder = to_radeon_encoder(encoder); |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 426 | /* only enable spread spectrum on LVDS */ |
Alex Deucher | d11aa88 | 2009-10-28 00:51:20 -0400 | [diff] [blame] | 427 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
| 428 | dig = radeon_encoder->enc_priv; |
| 429 | if (dig && dig->ss) { |
| 430 | percentage = dig->ss->percentage; |
| 431 | type = dig->ss->type; |
| 432 | step = dig->ss->step; |
| 433 | delay = dig->ss->delay; |
| 434 | range = dig->ss->range; |
Alex Deucher | b792210 | 2010-03-06 10:57:30 -0500 | [diff] [blame] | 435 | } else |
Alex Deucher | d11aa88 | 2009-10-28 00:51:20 -0400 | [diff] [blame] | 436 | return; |
Alex Deucher | b792210 | 2010-03-06 10:57:30 -0500 | [diff] [blame] | 437 | } else |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 438 | return; |
| 439 | break; |
| 440 | } |
| 441 | } |
| 442 | |
| 443 | if (!radeon_encoder) |
| 444 | return; |
| 445 | |
Alex Deucher | 26b9fc3 | 2010-02-01 16:39:11 -0500 | [diff] [blame] | 446 | memset(&args, 0, sizeof(args)); |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 447 | if (ASIC_IS_AVIVO(rdev)) { |
Alex Deucher | 26b9fc3 | 2010-02-01 16:39:11 -0500 | [diff] [blame] | 448 | args.v1.usSpreadSpectrumPercentage = cpu_to_le16(percentage); |
| 449 | args.v1.ucSpreadSpectrumType = type; |
| 450 | args.v1.ucSpreadSpectrumStep = step; |
| 451 | args.v1.ucSpreadSpectrumDelay = delay; |
| 452 | args.v1.ucSpreadSpectrumRange = range; |
| 453 | args.v1.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; |
Alex Deucher | b792210 | 2010-03-06 10:57:30 -0500 | [diff] [blame] | 454 | args.v1.ucEnable = ATOM_ENABLE; |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 455 | } else { |
Alex Deucher | 26b9fc3 | 2010-02-01 16:39:11 -0500 | [diff] [blame] | 456 | args.legacy.usSpreadSpectrumPercentage = cpu_to_le16(percentage); |
| 457 | args.legacy.ucSpreadSpectrumType = type; |
| 458 | args.legacy.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2; |
| 459 | args.legacy.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4; |
Alex Deucher | b792210 | 2010-03-06 10:57:30 -0500 | [diff] [blame] | 460 | args.legacy.ucEnable = ATOM_ENABLE; |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 461 | } |
Alex Deucher | 26b9fc3 | 2010-02-01 16:39:11 -0500 | [diff] [blame] | 462 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 463 | } |
| 464 | |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 465 | union adjust_pixel_clock { |
| 466 | ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 467 | ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 468 | }; |
| 469 | |
| 470 | static u32 atombios_adjust_pll(struct drm_crtc *crtc, |
| 471 | struct drm_display_mode *mode, |
| 472 | struct radeon_pll *pll) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 473 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 474 | struct drm_device *dev = crtc->dev; |
| 475 | struct radeon_device *rdev = dev->dev_private; |
| 476 | struct drm_encoder *encoder = NULL; |
| 477 | struct radeon_encoder *radeon_encoder = NULL; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 478 | u32 adjusted_clock = mode->clock; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 479 | int encoder_mode = 0; |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 480 | |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 481 | /* reset the pll flags */ |
| 482 | pll->flags = 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 483 | |
Alex Deucher | 7c27f87 | 2010-02-02 12:05:01 -0500 | [diff] [blame] | 484 | /* select the PLL algo */ |
| 485 | if (ASIC_IS_AVIVO(rdev)) { |
Alex Deucher | 383be5d | 2010-02-23 03:24:38 -0500 | [diff] [blame] | 486 | if (radeon_new_pll == 0) |
| 487 | pll->algo = PLL_ALGO_LEGACY; |
| 488 | else |
| 489 | pll->algo = PLL_ALGO_NEW; |
| 490 | } else { |
| 491 | if (radeon_new_pll == 1) |
| 492 | pll->algo = PLL_ALGO_NEW; |
Alex Deucher | 7c27f87 | 2010-02-02 12:05:01 -0500 | [diff] [blame] | 493 | else |
| 494 | pll->algo = PLL_ALGO_LEGACY; |
Alex Deucher | 383be5d | 2010-02-23 03:24:38 -0500 | [diff] [blame] | 495 | } |
Alex Deucher | 7c27f87 | 2010-02-02 12:05:01 -0500 | [diff] [blame] | 496 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 497 | if (ASIC_IS_AVIVO(rdev)) { |
Alex Deucher | eb1300b | 2009-07-13 11:09:56 -0400 | [diff] [blame] | 498 | if ((rdev->family == CHIP_RS600) || |
| 499 | (rdev->family == CHIP_RS690) || |
| 500 | (rdev->family == CHIP_RS740)) |
Alex Deucher | 2ff776c | 2010-06-08 19:44:36 -0400 | [diff] [blame] | 501 | pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 502 | RADEON_PLL_PREFER_CLOSEST_LOWER); |
Alex Deucher | eb1300b | 2009-07-13 11:09:56 -0400 | [diff] [blame] | 503 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 504 | if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 505 | pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 506 | else |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 507 | pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 508 | } else { |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 509 | pll->flags |= RADEON_PLL_LEGACY; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 510 | |
| 511 | if (mode->clock > 200000) /* range limits??? */ |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 512 | pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 513 | else |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 514 | pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 515 | |
| 516 | } |
| 517 | |
| 518 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 519 | if (encoder->crtc == crtc) { |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 520 | radeon_encoder = to_radeon_encoder(encoder); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 521 | encoder_mode = atombios_get_encoder_mode(encoder); |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 522 | if (ASIC_IS_AVIVO(rdev)) { |
| 523 | /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ |
| 524 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) |
| 525 | adjusted_clock = mode->clock * 2; |
Alex Deucher | a1a4b23 | 2010-04-09 15:31:56 -0400 | [diff] [blame] | 526 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { |
| 527 | pll->algo = PLL_ALGO_LEGACY; |
| 528 | pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; |
| 529 | } |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 530 | } else { |
| 531 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 532 | pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 533 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 534 | pll->flags |= RADEON_PLL_USE_REF_DIV; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 535 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 536 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 537 | } |
| 538 | } |
| 539 | |
Alex Deucher | 2606c88 | 2009-10-08 13:36:21 -0400 | [diff] [blame] | 540 | /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock |
| 541 | * accordingly based on the encoder/transmitter to work around |
| 542 | * special hw requirements. |
| 543 | */ |
| 544 | if (ASIC_IS_DCE3(rdev)) { |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 545 | union adjust_pixel_clock args; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 546 | u8 frev, crev; |
| 547 | int index; |
Alex Deucher | 2606c88 | 2009-10-08 13:36:21 -0400 | [diff] [blame] | 548 | |
Alex Deucher | 2606c88 | 2009-10-08 13:36:21 -0400 | [diff] [blame] | 549 | index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 550 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
| 551 | &crev)) |
| 552 | return adjusted_clock; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 553 | |
| 554 | memset(&args, 0, sizeof(args)); |
| 555 | |
| 556 | switch (frev) { |
| 557 | case 1: |
| 558 | switch (crev) { |
| 559 | case 1: |
| 560 | case 2: |
| 561 | args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); |
| 562 | args.v1.ucTransmitterID = radeon_encoder->encoder_id; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 563 | args.v1.ucEncodeMode = encoder_mode; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 564 | |
| 565 | atom_execute_table(rdev->mode_info.atom_context, |
| 566 | index, (uint32_t *)&args); |
| 567 | adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; |
| 568 | break; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 569 | case 3: |
| 570 | args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10); |
| 571 | args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; |
| 572 | args.v3.sInput.ucEncodeMode = encoder_mode; |
| 573 | args.v3.sInput.ucDispPllConfig = 0; |
| 574 | if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
| 575 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 576 | |
| 577 | if (encoder_mode == ATOM_ENCODER_MODE_DP) |
| 578 | args.v3.sInput.ucDispPllConfig |= |
| 579 | DISPPLL_CONFIG_COHERENT_MODE; |
| 580 | else { |
| 581 | if (dig->coherent_mode) |
| 582 | args.v3.sInput.ucDispPllConfig |= |
| 583 | DISPPLL_CONFIG_COHERENT_MODE; |
| 584 | if (mode->clock > 165000) |
| 585 | args.v3.sInput.ucDispPllConfig |= |
| 586 | DISPPLL_CONFIG_DUAL_LINK; |
| 587 | } |
| 588 | } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
| 589 | /* may want to enable SS on DP/eDP eventually */ |
Alex Deucher | 9f998ad | 2010-03-29 21:37:08 -0400 | [diff] [blame] | 590 | /*args.v3.sInput.ucDispPllConfig |= |
| 591 | DISPPLL_CONFIG_SS_ENABLE;*/ |
| 592 | if (encoder_mode == ATOM_ENCODER_MODE_DP) |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 593 | args.v3.sInput.ucDispPllConfig |= |
Alex Deucher | 9f998ad | 2010-03-29 21:37:08 -0400 | [diff] [blame] | 594 | DISPPLL_CONFIG_COHERENT_MODE; |
| 595 | else { |
| 596 | if (mode->clock > 165000) |
| 597 | args.v3.sInput.ucDispPllConfig |= |
| 598 | DISPPLL_CONFIG_DUAL_LINK; |
| 599 | } |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 600 | } |
| 601 | atom_execute_table(rdev->mode_info.atom_context, |
| 602 | index, (uint32_t *)&args); |
| 603 | adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; |
| 604 | if (args.v3.sOutput.ucRefDiv) { |
| 605 | pll->flags |= RADEON_PLL_USE_REF_DIV; |
| 606 | pll->reference_div = args.v3.sOutput.ucRefDiv; |
| 607 | } |
| 608 | if (args.v3.sOutput.ucPostDiv) { |
| 609 | pll->flags |= RADEON_PLL_USE_POST_DIV; |
| 610 | pll->post_div = args.v3.sOutput.ucPostDiv; |
| 611 | } |
| 612 | break; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 613 | default: |
| 614 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
| 615 | return adjusted_clock; |
| 616 | } |
| 617 | break; |
| 618 | default: |
| 619 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
| 620 | return adjusted_clock; |
| 621 | } |
Alex Deucher | d56ef9c | 2009-10-27 12:11:09 -0400 | [diff] [blame] | 622 | } |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 623 | return adjusted_clock; |
| 624 | } |
| 625 | |
| 626 | union set_pixel_clock { |
| 627 | SET_PIXEL_CLOCK_PS_ALLOCATION base; |
| 628 | PIXEL_CLOCK_PARAMETERS v1; |
| 629 | PIXEL_CLOCK_PARAMETERS_V2 v2; |
| 630 | PIXEL_CLOCK_PARAMETERS_V3 v3; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 631 | PIXEL_CLOCK_PARAMETERS_V5 v5; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 632 | }; |
| 633 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 634 | static void atombios_crtc_set_dcpll(struct drm_crtc *crtc) |
| 635 | { |
| 636 | struct drm_device *dev = crtc->dev; |
| 637 | struct radeon_device *rdev = dev->dev_private; |
| 638 | u8 frev, crev; |
| 639 | int index; |
| 640 | union set_pixel_clock args; |
| 641 | |
| 642 | memset(&args, 0, sizeof(args)); |
| 643 | |
| 644 | index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 645 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
| 646 | &crev)) |
| 647 | return; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 648 | |
| 649 | switch (frev) { |
| 650 | case 1: |
| 651 | switch (crev) { |
| 652 | case 5: |
| 653 | /* if the default dcpll clock is specified, |
| 654 | * SetPixelClock provides the dividers |
| 655 | */ |
| 656 | args.v5.ucCRTC = ATOM_CRTC_INVALID; |
| 657 | args.v5.usPixelClock = rdev->clock.default_dispclk; |
| 658 | args.v5.ucPpll = ATOM_DCPLL; |
| 659 | break; |
| 660 | default: |
| 661 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
| 662 | return; |
| 663 | } |
| 664 | break; |
| 665 | default: |
| 666 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
| 667 | return; |
| 668 | } |
| 669 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 670 | } |
| 671 | |
Alex Deucher | 37f9003 | 2010-06-11 17:58:38 -0400 | [diff] [blame] | 672 | static void atombios_crtc_program_pll(struct drm_crtc *crtc, |
| 673 | int crtc_id, |
| 674 | int pll_id, |
| 675 | u32 encoder_mode, |
| 676 | u32 encoder_id, |
| 677 | u32 clock, |
| 678 | u32 ref_div, |
| 679 | u32 fb_div, |
| 680 | u32 frac_fb_div, |
| 681 | u32 post_div) |
| 682 | { |
| 683 | struct drm_device *dev = crtc->dev; |
| 684 | struct radeon_device *rdev = dev->dev_private; |
| 685 | u8 frev, crev; |
| 686 | int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); |
| 687 | union set_pixel_clock args; |
| 688 | |
| 689 | memset(&args, 0, sizeof(args)); |
| 690 | |
| 691 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
| 692 | &crev)) |
| 693 | return; |
| 694 | |
| 695 | switch (frev) { |
| 696 | case 1: |
| 697 | switch (crev) { |
| 698 | case 1: |
| 699 | if (clock == ATOM_DISABLE) |
| 700 | return; |
| 701 | args.v1.usPixelClock = cpu_to_le16(clock / 10); |
| 702 | args.v1.usRefDiv = cpu_to_le16(ref_div); |
| 703 | args.v1.usFbDiv = cpu_to_le16(fb_div); |
| 704 | args.v1.ucFracFbDiv = frac_fb_div; |
| 705 | args.v1.ucPostDiv = post_div; |
| 706 | args.v1.ucPpll = pll_id; |
| 707 | args.v1.ucCRTC = crtc_id; |
| 708 | args.v1.ucRefDivSrc = 1; |
| 709 | break; |
| 710 | case 2: |
| 711 | args.v2.usPixelClock = cpu_to_le16(clock / 10); |
| 712 | args.v2.usRefDiv = cpu_to_le16(ref_div); |
| 713 | args.v2.usFbDiv = cpu_to_le16(fb_div); |
| 714 | args.v2.ucFracFbDiv = frac_fb_div; |
| 715 | args.v2.ucPostDiv = post_div; |
| 716 | args.v2.ucPpll = pll_id; |
| 717 | args.v2.ucCRTC = crtc_id; |
| 718 | args.v2.ucRefDivSrc = 1; |
| 719 | break; |
| 720 | case 3: |
| 721 | args.v3.usPixelClock = cpu_to_le16(clock / 10); |
| 722 | args.v3.usRefDiv = cpu_to_le16(ref_div); |
| 723 | args.v3.usFbDiv = cpu_to_le16(fb_div); |
| 724 | args.v3.ucFracFbDiv = frac_fb_div; |
| 725 | args.v3.ucPostDiv = post_div; |
| 726 | args.v3.ucPpll = pll_id; |
| 727 | args.v3.ucMiscInfo = (pll_id << 2); |
| 728 | args.v3.ucTransmitterId = encoder_id; |
| 729 | args.v3.ucEncoderMode = encoder_mode; |
| 730 | break; |
| 731 | case 5: |
| 732 | args.v5.ucCRTC = crtc_id; |
| 733 | args.v5.usPixelClock = cpu_to_le16(clock / 10); |
| 734 | args.v5.ucRefDiv = ref_div; |
| 735 | args.v5.usFbDiv = cpu_to_le16(fb_div); |
| 736 | args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); |
| 737 | args.v5.ucPostDiv = post_div; |
| 738 | args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ |
| 739 | args.v5.ucTransmitterID = encoder_id; |
| 740 | args.v5.ucEncoderMode = encoder_mode; |
| 741 | args.v5.ucPpll = pll_id; |
| 742 | break; |
| 743 | default: |
| 744 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
| 745 | return; |
| 746 | } |
| 747 | break; |
| 748 | default: |
| 749 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
| 750 | return; |
| 751 | } |
| 752 | |
| 753 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 754 | } |
| 755 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 756 | static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 757 | { |
| 758 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 759 | struct drm_device *dev = crtc->dev; |
| 760 | struct radeon_device *rdev = dev->dev_private; |
| 761 | struct drm_encoder *encoder = NULL; |
| 762 | struct radeon_encoder *radeon_encoder = NULL; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 763 | u32 pll_clock = mode->clock; |
| 764 | u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; |
| 765 | struct radeon_pll *pll; |
| 766 | u32 adjusted_clock; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 767 | int encoder_mode = 0; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 768 | |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 769 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 770 | if (encoder->crtc == crtc) { |
| 771 | radeon_encoder = to_radeon_encoder(encoder); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 772 | encoder_mode = atombios_get_encoder_mode(encoder); |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 773 | break; |
| 774 | } |
| 775 | } |
| 776 | |
| 777 | if (!radeon_encoder) |
| 778 | return; |
| 779 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 780 | switch (radeon_crtc->pll_id) { |
| 781 | case ATOM_PPLL1: |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 782 | pll = &rdev->clock.p1pll; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 783 | break; |
| 784 | case ATOM_PPLL2: |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 785 | pll = &rdev->clock.p2pll; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 786 | break; |
| 787 | case ATOM_DCPLL: |
| 788 | case ATOM_PPLL_INVALID: |
Stefan Richter | 921d98b | 2010-05-26 10:27:44 +1000 | [diff] [blame] | 789 | default: |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 790 | pll = &rdev->clock.dcpll; |
| 791 | break; |
| 792 | } |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 793 | |
| 794 | /* adjust pixel clock as needed */ |
| 795 | adjusted_clock = atombios_adjust_pll(crtc, mode, pll); |
Alex Deucher | 2606c88 | 2009-10-08 13:36:21 -0400 | [diff] [blame] | 796 | |
Alex Deucher | 7c27f87 | 2010-02-02 12:05:01 -0500 | [diff] [blame] | 797 | radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, |
| 798 | &ref_div, &post_div); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 799 | |
Alex Deucher | 37f9003 | 2010-06-11 17:58:38 -0400 | [diff] [blame] | 800 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
| 801 | encoder_mode, radeon_encoder->encoder_id, mode->clock, |
| 802 | ref_div, fb_div, frac_fb_div, post_div); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 803 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 804 | } |
| 805 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 806 | static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
| 807 | struct drm_framebuffer *old_fb) |
| 808 | { |
| 809 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 810 | struct drm_device *dev = crtc->dev; |
| 811 | struct radeon_device *rdev = dev->dev_private; |
| 812 | struct radeon_framebuffer *radeon_fb; |
| 813 | struct drm_gem_object *obj; |
| 814 | struct radeon_bo *rbo; |
| 815 | uint64_t fb_location; |
| 816 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
| 817 | int r; |
| 818 | |
| 819 | /* no fb bound */ |
| 820 | if (!crtc->fb) { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame^] | 821 | DRM_DEBUG_KMS("No FB bound\n"); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 822 | return 0; |
| 823 | } |
| 824 | |
| 825 | radeon_fb = to_radeon_framebuffer(crtc->fb); |
| 826 | |
| 827 | /* Pin framebuffer & get tilling informations */ |
| 828 | obj = radeon_fb->obj; |
| 829 | rbo = obj->driver_private; |
| 830 | r = radeon_bo_reserve(rbo, false); |
| 831 | if (unlikely(r != 0)) |
| 832 | return r; |
| 833 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); |
| 834 | if (unlikely(r != 0)) { |
| 835 | radeon_bo_unreserve(rbo); |
| 836 | return -EINVAL; |
| 837 | } |
| 838 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
| 839 | radeon_bo_unreserve(rbo); |
| 840 | |
| 841 | switch (crtc->fb->bits_per_pixel) { |
| 842 | case 8: |
| 843 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | |
| 844 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); |
| 845 | break; |
| 846 | case 15: |
| 847 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
| 848 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); |
| 849 | break; |
| 850 | case 16: |
| 851 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
| 852 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); |
| 853 | break; |
| 854 | case 24: |
| 855 | case 32: |
| 856 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | |
| 857 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); |
| 858 | break; |
| 859 | default: |
| 860 | DRM_ERROR("Unsupported screen depth %d\n", |
| 861 | crtc->fb->bits_per_pixel); |
| 862 | return -EINVAL; |
| 863 | } |
| 864 | |
Alex Deucher | 97d6632 | 2010-05-20 12:12:48 -0400 | [diff] [blame] | 865 | if (tiling_flags & RADEON_TILING_MACRO) |
| 866 | fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); |
| 867 | else if (tiling_flags & RADEON_TILING_MICRO) |
| 868 | fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); |
| 869 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 870 | switch (radeon_crtc->crtc_id) { |
| 871 | case 0: |
| 872 | WREG32(AVIVO_D1VGA_CONTROL, 0); |
| 873 | break; |
| 874 | case 1: |
| 875 | WREG32(AVIVO_D2VGA_CONTROL, 0); |
| 876 | break; |
| 877 | case 2: |
| 878 | WREG32(EVERGREEN_D3VGA_CONTROL, 0); |
| 879 | break; |
| 880 | case 3: |
| 881 | WREG32(EVERGREEN_D4VGA_CONTROL, 0); |
| 882 | break; |
| 883 | case 4: |
| 884 | WREG32(EVERGREEN_D5VGA_CONTROL, 0); |
| 885 | break; |
| 886 | case 5: |
| 887 | WREG32(EVERGREEN_D6VGA_CONTROL, 0); |
| 888 | break; |
| 889 | default: |
| 890 | break; |
| 891 | } |
| 892 | |
| 893 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
| 894 | upper_32_bits(fb_location)); |
| 895 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
| 896 | upper_32_bits(fb_location)); |
| 897 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
| 898 | (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); |
| 899 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
| 900 | (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); |
| 901 | WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
| 902 | |
| 903 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
| 904 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
| 905 | WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); |
| 906 | WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
| 907 | WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width); |
| 908 | WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height); |
| 909 | |
| 910 | fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); |
| 911 | WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
| 912 | WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); |
| 913 | |
| 914 | WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
| 915 | crtc->mode.vdisplay); |
| 916 | x &= ~3; |
| 917 | y &= ~1; |
| 918 | WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, |
| 919 | (x << 16) | y); |
| 920 | WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
| 921 | (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); |
| 922 | |
| 923 | if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) |
| 924 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, |
| 925 | EVERGREEN_INTERLEAVE_EN); |
| 926 | else |
| 927 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
| 928 | |
| 929 | if (old_fb && old_fb != crtc->fb) { |
| 930 | radeon_fb = to_radeon_framebuffer(old_fb); |
| 931 | rbo = radeon_fb->obj->driver_private; |
| 932 | r = radeon_bo_reserve(rbo, false); |
| 933 | if (unlikely(r != 0)) |
| 934 | return r; |
| 935 | radeon_bo_unpin(rbo); |
| 936 | radeon_bo_unreserve(rbo); |
| 937 | } |
| 938 | |
| 939 | /* Bytes per pixel may have changed */ |
| 940 | radeon_bandwidth_update(rdev); |
| 941 | |
| 942 | return 0; |
| 943 | } |
| 944 | |
Alex Deucher | 54f088a | 2010-01-19 16:34:01 -0500 | [diff] [blame] | 945 | static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
| 946 | struct drm_framebuffer *old_fb) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 947 | { |
| 948 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 949 | struct drm_device *dev = crtc->dev; |
| 950 | struct radeon_device *rdev = dev->dev_private; |
| 951 | struct radeon_framebuffer *radeon_fb; |
| 952 | struct drm_gem_object *obj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 953 | struct radeon_bo *rbo; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 954 | uint64_t fb_location; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 955 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 956 | int r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 957 | |
Jerome Glisse | 2de3b48 | 2009-11-17 14:08:55 -0800 | [diff] [blame] | 958 | /* no fb bound */ |
| 959 | if (!crtc->fb) { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame^] | 960 | DRM_DEBUG_KMS("No FB bound\n"); |
Jerome Glisse | 2de3b48 | 2009-11-17 14:08:55 -0800 | [diff] [blame] | 961 | return 0; |
| 962 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 963 | |
| 964 | radeon_fb = to_radeon_framebuffer(crtc->fb); |
| 965 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 966 | /* Pin framebuffer & get tilling informations */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 967 | obj = radeon_fb->obj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 968 | rbo = obj->driver_private; |
| 969 | r = radeon_bo_reserve(rbo, false); |
| 970 | if (unlikely(r != 0)) |
| 971 | return r; |
| 972 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); |
| 973 | if (unlikely(r != 0)) { |
| 974 | radeon_bo_unreserve(rbo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 975 | return -EINVAL; |
| 976 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 977 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
| 978 | radeon_bo_unreserve(rbo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 979 | |
| 980 | switch (crtc->fb->bits_per_pixel) { |
Dave Airlie | 41456df | 2009-09-16 10:15:21 +1000 | [diff] [blame] | 981 | case 8: |
| 982 | fb_format = |
| 983 | AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | |
| 984 | AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; |
| 985 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 986 | case 15: |
| 987 | fb_format = |
| 988 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
| 989 | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; |
| 990 | break; |
| 991 | case 16: |
| 992 | fb_format = |
| 993 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
| 994 | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; |
| 995 | break; |
| 996 | case 24: |
| 997 | case 32: |
| 998 | fb_format = |
| 999 | AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | |
| 1000 | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; |
| 1001 | break; |
| 1002 | default: |
| 1003 | DRM_ERROR("Unsupported screen depth %d\n", |
| 1004 | crtc->fb->bits_per_pixel); |
| 1005 | return -EINVAL; |
| 1006 | } |
| 1007 | |
Alex Deucher | 40c4ac1 | 2010-05-20 12:04:59 -0400 | [diff] [blame] | 1008 | if (rdev->family >= CHIP_R600) { |
| 1009 | if (tiling_flags & RADEON_TILING_MACRO) |
| 1010 | fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1; |
| 1011 | else if (tiling_flags & RADEON_TILING_MICRO) |
| 1012 | fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1; |
| 1013 | } else { |
| 1014 | if (tiling_flags & RADEON_TILING_MACRO) |
| 1015 | fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; |
Dave Airlie | cf2f05d | 2009-12-08 15:45:13 +1000 | [diff] [blame] | 1016 | |
Alex Deucher | 40c4ac1 | 2010-05-20 12:04:59 -0400 | [diff] [blame] | 1017 | if (tiling_flags & RADEON_TILING_MICRO) |
| 1018 | fb_format |= AVIVO_D1GRPH_TILED; |
| 1019 | } |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 1020 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1021 | if (radeon_crtc->crtc_id == 0) |
| 1022 | WREG32(AVIVO_D1VGA_CONTROL, 0); |
| 1023 | else |
| 1024 | WREG32(AVIVO_D2VGA_CONTROL, 0); |
Alex Deucher | c290dad | 2009-10-22 16:12:34 -0400 | [diff] [blame] | 1025 | |
| 1026 | if (rdev->family >= CHIP_RV770) { |
| 1027 | if (radeon_crtc->crtc_id) { |
| 1028 | WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0); |
| 1029 | WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0); |
| 1030 | } else { |
| 1031 | WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0); |
| 1032 | WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0); |
| 1033 | } |
| 1034 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1035 | WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
| 1036 | (u32) fb_location); |
| 1037 | WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + |
| 1038 | radeon_crtc->crtc_offset, (u32) fb_location); |
| 1039 | WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
| 1040 | |
| 1041 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
| 1042 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
| 1043 | WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); |
| 1044 | WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
| 1045 | WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width); |
| 1046 | WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height); |
| 1047 | |
| 1048 | fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); |
| 1049 | WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
| 1050 | WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); |
| 1051 | |
| 1052 | WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
| 1053 | crtc->mode.vdisplay); |
| 1054 | x &= ~3; |
| 1055 | y &= ~1; |
| 1056 | WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, |
| 1057 | (x << 16) | y); |
| 1058 | WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
| 1059 | (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); |
| 1060 | |
| 1061 | if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) |
| 1062 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, |
| 1063 | AVIVO_D1MODE_INTERLEAVE_EN); |
| 1064 | else |
| 1065 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
| 1066 | |
| 1067 | if (old_fb && old_fb != crtc->fb) { |
| 1068 | radeon_fb = to_radeon_framebuffer(old_fb); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1069 | rbo = radeon_fb->obj->driver_private; |
| 1070 | r = radeon_bo_reserve(rbo, false); |
| 1071 | if (unlikely(r != 0)) |
| 1072 | return r; |
| 1073 | radeon_bo_unpin(rbo); |
| 1074 | radeon_bo_unreserve(rbo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1075 | } |
Michel Dänzer | f30f37d | 2009-10-08 10:44:09 +0200 | [diff] [blame] | 1076 | |
| 1077 | /* Bytes per pixel may have changed */ |
| 1078 | radeon_bandwidth_update(rdev); |
| 1079 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1080 | return 0; |
| 1081 | } |
| 1082 | |
Alex Deucher | 54f088a | 2010-01-19 16:34:01 -0500 | [diff] [blame] | 1083 | int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
| 1084 | struct drm_framebuffer *old_fb) |
| 1085 | { |
| 1086 | struct drm_device *dev = crtc->dev; |
| 1087 | struct radeon_device *rdev = dev->dev_private; |
| 1088 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1089 | if (ASIC_IS_DCE4(rdev)) |
| 1090 | return evergreen_crtc_set_base(crtc, x, y, old_fb); |
| 1091 | else if (ASIC_IS_AVIVO(rdev)) |
Alex Deucher | 54f088a | 2010-01-19 16:34:01 -0500 | [diff] [blame] | 1092 | return avivo_crtc_set_base(crtc, x, y, old_fb); |
| 1093 | else |
| 1094 | return radeon_crtc_set_base(crtc, x, y, old_fb); |
| 1095 | } |
| 1096 | |
Alex Deucher | 615e0cb | 2010-01-20 16:22:53 -0500 | [diff] [blame] | 1097 | /* properly set additional regs when using atombios */ |
| 1098 | static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) |
| 1099 | { |
| 1100 | struct drm_device *dev = crtc->dev; |
| 1101 | struct radeon_device *rdev = dev->dev_private; |
| 1102 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 1103 | u32 disp_merge_cntl; |
| 1104 | |
| 1105 | switch (radeon_crtc->crtc_id) { |
| 1106 | case 0: |
| 1107 | disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); |
| 1108 | disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; |
| 1109 | WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); |
| 1110 | break; |
| 1111 | case 1: |
| 1112 | disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); |
| 1113 | disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; |
| 1114 | WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); |
| 1115 | WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); |
| 1116 | WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); |
| 1117 | break; |
| 1118 | } |
| 1119 | } |
| 1120 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1121 | static int radeon_atom_pick_pll(struct drm_crtc *crtc) |
| 1122 | { |
| 1123 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 1124 | struct drm_device *dev = crtc->dev; |
| 1125 | struct radeon_device *rdev = dev->dev_private; |
| 1126 | struct drm_encoder *test_encoder; |
| 1127 | struct drm_crtc *test_crtc; |
| 1128 | uint32_t pll_in_use = 0; |
| 1129 | |
| 1130 | if (ASIC_IS_DCE4(rdev)) { |
| 1131 | /* if crtc is driving DP and we have an ext clock, use that */ |
| 1132 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { |
| 1133 | if (test_encoder->crtc && (test_encoder->crtc == crtc)) { |
| 1134 | if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) { |
| 1135 | if (rdev->clock.dp_extclk) |
| 1136 | return ATOM_PPLL_INVALID; |
| 1137 | } |
| 1138 | } |
| 1139 | } |
| 1140 | |
| 1141 | /* otherwise, pick one of the plls */ |
| 1142 | list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { |
| 1143 | struct radeon_crtc *radeon_test_crtc; |
| 1144 | |
| 1145 | if (crtc == test_crtc) |
| 1146 | continue; |
| 1147 | |
| 1148 | radeon_test_crtc = to_radeon_crtc(test_crtc); |
| 1149 | if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) && |
| 1150 | (radeon_test_crtc->pll_id <= ATOM_PPLL2)) |
| 1151 | pll_in_use |= (1 << radeon_test_crtc->pll_id); |
| 1152 | } |
| 1153 | if (!(pll_in_use & 1)) |
| 1154 | return ATOM_PPLL1; |
| 1155 | return ATOM_PPLL2; |
| 1156 | } else |
| 1157 | return radeon_crtc->crtc_id; |
| 1158 | |
| 1159 | } |
| 1160 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1161 | int atombios_crtc_mode_set(struct drm_crtc *crtc, |
| 1162 | struct drm_display_mode *mode, |
| 1163 | struct drm_display_mode *adjusted_mode, |
| 1164 | int x, int y, struct drm_framebuffer *old_fb) |
| 1165 | { |
| 1166 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 1167 | struct drm_device *dev = crtc->dev; |
| 1168 | struct radeon_device *rdev = dev->dev_private; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1169 | |
| 1170 | /* TODO color tiling */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1171 | |
Alex Deucher | b792210 | 2010-03-06 10:57:30 -0500 | [diff] [blame] | 1172 | atombios_disable_ss(crtc); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1173 | /* always set DCPLL */ |
| 1174 | if (ASIC_IS_DCE4(rdev)) |
| 1175 | atombios_crtc_set_dcpll(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1176 | atombios_crtc_set_pll(crtc, adjusted_mode); |
Alex Deucher | b792210 | 2010-03-06 10:57:30 -0500 | [diff] [blame] | 1177 | atombios_enable_ss(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1178 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1179 | if (ASIC_IS_DCE4(rdev)) |
| 1180 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
| 1181 | else if (ASIC_IS_AVIVO(rdev)) |
| 1182 | atombios_crtc_set_timing(crtc, adjusted_mode); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1183 | else { |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1184 | atombios_crtc_set_timing(crtc, adjusted_mode); |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 1185 | if (radeon_crtc->crtc_id == 0) |
| 1186 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
Alex Deucher | 615e0cb | 2010-01-20 16:22:53 -0500 | [diff] [blame] | 1187 | radeon_legacy_atom_fixup(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1188 | } |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1189 | atombios_crtc_set_base(crtc, x, y, old_fb); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1190 | atombios_overscan_setup(crtc, mode, adjusted_mode); |
| 1191 | atombios_scaler_setup(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1192 | return 0; |
| 1193 | } |
| 1194 | |
| 1195 | static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, |
| 1196 | struct drm_display_mode *mode, |
| 1197 | struct drm_display_mode *adjusted_mode) |
| 1198 | { |
Alex Deucher | 03214bd | 2010-03-16 17:42:46 -0400 | [diff] [blame] | 1199 | struct drm_device *dev = crtc->dev; |
| 1200 | struct radeon_device *rdev = dev->dev_private; |
| 1201 | |
| 1202 | /* adjust pm to upcoming mode change */ |
| 1203 | radeon_pm_compute_clocks(rdev); |
| 1204 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1205 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
| 1206 | return false; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1207 | return true; |
| 1208 | } |
| 1209 | |
| 1210 | static void atombios_crtc_prepare(struct drm_crtc *crtc) |
| 1211 | { |
Alex Deucher | 267364a | 2010-03-08 17:10:41 -0500 | [diff] [blame] | 1212 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 1213 | |
| 1214 | /* pick pll */ |
| 1215 | radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); |
| 1216 | |
Alex Deucher | 37b4390 | 2010-02-09 12:04:43 -0500 | [diff] [blame] | 1217 | atombios_lock_crtc(crtc, ATOM_ENABLE); |
Alex Deucher | a348c84 | 2010-01-21 16:50:30 -0500 | [diff] [blame] | 1218 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1219 | } |
| 1220 | |
| 1221 | static void atombios_crtc_commit(struct drm_crtc *crtc) |
| 1222 | { |
| 1223 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
Alex Deucher | 37b4390 | 2010-02-09 12:04:43 -0500 | [diff] [blame] | 1224 | atombios_lock_crtc(crtc, ATOM_DISABLE); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1225 | } |
| 1226 | |
Alex Deucher | 37f9003 | 2010-06-11 17:58:38 -0400 | [diff] [blame] | 1227 | static void atombios_crtc_disable(struct drm_crtc *crtc) |
| 1228 | { |
| 1229 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 1230 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
| 1231 | |
| 1232 | switch (radeon_crtc->pll_id) { |
| 1233 | case ATOM_PPLL1: |
| 1234 | case ATOM_PPLL2: |
| 1235 | /* disable the ppll */ |
| 1236 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
| 1237 | 0, 0, ATOM_DISABLE, 0, 0, 0, 0); |
| 1238 | break; |
| 1239 | default: |
| 1240 | break; |
| 1241 | } |
| 1242 | radeon_crtc->pll_id = -1; |
| 1243 | } |
| 1244 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1245 | static const struct drm_crtc_helper_funcs atombios_helper_funcs = { |
| 1246 | .dpms = atombios_crtc_dpms, |
| 1247 | .mode_fixup = atombios_crtc_mode_fixup, |
| 1248 | .mode_set = atombios_crtc_mode_set, |
| 1249 | .mode_set_base = atombios_crtc_set_base, |
| 1250 | .prepare = atombios_crtc_prepare, |
| 1251 | .commit = atombios_crtc_commit, |
Dave Airlie | 068143d | 2009-10-05 09:58:02 +1000 | [diff] [blame] | 1252 | .load_lut = radeon_crtc_load_lut, |
Alex Deucher | 37f9003 | 2010-06-11 17:58:38 -0400 | [diff] [blame] | 1253 | .disable = atombios_crtc_disable, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1254 | }; |
| 1255 | |
| 1256 | void radeon_atombios_init_crtc(struct drm_device *dev, |
| 1257 | struct radeon_crtc *radeon_crtc) |
| 1258 | { |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1259 | struct radeon_device *rdev = dev->dev_private; |
| 1260 | |
| 1261 | if (ASIC_IS_DCE4(rdev)) { |
| 1262 | switch (radeon_crtc->crtc_id) { |
| 1263 | case 0: |
| 1264 | default: |
Alex Deucher | 12d7798 | 2010-02-09 17:18:48 -0500 | [diff] [blame] | 1265 | radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1266 | break; |
| 1267 | case 1: |
Alex Deucher | 12d7798 | 2010-02-09 17:18:48 -0500 | [diff] [blame] | 1268 | radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1269 | break; |
| 1270 | case 2: |
Alex Deucher | 12d7798 | 2010-02-09 17:18:48 -0500 | [diff] [blame] | 1271 | radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1272 | break; |
| 1273 | case 3: |
Alex Deucher | 12d7798 | 2010-02-09 17:18:48 -0500 | [diff] [blame] | 1274 | radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1275 | break; |
| 1276 | case 4: |
Alex Deucher | 12d7798 | 2010-02-09 17:18:48 -0500 | [diff] [blame] | 1277 | radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1278 | break; |
| 1279 | case 5: |
Alex Deucher | 12d7798 | 2010-02-09 17:18:48 -0500 | [diff] [blame] | 1280 | radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1281 | break; |
| 1282 | } |
| 1283 | } else { |
| 1284 | if (radeon_crtc->crtc_id == 1) |
| 1285 | radeon_crtc->crtc_offset = |
| 1286 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; |
| 1287 | else |
| 1288 | radeon_crtc->crtc_offset = 0; |
| 1289 | } |
| 1290 | radeon_crtc->pll_id = -1; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1291 | drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); |
| 1292 | } |