blob: a0241fe72d8b79f0cbeabbe31955becd6eaa7906 [file] [log] [blame]
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001/******************************************************************************
2 * This software may be used and distributed according to the terms of
3 * the GNU General Public License (GPL), incorporated herein by reference.
4 * Drivers based on or derived from this code fall under the GPL and must
5 * retain the authorship, copyright and license notice. This file is not
6 * a complete program and may only be used when the entire operating
7 * system is licensed under the GPL.
8 * See the file COPYING in this distribution for more information.
9 *
Jon Mason926bd902010-07-15 08:47:26 +000010 * vxge-config.c: Driver for Exar Corp's X3100 Series 10GbE PCIe I/O
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +000011 * Virtualized Server Adapter.
Jon Mason926bd902010-07-15 08:47:26 +000012 * Copyright(c) 2002-2010 Exar Corp.
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +000013 ******************************************************************************/
14#include <linux/vmalloc.h>
15#include <linux/etherdevice.h>
16#include <linux/pci.h>
17#include <linux/pci_hotplug.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090018#include <linux/slab.h>
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +000019
20#include "vxge-traffic.h"
21#include "vxge-config.h"
Jon Mason8424e002010-11-11 04:25:56 +000022#include "vxge-main.h"
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +000023
stephen hemminger42821a52010-10-21 07:50:53 +000024static enum vxge_hw_status
stephen hemminger42821a52010-10-21 07:50:53 +000025__vxge_hw_fifo_delete(
26 struct __vxge_hw_vpath_handle *vpath_handle);
27
28static struct __vxge_hw_blockpool_entry *
29__vxge_hw_blockpool_block_allocate(struct __vxge_hw_device *hldev,
30 u32 size);
31
32static void
33__vxge_hw_blockpool_block_free(struct __vxge_hw_device *hldev,
34 struct __vxge_hw_blockpool_entry *entry);
35
36static void vxge_hw_blockpool_block_add(struct __vxge_hw_device *devh,
37 void *block_addr,
38 u32 length,
39 struct pci_dev *dma_h,
40 struct pci_dev *acc_handle);
41
42static enum vxge_hw_status
43__vxge_hw_blockpool_create(struct __vxge_hw_device *hldev,
44 struct __vxge_hw_blockpool *blockpool,
45 u32 pool_size,
46 u32 pool_max);
47
48static void
49__vxge_hw_blockpool_destroy(struct __vxge_hw_blockpool *blockpool);
50
51static void *
52__vxge_hw_blockpool_malloc(struct __vxge_hw_device *hldev,
53 u32 size,
54 struct vxge_hw_mempool_dma *dma_object);
55
56static void
57__vxge_hw_blockpool_free(struct __vxge_hw_device *hldev,
58 void *memblock,
59 u32 size,
60 struct vxge_hw_mempool_dma *dma_object);
61
stephen hemminger42821a52010-10-21 07:50:53 +000062static void
63__vxge_hw_channel_free(
64 struct __vxge_hw_channel *channel);
65
stephen hemminger42821a52010-10-21 07:50:53 +000066static enum vxge_hw_status __vxge_hw_ring_delete(struct __vxge_hw_vpath_handle *vp);
67
68static enum vxge_hw_status
stephen hemminger42821a52010-10-21 07:50:53 +000069__vxge_hw_device_config_check(struct vxge_hw_device_config *new_config);
70
stephen hemminger42821a52010-10-21 07:50:53 +000071static enum vxge_hw_status
72__vxge_hw_device_register_poll(
73 void __iomem *reg,
74 u64 mask, u32 max_millis);
75
76static inline enum vxge_hw_status
77__vxge_hw_pio_mem_write64(u64 val64, void __iomem *addr,
78 u64 mask, u32 max_millis)
79{
80 __vxge_hw_pio_mem_write32_lower((u32)vxge_bVALn(val64, 32, 32), addr);
81 wmb();
82
83 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), addr);
84 wmb();
85
86 return __vxge_hw_device_register_poll(addr, mask, max_millis);
87}
88
89static struct vxge_hw_mempool*
90__vxge_hw_mempool_create(struct __vxge_hw_device *devh, u32 memblock_size,
Jon Mason2c913082010-11-11 04:26:03 +000091 u32 item_size, u32 private_size, u32 items_initial,
92 u32 items_max, struct vxge_hw_mempool_cbs *mp_callback,
93 void *userdata);
94
stephen hemminger42821a52010-10-21 07:50:53 +000095static void __vxge_hw_mempool_destroy(struct vxge_hw_mempool *mempool);
96
97static enum vxge_hw_status
98__vxge_hw_vpath_stats_get(struct __vxge_hw_virtualpath *vpath,
99 struct vxge_hw_vpath_stats_hw_info *hw_stats);
100
101static enum vxge_hw_status
102vxge_hw_vpath_stats_enable(struct __vxge_hw_vpath_handle *vpath_handle);
103
104static enum vxge_hw_status
105__vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg);
106
stephen hemminger42821a52010-10-21 07:50:53 +0000107static void
108__vxge_hw_vp_terminate(struct __vxge_hw_device *devh, u32 vp_id);
109
110static enum vxge_hw_status
stephen hemminger42821a52010-10-21 07:50:53 +0000111__vxge_hw_vpath_xmac_tx_stats_get(struct __vxge_hw_virtualpath *vpath,
112 struct vxge_hw_xmac_vpath_tx_stats *vpath_tx_stats);
113
114static enum vxge_hw_status
115__vxge_hw_vpath_xmac_rx_stats_get(struct __vxge_hw_virtualpath *vpath,
116 struct vxge_hw_xmac_vpath_rx_stats *vpath_rx_stats);
117
Jon Mason4d2a5b42010-11-11 04:25:54 +0000118static void
119vxge_hw_vpath_set_zero_rx_frm_len(struct vxge_hw_vpath_reg __iomem *vp_reg)
120{
121 u64 val64;
122
123 val64 = readq(&vp_reg->rxmac_vcfg0);
124 val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
125 writeq(val64, &vp_reg->rxmac_vcfg0);
126 val64 = readq(&vp_reg->rxmac_vcfg0);
127
128 return;
129}
130
131/*
132 * vxge_hw_vpath_wait_receive_idle - Wait for Rx to become idle
133 */
134int vxge_hw_vpath_wait_receive_idle(struct __vxge_hw_device *hldev, u32 vp_id)
135{
136 struct vxge_hw_vpath_reg __iomem *vp_reg;
137 struct __vxge_hw_virtualpath *vpath;
138 u64 val64, rxd_count, rxd_spat;
139 int count = 0, total_count = 0;
140
141 vpath = &hldev->virtual_paths[vp_id];
142 vp_reg = vpath->vp_reg;
143
144 vxge_hw_vpath_set_zero_rx_frm_len(vp_reg);
145
146 /* Check that the ring controller for this vpath has enough free RxDs
147 * to send frames to the host. This is done by reading the
148 * PRC_RXD_DOORBELL_VPn register and comparing the read value to the
149 * RXD_SPAT value for the vpath.
150 */
151 val64 = readq(&vp_reg->prc_cfg6);
152 rxd_spat = VXGE_HW_PRC_CFG6_GET_RXD_SPAT(val64) + 1;
153 /* Use a factor of 2 when comparing rxd_count against rxd_spat for some
154 * leg room.
155 */
156 rxd_spat *= 2;
157
158 do {
159 mdelay(1);
160
161 rxd_count = readq(&vp_reg->prc_rxd_doorbell);
162
163 /* Check that the ring controller for this vpath does
164 * not have any frame in its pipeline.
165 */
166 val64 = readq(&vp_reg->frm_in_progress_cnt);
167 if ((rxd_count <= rxd_spat) || (val64 > 0))
168 count = 0;
169 else
170 count++;
171 total_count++;
172 } while ((count < VXGE_HW_MIN_SUCCESSIVE_IDLE_COUNT) &&
173 (total_count < VXGE_HW_MAX_POLLING_COUNT));
174
175 if (total_count >= VXGE_HW_MAX_POLLING_COUNT)
176 printk(KERN_ALERT "%s: Still Receiving traffic. Abort wait\n",
177 __func__);
178
179 return total_count;
180}
181
182/* vxge_hw_device_wait_receive_idle - This function waits until all frames
183 * stored in the frame buffer for each vpath assigned to the given
184 * function (hldev) have been sent to the host.
185 */
186void vxge_hw_device_wait_receive_idle(struct __vxge_hw_device *hldev)
187{
188 int i, total_count = 0;
189
190 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
191 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
192 continue;
193
194 total_count += vxge_hw_vpath_wait_receive_idle(hldev, i);
195 if (total_count >= VXGE_HW_MAX_POLLING_COUNT)
196 break;
197 }
198}
199
Jon Mason8424e002010-11-11 04:25:56 +0000200static enum vxge_hw_status
201vxge_hw_vpath_fw_api(struct __vxge_hw_virtualpath *vpath, u32 action,
202 u32 fw_memo, u32 offset, u64 *data0, u64 *data1,
203 u64 *steer_ctrl)
204{
205 struct vxge_hw_vpath_reg __iomem *vp_reg;
206 enum vxge_hw_status status;
207 u64 val64;
208 u32 retry = 0, max_retry = 100;
209
210 vp_reg = vpath->vp_reg;
211
212 if (vpath->vp_open) {
213 max_retry = 3;
214 spin_lock(&vpath->lock);
215 }
216
217 writeq(*data0, &vp_reg->rts_access_steer_data0);
218 writeq(*data1, &vp_reg->rts_access_steer_data1);
219 wmb();
220
221 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) |
222 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(fw_memo) |
223 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(offset) |
224 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
225 *steer_ctrl;
226
227 status = __vxge_hw_pio_mem_write64(val64,
228 &vp_reg->rts_access_steer_ctrl,
229 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
230 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
231
232 /* The __vxge_hw_device_register_poll can udelay for a significant
233 * amount of time, blocking other proccess from the CPU. If it delays
234 * for ~5secs, a NMI error can occur. A way around this is to give up
235 * the processor via msleep, but this is not allowed is under lock.
236 * So, only allow it to sleep for ~4secs if open. Otherwise, delay for
237 * 1sec and sleep for 10ms until the firmware operation has completed
238 * or timed-out.
239 */
240 while ((status != VXGE_HW_OK) && retry++ < max_retry) {
241 if (!vpath->vp_open)
242 msleep(20);
243 status = __vxge_hw_device_register_poll(
244 &vp_reg->rts_access_steer_ctrl,
245 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
246 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
247 }
248
249 if (status != VXGE_HW_OK)
250 goto out;
251
252 val64 = readq(&vp_reg->rts_access_steer_ctrl);
253 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
254 *data0 = readq(&vp_reg->rts_access_steer_data0);
255 *data1 = readq(&vp_reg->rts_access_steer_data1);
256 *steer_ctrl = val64;
257 } else
258 status = VXGE_HW_FAIL;
259
260out:
261 if (vpath->vp_open)
262 spin_unlock(&vpath->lock);
263 return status;
264}
265
Jon Masone8ac1752010-11-11 04:25:57 +0000266enum vxge_hw_status
267vxge_hw_upgrade_read_version(struct __vxge_hw_device *hldev, u32 *major,
268 u32 *minor, u32 *build)
269{
270 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
271 struct __vxge_hw_virtualpath *vpath;
272 enum vxge_hw_status status;
273
274 vpath = &hldev->virtual_paths[hldev->first_vp_id];
275
276 status = vxge_hw_vpath_fw_api(vpath,
277 VXGE_HW_FW_UPGRADE_ACTION,
278 VXGE_HW_FW_UPGRADE_MEMO,
279 VXGE_HW_FW_UPGRADE_OFFSET_READ,
280 &data0, &data1, &steer_ctrl);
281 if (status != VXGE_HW_OK)
282 return status;
283
284 *major = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data0);
285 *minor = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data0);
286 *build = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data0);
287
288 return status;
289}
290
291enum vxge_hw_status vxge_hw_flash_fw(struct __vxge_hw_device *hldev)
292{
293 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
294 struct __vxge_hw_virtualpath *vpath;
295 enum vxge_hw_status status;
296 u32 ret;
297
298 vpath = &hldev->virtual_paths[hldev->first_vp_id];
299
300 status = vxge_hw_vpath_fw_api(vpath,
301 VXGE_HW_FW_UPGRADE_ACTION,
302 VXGE_HW_FW_UPGRADE_MEMO,
303 VXGE_HW_FW_UPGRADE_OFFSET_COMMIT,
304 &data0, &data1, &steer_ctrl);
305 if (status != VXGE_HW_OK) {
306 vxge_debug_init(VXGE_ERR, "%s: FW upgrade failed", __func__);
307 goto exit;
308 }
309
310 ret = VXGE_HW_RTS_ACCESS_STEER_CTRL_GET_ACTION(steer_ctrl) & 0x7F;
311 if (ret != 1) {
312 vxge_debug_init(VXGE_ERR, "%s: FW commit failed with error %d",
313 __func__, ret);
314 status = VXGE_HW_FAIL;
315 }
316
317exit:
318 return status;
319}
320
321enum vxge_hw_status
322vxge_update_fw_image(struct __vxge_hw_device *hldev, const u8 *fwdata, int size)
323{
324 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
325 struct __vxge_hw_virtualpath *vpath;
326 enum vxge_hw_status status;
327 int ret_code, sec_code;
328
329 vpath = &hldev->virtual_paths[hldev->first_vp_id];
330
331 /* send upgrade start command */
332 status = vxge_hw_vpath_fw_api(vpath,
333 VXGE_HW_FW_UPGRADE_ACTION,
334 VXGE_HW_FW_UPGRADE_MEMO,
335 VXGE_HW_FW_UPGRADE_OFFSET_START,
336 &data0, &data1, &steer_ctrl);
337 if (status != VXGE_HW_OK) {
338 vxge_debug_init(VXGE_ERR, " %s: Upgrade start cmd failed",
339 __func__);
340 return status;
341 }
342
343 /* Transfer fw image to adapter 16 bytes at a time */
344 for (; size > 0; size -= VXGE_HW_FW_UPGRADE_BLK_SIZE) {
345 steer_ctrl = 0;
346
347 /* The next 128bits of fwdata to be loaded onto the adapter */
348 data0 = *((u64 *)fwdata);
349 data1 = *((u64 *)fwdata + 1);
350
351 status = vxge_hw_vpath_fw_api(vpath,
352 VXGE_HW_FW_UPGRADE_ACTION,
353 VXGE_HW_FW_UPGRADE_MEMO,
354 VXGE_HW_FW_UPGRADE_OFFSET_SEND,
355 &data0, &data1, &steer_ctrl);
356 if (status != VXGE_HW_OK) {
357 vxge_debug_init(VXGE_ERR, "%s: Upgrade send failed",
358 __func__);
359 goto out;
360 }
361
362 ret_code = VXGE_HW_UPGRADE_GET_RET_ERR_CODE(data0);
363 switch (ret_code) {
364 case VXGE_HW_FW_UPGRADE_OK:
365 /* All OK, send next 16 bytes. */
366 break;
367 case VXGE_FW_UPGRADE_BYTES2SKIP:
368 /* skip bytes in the stream */
369 fwdata += (data0 >> 8) & 0xFFFFFFFF;
370 break;
371 case VXGE_HW_FW_UPGRADE_DONE:
372 goto out;
373 case VXGE_HW_FW_UPGRADE_ERR:
374 sec_code = VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(data0);
375 switch (sec_code) {
376 case VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_1:
377 case VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_7:
378 printk(KERN_ERR
379 "corrupted data from .ncf file\n");
380 break;
381 case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_3:
382 case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_4:
383 case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_5:
384 case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_6:
385 case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_8:
386 printk(KERN_ERR "invalid .ncf file\n");
387 break;
388 case VXGE_HW_FW_UPGRADE_ERR_BUFFER_OVERFLOW:
389 printk(KERN_ERR "buffer overflow\n");
390 break;
391 case VXGE_HW_FW_UPGRADE_ERR_FAILED_TO_FLASH:
392 printk(KERN_ERR "failed to flash the image\n");
393 break;
394 case VXGE_HW_FW_UPGRADE_ERR_GENERIC_ERROR_UNKNOWN:
395 printk(KERN_ERR
396 "generic error. Unknown error type\n");
397 break;
398 default:
399 printk(KERN_ERR "Unknown error of type %d\n",
400 sec_code);
401 break;
402 }
403 status = VXGE_HW_FAIL;
404 goto out;
405 default:
406 printk(KERN_ERR "Unknown FW error: %d\n", ret_code);
407 status = VXGE_HW_FAIL;
408 goto out;
409 }
410 /* point to next 16 bytes */
411 fwdata += VXGE_HW_FW_UPGRADE_BLK_SIZE;
412 }
413out:
414 return status;
415}
416
417enum vxge_hw_status
418vxge_hw_vpath_eprom_img_ver_get(struct __vxge_hw_device *hldev,
419 struct eprom_image *img)
420{
421 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
422 struct __vxge_hw_virtualpath *vpath;
423 enum vxge_hw_status status;
424 int i;
425
426 vpath = &hldev->virtual_paths[hldev->first_vp_id];
427
428 for (i = 0; i < VXGE_HW_MAX_ROM_IMAGES; i++) {
429 data0 = VXGE_HW_RTS_ACCESS_STEER_ROM_IMAGE_INDEX(i);
430 data1 = steer_ctrl = 0;
431
432 status = vxge_hw_vpath_fw_api(vpath,
433 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
434 VXGE_HW_FW_API_GET_EPROM_REV,
435 0, &data0, &data1, &steer_ctrl);
436 if (status != VXGE_HW_OK)
437 break;
438
439 img[i].is_valid = VXGE_HW_GET_EPROM_IMAGE_VALID(data0);
440 img[i].index = VXGE_HW_GET_EPROM_IMAGE_INDEX(data0);
441 img[i].type = VXGE_HW_GET_EPROM_IMAGE_TYPE(data0);
442 img[i].version = VXGE_HW_GET_EPROM_IMAGE_REV(data0);
443 }
444
445 return status;
446}
447
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000448/*
449 * __vxge_hw_channel_allocate - Allocate memory for channel
450 * This function allocates required memory for the channel and various arrays
451 * in the channel
452 */
Jon Mason2c913082010-11-11 04:26:03 +0000453static struct __vxge_hw_channel *
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000454__vxge_hw_channel_allocate(struct __vxge_hw_vpath_handle *vph,
455 enum __vxge_hw_channel_type type,
456 u32 length, u32 per_dtr_space, void *userdata)
457{
458 struct __vxge_hw_channel *channel;
459 struct __vxge_hw_device *hldev;
460 int size = 0;
461 u32 vp_id;
462
463 hldev = vph->vpath->hldev;
464 vp_id = vph->vpath->vp_id;
465
466 switch (type) {
467 case VXGE_HW_CHANNEL_TYPE_FIFO:
468 size = sizeof(struct __vxge_hw_fifo);
469 break;
470 case VXGE_HW_CHANNEL_TYPE_RING:
471 size = sizeof(struct __vxge_hw_ring);
472 break;
473 default:
474 break;
475 }
476
477 channel = kzalloc(size, GFP_KERNEL);
478 if (channel == NULL)
479 goto exit0;
480 INIT_LIST_HEAD(&channel->item);
481
482 channel->common_reg = hldev->common_reg;
483 channel->first_vp_id = hldev->first_vp_id;
484 channel->type = type;
485 channel->devh = hldev;
486 channel->vph = vph;
487 channel->userdata = userdata;
488 channel->per_dtr_space = per_dtr_space;
489 channel->length = length;
490 channel->vp_id = vp_id;
491
492 channel->work_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
493 if (channel->work_arr == NULL)
494 goto exit1;
495
496 channel->free_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
497 if (channel->free_arr == NULL)
498 goto exit1;
499 channel->free_ptr = length;
500
501 channel->reserve_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
502 if (channel->reserve_arr == NULL)
503 goto exit1;
504 channel->reserve_ptr = length;
505 channel->reserve_top = 0;
506
507 channel->orig_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
508 if (channel->orig_arr == NULL)
509 goto exit1;
510
511 return channel;
512exit1:
513 __vxge_hw_channel_free(channel);
514
515exit0:
516 return NULL;
517}
518
519/*
520 * __vxge_hw_channel_free - Free memory allocated for channel
521 * This function deallocates memory from the channel and various arrays
522 * in the channel
523 */
Jon Mason2c913082010-11-11 04:26:03 +0000524static void __vxge_hw_channel_free(struct __vxge_hw_channel *channel)
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000525{
526 kfree(channel->work_arr);
527 kfree(channel->free_arr);
528 kfree(channel->reserve_arr);
529 kfree(channel->orig_arr);
530 kfree(channel);
531}
532
533/*
534 * __vxge_hw_channel_initialize - Initialize a channel
535 * This function initializes a channel by properly setting the
536 * various references
537 */
Jon Mason2c913082010-11-11 04:26:03 +0000538static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000539__vxge_hw_channel_initialize(struct __vxge_hw_channel *channel)
540{
541 u32 i;
542 struct __vxge_hw_virtualpath *vpath;
543
544 vpath = channel->vph->vpath;
545
546 if ((channel->reserve_arr != NULL) && (channel->orig_arr != NULL)) {
547 for (i = 0; i < channel->length; i++)
548 channel->orig_arr[i] = channel->reserve_arr[i];
549 }
550
551 switch (channel->type) {
552 case VXGE_HW_CHANNEL_TYPE_FIFO:
553 vpath->fifoh = (struct __vxge_hw_fifo *)channel;
554 channel->stats = &((struct __vxge_hw_fifo *)
555 channel)->stats->common_stats;
556 break;
557 case VXGE_HW_CHANNEL_TYPE_RING:
558 vpath->ringh = (struct __vxge_hw_ring *)channel;
559 channel->stats = &((struct __vxge_hw_ring *)
560 channel)->stats->common_stats;
561 break;
562 default:
563 break;
564 }
565
566 return VXGE_HW_OK;
567}
568
569/*
570 * __vxge_hw_channel_reset - Resets a channel
571 * This function resets a channel by properly setting the various references
572 */
Jon Mason2c913082010-11-11 04:26:03 +0000573static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000574__vxge_hw_channel_reset(struct __vxge_hw_channel *channel)
575{
576 u32 i;
577
578 for (i = 0; i < channel->length; i++) {
579 if (channel->reserve_arr != NULL)
580 channel->reserve_arr[i] = channel->orig_arr[i];
581 if (channel->free_arr != NULL)
582 channel->free_arr[i] = NULL;
583 if (channel->work_arr != NULL)
584 channel->work_arr[i] = NULL;
585 }
586 channel->free_ptr = channel->length;
587 channel->reserve_ptr = channel->length;
588 channel->reserve_top = 0;
589 channel->post_index = 0;
590 channel->compl_index = 0;
591
592 return VXGE_HW_OK;
593}
594
595/*
596 * __vxge_hw_device_pci_e_init
597 * Initialize certain PCI/PCI-X configuration registers
598 * with recommended values. Save config space for future hw resets.
599 */
Jon Mason2c913082010-11-11 04:26:03 +0000600static void __vxge_hw_device_pci_e_init(struct __vxge_hw_device *hldev)
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000601{
602 u16 cmd = 0;
603
604 /* Set the PErr Repconse bit and SERR in PCI command register. */
605 pci_read_config_word(hldev->pdev, PCI_COMMAND, &cmd);
606 cmd |= 0x140;
607 pci_write_config_word(hldev->pdev, PCI_COMMAND, cmd);
608
609 pci_save_state(hldev->pdev);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000610}
611
612/*
613 * __vxge_hw_device_register_poll
614 * Will poll certain register for specified amount of time.
615 * Will poll until masked bit is not cleared.
616 */
stephen hemminger42821a52010-10-21 07:50:53 +0000617static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000618__vxge_hw_device_register_poll(void __iomem *reg, u64 mask, u32 max_millis)
619{
620 u64 val64;
621 u32 i = 0;
622 enum vxge_hw_status ret = VXGE_HW_FAIL;
623
624 udelay(10);
625
626 do {
627 val64 = readq(reg);
628 if (!(val64 & mask))
629 return VXGE_HW_OK;
630 udelay(100);
631 } while (++i <= 9);
632
633 i = 0;
634 do {
635 val64 = readq(reg);
636 if (!(val64 & mask))
637 return VXGE_HW_OK;
638 mdelay(1);
639 } while (++i <= max_millis);
640
641 return ret;
642}
643
Jon Mason4d2a5b42010-11-11 04:25:54 +0000644/* __vxge_hw_device_vpath_reset_in_prog_check - Check if vpath reset
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000645 * in progress
646 * This routine checks the vpath reset in progress register is turned zero
647 */
stephen hemminger42821a52010-10-21 07:50:53 +0000648static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000649__vxge_hw_device_vpath_reset_in_prog_check(u64 __iomem *vpath_rst_in_prog)
650{
651 enum vxge_hw_status status;
652 status = __vxge_hw_device_register_poll(vpath_rst_in_prog,
653 VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(0x1ffff),
654 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
655 return status;
656}
657
658/*
659 * __vxge_hw_device_toc_get
660 * This routine sets the swapper and reads the toc pointer and returns the
661 * memory mapped address of the toc
662 */
stephen hemminger42821a52010-10-21 07:50:53 +0000663static struct vxge_hw_toc_reg __iomem *
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000664__vxge_hw_device_toc_get(void __iomem *bar0)
665{
666 u64 val64;
667 struct vxge_hw_toc_reg __iomem *toc = NULL;
668 enum vxge_hw_status status;
669
670 struct vxge_hw_legacy_reg __iomem *legacy_reg =
671 (struct vxge_hw_legacy_reg __iomem *)bar0;
672
673 status = __vxge_hw_legacy_swapper_set(legacy_reg);
674 if (status != VXGE_HW_OK)
675 goto exit;
676
677 val64 = readq(&legacy_reg->toc_first_pointer);
678 toc = (struct vxge_hw_toc_reg __iomem *)(bar0+val64);
679exit:
680 return toc;
681}
682
683/*
684 * __vxge_hw_device_reg_addr_get
685 * This routine sets the swapper and reads the toc pointer and initializes the
686 * register location pointers in the device object. It waits until the ric is
687 * completed initializing registers.
688 */
Jon Mason2c913082010-11-11 04:26:03 +0000689static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000690__vxge_hw_device_reg_addr_get(struct __vxge_hw_device *hldev)
691{
692 u64 val64;
693 u32 i;
694 enum vxge_hw_status status = VXGE_HW_OK;
695
696 hldev->legacy_reg = (struct vxge_hw_legacy_reg __iomem *)hldev->bar0;
697
698 hldev->toc_reg = __vxge_hw_device_toc_get(hldev->bar0);
699 if (hldev->toc_reg == NULL) {
700 status = VXGE_HW_FAIL;
701 goto exit;
702 }
703
704 val64 = readq(&hldev->toc_reg->toc_common_pointer);
705 hldev->common_reg =
706 (struct vxge_hw_common_reg __iomem *)(hldev->bar0 + val64);
707
708 val64 = readq(&hldev->toc_reg->toc_mrpcim_pointer);
709 hldev->mrpcim_reg =
710 (struct vxge_hw_mrpcim_reg __iomem *)(hldev->bar0 + val64);
711
712 for (i = 0; i < VXGE_HW_TITAN_SRPCIM_REG_SPACES; i++) {
713 val64 = readq(&hldev->toc_reg->toc_srpcim_pointer[i]);
714 hldev->srpcim_reg[i] =
715 (struct vxge_hw_srpcim_reg __iomem *)
716 (hldev->bar0 + val64);
717 }
718
719 for (i = 0; i < VXGE_HW_TITAN_VPMGMT_REG_SPACES; i++) {
720 val64 = readq(&hldev->toc_reg->toc_vpmgmt_pointer[i]);
721 hldev->vpmgmt_reg[i] =
722 (struct vxge_hw_vpmgmt_reg __iomem *)(hldev->bar0 + val64);
723 }
724
725 for (i = 0; i < VXGE_HW_TITAN_VPATH_REG_SPACES; i++) {
726 val64 = readq(&hldev->toc_reg->toc_vpath_pointer[i]);
727 hldev->vpath_reg[i] =
728 (struct vxge_hw_vpath_reg __iomem *)
729 (hldev->bar0 + val64);
730 }
731
732 val64 = readq(&hldev->toc_reg->toc_kdfc);
733
734 switch (VXGE_HW_TOC_GET_KDFC_INITIAL_BIR(val64)) {
735 case 0:
736 hldev->kdfc = (u8 __iomem *)(hldev->bar0 +
737 VXGE_HW_TOC_GET_KDFC_INITIAL_OFFSET(val64));
738 break;
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000739 default:
740 break;
741 }
742
743 status = __vxge_hw_device_vpath_reset_in_prog_check(
744 (u64 __iomem *)&hldev->common_reg->vpath_rst_in_prog);
745exit:
746 return status;
747}
748
749/*
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000750 * __vxge_hw_device_access_rights_get: Get Access Rights of the driver
751 * This routine returns the Access Rights of the driver
752 */
753static u32
754__vxge_hw_device_access_rights_get(u32 host_type, u32 func_id)
755{
756 u32 access_rights = VXGE_HW_DEVICE_ACCESS_RIGHT_VPATH;
757
758 switch (host_type) {
759 case VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION:
Sreenivasa Honnur1dc47a92010-03-28 22:12:33 +0000760 if (func_id == 0) {
761 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
762 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
763 }
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000764 break;
765 case VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION:
766 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
767 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
768 break;
769 case VXGE_HW_NO_MR_SR_VH0_FUNCTION0:
770 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
771 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
772 break;
773 case VXGE_HW_NO_MR_SR_VH0_VIRTUAL_FUNCTION:
774 case VXGE_HW_SR_VH_VIRTUAL_FUNCTION:
775 case VXGE_HW_MR_SR_VH0_INVALID_CONFIG:
776 break;
777 case VXGE_HW_SR_VH_FUNCTION0:
778 case VXGE_HW_VH_NORMAL_FUNCTION:
779 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
780 break;
781 }
782
783 return access_rights;
784}
785/*
Sreenivasa Honnur92cdd7c2009-10-05 01:51:38 +0000786 * __vxge_hw_device_is_privilaged
787 * This routine checks if the device function is privilaged or not
788 */
789
790enum vxge_hw_status
791__vxge_hw_device_is_privilaged(u32 host_type, u32 func_id)
792{
793 if (__vxge_hw_device_access_rights_get(host_type,
794 func_id) &
795 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)
796 return VXGE_HW_OK;
797 else
798 return VXGE_HW_ERR_PRIVILAGED_OPEARATION;
799}
800
801/*
Jon Mason8424e002010-11-11 04:25:56 +0000802 * __vxge_hw_vpath_func_id_get - Get the function id of the vpath.
803 * Returns the function number of the vpath.
804 */
805static u32
806__vxge_hw_vpath_func_id_get(struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg)
807{
808 u64 val64;
809
810 val64 = readq(&vpmgmt_reg->vpath_to_func_map_cfg1);
811
812 return
813 (u32)VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(val64);
814}
815
816/*
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000817 * __vxge_hw_device_host_info_get
818 * This routine returns the host type assignments
819 */
Jon Mason8424e002010-11-11 04:25:56 +0000820static void __vxge_hw_device_host_info_get(struct __vxge_hw_device *hldev)
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000821{
822 u64 val64;
823 u32 i;
824
825 val64 = readq(&hldev->common_reg->host_type_assignments);
826
827 hldev->host_type =
828 (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
829
830 hldev->vpath_assignments = readq(&hldev->common_reg->vpath_assignments);
831
832 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000833 if (!(hldev->vpath_assignments & vxge_mBIT(i)))
834 continue;
835
836 hldev->func_id =
Jon Mason8424e002010-11-11 04:25:56 +0000837 __vxge_hw_vpath_func_id_get(hldev->vpmgmt_reg[i]);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000838
839 hldev->access_rights = __vxge_hw_device_access_rights_get(
840 hldev->host_type, hldev->func_id);
841
Jon Mason8424e002010-11-11 04:25:56 +0000842 hldev->virtual_paths[i].vp_open = VXGE_HW_VP_NOT_OPEN;
843 hldev->virtual_paths[i].vp_reg = hldev->vpath_reg[i];
844
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000845 hldev->first_vp_id = i;
846 break;
847 }
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000848}
849
850/*
851 * __vxge_hw_verify_pci_e_info - Validate the pci-e link parameters such as
852 * link width and signalling rate.
853 */
854static enum vxge_hw_status
855__vxge_hw_verify_pci_e_info(struct __vxge_hw_device *hldev)
856{
857 int exp_cap;
858 u16 lnk;
859
860 /* Get the negotiated link width and speed from PCI config space */
861 exp_cap = pci_find_capability(hldev->pdev, PCI_CAP_ID_EXP);
862 pci_read_config_word(hldev->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
863
864 if ((lnk & PCI_EXP_LNKSTA_CLS) != 1)
865 return VXGE_HW_ERR_INVALID_PCI_INFO;
866
867 switch ((lnk & PCI_EXP_LNKSTA_NLW) >> 4) {
868 case PCIE_LNK_WIDTH_RESRV:
869 case PCIE_LNK_X1:
870 case PCIE_LNK_X2:
871 case PCIE_LNK_X4:
872 case PCIE_LNK_X8:
873 break;
874 default:
875 return VXGE_HW_ERR_INVALID_PCI_INFO;
876 }
877
878 return VXGE_HW_OK;
879}
880
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000881/*
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000882 * __vxge_hw_device_initialize
883 * Initialize Titan-V hardware.
884 */
Jon Mason2c913082010-11-11 04:26:03 +0000885static enum vxge_hw_status
886__vxge_hw_device_initialize(struct __vxge_hw_device *hldev)
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000887{
888 enum vxge_hw_status status = VXGE_HW_OK;
889
Sreenivasa Honnur92cdd7c2009-10-05 01:51:38 +0000890 if (VXGE_HW_OK == __vxge_hw_device_is_privilaged(hldev->host_type,
891 hldev->func_id)) {
Sivakumar Subramani5dbc9012009-06-16 18:48:55 +0000892 /* Validate the pci-e link width and speed */
893 status = __vxge_hw_verify_pci_e_info(hldev);
894 if (status != VXGE_HW_OK)
895 goto exit;
896 }
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000897
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +0000898exit:
899 return status;
900}
901
Jon Mason8424e002010-11-11 04:25:56 +0000902/*
903 * __vxge_hw_vpath_fw_ver_get - Get the fw version
904 * Returns FW Version
905 */
906static enum vxge_hw_status
907__vxge_hw_vpath_fw_ver_get(struct __vxge_hw_virtualpath *vpath,
908 struct vxge_hw_device_hw_info *hw_info)
909{
910 struct vxge_hw_device_version *fw_version = &hw_info->fw_version;
911 struct vxge_hw_device_date *fw_date = &hw_info->fw_date;
912 struct vxge_hw_device_version *flash_version = &hw_info->flash_version;
913 struct vxge_hw_device_date *flash_date = &hw_info->flash_date;
914 u64 data0, data1 = 0, steer_ctrl = 0;
915 enum vxge_hw_status status;
916
917 status = vxge_hw_vpath_fw_api(vpath,
918 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
919 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
920 0, &data0, &data1, &steer_ctrl);
921 if (status != VXGE_HW_OK)
922 goto exit;
923
924 fw_date->day =
925 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(data0);
926 fw_date->month =
927 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(data0);
928 fw_date->year =
929 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(data0);
930
931 snprintf(fw_date->date, VXGE_HW_FW_STRLEN, "%2.2d/%2.2d/%4.4d",
932 fw_date->month, fw_date->day, fw_date->year);
933
934 fw_version->major =
935 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data0);
936 fw_version->minor =
937 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data0);
938 fw_version->build =
939 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data0);
940
941 snprintf(fw_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
942 fw_version->major, fw_version->minor, fw_version->build);
943
944 flash_date->day =
945 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY(data1);
946 flash_date->month =
947 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH(data1);
948 flash_date->year =
949 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR(data1);
950
951 snprintf(flash_date->date, VXGE_HW_FW_STRLEN, "%2.2d/%2.2d/%4.4d",
952 flash_date->month, flash_date->day, flash_date->year);
953
954 flash_version->major =
955 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR(data1);
956 flash_version->minor =
957 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR(data1);
958 flash_version->build =
959 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(data1);
960
961 snprintf(flash_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
962 flash_version->major, flash_version->minor,
963 flash_version->build);
964
965exit:
966 return status;
967}
968
969/*
970 * __vxge_hw_vpath_card_info_get - Get the serial numbers,
971 * part number and product description.
972 */
973static enum vxge_hw_status
974__vxge_hw_vpath_card_info_get(struct __vxge_hw_virtualpath *vpath,
975 struct vxge_hw_device_hw_info *hw_info)
976{
977 enum vxge_hw_status status;
978 u64 data0, data1 = 0, steer_ctrl = 0;
979 u8 *serial_number = hw_info->serial_number;
980 u8 *part_number = hw_info->part_number;
981 u8 *product_desc = hw_info->product_desc;
982 u32 i, j = 0;
983
984 data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER;
985
986 status = vxge_hw_vpath_fw_api(vpath,
987 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
988 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
989 0, &data0, &data1, &steer_ctrl);
990 if (status != VXGE_HW_OK)
991 return status;
992
993 ((u64 *)serial_number)[0] = be64_to_cpu(data0);
994 ((u64 *)serial_number)[1] = be64_to_cpu(data1);
995
996 data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER;
997 data1 = steer_ctrl = 0;
998
999 status = vxge_hw_vpath_fw_api(vpath,
1000 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
1001 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
1002 0, &data0, &data1, &steer_ctrl);
1003 if (status != VXGE_HW_OK)
1004 return status;
1005
1006 ((u64 *)part_number)[0] = be64_to_cpu(data0);
1007 ((u64 *)part_number)[1] = be64_to_cpu(data1);
1008
1009 for (i = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0;
1010 i <= VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3; i++) {
1011 data0 = i;
1012 data1 = steer_ctrl = 0;
1013
1014 status = vxge_hw_vpath_fw_api(vpath,
1015 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
1016 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
1017 0, &data0, &data1, &steer_ctrl);
1018 if (status != VXGE_HW_OK)
1019 return status;
1020
1021 ((u64 *)product_desc)[j++] = be64_to_cpu(data0);
1022 ((u64 *)product_desc)[j++] = be64_to_cpu(data1);
1023 }
1024
1025 return status;
1026}
1027
1028/*
1029 * __vxge_hw_vpath_pci_func_mode_get - Get the pci mode
1030 * Returns pci function mode
1031 */
Jon Masonc3150ea2010-11-11 04:25:59 +00001032static enum vxge_hw_status
1033__vxge_hw_vpath_pci_func_mode_get(struct __vxge_hw_virtualpath *vpath,
1034 struct vxge_hw_device_hw_info *hw_info)
Jon Mason8424e002010-11-11 04:25:56 +00001035{
1036 u64 data0, data1 = 0, steer_ctrl = 0;
1037 enum vxge_hw_status status;
1038
Jon Masonca3e3b82010-11-11 04:26:01 +00001039 data0 = 0;
Jon Mason8424e002010-11-11 04:25:56 +00001040
1041 status = vxge_hw_vpath_fw_api(vpath,
Jon Masonca3e3b82010-11-11 04:26:01 +00001042 VXGE_HW_FW_API_GET_FUNC_MODE,
Jon Mason8424e002010-11-11 04:25:56 +00001043 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
1044 0, &data0, &data1, &steer_ctrl);
Jon Masonc3150ea2010-11-11 04:25:59 +00001045 if (status != VXGE_HW_OK)
1046 return status;
Jon Mason8424e002010-11-11 04:25:56 +00001047
Jon Masonca3e3b82010-11-11 04:26:01 +00001048 hw_info->function_mode = VXGE_HW_GET_FUNC_MODE_VAL(data0);
Jon Masonc3150ea2010-11-11 04:25:59 +00001049 return status;
Jon Mason8424e002010-11-11 04:25:56 +00001050}
1051
1052/*
1053 * __vxge_hw_vpath_addr_get - Get the hw address entry for this vpath
1054 * from MAC address table.
1055 */
1056static enum vxge_hw_status
1057__vxge_hw_vpath_addr_get(struct __vxge_hw_virtualpath *vpath,
1058 u8 *macaddr, u8 *macaddr_mask)
1059{
1060 u64 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY,
1061 data0 = 0, data1 = 0, steer_ctrl = 0;
1062 enum vxge_hw_status status;
1063 int i;
1064
1065 do {
1066 status = vxge_hw_vpath_fw_api(vpath, action,
1067 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
1068 0, &data0, &data1, &steer_ctrl);
1069 if (status != VXGE_HW_OK)
1070 goto exit;
1071
1072 data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data0);
1073 data1 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(
1074 data1);
1075
1076 for (i = ETH_ALEN; i > 0; i--) {
1077 macaddr[i - 1] = (u8) (data0 & 0xFF);
1078 data0 >>= 8;
1079
1080 macaddr_mask[i - 1] = (u8) (data1 & 0xFF);
1081 data1 >>= 8;
1082 }
1083
1084 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY;
1085 data0 = 0, data1 = 0, steer_ctrl = 0;
1086
1087 } while (!is_valid_ether_addr(macaddr));
1088exit:
1089 return status;
1090}
1091
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001092/**
1093 * vxge_hw_device_hw_info_get - Get the hw information
1094 * Returns the vpath mask that has the bits set for each vpath allocated
1095 * for the driver, FW version information and the first mac addresse for
1096 * each vpath
1097 */
1098enum vxge_hw_status __devinit
1099vxge_hw_device_hw_info_get(void __iomem *bar0,
1100 struct vxge_hw_device_hw_info *hw_info)
1101{
1102 u32 i;
1103 u64 val64;
1104 struct vxge_hw_toc_reg __iomem *toc;
1105 struct vxge_hw_mrpcim_reg __iomem *mrpcim_reg;
1106 struct vxge_hw_common_reg __iomem *common_reg;
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001107 struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg;
1108 enum vxge_hw_status status;
Jon Mason8424e002010-11-11 04:25:56 +00001109 struct __vxge_hw_virtualpath vpath;
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001110
1111 memset(hw_info, 0, sizeof(struct vxge_hw_device_hw_info));
1112
1113 toc = __vxge_hw_device_toc_get(bar0);
1114 if (toc == NULL) {
1115 status = VXGE_HW_ERR_CRITICAL;
1116 goto exit;
1117 }
1118
1119 val64 = readq(&toc->toc_common_pointer);
1120 common_reg = (struct vxge_hw_common_reg __iomem *)(bar0 + val64);
1121
1122 status = __vxge_hw_device_vpath_reset_in_prog_check(
1123 (u64 __iomem *)&common_reg->vpath_rst_in_prog);
1124 if (status != VXGE_HW_OK)
1125 goto exit;
1126
1127 hw_info->vpath_mask = readq(&common_reg->vpath_assignments);
1128
1129 val64 = readq(&common_reg->host_type_assignments);
1130
1131 hw_info->host_type =
1132 (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
1133
1134 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1135
1136 if (!((hw_info->vpath_mask) & vxge_mBIT(i)))
1137 continue;
1138
1139 val64 = readq(&toc->toc_vpmgmt_pointer[i]);
1140
1141 vpmgmt_reg = (struct vxge_hw_vpmgmt_reg __iomem *)
1142 (bar0 + val64);
1143
Jon Mason8424e002010-11-11 04:25:56 +00001144 hw_info->func_id = __vxge_hw_vpath_func_id_get(vpmgmt_reg);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001145 if (__vxge_hw_device_access_rights_get(hw_info->host_type,
1146 hw_info->func_id) &
1147 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM) {
1148
1149 val64 = readq(&toc->toc_mrpcim_pointer);
1150
1151 mrpcim_reg = (struct vxge_hw_mrpcim_reg __iomem *)
1152 (bar0 + val64);
1153
1154 writeq(0, &mrpcim_reg->xgmac_gen_fw_memo_mask);
1155 wmb();
1156 }
1157
1158 val64 = readq(&toc->toc_vpath_pointer[i]);
1159
Jon Mason8424e002010-11-11 04:25:56 +00001160 vpath.vp_reg = (struct vxge_hw_vpath_reg __iomem *)
1161 (bar0 + val64);
1162 vpath.vp_open = 0;
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001163
Jon Masonc3150ea2010-11-11 04:25:59 +00001164 status = __vxge_hw_vpath_pci_func_mode_get(&vpath, hw_info);
1165 if (status != VXGE_HW_OK)
1166 goto exit;
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001167
Jon Mason8424e002010-11-11 04:25:56 +00001168 status = __vxge_hw_vpath_fw_ver_get(&vpath, hw_info);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001169 if (status != VXGE_HW_OK)
1170 goto exit;
1171
Jon Mason8424e002010-11-11 04:25:56 +00001172 status = __vxge_hw_vpath_card_info_get(&vpath, hw_info);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001173 if (status != VXGE_HW_OK)
1174 goto exit;
1175
1176 break;
1177 }
1178
1179 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001180 if (!((hw_info->vpath_mask) & vxge_mBIT(i)))
1181 continue;
1182
1183 val64 = readq(&toc->toc_vpath_pointer[i]);
Jon Mason8424e002010-11-11 04:25:56 +00001184 vpath.vp_reg = (struct vxge_hw_vpath_reg __iomem *)
1185 (bar0 + val64);
1186 vpath.vp_open = 0;
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001187
Jon Mason8424e002010-11-11 04:25:56 +00001188 status = __vxge_hw_vpath_addr_get(&vpath,
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001189 hw_info->mac_addrs[i],
1190 hw_info->mac_addr_masks[i]);
1191 if (status != VXGE_HW_OK)
1192 goto exit;
1193 }
1194exit:
1195 return status;
1196}
1197
1198/*
1199 * vxge_hw_device_initialize - Initialize Titan device.
1200 * Initialize Titan device. Note that all the arguments of this public API
1201 * are 'IN', including @hldev. Driver cooperates with
1202 * OS to find new Titan device, locate its PCI and memory spaces.
1203 *
1204 * When done, the driver allocates sizeof(struct __vxge_hw_device) bytes for HW
1205 * to enable the latter to perform Titan hardware initialization.
1206 */
1207enum vxge_hw_status __devinit
1208vxge_hw_device_initialize(
1209 struct __vxge_hw_device **devh,
1210 struct vxge_hw_device_attr *attr,
1211 struct vxge_hw_device_config *device_config)
1212{
1213 u32 i;
1214 u32 nblocks = 0;
1215 struct __vxge_hw_device *hldev = NULL;
1216 enum vxge_hw_status status = VXGE_HW_OK;
1217
1218 status = __vxge_hw_device_config_check(device_config);
1219 if (status != VXGE_HW_OK)
1220 goto exit;
1221
Joe Perchese80be0b2010-11-27 23:05:45 +00001222 hldev = vzalloc(sizeof(struct __vxge_hw_device));
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001223 if (hldev == NULL) {
1224 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1225 goto exit;
1226 }
1227
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001228 hldev->magic = VXGE_HW_DEVICE_MAGIC;
1229
1230 vxge_hw_device_debug_set(hldev, VXGE_ERR, VXGE_COMPONENT_ALL);
1231
1232 /* apply config */
1233 memcpy(&hldev->config, device_config,
1234 sizeof(struct vxge_hw_device_config));
1235
1236 hldev->bar0 = attr->bar0;
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001237 hldev->pdev = attr->pdev;
1238
1239 hldev->uld_callbacks.link_up = attr->uld_callbacks.link_up;
1240 hldev->uld_callbacks.link_down = attr->uld_callbacks.link_down;
1241 hldev->uld_callbacks.crit_err = attr->uld_callbacks.crit_err;
1242
1243 __vxge_hw_device_pci_e_init(hldev);
1244
1245 status = __vxge_hw_device_reg_addr_get(hldev);
Sreenivasa Honnuraaffbd92010-04-08 01:44:39 -07001246 if (status != VXGE_HW_OK) {
1247 vfree(hldev);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001248 goto exit;
Sreenivasa Honnuraaffbd92010-04-08 01:44:39 -07001249 }
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001250
1251 __vxge_hw_device_host_info_get(hldev);
1252
1253 /* Incrementing for stats blocks */
1254 nblocks++;
1255
1256 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001257 if (!(hldev->vpath_assignments & vxge_mBIT(i)))
1258 continue;
1259
1260 if (device_config->vp_config[i].ring.enable ==
1261 VXGE_HW_RING_ENABLE)
1262 nblocks += device_config->vp_config[i].ring.ring_blocks;
1263
1264 if (device_config->vp_config[i].fifo.enable ==
1265 VXGE_HW_FIFO_ENABLE)
1266 nblocks += device_config->vp_config[i].fifo.fifo_blocks;
1267 nblocks++;
1268 }
1269
1270 if (__vxge_hw_blockpool_create(hldev,
1271 &hldev->block_pool,
1272 device_config->dma_blockpool_initial + nblocks,
1273 device_config->dma_blockpool_max + nblocks) != VXGE_HW_OK) {
1274
1275 vxge_hw_device_terminate(hldev);
1276 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1277 goto exit;
1278 }
1279
1280 status = __vxge_hw_device_initialize(hldev);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001281 if (status != VXGE_HW_OK) {
1282 vxge_hw_device_terminate(hldev);
1283 goto exit;
1284 }
1285
1286 *devh = hldev;
1287exit:
1288 return status;
1289}
1290
1291/*
1292 * vxge_hw_device_terminate - Terminate Titan device.
1293 * Terminate HW device.
1294 */
1295void
1296vxge_hw_device_terminate(struct __vxge_hw_device *hldev)
1297{
1298 vxge_assert(hldev->magic == VXGE_HW_DEVICE_MAGIC);
1299
1300 hldev->magic = VXGE_HW_DEVICE_DEAD;
1301 __vxge_hw_blockpool_destroy(&hldev->block_pool);
1302 vfree(hldev);
1303}
1304
1305/*
1306 * vxge_hw_device_stats_get - Get the device hw statistics.
1307 * Returns the vpath h/w stats for the device.
1308 */
1309enum vxge_hw_status
1310vxge_hw_device_stats_get(struct __vxge_hw_device *hldev,
1311 struct vxge_hw_device_stats_hw_info *hw_stats)
1312{
1313 u32 i;
1314 enum vxge_hw_status status = VXGE_HW_OK;
1315
1316 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001317 if (!(hldev->vpaths_deployed & vxge_mBIT(i)) ||
1318 (hldev->virtual_paths[i].vp_open ==
1319 VXGE_HW_VP_NOT_OPEN))
1320 continue;
1321
1322 memcpy(hldev->virtual_paths[i].hw_stats_sav,
1323 hldev->virtual_paths[i].hw_stats,
1324 sizeof(struct vxge_hw_vpath_stats_hw_info));
1325
1326 status = __vxge_hw_vpath_stats_get(
1327 &hldev->virtual_paths[i],
1328 hldev->virtual_paths[i].hw_stats);
1329 }
1330
1331 memcpy(hw_stats, &hldev->stats.hw_dev_info_stats,
1332 sizeof(struct vxge_hw_device_stats_hw_info));
1333
1334 return status;
1335}
1336
1337/*
1338 * vxge_hw_driver_stats_get - Get the device sw statistics.
1339 * Returns the vpath s/w stats for the device.
1340 */
1341enum vxge_hw_status vxge_hw_driver_stats_get(
1342 struct __vxge_hw_device *hldev,
1343 struct vxge_hw_device_stats_sw_info *sw_stats)
1344{
1345 enum vxge_hw_status status = VXGE_HW_OK;
1346
1347 memcpy(sw_stats, &hldev->stats.sw_dev_info_stats,
1348 sizeof(struct vxge_hw_device_stats_sw_info));
1349
1350 return status;
1351}
1352
1353/*
1354 * vxge_hw_mrpcim_stats_access - Access the statistics from the given location
1355 * and offset and perform an operation
1356 * Get the statistics from the given location and offset.
1357 */
1358enum vxge_hw_status
1359vxge_hw_mrpcim_stats_access(struct __vxge_hw_device *hldev,
1360 u32 operation, u32 location, u32 offset, u64 *stat)
1361{
1362 u64 val64;
1363 enum vxge_hw_status status = VXGE_HW_OK;
1364
Sreenivasa Honnur92cdd7c2009-10-05 01:51:38 +00001365 status = __vxge_hw_device_is_privilaged(hldev->host_type,
1366 hldev->func_id);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001367 if (status != VXGE_HW_OK)
1368 goto exit;
1369
1370 val64 = VXGE_HW_XMAC_STATS_SYS_CMD_OP(operation) |
1371 VXGE_HW_XMAC_STATS_SYS_CMD_STROBE |
1372 VXGE_HW_XMAC_STATS_SYS_CMD_LOC_SEL(location) |
1373 VXGE_HW_XMAC_STATS_SYS_CMD_OFFSET_SEL(offset);
1374
1375 status = __vxge_hw_pio_mem_write64(val64,
1376 &hldev->mrpcim_reg->xmac_stats_sys_cmd,
1377 VXGE_HW_XMAC_STATS_SYS_CMD_STROBE,
1378 hldev->config.device_poll_millis);
1379
1380 if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ))
1381 *stat = readq(&hldev->mrpcim_reg->xmac_stats_sys_data);
1382 else
1383 *stat = 0;
1384exit:
1385 return status;
1386}
1387
1388/*
1389 * vxge_hw_device_xmac_aggr_stats_get - Get the Statistics on aggregate port
1390 * Get the Statistics on aggregate port
1391 */
stephen hemminger42821a52010-10-21 07:50:53 +00001392static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001393vxge_hw_device_xmac_aggr_stats_get(struct __vxge_hw_device *hldev, u32 port,
1394 struct vxge_hw_xmac_aggr_stats *aggr_stats)
1395{
1396 u64 *val64;
1397 int i;
1398 u32 offset = VXGE_HW_STATS_AGGRn_OFFSET;
1399 enum vxge_hw_status status = VXGE_HW_OK;
1400
1401 val64 = (u64 *)aggr_stats;
1402
Sreenivasa Honnur92cdd7c2009-10-05 01:51:38 +00001403 status = __vxge_hw_device_is_privilaged(hldev->host_type,
1404 hldev->func_id);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001405 if (status != VXGE_HW_OK)
1406 goto exit;
1407
1408 for (i = 0; i < sizeof(struct vxge_hw_xmac_aggr_stats) / 8; i++) {
1409 status = vxge_hw_mrpcim_stats_access(hldev,
1410 VXGE_HW_STATS_OP_READ,
1411 VXGE_HW_STATS_LOC_AGGR,
1412 ((offset + (104 * port)) >> 3), val64);
1413 if (status != VXGE_HW_OK)
1414 goto exit;
1415
1416 offset += 8;
1417 val64++;
1418 }
1419exit:
1420 return status;
1421}
1422
1423/*
1424 * vxge_hw_device_xmac_port_stats_get - Get the Statistics on a port
1425 * Get the Statistics on port
1426 */
stephen hemminger42821a52010-10-21 07:50:53 +00001427static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001428vxge_hw_device_xmac_port_stats_get(struct __vxge_hw_device *hldev, u32 port,
1429 struct vxge_hw_xmac_port_stats *port_stats)
1430{
1431 u64 *val64;
1432 enum vxge_hw_status status = VXGE_HW_OK;
1433 int i;
1434 u32 offset = 0x0;
1435 val64 = (u64 *) port_stats;
1436
Sreenivasa Honnur92cdd7c2009-10-05 01:51:38 +00001437 status = __vxge_hw_device_is_privilaged(hldev->host_type,
1438 hldev->func_id);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001439 if (status != VXGE_HW_OK)
1440 goto exit;
1441
1442 for (i = 0; i < sizeof(struct vxge_hw_xmac_port_stats) / 8; i++) {
1443 status = vxge_hw_mrpcim_stats_access(hldev,
1444 VXGE_HW_STATS_OP_READ,
1445 VXGE_HW_STATS_LOC_AGGR,
1446 ((offset + (608 * port)) >> 3), val64);
1447 if (status != VXGE_HW_OK)
1448 goto exit;
1449
1450 offset += 8;
1451 val64++;
1452 }
1453
1454exit:
1455 return status;
1456}
1457
1458/*
1459 * vxge_hw_device_xmac_stats_get - Get the XMAC Statistics
1460 * Get the XMAC Statistics
1461 */
1462enum vxge_hw_status
1463vxge_hw_device_xmac_stats_get(struct __vxge_hw_device *hldev,
1464 struct vxge_hw_xmac_stats *xmac_stats)
1465{
1466 enum vxge_hw_status status = VXGE_HW_OK;
1467 u32 i;
1468
1469 status = vxge_hw_device_xmac_aggr_stats_get(hldev,
1470 0, &xmac_stats->aggr_stats[0]);
1471
1472 if (status != VXGE_HW_OK)
1473 goto exit;
1474
1475 status = vxge_hw_device_xmac_aggr_stats_get(hldev,
1476 1, &xmac_stats->aggr_stats[1]);
1477 if (status != VXGE_HW_OK)
1478 goto exit;
1479
1480 for (i = 0; i <= VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) {
1481
1482 status = vxge_hw_device_xmac_port_stats_get(hldev,
1483 i, &xmac_stats->port_stats[i]);
1484 if (status != VXGE_HW_OK)
1485 goto exit;
1486 }
1487
1488 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1489
1490 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
1491 continue;
1492
1493 status = __vxge_hw_vpath_xmac_tx_stats_get(
1494 &hldev->virtual_paths[i],
1495 &xmac_stats->vpath_tx_stats[i]);
1496 if (status != VXGE_HW_OK)
1497 goto exit;
1498
1499 status = __vxge_hw_vpath_xmac_rx_stats_get(
1500 &hldev->virtual_paths[i],
1501 &xmac_stats->vpath_rx_stats[i]);
1502 if (status != VXGE_HW_OK)
1503 goto exit;
1504 }
1505exit:
1506 return status;
1507}
1508
1509/*
1510 * vxge_hw_device_debug_set - Set the debug module, level and timestamp
1511 * This routine is used to dynamically change the debug output
1512 */
1513void vxge_hw_device_debug_set(struct __vxge_hw_device *hldev,
1514 enum vxge_debug_level level, u32 mask)
1515{
1516 if (hldev == NULL)
1517 return;
1518
1519#if defined(VXGE_DEBUG_TRACE_MASK) || \
1520 defined(VXGE_DEBUG_ERR_MASK)
1521 hldev->debug_module_mask = mask;
1522 hldev->debug_level = level;
1523#endif
1524
1525#if defined(VXGE_DEBUG_ERR_MASK)
1526 hldev->level_err = level & VXGE_ERR;
1527#endif
1528
1529#if defined(VXGE_DEBUG_TRACE_MASK)
1530 hldev->level_trace = level & VXGE_TRACE;
1531#endif
1532}
1533
1534/*
1535 * vxge_hw_device_error_level_get - Get the error level
1536 * This routine returns the current error level set
1537 */
1538u32 vxge_hw_device_error_level_get(struct __vxge_hw_device *hldev)
1539{
1540#if defined(VXGE_DEBUG_ERR_MASK)
1541 if (hldev == NULL)
1542 return VXGE_ERR;
1543 else
1544 return hldev->level_err;
1545#else
1546 return 0;
1547#endif
1548}
1549
1550/*
1551 * vxge_hw_device_trace_level_get - Get the trace level
1552 * This routine returns the current trace level set
1553 */
1554u32 vxge_hw_device_trace_level_get(struct __vxge_hw_device *hldev)
1555{
1556#if defined(VXGE_DEBUG_TRACE_MASK)
1557 if (hldev == NULL)
1558 return VXGE_TRACE;
1559 else
1560 return hldev->level_trace;
1561#else
1562 return 0;
1563#endif
1564}
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001565
1566/*
1567 * vxge_hw_getpause_data -Pause frame frame generation and reception.
1568 * Returns the Pause frame generation and reception capability of the NIC.
1569 */
1570enum vxge_hw_status vxge_hw_device_getpause_data(struct __vxge_hw_device *hldev,
1571 u32 port, u32 *tx, u32 *rx)
1572{
1573 u64 val64;
1574 enum vxge_hw_status status = VXGE_HW_OK;
1575
1576 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
1577 status = VXGE_HW_ERR_INVALID_DEVICE;
1578 goto exit;
1579 }
1580
1581 if (port > VXGE_HW_MAC_MAX_MAC_PORT_ID) {
1582 status = VXGE_HW_ERR_INVALID_PORT;
1583 goto exit;
1584 }
1585
1586 if (!(hldev->access_rights & VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
1587 status = VXGE_HW_ERR_PRIVILAGED_OPEARATION;
1588 goto exit;
1589 }
1590
1591 val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1592 if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN)
1593 *tx = 1;
1594 if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN)
1595 *rx = 1;
1596exit:
1597 return status;
1598}
1599
1600/*
1601 * vxge_hw_device_setpause_data - set/reset pause frame generation.
1602 * It can be used to set or reset Pause frame generation or reception
1603 * support of the NIC.
1604 */
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001605enum vxge_hw_status vxge_hw_device_setpause_data(struct __vxge_hw_device *hldev,
1606 u32 port, u32 tx, u32 rx)
1607{
1608 u64 val64;
1609 enum vxge_hw_status status = VXGE_HW_OK;
1610
1611 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
1612 status = VXGE_HW_ERR_INVALID_DEVICE;
1613 goto exit;
1614 }
1615
1616 if (port > VXGE_HW_MAC_MAX_MAC_PORT_ID) {
1617 status = VXGE_HW_ERR_INVALID_PORT;
1618 goto exit;
1619 }
1620
Sreenivasa Honnur92cdd7c2009-10-05 01:51:38 +00001621 status = __vxge_hw_device_is_privilaged(hldev->host_type,
1622 hldev->func_id);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001623 if (status != VXGE_HW_OK)
1624 goto exit;
1625
1626 val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1627 if (tx)
1628 val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN;
1629 else
1630 val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN;
1631 if (rx)
1632 val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN;
1633 else
1634 val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN;
1635
1636 writeq(val64, &hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1637exit:
1638 return status;
1639}
1640
1641u16 vxge_hw_device_link_width_get(struct __vxge_hw_device *hldev)
1642{
1643 int link_width, exp_cap;
1644 u16 lnk;
1645
1646 exp_cap = pci_find_capability(hldev->pdev, PCI_CAP_ID_EXP);
1647 pci_read_config_word(hldev->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
1648 link_width = (lnk & VXGE_HW_PCI_EXP_LNKCAP_LNK_WIDTH) >> 4;
1649 return link_width;
1650}
1651
1652/*
1653 * __vxge_hw_ring_block_memblock_idx - Return the memblock index
1654 * This function returns the index of memory block
1655 */
1656static inline u32
1657__vxge_hw_ring_block_memblock_idx(u8 *block)
1658{
1659 return (u32)*((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET));
1660}
1661
1662/*
1663 * __vxge_hw_ring_block_memblock_idx_set - Sets the memblock index
1664 * This function sets index to a memory block
1665 */
1666static inline void
1667__vxge_hw_ring_block_memblock_idx_set(u8 *block, u32 memblock_idx)
1668{
1669 *((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET)) = memblock_idx;
1670}
1671
1672/*
1673 * __vxge_hw_ring_block_next_pointer_set - Sets the next block pointer
1674 * in RxD block
1675 * Sets the next block pointer in RxD block
1676 */
1677static inline void
1678__vxge_hw_ring_block_next_pointer_set(u8 *block, dma_addr_t dma_next)
1679{
1680 *((u64 *)(block + VXGE_HW_RING_NEXT_BLOCK_POINTER_OFFSET)) = dma_next;
1681}
1682
1683/*
1684 * __vxge_hw_ring_first_block_address_get - Returns the dma address of the
1685 * first block
1686 * Returns the dma address of the first RxD block
1687 */
stephen hemminger42821a52010-10-21 07:50:53 +00001688static u64 __vxge_hw_ring_first_block_address_get(struct __vxge_hw_ring *ring)
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001689{
1690 struct vxge_hw_mempool_dma *dma_object;
1691
1692 dma_object = ring->mempool->memblocks_dma_arr;
1693 vxge_assert(dma_object != NULL);
1694
1695 return dma_object->addr;
1696}
1697
1698/*
1699 * __vxge_hw_ring_item_dma_addr - Return the dma address of an item
1700 * This function returns the dma address of a given item
1701 */
1702static dma_addr_t __vxge_hw_ring_item_dma_addr(struct vxge_hw_mempool *mempoolh,
1703 void *item)
1704{
1705 u32 memblock_idx;
1706 void *memblock;
1707 struct vxge_hw_mempool_dma *memblock_dma_object;
1708 ptrdiff_t dma_item_offset;
1709
1710 /* get owner memblock index */
1711 memblock_idx = __vxge_hw_ring_block_memblock_idx(item);
1712
1713 /* get owner memblock by memblock index */
1714 memblock = mempoolh->memblocks_arr[memblock_idx];
1715
1716 /* get memblock DMA object by memblock index */
1717 memblock_dma_object = mempoolh->memblocks_dma_arr + memblock_idx;
1718
1719 /* calculate offset in the memblock of this item */
1720 dma_item_offset = (u8 *)item - (u8 *)memblock;
1721
1722 return memblock_dma_object->addr + dma_item_offset;
1723}
1724
1725/*
1726 * __vxge_hw_ring_rxdblock_link - Link the RxD blocks
1727 * This function returns the dma address of a given item
1728 */
1729static void __vxge_hw_ring_rxdblock_link(struct vxge_hw_mempool *mempoolh,
1730 struct __vxge_hw_ring *ring, u32 from,
1731 u32 to)
1732{
1733 u8 *to_item , *from_item;
1734 dma_addr_t to_dma;
1735
1736 /* get "from" RxD block */
1737 from_item = mempoolh->items_arr[from];
1738 vxge_assert(from_item);
1739
1740 /* get "to" RxD block */
1741 to_item = mempoolh->items_arr[to];
1742 vxge_assert(to_item);
1743
1744 /* return address of the beginning of previous RxD block */
1745 to_dma = __vxge_hw_ring_item_dma_addr(mempoolh, to_item);
1746
1747 /* set next pointer for this RxD block to point on
1748 * previous item's DMA start address */
1749 __vxge_hw_ring_block_next_pointer_set(from_item, to_dma);
1750}
1751
1752/*
1753 * __vxge_hw_ring_mempool_item_alloc - Allocate List blocks for RxD
1754 * block callback
1755 * This function is callback passed to __vxge_hw_mempool_create to create memory
1756 * pool for RxD block
1757 */
1758static void
1759__vxge_hw_ring_mempool_item_alloc(struct vxge_hw_mempool *mempoolh,
1760 u32 memblock_index,
1761 struct vxge_hw_mempool_dma *dma_object,
1762 u32 index, u32 is_last)
1763{
1764 u32 i;
1765 void *item = mempoolh->items_arr[index];
1766 struct __vxge_hw_ring *ring =
1767 (struct __vxge_hw_ring *)mempoolh->userdata;
1768
1769 /* format rxds array */
1770 for (i = 0; i < ring->rxds_per_block; i++) {
1771 void *rxdblock_priv;
1772 void *uld_priv;
1773 struct vxge_hw_ring_rxd_1 *rxdp;
1774
1775 u32 reserve_index = ring->channel.reserve_ptr -
1776 (index * ring->rxds_per_block + i + 1);
1777 u32 memblock_item_idx;
1778
1779 ring->channel.reserve_arr[reserve_index] = ((u8 *)item) +
1780 i * ring->rxd_size;
1781
1782 /* Note: memblock_item_idx is index of the item within
1783 * the memblock. For instance, in case of three RxD-blocks
1784 * per memblock this value can be 0, 1 or 2. */
1785 rxdblock_priv = __vxge_hw_mempool_item_priv(mempoolh,
1786 memblock_index, item,
1787 &memblock_item_idx);
1788
1789 rxdp = (struct vxge_hw_ring_rxd_1 *)
1790 ring->channel.reserve_arr[reserve_index];
1791
1792 uld_priv = ((u8 *)rxdblock_priv + ring->rxd_priv_size * i);
1793
1794 /* pre-format Host_Control */
1795 rxdp->host_control = (u64)(size_t)uld_priv;
1796 }
1797
1798 __vxge_hw_ring_block_memblock_idx_set(item, memblock_index);
1799
1800 if (is_last) {
1801 /* link last one with first one */
1802 __vxge_hw_ring_rxdblock_link(mempoolh, ring, index, 0);
1803 }
1804
1805 if (index > 0) {
1806 /* link this RxD block with previous one */
1807 __vxge_hw_ring_rxdblock_link(mempoolh, ring, index - 1, index);
1808 }
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001809}
1810
1811/*
Sreenivasa Honnur33632762010-03-28 22:08:30 +00001812 * __vxge_hw_ring_replenish - Initial replenish of RxDs
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001813 * This function replenishes the RxDs from reserve array to work array
1814 */
1815enum vxge_hw_status
Sreenivasa Honnur33632762010-03-28 22:08:30 +00001816vxge_hw_ring_replenish(struct __vxge_hw_ring *ring)
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001817{
1818 void *rxd;
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001819 struct __vxge_hw_channel *channel;
1820 enum vxge_hw_status status = VXGE_HW_OK;
1821
1822 channel = &ring->channel;
1823
1824 while (vxge_hw_channel_dtr_count(channel) > 0) {
1825
1826 status = vxge_hw_ring_rxd_reserve(ring, &rxd);
1827
1828 vxge_assert(status == VXGE_HW_OK);
1829
1830 if (ring->rxd_init) {
1831 status = ring->rxd_init(rxd, channel->userdata);
1832 if (status != VXGE_HW_OK) {
1833 vxge_hw_ring_rxd_free(ring, rxd);
1834 goto exit;
1835 }
1836 }
1837
1838 vxge_hw_ring_rxd_post(ring, rxd);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001839 }
1840 status = VXGE_HW_OK;
1841exit:
1842 return status;
1843}
1844
1845/*
1846 * __vxge_hw_ring_create - Create a Ring
1847 * This function creates Ring and initializes it.
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001848 */
stephen hemminger42821a52010-10-21 07:50:53 +00001849static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001850__vxge_hw_ring_create(struct __vxge_hw_vpath_handle *vp,
1851 struct vxge_hw_ring_attr *attr)
1852{
1853 enum vxge_hw_status status = VXGE_HW_OK;
1854 struct __vxge_hw_ring *ring;
1855 u32 ring_length;
1856 struct vxge_hw_ring_config *config;
1857 struct __vxge_hw_device *hldev;
1858 u32 vp_id;
1859 struct vxge_hw_mempool_cbs ring_mp_callback;
1860
1861 if ((vp == NULL) || (attr == NULL)) {
1862 status = VXGE_HW_FAIL;
1863 goto exit;
1864 }
1865
1866 hldev = vp->vpath->hldev;
1867 vp_id = vp->vpath->vp_id;
1868
1869 config = &hldev->config.vp_config[vp_id].ring;
1870
1871 ring_length = config->ring_blocks *
1872 vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
1873
1874 ring = (struct __vxge_hw_ring *)__vxge_hw_channel_allocate(vp,
1875 VXGE_HW_CHANNEL_TYPE_RING,
1876 ring_length,
1877 attr->per_rxd_space,
1878 attr->userdata);
1879
1880 if (ring == NULL) {
1881 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1882 goto exit;
1883 }
1884
1885 vp->vpath->ringh = ring;
1886 ring->vp_id = vp_id;
1887 ring->vp_reg = vp->vpath->vp_reg;
1888 ring->common_reg = hldev->common_reg;
1889 ring->stats = &vp->vpath->sw_stats->ring_stats;
1890 ring->config = config;
1891 ring->callback = attr->callback;
1892 ring->rxd_init = attr->rxd_init;
1893 ring->rxd_term = attr->rxd_term;
1894 ring->buffer_mode = config->buffer_mode;
1895 ring->rxds_limit = config->rxds_limit;
1896
1897 ring->rxd_size = vxge_hw_ring_rxd_size_get(config->buffer_mode);
1898 ring->rxd_priv_size =
1899 sizeof(struct __vxge_hw_ring_rxd_priv) + attr->per_rxd_space;
1900 ring->per_rxd_space = attr->per_rxd_space;
1901
1902 ring->rxd_priv_size =
1903 ((ring->rxd_priv_size + VXGE_CACHE_LINE_SIZE - 1) /
1904 VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE;
1905
1906 /* how many RxDs can fit into one block. Depends on configured
1907 * buffer_mode. */
1908 ring->rxds_per_block =
1909 vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
1910
1911 /* calculate actual RxD block private size */
1912 ring->rxdblock_priv_size = ring->rxd_priv_size * ring->rxds_per_block;
1913 ring_mp_callback.item_func_alloc = __vxge_hw_ring_mempool_item_alloc;
1914 ring->mempool = __vxge_hw_mempool_create(hldev,
1915 VXGE_HW_BLOCK_SIZE,
1916 VXGE_HW_BLOCK_SIZE,
1917 ring->rxdblock_priv_size,
1918 ring->config->ring_blocks,
1919 ring->config->ring_blocks,
1920 &ring_mp_callback,
1921 ring);
1922
1923 if (ring->mempool == NULL) {
1924 __vxge_hw_ring_delete(vp);
1925 return VXGE_HW_ERR_OUT_OF_MEMORY;
1926 }
1927
1928 status = __vxge_hw_channel_initialize(&ring->channel);
1929 if (status != VXGE_HW_OK) {
1930 __vxge_hw_ring_delete(vp);
1931 goto exit;
1932 }
1933
1934 /* Note:
1935 * Specifying rxd_init callback means two things:
1936 * 1) rxds need to be initialized by driver at channel-open time;
1937 * 2) rxds need to be posted at channel-open time
1938 * (that's what the initial_replenish() below does)
1939 * Currently we don't have a case when the 1) is done without the 2).
1940 */
1941 if (ring->rxd_init) {
Sreenivasa Honnur33632762010-03-28 22:08:30 +00001942 status = vxge_hw_ring_replenish(ring);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001943 if (status != VXGE_HW_OK) {
1944 __vxge_hw_ring_delete(vp);
1945 goto exit;
1946 }
1947 }
1948
1949 /* initial replenish will increment the counter in its post() routine,
1950 * we have to reset it */
1951 ring->stats->common_stats.usage_cnt = 0;
1952exit:
1953 return status;
1954}
1955
1956/*
1957 * __vxge_hw_ring_abort - Returns the RxD
1958 * This function terminates the RxDs of ring
1959 */
stephen hemminger42821a52010-10-21 07:50:53 +00001960static enum vxge_hw_status __vxge_hw_ring_abort(struct __vxge_hw_ring *ring)
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001961{
1962 void *rxdh;
1963 struct __vxge_hw_channel *channel;
1964
1965 channel = &ring->channel;
1966
1967 for (;;) {
1968 vxge_hw_channel_dtr_try_complete(channel, &rxdh);
1969
1970 if (rxdh == NULL)
1971 break;
1972
1973 vxge_hw_channel_dtr_complete(channel);
1974
1975 if (ring->rxd_term)
1976 ring->rxd_term(rxdh, VXGE_HW_RXD_STATE_POSTED,
1977 channel->userdata);
1978
1979 vxge_hw_channel_dtr_free(channel, rxdh);
1980 }
1981
1982 return VXGE_HW_OK;
1983}
1984
1985/*
1986 * __vxge_hw_ring_reset - Resets the ring
1987 * This function resets the ring during vpath reset operation
1988 */
stephen hemminger42821a52010-10-21 07:50:53 +00001989static enum vxge_hw_status __vxge_hw_ring_reset(struct __vxge_hw_ring *ring)
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00001990{
1991 enum vxge_hw_status status = VXGE_HW_OK;
1992 struct __vxge_hw_channel *channel;
1993
1994 channel = &ring->channel;
1995
1996 __vxge_hw_ring_abort(ring);
1997
1998 status = __vxge_hw_channel_reset(channel);
1999
2000 if (status != VXGE_HW_OK)
2001 goto exit;
2002
2003 if (ring->rxd_init) {
Sreenivasa Honnur33632762010-03-28 22:08:30 +00002004 status = vxge_hw_ring_replenish(ring);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002005 if (status != VXGE_HW_OK)
2006 goto exit;
2007 }
2008exit:
2009 return status;
2010}
2011
2012/*
2013 * __vxge_hw_ring_delete - Removes the ring
2014 * This function freeup the memory pool and removes the ring
2015 */
stephen hemminger42821a52010-10-21 07:50:53 +00002016static enum vxge_hw_status __vxge_hw_ring_delete(struct __vxge_hw_vpath_handle *vp)
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002017{
2018 struct __vxge_hw_ring *ring = vp->vpath->ringh;
2019
2020 __vxge_hw_ring_abort(ring);
2021
2022 if (ring->mempool)
2023 __vxge_hw_mempool_destroy(ring->mempool);
2024
2025 vp->vpath->ringh = NULL;
2026 __vxge_hw_channel_free(&ring->channel);
2027
2028 return VXGE_HW_OK;
2029}
2030
2031/*
2032 * __vxge_hw_mempool_grow
2033 * Will resize mempool up to %num_allocate value.
2034 */
stephen hemminger42821a52010-10-21 07:50:53 +00002035static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002036__vxge_hw_mempool_grow(struct vxge_hw_mempool *mempool, u32 num_allocate,
2037 u32 *num_allocated)
2038{
2039 u32 i, first_time = mempool->memblocks_allocated == 0 ? 1 : 0;
2040 u32 n_items = mempool->items_per_memblock;
2041 u32 start_block_idx = mempool->memblocks_allocated;
2042 u32 end_block_idx = mempool->memblocks_allocated + num_allocate;
2043 enum vxge_hw_status status = VXGE_HW_OK;
2044
2045 *num_allocated = 0;
2046
2047 if (end_block_idx > mempool->memblocks_max) {
2048 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2049 goto exit;
2050 }
2051
2052 for (i = start_block_idx; i < end_block_idx; i++) {
2053 u32 j;
2054 u32 is_last = ((end_block_idx - 1) == i);
2055 struct vxge_hw_mempool_dma *dma_object =
2056 mempool->memblocks_dma_arr + i;
2057 void *the_memblock;
2058
2059 /* allocate memblock's private part. Each DMA memblock
2060 * has a space allocated for item's private usage upon
2061 * mempool's user request. Each time mempool grows, it will
2062 * allocate new memblock and its private part at once.
2063 * This helps to minimize memory usage a lot. */
2064 mempool->memblocks_priv_arr[i] =
Eric Dumazet89bf67f2010-11-22 00:15:06 +00002065 vzalloc(mempool->items_priv_size * n_items);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002066 if (mempool->memblocks_priv_arr[i] == NULL) {
2067 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2068 goto exit;
2069 }
2070
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002071 /* allocate DMA-capable memblock */
2072 mempool->memblocks_arr[i] =
2073 __vxge_hw_blockpool_malloc(mempool->devh,
2074 mempool->memblock_size, dma_object);
2075 if (mempool->memblocks_arr[i] == NULL) {
2076 vfree(mempool->memblocks_priv_arr[i]);
2077 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2078 goto exit;
2079 }
2080
2081 (*num_allocated)++;
2082 mempool->memblocks_allocated++;
2083
2084 memset(mempool->memblocks_arr[i], 0, mempool->memblock_size);
2085
2086 the_memblock = mempool->memblocks_arr[i];
2087
2088 /* fill the items hash array */
2089 for (j = 0; j < n_items; j++) {
2090 u32 index = i * n_items + j;
2091
2092 if (first_time && index >= mempool->items_initial)
2093 break;
2094
2095 mempool->items_arr[index] =
2096 ((char *)the_memblock + j*mempool->item_size);
2097
2098 /* let caller to do more job on each item */
2099 if (mempool->item_func_alloc != NULL)
2100 mempool->item_func_alloc(mempool, i,
2101 dma_object, index, is_last);
2102
2103 mempool->items_current = index + 1;
2104 }
2105
2106 if (first_time && mempool->items_current ==
2107 mempool->items_initial)
2108 break;
2109 }
2110exit:
2111 return status;
2112}
2113
2114/*
2115 * vxge_hw_mempool_create
2116 * This function will create memory pool object. Pool may grow but will
2117 * never shrink. Pool consists of number of dynamically allocated blocks
2118 * with size enough to hold %items_initial number of items. Memory is
2119 * DMA-able but client must map/unmap before interoperating with the device.
2120 */
stephen hemminger42821a52010-10-21 07:50:53 +00002121static struct vxge_hw_mempool*
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002122__vxge_hw_mempool_create(
2123 struct __vxge_hw_device *devh,
2124 u32 memblock_size,
2125 u32 item_size,
2126 u32 items_priv_size,
2127 u32 items_initial,
2128 u32 items_max,
2129 struct vxge_hw_mempool_cbs *mp_callback,
2130 void *userdata)
2131{
2132 enum vxge_hw_status status = VXGE_HW_OK;
2133 u32 memblocks_to_allocate;
2134 struct vxge_hw_mempool *mempool = NULL;
2135 u32 allocated;
2136
2137 if (memblock_size < item_size) {
2138 status = VXGE_HW_FAIL;
2139 goto exit;
2140 }
2141
Joe Perchese80be0b2010-11-27 23:05:45 +00002142 mempool = vzalloc(sizeof(struct vxge_hw_mempool));
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002143 if (mempool == NULL) {
2144 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2145 goto exit;
2146 }
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002147
2148 mempool->devh = devh;
2149 mempool->memblock_size = memblock_size;
2150 mempool->items_max = items_max;
2151 mempool->items_initial = items_initial;
2152 mempool->item_size = item_size;
2153 mempool->items_priv_size = items_priv_size;
2154 mempool->item_func_alloc = mp_callback->item_func_alloc;
2155 mempool->userdata = userdata;
2156
2157 mempool->memblocks_allocated = 0;
2158
2159 mempool->items_per_memblock = memblock_size / item_size;
2160
2161 mempool->memblocks_max = (items_max + mempool->items_per_memblock - 1) /
2162 mempool->items_per_memblock;
2163
2164 /* allocate array of memblocks */
2165 mempool->memblocks_arr =
Joe Perchese80be0b2010-11-27 23:05:45 +00002166 vzalloc(sizeof(void *) * mempool->memblocks_max);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002167 if (mempool->memblocks_arr == NULL) {
2168 __vxge_hw_mempool_destroy(mempool);
2169 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2170 mempool = NULL;
2171 goto exit;
2172 }
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002173
2174 /* allocate array of private parts of items per memblocks */
2175 mempool->memblocks_priv_arr =
Joe Perchese80be0b2010-11-27 23:05:45 +00002176 vzalloc(sizeof(void *) * mempool->memblocks_max);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002177 if (mempool->memblocks_priv_arr == NULL) {
2178 __vxge_hw_mempool_destroy(mempool);
2179 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2180 mempool = NULL;
2181 goto exit;
2182 }
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002183
2184 /* allocate array of memblocks DMA objects */
Joe Perchese80be0b2010-11-27 23:05:45 +00002185 mempool->memblocks_dma_arr =
Eric Dumazet89bf67f2010-11-22 00:15:06 +00002186 vzalloc(sizeof(struct vxge_hw_mempool_dma) *
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002187 mempool->memblocks_max);
2188
2189 if (mempool->memblocks_dma_arr == NULL) {
2190 __vxge_hw_mempool_destroy(mempool);
2191 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2192 mempool = NULL;
2193 goto exit;
2194 }
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002195
2196 /* allocate hash array of items */
Joe Perchese80be0b2010-11-27 23:05:45 +00002197 mempool->items_arr = vzalloc(sizeof(void *) * mempool->items_max);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002198 if (mempool->items_arr == NULL) {
2199 __vxge_hw_mempool_destroy(mempool);
2200 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2201 mempool = NULL;
2202 goto exit;
2203 }
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002204
2205 /* calculate initial number of memblocks */
2206 memblocks_to_allocate = (mempool->items_initial +
2207 mempool->items_per_memblock - 1) /
2208 mempool->items_per_memblock;
2209
2210 /* pre-allocate the mempool */
2211 status = __vxge_hw_mempool_grow(mempool, memblocks_to_allocate,
2212 &allocated);
2213 if (status != VXGE_HW_OK) {
2214 __vxge_hw_mempool_destroy(mempool);
2215 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2216 mempool = NULL;
2217 goto exit;
2218 }
2219
2220exit:
2221 return mempool;
2222}
2223
2224/*
2225 * vxge_hw_mempool_destroy
2226 */
stephen hemminger42821a52010-10-21 07:50:53 +00002227static void __vxge_hw_mempool_destroy(struct vxge_hw_mempool *mempool)
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002228{
2229 u32 i, j;
2230 struct __vxge_hw_device *devh = mempool->devh;
2231
2232 for (i = 0; i < mempool->memblocks_allocated; i++) {
2233 struct vxge_hw_mempool_dma *dma_object;
2234
2235 vxge_assert(mempool->memblocks_arr[i]);
2236 vxge_assert(mempool->memblocks_dma_arr + i);
2237
2238 dma_object = mempool->memblocks_dma_arr + i;
2239
2240 for (j = 0; j < mempool->items_per_memblock; j++) {
2241 u32 index = i * mempool->items_per_memblock + j;
2242
2243 /* to skip last partially filled(if any) memblock */
2244 if (index >= mempool->items_current)
2245 break;
2246 }
2247
2248 vfree(mempool->memblocks_priv_arr[i]);
2249
2250 __vxge_hw_blockpool_free(devh, mempool->memblocks_arr[i],
2251 mempool->memblock_size, dma_object);
2252 }
2253
Figo.zhang50d36a92009-06-10 04:21:55 +00002254 vfree(mempool->items_arr);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002255
Figo.zhang50d36a92009-06-10 04:21:55 +00002256 vfree(mempool->memblocks_dma_arr);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002257
Figo.zhang50d36a92009-06-10 04:21:55 +00002258 vfree(mempool->memblocks_priv_arr);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002259
Figo.zhang50d36a92009-06-10 04:21:55 +00002260 vfree(mempool->memblocks_arr);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002261
2262 vfree(mempool);
2263}
2264
2265/*
2266 * __vxge_hw_device_fifo_config_check - Check fifo configuration.
2267 * Check the fifo configuration
2268 */
Jon Mason2c913082010-11-11 04:26:03 +00002269static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002270__vxge_hw_device_fifo_config_check(struct vxge_hw_fifo_config *fifo_config)
2271{
2272 if ((fifo_config->fifo_blocks < VXGE_HW_MIN_FIFO_BLOCKS) ||
2273 (fifo_config->fifo_blocks > VXGE_HW_MAX_FIFO_BLOCKS))
2274 return VXGE_HW_BADCFG_FIFO_BLOCKS;
2275
2276 return VXGE_HW_OK;
2277}
2278
2279/*
2280 * __vxge_hw_device_vpath_config_check - Check vpath configuration.
2281 * Check the vpath configuration
2282 */
stephen hemminger42821a52010-10-21 07:50:53 +00002283static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002284__vxge_hw_device_vpath_config_check(struct vxge_hw_vp_config *vp_config)
2285{
2286 enum vxge_hw_status status;
2287
2288 if ((vp_config->min_bandwidth < VXGE_HW_VPATH_BANDWIDTH_MIN) ||
2289 (vp_config->min_bandwidth >
2290 VXGE_HW_VPATH_BANDWIDTH_MAX))
2291 return VXGE_HW_BADCFG_VPATH_MIN_BANDWIDTH;
2292
2293 status = __vxge_hw_device_fifo_config_check(&vp_config->fifo);
2294 if (status != VXGE_HW_OK)
2295 return status;
2296
2297 if ((vp_config->mtu != VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) &&
2298 ((vp_config->mtu < VXGE_HW_VPATH_MIN_INITIAL_MTU) ||
2299 (vp_config->mtu > VXGE_HW_VPATH_MAX_INITIAL_MTU)))
2300 return VXGE_HW_BADCFG_VPATH_MTU;
2301
2302 if ((vp_config->rpa_strip_vlan_tag !=
2303 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) &&
2304 (vp_config->rpa_strip_vlan_tag !=
2305 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_ENABLE) &&
2306 (vp_config->rpa_strip_vlan_tag !=
2307 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_DISABLE))
2308 return VXGE_HW_BADCFG_VPATH_RPA_STRIP_VLAN_TAG;
2309
2310 return VXGE_HW_OK;
2311}
2312
2313/*
2314 * __vxge_hw_device_config_check - Check device configuration.
2315 * Check the device configuration
2316 */
Jon Mason2c913082010-11-11 04:26:03 +00002317static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002318__vxge_hw_device_config_check(struct vxge_hw_device_config *new_config)
2319{
2320 u32 i;
2321 enum vxge_hw_status status;
2322
2323 if ((new_config->intr_mode != VXGE_HW_INTR_MODE_IRQLINE) &&
2324 (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX) &&
2325 (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) &&
2326 (new_config->intr_mode != VXGE_HW_INTR_MODE_DEF))
2327 return VXGE_HW_BADCFG_INTR_MODE;
2328
2329 if ((new_config->rts_mac_en != VXGE_HW_RTS_MAC_DISABLE) &&
2330 (new_config->rts_mac_en != VXGE_HW_RTS_MAC_ENABLE))
2331 return VXGE_HW_BADCFG_RTS_MAC_EN;
2332
2333 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
2334 status = __vxge_hw_device_vpath_config_check(
2335 &new_config->vp_config[i]);
2336 if (status != VXGE_HW_OK)
2337 return status;
2338 }
2339
2340 return VXGE_HW_OK;
2341}
2342
2343/*
2344 * vxge_hw_device_config_default_get - Initialize device config with defaults.
2345 * Initialize Titan device config with default values.
2346 */
2347enum vxge_hw_status __devinit
2348vxge_hw_device_config_default_get(struct vxge_hw_device_config *device_config)
2349{
2350 u32 i;
2351
2352 device_config->dma_blockpool_initial =
2353 VXGE_HW_INITIAL_DMA_BLOCK_POOL_SIZE;
2354 device_config->dma_blockpool_max = VXGE_HW_MAX_DMA_BLOCK_POOL_SIZE;
2355 device_config->intr_mode = VXGE_HW_INTR_MODE_DEF;
2356 device_config->rth_en = VXGE_HW_RTH_DEFAULT;
2357 device_config->rth_it_type = VXGE_HW_RTH_IT_TYPE_DEFAULT;
2358 device_config->device_poll_millis = VXGE_HW_DEF_DEVICE_POLL_MILLIS;
2359 device_config->rts_mac_en = VXGE_HW_RTS_MAC_DEFAULT;
2360
2361 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
2362
2363 device_config->vp_config[i].vp_id = i;
2364
2365 device_config->vp_config[i].min_bandwidth =
2366 VXGE_HW_VPATH_BANDWIDTH_DEFAULT;
2367
2368 device_config->vp_config[i].ring.enable = VXGE_HW_RING_DEFAULT;
2369
2370 device_config->vp_config[i].ring.ring_blocks =
2371 VXGE_HW_DEF_RING_BLOCKS;
2372
2373 device_config->vp_config[i].ring.buffer_mode =
2374 VXGE_HW_RING_RXD_BUFFER_MODE_DEFAULT;
2375
2376 device_config->vp_config[i].ring.scatter_mode =
2377 VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT;
2378
2379 device_config->vp_config[i].ring.rxds_limit =
2380 VXGE_HW_DEF_RING_RXDS_LIMIT;
2381
2382 device_config->vp_config[i].fifo.enable = VXGE_HW_FIFO_ENABLE;
2383
2384 device_config->vp_config[i].fifo.fifo_blocks =
2385 VXGE_HW_MIN_FIFO_BLOCKS;
2386
2387 device_config->vp_config[i].fifo.max_frags =
2388 VXGE_HW_MAX_FIFO_FRAGS;
2389
2390 device_config->vp_config[i].fifo.memblock_size =
2391 VXGE_HW_DEF_FIFO_MEMBLOCK_SIZE;
2392
2393 device_config->vp_config[i].fifo.alignment_size =
2394 VXGE_HW_DEF_FIFO_ALIGNMENT_SIZE;
2395
2396 device_config->vp_config[i].fifo.intr =
2397 VXGE_HW_FIFO_QUEUE_INTR_DEFAULT;
2398
2399 device_config->vp_config[i].fifo.no_snoop_bits =
2400 VXGE_HW_FIFO_NO_SNOOP_DEFAULT;
2401 device_config->vp_config[i].tti.intr_enable =
2402 VXGE_HW_TIM_INTR_DEFAULT;
2403
2404 device_config->vp_config[i].tti.btimer_val =
2405 VXGE_HW_USE_FLASH_DEFAULT;
2406
2407 device_config->vp_config[i].tti.timer_ac_en =
2408 VXGE_HW_USE_FLASH_DEFAULT;
2409
2410 device_config->vp_config[i].tti.timer_ci_en =
2411 VXGE_HW_USE_FLASH_DEFAULT;
2412
2413 device_config->vp_config[i].tti.timer_ri_en =
2414 VXGE_HW_USE_FLASH_DEFAULT;
2415
2416 device_config->vp_config[i].tti.rtimer_val =
2417 VXGE_HW_USE_FLASH_DEFAULT;
2418
2419 device_config->vp_config[i].tti.util_sel =
2420 VXGE_HW_USE_FLASH_DEFAULT;
2421
2422 device_config->vp_config[i].tti.ltimer_val =
2423 VXGE_HW_USE_FLASH_DEFAULT;
2424
2425 device_config->vp_config[i].tti.urange_a =
2426 VXGE_HW_USE_FLASH_DEFAULT;
2427
2428 device_config->vp_config[i].tti.uec_a =
2429 VXGE_HW_USE_FLASH_DEFAULT;
2430
2431 device_config->vp_config[i].tti.urange_b =
2432 VXGE_HW_USE_FLASH_DEFAULT;
2433
2434 device_config->vp_config[i].tti.uec_b =
2435 VXGE_HW_USE_FLASH_DEFAULT;
2436
2437 device_config->vp_config[i].tti.urange_c =
2438 VXGE_HW_USE_FLASH_DEFAULT;
2439
2440 device_config->vp_config[i].tti.uec_c =
2441 VXGE_HW_USE_FLASH_DEFAULT;
2442
2443 device_config->vp_config[i].tti.uec_d =
2444 VXGE_HW_USE_FLASH_DEFAULT;
2445
2446 device_config->vp_config[i].rti.intr_enable =
2447 VXGE_HW_TIM_INTR_DEFAULT;
2448
2449 device_config->vp_config[i].rti.btimer_val =
2450 VXGE_HW_USE_FLASH_DEFAULT;
2451
2452 device_config->vp_config[i].rti.timer_ac_en =
2453 VXGE_HW_USE_FLASH_DEFAULT;
2454
2455 device_config->vp_config[i].rti.timer_ci_en =
2456 VXGE_HW_USE_FLASH_DEFAULT;
2457
2458 device_config->vp_config[i].rti.timer_ri_en =
2459 VXGE_HW_USE_FLASH_DEFAULT;
2460
2461 device_config->vp_config[i].rti.rtimer_val =
2462 VXGE_HW_USE_FLASH_DEFAULT;
2463
2464 device_config->vp_config[i].rti.util_sel =
2465 VXGE_HW_USE_FLASH_DEFAULT;
2466
2467 device_config->vp_config[i].rti.ltimer_val =
2468 VXGE_HW_USE_FLASH_DEFAULT;
2469
2470 device_config->vp_config[i].rti.urange_a =
2471 VXGE_HW_USE_FLASH_DEFAULT;
2472
2473 device_config->vp_config[i].rti.uec_a =
2474 VXGE_HW_USE_FLASH_DEFAULT;
2475
2476 device_config->vp_config[i].rti.urange_b =
2477 VXGE_HW_USE_FLASH_DEFAULT;
2478
2479 device_config->vp_config[i].rti.uec_b =
2480 VXGE_HW_USE_FLASH_DEFAULT;
2481
2482 device_config->vp_config[i].rti.urange_c =
2483 VXGE_HW_USE_FLASH_DEFAULT;
2484
2485 device_config->vp_config[i].rti.uec_c =
2486 VXGE_HW_USE_FLASH_DEFAULT;
2487
2488 device_config->vp_config[i].rti.uec_d =
2489 VXGE_HW_USE_FLASH_DEFAULT;
2490
2491 device_config->vp_config[i].mtu =
2492 VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU;
2493
2494 device_config->vp_config[i].rpa_strip_vlan_tag =
2495 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT;
2496 }
2497
2498 return VXGE_HW_OK;
2499}
2500
2501/*
2502 * _hw_legacy_swapper_set - Set the swapper bits for the legacy secion.
2503 * Set the swapper bits appropriately for the lagacy section.
2504 */
stephen hemminger42821a52010-10-21 07:50:53 +00002505static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002506__vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg)
2507{
2508 u64 val64;
2509 enum vxge_hw_status status = VXGE_HW_OK;
2510
2511 val64 = readq(&legacy_reg->toc_swapper_fb);
2512
2513 wmb();
2514
2515 switch (val64) {
2516
2517 case VXGE_HW_SWAPPER_INITIAL_VALUE:
2518 return status;
2519
2520 case VXGE_HW_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED:
2521 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
2522 &legacy_reg->pifm_rd_swap_en);
2523 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
2524 &legacy_reg->pifm_rd_flip_en);
2525 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
2526 &legacy_reg->pifm_wr_swap_en);
2527 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
2528 &legacy_reg->pifm_wr_flip_en);
2529 break;
2530
2531 case VXGE_HW_SWAPPER_BYTE_SWAPPED:
2532 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
2533 &legacy_reg->pifm_rd_swap_en);
2534 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
2535 &legacy_reg->pifm_wr_swap_en);
2536 break;
2537
2538 case VXGE_HW_SWAPPER_BIT_FLIPPED:
2539 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
2540 &legacy_reg->pifm_rd_flip_en);
2541 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
2542 &legacy_reg->pifm_wr_flip_en);
2543 break;
2544 }
2545
2546 wmb();
2547
2548 val64 = readq(&legacy_reg->toc_swapper_fb);
2549
2550 if (val64 != VXGE_HW_SWAPPER_INITIAL_VALUE)
2551 status = VXGE_HW_ERR_SWAPPER_CTRL;
2552
2553 return status;
2554}
2555
2556/*
2557 * __vxge_hw_vpath_swapper_set - Set the swapper bits for the vpath.
2558 * Set the swapper bits appropriately for the vpath.
2559 */
stephen hemminger42821a52010-10-21 07:50:53 +00002560static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002561__vxge_hw_vpath_swapper_set(struct vxge_hw_vpath_reg __iomem *vpath_reg)
2562{
2563#ifndef __BIG_ENDIAN
2564 u64 val64;
2565
2566 val64 = readq(&vpath_reg->vpath_general_cfg1);
2567 wmb();
2568 val64 |= VXGE_HW_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN;
2569 writeq(val64, &vpath_reg->vpath_general_cfg1);
2570 wmb();
2571#endif
2572 return VXGE_HW_OK;
2573}
2574
2575/*
2576 * __vxge_hw_kdfc_swapper_set - Set the swapper bits for the kdfc.
2577 * Set the swapper bits appropriately for the vpath.
2578 */
stephen hemminger42821a52010-10-21 07:50:53 +00002579static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002580__vxge_hw_kdfc_swapper_set(
2581 struct vxge_hw_legacy_reg __iomem *legacy_reg,
2582 struct vxge_hw_vpath_reg __iomem *vpath_reg)
2583{
2584 u64 val64;
2585
2586 val64 = readq(&legacy_reg->pifm_wr_swap_en);
2587
2588 if (val64 == VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE) {
2589 val64 = readq(&vpath_reg->kdfcctl_cfg0);
2590 wmb();
2591
2592 val64 |= VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0 |
2593 VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1 |
2594 VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2;
2595
2596 writeq(val64, &vpath_reg->kdfcctl_cfg0);
2597 wmb();
2598 }
2599
2600 return VXGE_HW_OK;
2601}
2602
2603/*
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002604 * vxge_hw_mgmt_reg_read - Read Titan register.
2605 */
2606enum vxge_hw_status
2607vxge_hw_mgmt_reg_read(struct __vxge_hw_device *hldev,
2608 enum vxge_hw_mgmt_reg_type type,
2609 u32 index, u32 offset, u64 *value)
2610{
2611 enum vxge_hw_status status = VXGE_HW_OK;
2612
2613 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
2614 status = VXGE_HW_ERR_INVALID_DEVICE;
2615 goto exit;
2616 }
2617
2618 switch (type) {
2619 case vxge_hw_mgmt_reg_type_legacy:
2620 if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) {
2621 status = VXGE_HW_ERR_INVALID_OFFSET;
2622 break;
2623 }
2624 *value = readq((void __iomem *)hldev->legacy_reg + offset);
2625 break;
2626 case vxge_hw_mgmt_reg_type_toc:
2627 if (offset > sizeof(struct vxge_hw_toc_reg) - 8) {
2628 status = VXGE_HW_ERR_INVALID_OFFSET;
2629 break;
2630 }
2631 *value = readq((void __iomem *)hldev->toc_reg + offset);
2632 break;
2633 case vxge_hw_mgmt_reg_type_common:
2634 if (offset > sizeof(struct vxge_hw_common_reg) - 8) {
2635 status = VXGE_HW_ERR_INVALID_OFFSET;
2636 break;
2637 }
2638 *value = readq((void __iomem *)hldev->common_reg + offset);
2639 break;
2640 case vxge_hw_mgmt_reg_type_mrpcim:
2641 if (!(hldev->access_rights &
2642 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
2643 status = VXGE_HW_ERR_PRIVILAGED_OPEARATION;
2644 break;
2645 }
2646 if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) {
2647 status = VXGE_HW_ERR_INVALID_OFFSET;
2648 break;
2649 }
2650 *value = readq((void __iomem *)hldev->mrpcim_reg + offset);
2651 break;
2652 case vxge_hw_mgmt_reg_type_srpcim:
2653 if (!(hldev->access_rights &
2654 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) {
2655 status = VXGE_HW_ERR_PRIVILAGED_OPEARATION;
2656 break;
2657 }
2658 if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) {
2659 status = VXGE_HW_ERR_INVALID_INDEX;
2660 break;
2661 }
2662 if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) {
2663 status = VXGE_HW_ERR_INVALID_OFFSET;
2664 break;
2665 }
2666 *value = readq((void __iomem *)hldev->srpcim_reg[index] +
2667 offset);
2668 break;
2669 case vxge_hw_mgmt_reg_type_vpmgmt:
2670 if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) ||
2671 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
2672 status = VXGE_HW_ERR_INVALID_INDEX;
2673 break;
2674 }
2675 if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) {
2676 status = VXGE_HW_ERR_INVALID_OFFSET;
2677 break;
2678 }
2679 *value = readq((void __iomem *)hldev->vpmgmt_reg[index] +
2680 offset);
2681 break;
2682 case vxge_hw_mgmt_reg_type_vpath:
2683 if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) ||
2684 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
2685 status = VXGE_HW_ERR_INVALID_INDEX;
2686 break;
2687 }
2688 if (index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) {
2689 status = VXGE_HW_ERR_INVALID_INDEX;
2690 break;
2691 }
2692 if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) {
2693 status = VXGE_HW_ERR_INVALID_OFFSET;
2694 break;
2695 }
2696 *value = readq((void __iomem *)hldev->vpath_reg[index] +
2697 offset);
2698 break;
2699 default:
2700 status = VXGE_HW_ERR_INVALID_TYPE;
2701 break;
2702 }
2703
2704exit:
2705 return status;
2706}
2707
2708/*
Sreenivasa Honnurfa41fd12009-10-05 01:56:35 +00002709 * vxge_hw_vpath_strip_fcs_check - Check for FCS strip.
2710 */
2711enum vxge_hw_status
2712vxge_hw_vpath_strip_fcs_check(struct __vxge_hw_device *hldev, u64 vpath_mask)
2713{
2714 struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg;
2715 enum vxge_hw_status status = VXGE_HW_OK;
2716 int i = 0, j = 0;
2717
2718 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
2719 if (!((vpath_mask) & vxge_mBIT(i)))
2720 continue;
2721 vpmgmt_reg = hldev->vpmgmt_reg[i];
2722 for (j = 0; j < VXGE_HW_MAC_MAX_MAC_PORT_ID; j++) {
2723 if (readq(&vpmgmt_reg->rxmac_cfg0_port_vpmgmt_clone[j])
2724 & VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_STRIP_FCS)
2725 return VXGE_HW_FAIL;
2726 }
2727 }
2728 return status;
2729}
2730/*
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002731 * vxge_hw_mgmt_reg_Write - Write Titan register.
2732 */
2733enum vxge_hw_status
2734vxge_hw_mgmt_reg_write(struct __vxge_hw_device *hldev,
2735 enum vxge_hw_mgmt_reg_type type,
2736 u32 index, u32 offset, u64 value)
2737{
2738 enum vxge_hw_status status = VXGE_HW_OK;
2739
2740 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
2741 status = VXGE_HW_ERR_INVALID_DEVICE;
2742 goto exit;
2743 }
2744
2745 switch (type) {
2746 case vxge_hw_mgmt_reg_type_legacy:
2747 if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) {
2748 status = VXGE_HW_ERR_INVALID_OFFSET;
2749 break;
2750 }
2751 writeq(value, (void __iomem *)hldev->legacy_reg + offset);
2752 break;
2753 case vxge_hw_mgmt_reg_type_toc:
2754 if (offset > sizeof(struct vxge_hw_toc_reg) - 8) {
2755 status = VXGE_HW_ERR_INVALID_OFFSET;
2756 break;
2757 }
2758 writeq(value, (void __iomem *)hldev->toc_reg + offset);
2759 break;
2760 case vxge_hw_mgmt_reg_type_common:
2761 if (offset > sizeof(struct vxge_hw_common_reg) - 8) {
2762 status = VXGE_HW_ERR_INVALID_OFFSET;
2763 break;
2764 }
2765 writeq(value, (void __iomem *)hldev->common_reg + offset);
2766 break;
2767 case vxge_hw_mgmt_reg_type_mrpcim:
2768 if (!(hldev->access_rights &
2769 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
2770 status = VXGE_HW_ERR_PRIVILAGED_OPEARATION;
2771 break;
2772 }
2773 if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) {
2774 status = VXGE_HW_ERR_INVALID_OFFSET;
2775 break;
2776 }
2777 writeq(value, (void __iomem *)hldev->mrpcim_reg + offset);
2778 break;
2779 case vxge_hw_mgmt_reg_type_srpcim:
2780 if (!(hldev->access_rights &
2781 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) {
2782 status = VXGE_HW_ERR_PRIVILAGED_OPEARATION;
2783 break;
2784 }
2785 if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) {
2786 status = VXGE_HW_ERR_INVALID_INDEX;
2787 break;
2788 }
2789 if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) {
2790 status = VXGE_HW_ERR_INVALID_OFFSET;
2791 break;
2792 }
2793 writeq(value, (void __iomem *)hldev->srpcim_reg[index] +
2794 offset);
2795
2796 break;
2797 case vxge_hw_mgmt_reg_type_vpmgmt:
2798 if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) ||
2799 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
2800 status = VXGE_HW_ERR_INVALID_INDEX;
2801 break;
2802 }
2803 if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) {
2804 status = VXGE_HW_ERR_INVALID_OFFSET;
2805 break;
2806 }
2807 writeq(value, (void __iomem *)hldev->vpmgmt_reg[index] +
2808 offset);
2809 break;
2810 case vxge_hw_mgmt_reg_type_vpath:
2811 if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES-1) ||
2812 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
2813 status = VXGE_HW_ERR_INVALID_INDEX;
2814 break;
2815 }
2816 if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) {
2817 status = VXGE_HW_ERR_INVALID_OFFSET;
2818 break;
2819 }
2820 writeq(value, (void __iomem *)hldev->vpath_reg[index] +
2821 offset);
2822 break;
2823 default:
2824 status = VXGE_HW_ERR_INVALID_TYPE;
2825 break;
2826 }
2827exit:
2828 return status;
2829}
2830
2831/*
2832 * __vxge_hw_fifo_mempool_item_alloc - Allocate List blocks for TxD
2833 * list callback
2834 * This function is callback passed to __vxge_hw_mempool_create to create memory
2835 * pool for TxD list
2836 */
2837static void
2838__vxge_hw_fifo_mempool_item_alloc(
2839 struct vxge_hw_mempool *mempoolh,
2840 u32 memblock_index, struct vxge_hw_mempool_dma *dma_object,
2841 u32 index, u32 is_last)
2842{
2843 u32 memblock_item_idx;
2844 struct __vxge_hw_fifo_txdl_priv *txdl_priv;
2845 struct vxge_hw_fifo_txd *txdp =
2846 (struct vxge_hw_fifo_txd *)mempoolh->items_arr[index];
2847 struct __vxge_hw_fifo *fifo =
2848 (struct __vxge_hw_fifo *)mempoolh->userdata;
2849 void *memblock = mempoolh->memblocks_arr[memblock_index];
2850
2851 vxge_assert(txdp);
2852
2853 txdp->host_control = (u64) (size_t)
2854 __vxge_hw_mempool_item_priv(mempoolh, memblock_index, txdp,
2855 &memblock_item_idx);
2856
2857 txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdp);
2858
2859 vxge_assert(txdl_priv);
2860
2861 fifo->channel.reserve_arr[fifo->channel.reserve_ptr - 1 - index] = txdp;
2862
2863 /* pre-format HW's TxDL's private */
2864 txdl_priv->dma_offset = (char *)txdp - (char *)memblock;
2865 txdl_priv->dma_addr = dma_object->addr + txdl_priv->dma_offset;
2866 txdl_priv->dma_handle = dma_object->handle;
2867 txdl_priv->memblock = memblock;
2868 txdl_priv->first_txdp = txdp;
2869 txdl_priv->next_txdl_priv = NULL;
2870 txdl_priv->alloc_frags = 0;
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002871}
2872
2873/*
2874 * __vxge_hw_fifo_create - Create a FIFO
2875 * This function creates FIFO and initializes it.
2876 */
Jon Mason2c913082010-11-11 04:26:03 +00002877static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00002878__vxge_hw_fifo_create(struct __vxge_hw_vpath_handle *vp,
2879 struct vxge_hw_fifo_attr *attr)
2880{
2881 enum vxge_hw_status status = VXGE_HW_OK;
2882 struct __vxge_hw_fifo *fifo;
2883 struct vxge_hw_fifo_config *config;
2884 u32 txdl_size, txdl_per_memblock;
2885 struct vxge_hw_mempool_cbs fifo_mp_callback;
2886 struct __vxge_hw_virtualpath *vpath;
2887
2888 if ((vp == NULL) || (attr == NULL)) {
2889 status = VXGE_HW_ERR_INVALID_HANDLE;
2890 goto exit;
2891 }
2892 vpath = vp->vpath;
2893 config = &vpath->hldev->config.vp_config[vpath->vp_id].fifo;
2894
2895 txdl_size = config->max_frags * sizeof(struct vxge_hw_fifo_txd);
2896
2897 txdl_per_memblock = config->memblock_size / txdl_size;
2898
2899 fifo = (struct __vxge_hw_fifo *)__vxge_hw_channel_allocate(vp,
2900 VXGE_HW_CHANNEL_TYPE_FIFO,
2901 config->fifo_blocks * txdl_per_memblock,
2902 attr->per_txdl_space, attr->userdata);
2903
2904 if (fifo == NULL) {
2905 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2906 goto exit;
2907 }
2908
2909 vpath->fifoh = fifo;
2910 fifo->nofl_db = vpath->nofl_db;
2911
2912 fifo->vp_id = vpath->vp_id;
2913 fifo->vp_reg = vpath->vp_reg;
2914 fifo->stats = &vpath->sw_stats->fifo_stats;
2915
2916 fifo->config = config;
2917
2918 /* apply "interrupts per txdl" attribute */
2919 fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_UTILZ;
2920
2921 if (fifo->config->intr)
2922 fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST;
2923
2924 fifo->no_snoop_bits = config->no_snoop_bits;
2925
2926 /*
2927 * FIFO memory management strategy:
2928 *
2929 * TxDL split into three independent parts:
2930 * - set of TxD's
2931 * - TxD HW private part
2932 * - driver private part
2933 *
2934 * Adaptative memory allocation used. i.e. Memory allocated on
2935 * demand with the size which will fit into one memory block.
2936 * One memory block may contain more than one TxDL.
2937 *
2938 * During "reserve" operations more memory can be allocated on demand
2939 * for example due to FIFO full condition.
2940 *
2941 * Pool of memory memblocks never shrinks except in __vxge_hw_fifo_close
2942 * routine which will essentially stop the channel and free resources.
2943 */
2944
2945 /* TxDL common private size == TxDL private + driver private */
2946 fifo->priv_size =
2947 sizeof(struct __vxge_hw_fifo_txdl_priv) + attr->per_txdl_space;
2948 fifo->priv_size = ((fifo->priv_size + VXGE_CACHE_LINE_SIZE - 1) /
2949 VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE;
2950
2951 fifo->per_txdl_space = attr->per_txdl_space;
2952
2953 /* recompute txdl size to be cacheline aligned */
2954 fifo->txdl_size = txdl_size;
2955 fifo->txdl_per_memblock = txdl_per_memblock;
2956
2957 fifo->txdl_term = attr->txdl_term;
2958 fifo->callback = attr->callback;
2959
2960 if (fifo->txdl_per_memblock == 0) {
2961 __vxge_hw_fifo_delete(vp);
2962 status = VXGE_HW_ERR_INVALID_BLOCK_SIZE;
2963 goto exit;
2964 }
2965
2966 fifo_mp_callback.item_func_alloc = __vxge_hw_fifo_mempool_item_alloc;
2967
2968 fifo->mempool =
2969 __vxge_hw_mempool_create(vpath->hldev,
2970 fifo->config->memblock_size,
2971 fifo->txdl_size,
2972 fifo->priv_size,
2973 (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
2974 (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
2975 &fifo_mp_callback,
2976 fifo);
2977
2978 if (fifo->mempool == NULL) {
2979 __vxge_hw_fifo_delete(vp);
2980 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2981 goto exit;
2982 }
2983
2984 status = __vxge_hw_channel_initialize(&fifo->channel);
2985 if (status != VXGE_HW_OK) {
2986 __vxge_hw_fifo_delete(vp);
2987 goto exit;
2988 }
2989
2990 vxge_assert(fifo->channel.reserve_ptr);
2991exit:
2992 return status;
2993}
2994
2995/*
2996 * __vxge_hw_fifo_abort - Returns the TxD
2997 * This function terminates the TxDs of fifo
2998 */
stephen hemminger42821a52010-10-21 07:50:53 +00002999static enum vxge_hw_status __vxge_hw_fifo_abort(struct __vxge_hw_fifo *fifo)
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003000{
3001 void *txdlh;
3002
3003 for (;;) {
3004 vxge_hw_channel_dtr_try_complete(&fifo->channel, &txdlh);
3005
3006 if (txdlh == NULL)
3007 break;
3008
3009 vxge_hw_channel_dtr_complete(&fifo->channel);
3010
3011 if (fifo->txdl_term) {
3012 fifo->txdl_term(txdlh,
3013 VXGE_HW_TXDL_STATE_POSTED,
3014 fifo->channel.userdata);
3015 }
3016
3017 vxge_hw_channel_dtr_free(&fifo->channel, txdlh);
3018 }
3019
3020 return VXGE_HW_OK;
3021}
3022
3023/*
3024 * __vxge_hw_fifo_reset - Resets the fifo
3025 * This function resets the fifo during vpath reset operation
3026 */
stephen hemminger42821a52010-10-21 07:50:53 +00003027static enum vxge_hw_status __vxge_hw_fifo_reset(struct __vxge_hw_fifo *fifo)
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003028{
3029 enum vxge_hw_status status = VXGE_HW_OK;
3030
3031 __vxge_hw_fifo_abort(fifo);
3032 status = __vxge_hw_channel_reset(&fifo->channel);
3033
3034 return status;
3035}
3036
3037/*
3038 * __vxge_hw_fifo_delete - Removes the FIFO
3039 * This function freeup the memory pool and removes the FIFO
3040 */
Jon Mason2c913082010-11-11 04:26:03 +00003041static enum vxge_hw_status
3042__vxge_hw_fifo_delete(struct __vxge_hw_vpath_handle *vp)
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003043{
3044 struct __vxge_hw_fifo *fifo = vp->vpath->fifoh;
3045
3046 __vxge_hw_fifo_abort(fifo);
3047
3048 if (fifo->mempool)
3049 __vxge_hw_mempool_destroy(fifo->mempool);
3050
3051 vp->vpath->fifoh = NULL;
3052
3053 __vxge_hw_channel_free(&fifo->channel);
3054
3055 return VXGE_HW_OK;
3056}
3057
3058/*
3059 * __vxge_hw_vpath_pci_read - Read the content of given address
3060 * in pci config space.
3061 * Read from the vpath pci config space.
3062 */
stephen hemminger42821a52010-10-21 07:50:53 +00003063static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003064__vxge_hw_vpath_pci_read(struct __vxge_hw_virtualpath *vpath,
3065 u32 phy_func_0, u32 offset, u32 *val)
3066{
3067 u64 val64;
3068 enum vxge_hw_status status = VXGE_HW_OK;
3069 struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;
3070
3071 val64 = VXGE_HW_PCI_CONFIG_ACCESS_CFG1_ADDRESS(offset);
3072
3073 if (phy_func_0)
3074 val64 |= VXGE_HW_PCI_CONFIG_ACCESS_CFG1_SEL_FUNC0;
3075
3076 writeq(val64, &vp_reg->pci_config_access_cfg1);
3077 wmb();
3078 writeq(VXGE_HW_PCI_CONFIG_ACCESS_CFG2_REQ,
3079 &vp_reg->pci_config_access_cfg2);
3080 wmb();
3081
3082 status = __vxge_hw_device_register_poll(
3083 &vp_reg->pci_config_access_cfg2,
3084 VXGE_HW_INTR_MASK_ALL, VXGE_HW_DEF_DEVICE_POLL_MILLIS);
3085
3086 if (status != VXGE_HW_OK)
3087 goto exit;
3088
3089 val64 = readq(&vp_reg->pci_config_access_status);
3090
3091 if (val64 & VXGE_HW_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR) {
3092 status = VXGE_HW_FAIL;
3093 *val = 0;
3094 } else
3095 *val = (u32)vxge_bVALn(val64, 32, 32);
3096exit:
3097 return status;
3098}
3099
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003100/**
3101 * vxge_hw_device_flick_link_led - Flick (blink) link LED.
3102 * @hldev: HW device.
3103 * @on_off: TRUE if flickering to be on, FALSE to be off
3104 *
3105 * Flicker the link LED.
3106 */
3107enum vxge_hw_status
Jon Mason8424e002010-11-11 04:25:56 +00003108vxge_hw_device_flick_link_led(struct __vxge_hw_device *hldev, u64 on_off)
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003109{
Jon Mason8424e002010-11-11 04:25:56 +00003110 struct __vxge_hw_virtualpath *vpath;
3111 u64 data0, data1 = 0, steer_ctrl = 0;
3112 enum vxge_hw_status status;
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003113
3114 if (hldev == NULL) {
3115 status = VXGE_HW_ERR_INVALID_DEVICE;
3116 goto exit;
3117 }
3118
Jon Mason8424e002010-11-11 04:25:56 +00003119 vpath = &hldev->virtual_paths[hldev->first_vp_id];
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003120
Jon Mason8424e002010-11-11 04:25:56 +00003121 data0 = on_off;
3122 status = vxge_hw_vpath_fw_api(vpath,
3123 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL,
3124 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
3125 0, &data0, &data1, &steer_ctrl);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003126exit:
3127 return status;
3128}
3129
3130/*
3131 * __vxge_hw_vpath_rts_table_get - Get the entries from RTS access tables
3132 */
3133enum vxge_hw_status
Jon Mason8424e002010-11-11 04:25:56 +00003134__vxge_hw_vpath_rts_table_get(struct __vxge_hw_vpath_handle *vp,
3135 u32 action, u32 rts_table, u32 offset,
3136 u64 *data0, u64 *data1)
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003137{
Jon Mason8424e002010-11-11 04:25:56 +00003138 enum vxge_hw_status status;
3139 u64 steer_ctrl = 0;
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003140
3141 if (vp == NULL) {
3142 status = VXGE_HW_ERR_INVALID_HANDLE;
3143 goto exit;
3144 }
3145
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003146 if ((rts_table ==
Jon Mason8424e002010-11-11 04:25:56 +00003147 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT) ||
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003148 (rts_table ==
Jon Mason8424e002010-11-11 04:25:56 +00003149 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT) ||
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003150 (rts_table ==
Jon Mason8424e002010-11-11 04:25:56 +00003151 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK) ||
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003152 (rts_table ==
Jon Mason8424e002010-11-11 04:25:56 +00003153 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY)) {
3154 steer_ctrl = VXGE_HW_RTS_ACCESS_STEER_CTRL_TABLE_SEL;
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003155 }
3156
Jon Mason8424e002010-11-11 04:25:56 +00003157 status = vxge_hw_vpath_fw_api(vp->vpath, action, rts_table, offset,
3158 data0, data1, &steer_ctrl);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003159 if (status != VXGE_HW_OK)
3160 goto exit;
3161
Jon Mason8424e002010-11-11 04:25:56 +00003162 if ((rts_table != VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) ||
3163 (rts_table !=
3164 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT))
3165 *data1 = 0;
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003166exit:
3167 return status;
3168}
3169
3170/*
3171 * __vxge_hw_vpath_rts_table_set - Set the entries of RTS access tables
3172 */
3173enum vxge_hw_status
Jon Mason8424e002010-11-11 04:25:56 +00003174__vxge_hw_vpath_rts_table_set(struct __vxge_hw_vpath_handle *vp, u32 action,
3175 u32 rts_table, u32 offset, u64 steer_data0,
3176 u64 steer_data1)
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003177{
Jon Mason8424e002010-11-11 04:25:56 +00003178 u64 data0, data1 = 0, steer_ctrl = 0;
3179 enum vxge_hw_status status;
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003180
3181 if (vp == NULL) {
3182 status = VXGE_HW_ERR_INVALID_HANDLE;
3183 goto exit;
3184 }
3185
Jon Mason8424e002010-11-11 04:25:56 +00003186 data0 = steer_data0;
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003187
3188 if ((rts_table == VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) ||
3189 (rts_table ==
Jon Mason8424e002010-11-11 04:25:56 +00003190 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT))
3191 data1 = steer_data1;
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003192
Jon Mason8424e002010-11-11 04:25:56 +00003193 status = vxge_hw_vpath_fw_api(vp->vpath, action, rts_table, offset,
3194 &data0, &data1, &steer_ctrl);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003195exit:
3196 return status;
3197}
3198
3199/*
3200 * vxge_hw_vpath_rts_rth_set - Set/configure RTS hashing.
3201 */
3202enum vxge_hw_status vxge_hw_vpath_rts_rth_set(
3203 struct __vxge_hw_vpath_handle *vp,
3204 enum vxge_hw_rth_algoritms algorithm,
3205 struct vxge_hw_rth_hash_types *hash_type,
3206 u16 bucket_size)
3207{
3208 u64 data0, data1;
3209 enum vxge_hw_status status = VXGE_HW_OK;
3210
3211 if (vp == NULL) {
3212 status = VXGE_HW_ERR_INVALID_HANDLE;
3213 goto exit;
3214 }
3215
3216 status = __vxge_hw_vpath_rts_table_get(vp,
3217 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
3218 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
3219 0, &data0, &data1);
Jon Mason47f01db2010-11-11 04:25:53 +00003220 if (status != VXGE_HW_OK)
3221 goto exit;
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003222
3223 data0 &= ~(VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(0xf) |
3224 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(0x3));
3225
3226 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN |
3227 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(bucket_size) |
3228 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(algorithm);
3229
3230 if (hash_type->hash_type_tcpipv4_en)
3231 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN;
3232
3233 if (hash_type->hash_type_ipv4_en)
3234 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV4_EN;
3235
3236 if (hash_type->hash_type_tcpipv6_en)
3237 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EN;
3238
3239 if (hash_type->hash_type_ipv6_en)
3240 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EN;
3241
3242 if (hash_type->hash_type_tcpipv6ex_en)
3243 data0 |=
3244 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EX_EN;
3245
3246 if (hash_type->hash_type_ipv6ex_en)
3247 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EX_EN;
3248
3249 if (VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(data0))
3250 data0 &= ~VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
3251 else
3252 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
3253
3254 status = __vxge_hw_vpath_rts_table_set(vp,
3255 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
3256 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
3257 0, data0, 0);
3258exit:
3259 return status;
3260}
3261
3262static void
3263vxge_hw_rts_rth_data0_data1_get(u32 j, u64 *data0, u64 *data1,
3264 u16 flag, u8 *itable)
3265{
3266 switch (flag) {
3267 case 1:
3268 *data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(j)|
3269 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_ENTRY_EN |
3270 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA(
3271 itable[j]);
3272 case 2:
3273 *data0 |=
3274 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(j)|
3275 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_ENTRY_EN |
3276 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA(
3277 itable[j]);
3278 case 3:
3279 *data1 = VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(j)|
3280 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_ENTRY_EN |
3281 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA(
3282 itable[j]);
3283 case 4:
3284 *data1 |=
3285 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(j)|
3286 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_ENTRY_EN |
3287 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA(
3288 itable[j]);
3289 default:
3290 return;
3291 }
3292}
3293/*
3294 * vxge_hw_vpath_rts_rth_itable_set - Set/configure indirection table (IT).
3295 */
3296enum vxge_hw_status vxge_hw_vpath_rts_rth_itable_set(
3297 struct __vxge_hw_vpath_handle **vpath_handles,
3298 u32 vpath_count,
3299 u8 *mtable,
3300 u8 *itable,
3301 u32 itable_size)
3302{
3303 u32 i, j, action, rts_table;
3304 u64 data0;
3305 u64 data1;
3306 u32 max_entries;
3307 enum vxge_hw_status status = VXGE_HW_OK;
3308 struct __vxge_hw_vpath_handle *vp = vpath_handles[0];
3309
3310 if (vp == NULL) {
3311 status = VXGE_HW_ERR_INVALID_HANDLE;
3312 goto exit;
3313 }
3314
3315 max_entries = (((u32)1) << itable_size);
3316
3317 if (vp->vpath->hldev->config.rth_it_type
3318 == VXGE_HW_RTH_IT_TYPE_SOLO_IT) {
3319 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY;
3320 rts_table =
3321 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT;
3322
3323 for (j = 0; j < max_entries; j++) {
3324
3325 data1 = 0;
3326
3327 data0 =
3328 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(
3329 itable[j]);
3330
3331 status = __vxge_hw_vpath_rts_table_set(vpath_handles[0],
3332 action, rts_table, j, data0, data1);
3333
3334 if (status != VXGE_HW_OK)
3335 goto exit;
3336 }
3337
3338 for (j = 0; j < max_entries; j++) {
3339
3340 data1 = 0;
3341
3342 data0 =
3343 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_ENTRY_EN |
3344 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(
3345 itable[j]);
3346
3347 status = __vxge_hw_vpath_rts_table_set(
3348 vpath_handles[mtable[itable[j]]], action,
3349 rts_table, j, data0, data1);
3350
3351 if (status != VXGE_HW_OK)
3352 goto exit;
3353 }
3354 } else {
3355 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY;
3356 rts_table =
3357 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT;
3358 for (i = 0; i < vpath_count; i++) {
3359
3360 for (j = 0; j < max_entries;) {
3361
3362 data0 = 0;
3363 data1 = 0;
3364
3365 while (j < max_entries) {
3366 if (mtable[itable[j]] != i) {
3367 j++;
3368 continue;
3369 }
3370 vxge_hw_rts_rth_data0_data1_get(j,
3371 &data0, &data1, 1, itable);
3372 j++;
3373 break;
3374 }
3375
3376 while (j < max_entries) {
3377 if (mtable[itable[j]] != i) {
3378 j++;
3379 continue;
3380 }
3381 vxge_hw_rts_rth_data0_data1_get(j,
3382 &data0, &data1, 2, itable);
3383 j++;
3384 break;
3385 }
3386
3387 while (j < max_entries) {
3388 if (mtable[itable[j]] != i) {
3389 j++;
3390 continue;
3391 }
3392 vxge_hw_rts_rth_data0_data1_get(j,
3393 &data0, &data1, 3, itable);
3394 j++;
3395 break;
3396 }
3397
3398 while (j < max_entries) {
3399 if (mtable[itable[j]] != i) {
3400 j++;
3401 continue;
3402 }
3403 vxge_hw_rts_rth_data0_data1_get(j,
3404 &data0, &data1, 4, itable);
3405 j++;
3406 break;
3407 }
3408
3409 if (data0 != 0) {
3410 status = __vxge_hw_vpath_rts_table_set(
3411 vpath_handles[i],
3412 action, rts_table,
3413 0, data0, data1);
3414
3415 if (status != VXGE_HW_OK)
3416 goto exit;
3417 }
3418 }
3419 }
3420 }
3421exit:
3422 return status;
3423}
3424
3425/**
3426 * vxge_hw_vpath_check_leak - Check for memory leak
3427 * @ringh: Handle to the ring object used for receive
3428 *
3429 * If PRC_RXD_DOORBELL_VPn.NEW_QW_CNT is larger or equal to
3430 * PRC_CFG6_VPn.RXD_SPAT then a leak has occurred.
3431 * Returns: VXGE_HW_FAIL, if leak has occurred.
3432 *
3433 */
3434enum vxge_hw_status
3435vxge_hw_vpath_check_leak(struct __vxge_hw_ring *ring)
3436{
3437 enum vxge_hw_status status = VXGE_HW_OK;
3438 u64 rxd_new_count, rxd_spat;
3439
3440 if (ring == NULL)
3441 return status;
3442
3443 rxd_new_count = readl(&ring->vp_reg->prc_rxd_doorbell);
3444 rxd_spat = readq(&ring->vp_reg->prc_cfg6);
3445 rxd_spat = VXGE_HW_PRC_CFG6_RXD_SPAT(rxd_spat);
3446
3447 if (rxd_new_count >= rxd_spat)
3448 status = VXGE_HW_FAIL;
3449
3450 return status;
3451}
3452
3453/*
3454 * __vxge_hw_vpath_mgmt_read
3455 * This routine reads the vpath_mgmt registers
3456 */
3457static enum vxge_hw_status
3458__vxge_hw_vpath_mgmt_read(
3459 struct __vxge_hw_device *hldev,
3460 struct __vxge_hw_virtualpath *vpath)
3461{
3462 u32 i, mtu = 0, max_pyld = 0;
3463 u64 val64;
3464 enum vxge_hw_status status = VXGE_HW_OK;
3465
3466 for (i = 0; i < VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) {
3467
3468 val64 = readq(&vpath->vpmgmt_reg->
3469 rxmac_cfg0_port_vpmgmt_clone[i]);
3470 max_pyld =
3471 (u32)
3472 VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN
3473 (val64);
3474 if (mtu < max_pyld)
3475 mtu = max_pyld;
3476 }
3477
3478 vpath->max_mtu = mtu + VXGE_HW_MAC_HEADER_MAX_SIZE;
3479
3480 val64 = readq(&vpath->vpmgmt_reg->xmac_vsport_choices_vp);
3481
3482 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
3483 if (val64 & vxge_mBIT(i))
3484 vpath->vsport_number = i;
3485 }
3486
3487 val64 = readq(&vpath->vpmgmt_reg->xgmac_gen_status_vpmgmt_clone);
3488
3489 if (val64 & VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK)
3490 VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_UP);
3491 else
3492 VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_DOWN);
3493
3494 return status;
3495}
3496
3497/*
3498 * __vxge_hw_vpath_reset_check - Check if resetting the vpath completed
3499 * This routine checks the vpath_rst_in_prog register to see if
3500 * adapter completed the reset process for the vpath
3501 */
stephen hemminger42821a52010-10-21 07:50:53 +00003502static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003503__vxge_hw_vpath_reset_check(struct __vxge_hw_virtualpath *vpath)
3504{
3505 enum vxge_hw_status status;
3506
3507 status = __vxge_hw_device_register_poll(
3508 &vpath->hldev->common_reg->vpath_rst_in_prog,
3509 VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(
3510 1 << (16 - vpath->vp_id)),
3511 vpath->hldev->config.device_poll_millis);
3512
3513 return status;
3514}
3515
3516/*
3517 * __vxge_hw_vpath_reset
3518 * This routine resets the vpath on the device
3519 */
stephen hemminger42821a52010-10-21 07:50:53 +00003520static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003521__vxge_hw_vpath_reset(struct __vxge_hw_device *hldev, u32 vp_id)
3522{
3523 u64 val64;
3524 enum vxge_hw_status status = VXGE_HW_OK;
3525
3526 val64 = VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(1 << (16 - vp_id));
3527
3528 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
3529 &hldev->common_reg->cmn_rsthdlr_cfg0);
3530
3531 return status;
3532}
3533
3534/*
3535 * __vxge_hw_vpath_sw_reset
3536 * This routine resets the vpath structures
3537 */
stephen hemminger42821a52010-10-21 07:50:53 +00003538static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003539__vxge_hw_vpath_sw_reset(struct __vxge_hw_device *hldev, u32 vp_id)
3540{
3541 enum vxge_hw_status status = VXGE_HW_OK;
3542 struct __vxge_hw_virtualpath *vpath;
3543
3544 vpath = (struct __vxge_hw_virtualpath *)&hldev->virtual_paths[vp_id];
3545
3546 if (vpath->ringh) {
3547 status = __vxge_hw_ring_reset(vpath->ringh);
3548 if (status != VXGE_HW_OK)
3549 goto exit;
3550 }
3551
3552 if (vpath->fifoh)
3553 status = __vxge_hw_fifo_reset(vpath->fifoh);
3554exit:
3555 return status;
3556}
3557
3558/*
3559 * __vxge_hw_vpath_prc_configure
3560 * This routine configures the prc registers of virtual path using the config
3561 * passed
3562 */
stephen hemminger42821a52010-10-21 07:50:53 +00003563static void
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003564__vxge_hw_vpath_prc_configure(struct __vxge_hw_device *hldev, u32 vp_id)
3565{
3566 u64 val64;
3567 struct __vxge_hw_virtualpath *vpath;
3568 struct vxge_hw_vp_config *vp_config;
3569 struct vxge_hw_vpath_reg __iomem *vp_reg;
3570
3571 vpath = &hldev->virtual_paths[vp_id];
3572 vp_reg = vpath->vp_reg;
3573 vp_config = vpath->vp_config;
3574
3575 if (vp_config->ring.enable == VXGE_HW_RING_DISABLE)
3576 return;
3577
3578 val64 = readq(&vp_reg->prc_cfg1);
3579 val64 |= VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE;
3580 writeq(val64, &vp_reg->prc_cfg1);
3581
3582 val64 = readq(&vpath->vp_reg->prc_cfg6);
3583 val64 |= VXGE_HW_PRC_CFG6_DOORBELL_MODE_EN;
3584 writeq(val64, &vpath->vp_reg->prc_cfg6);
3585
3586 val64 = readq(&vp_reg->prc_cfg7);
3587
3588 if (vpath->vp_config->ring.scatter_mode !=
3589 VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT) {
3590
3591 val64 &= ~VXGE_HW_PRC_CFG7_SCATTER_MODE(0x3);
3592
3593 switch (vpath->vp_config->ring.scatter_mode) {
3594 case VXGE_HW_RING_SCATTER_MODE_A:
3595 val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
3596 VXGE_HW_PRC_CFG7_SCATTER_MODE_A);
3597 break;
3598 case VXGE_HW_RING_SCATTER_MODE_B:
3599 val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
3600 VXGE_HW_PRC_CFG7_SCATTER_MODE_B);
3601 break;
3602 case VXGE_HW_RING_SCATTER_MODE_C:
3603 val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
3604 VXGE_HW_PRC_CFG7_SCATTER_MODE_C);
3605 break;
3606 }
3607 }
3608
3609 writeq(val64, &vp_reg->prc_cfg7);
3610
3611 writeq(VXGE_HW_PRC_CFG5_RXD0_ADD(
3612 __vxge_hw_ring_first_block_address_get(
3613 vpath->ringh) >> 3), &vp_reg->prc_cfg5);
3614
3615 val64 = readq(&vp_reg->prc_cfg4);
3616 val64 |= VXGE_HW_PRC_CFG4_IN_SVC;
3617 val64 &= ~VXGE_HW_PRC_CFG4_RING_MODE(0x3);
3618
3619 val64 |= VXGE_HW_PRC_CFG4_RING_MODE(
3620 VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER);
3621
3622 if (hldev->config.rth_en == VXGE_HW_RTH_DISABLE)
3623 val64 |= VXGE_HW_PRC_CFG4_RTH_DISABLE;
3624 else
3625 val64 &= ~VXGE_HW_PRC_CFG4_RTH_DISABLE;
3626
3627 writeq(val64, &vp_reg->prc_cfg4);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003628}
3629
3630/*
3631 * __vxge_hw_vpath_kdfc_configure
3632 * This routine configures the kdfc registers of virtual path using the
3633 * config passed
3634 */
stephen hemminger42821a52010-10-21 07:50:53 +00003635static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003636__vxge_hw_vpath_kdfc_configure(struct __vxge_hw_device *hldev, u32 vp_id)
3637{
3638 u64 val64;
3639 u64 vpath_stride;
3640 enum vxge_hw_status status = VXGE_HW_OK;
3641 struct __vxge_hw_virtualpath *vpath;
3642 struct vxge_hw_vpath_reg __iomem *vp_reg;
3643
3644 vpath = &hldev->virtual_paths[vp_id];
3645 vp_reg = vpath->vp_reg;
3646 status = __vxge_hw_kdfc_swapper_set(hldev->legacy_reg, vp_reg);
3647
3648 if (status != VXGE_HW_OK)
3649 goto exit;
3650
3651 val64 = readq(&vp_reg->kdfc_drbl_triplet_total);
3652
3653 vpath->max_kdfc_db =
3654 (u32)VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(
3655 val64+1)/2;
3656
3657 if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
3658
3659 vpath->max_nofl_db = vpath->max_kdfc_db;
3660
3661 if (vpath->max_nofl_db <
3662 ((vpath->vp_config->fifo.memblock_size /
3663 (vpath->vp_config->fifo.max_frags *
3664 sizeof(struct vxge_hw_fifo_txd))) *
3665 vpath->vp_config->fifo.fifo_blocks)) {
3666
3667 return VXGE_HW_BADCFG_FIFO_BLOCKS;
3668 }
3669 val64 = VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(
3670 (vpath->max_nofl_db*2)-1);
3671 }
3672
3673 writeq(val64, &vp_reg->kdfc_fifo_trpl_partition);
3674
3675 writeq(VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE,
3676 &vp_reg->kdfc_fifo_trpl_ctrl);
3677
3678 val64 = readq(&vp_reg->kdfc_trpl_fifo_0_ctrl);
3679
3680 val64 &= ~(VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(0x3) |
3681 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0xFF));
3682
3683 val64 |= VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(
3684 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY) |
3685#ifndef __BIG_ENDIAN
3686 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN |
3687#endif
3688 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0);
3689
3690 writeq(val64, &vp_reg->kdfc_trpl_fifo_0_ctrl);
3691 writeq((u64)0, &vp_reg->kdfc_trpl_fifo_0_wb_address);
3692 wmb();
3693 vpath_stride = readq(&hldev->toc_reg->toc_kdfc_vpath_stride);
3694
3695 vpath->nofl_db =
3696 (struct __vxge_hw_non_offload_db_wrapper __iomem *)
3697 (hldev->kdfc + (vp_id *
3698 VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(
3699 vpath_stride)));
3700exit:
3701 return status;
3702}
3703
3704/*
3705 * __vxge_hw_vpath_mac_configure
3706 * This routine configures the mac of virtual path using the config passed
3707 */
stephen hemminger42821a52010-10-21 07:50:53 +00003708static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003709__vxge_hw_vpath_mac_configure(struct __vxge_hw_device *hldev, u32 vp_id)
3710{
3711 u64 val64;
3712 enum vxge_hw_status status = VXGE_HW_OK;
3713 struct __vxge_hw_virtualpath *vpath;
3714 struct vxge_hw_vp_config *vp_config;
3715 struct vxge_hw_vpath_reg __iomem *vp_reg;
3716
3717 vpath = &hldev->virtual_paths[vp_id];
3718 vp_reg = vpath->vp_reg;
3719 vp_config = vpath->vp_config;
3720
3721 writeq(VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(
3722 vpath->vsport_number), &vp_reg->xmac_vsport_choice);
3723
3724 if (vp_config->ring.enable == VXGE_HW_RING_ENABLE) {
3725
3726 val64 = readq(&vp_reg->xmac_rpa_vcfg);
3727
3728 if (vp_config->rpa_strip_vlan_tag !=
3729 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) {
3730 if (vp_config->rpa_strip_vlan_tag)
3731 val64 |= VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
3732 else
3733 val64 &= ~VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
3734 }
3735
3736 writeq(val64, &vp_reg->xmac_rpa_vcfg);
3737 val64 = readq(&vp_reg->rxmac_vcfg0);
3738
3739 if (vp_config->mtu !=
3740 VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) {
3741 val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
3742 if ((vp_config->mtu +
3743 VXGE_HW_MAC_HEADER_MAX_SIZE) < vpath->max_mtu)
3744 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
3745 vp_config->mtu +
3746 VXGE_HW_MAC_HEADER_MAX_SIZE);
3747 else
3748 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
3749 vpath->max_mtu);
3750 }
3751
3752 writeq(val64, &vp_reg->rxmac_vcfg0);
3753
3754 val64 = readq(&vp_reg->rxmac_vcfg1);
3755
3756 val64 &= ~(VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(0x3) |
3757 VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE);
3758
3759 if (hldev->config.rth_it_type ==
3760 VXGE_HW_RTH_IT_TYPE_MULTI_IT) {
3761 val64 |= VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(
3762 0x2) |
3763 VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE;
3764 }
3765
3766 writeq(val64, &vp_reg->rxmac_vcfg1);
3767 }
3768 return status;
3769}
3770
3771/*
3772 * __vxge_hw_vpath_tim_configure
3773 * This routine configures the tim registers of virtual path using the config
3774 * passed
3775 */
stephen hemminger42821a52010-10-21 07:50:53 +00003776static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00003777__vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
3778{
3779 u64 val64;
3780 enum vxge_hw_status status = VXGE_HW_OK;
3781 struct __vxge_hw_virtualpath *vpath;
3782 struct vxge_hw_vpath_reg __iomem *vp_reg;
3783 struct vxge_hw_vp_config *config;
3784
3785 vpath = &hldev->virtual_paths[vp_id];
3786 vp_reg = vpath->vp_reg;
3787 config = vpath->vp_config;
3788
3789 writeq((u64)0, &vp_reg->tim_dest_addr);
3790 writeq((u64)0, &vp_reg->tim_vpath_map);
3791 writeq((u64)0, &vp_reg->tim_bitmap);
3792 writeq((u64)0, &vp_reg->tim_remap);
3793
3794 if (config->ring.enable == VXGE_HW_RING_ENABLE)
3795 writeq(VXGE_HW_TIM_RING_ASSN_INT_NUM(
3796 (vp_id * VXGE_HW_MAX_INTR_PER_VP) +
3797 VXGE_HW_VPATH_INTR_RX), &vp_reg->tim_ring_assn);
3798
3799 val64 = readq(&vp_reg->tim_pci_cfg);
3800 val64 |= VXGE_HW_TIM_PCI_CFG_ADD_PAD;
3801 writeq(val64, &vp_reg->tim_pci_cfg);
3802
3803 if (config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
3804
3805 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
3806
3807 if (config->tti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
3808 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
3809 0x3ffffff);
3810 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
3811 config->tti.btimer_val);
3812 }
3813
3814 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN;
3815
3816 if (config->tti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) {
3817 if (config->tti.timer_ac_en)
3818 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
3819 else
3820 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
3821 }
3822
3823 if (config->tti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) {
3824 if (config->tti.timer_ci_en)
3825 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
3826 else
3827 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
3828 }
3829
3830 if (config->tti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) {
3831 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f);
3832 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(
3833 config->tti.urange_a);
3834 }
3835
3836 if (config->tti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) {
3837 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f);
3838 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(
3839 config->tti.urange_b);
3840 }
3841
3842 if (config->tti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) {
3843 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f);
3844 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(
3845 config->tti.urange_c);
3846 }
3847
3848 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
3849 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
3850
3851 if (config->tti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
3852 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff);
3853 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(
3854 config->tti.uec_a);
3855 }
3856
3857 if (config->tti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) {
3858 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff);
3859 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(
3860 config->tti.uec_b);
3861 }
3862
3863 if (config->tti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) {
3864 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff);
3865 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(
3866 config->tti.uec_c);
3867 }
3868
3869 if (config->tti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) {
3870 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff);
3871 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(
3872 config->tti.uec_d);
3873 }
3874
3875 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
3876 val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
3877
3878 if (config->tti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) {
3879 if (config->tti.timer_ri_en)
3880 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
3881 else
3882 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
3883 }
3884
3885 if (config->tti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
3886 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
3887 0x3ffffff);
3888 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
3889 config->tti.rtimer_val);
3890 }
3891
3892 if (config->tti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
3893 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
3894 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(
3895 config->tti.util_sel);
3896 }
3897
3898 if (config->tti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
3899 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
3900 0x3ffffff);
3901 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
3902 config->tti.ltimer_val);
3903 }
3904
3905 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
3906 }
3907
3908 if (config->ring.enable == VXGE_HW_RING_ENABLE) {
3909
3910 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
3911
3912 if (config->rti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
3913 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
3914 0x3ffffff);
3915 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
3916 config->rti.btimer_val);
3917 }
3918
3919 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN;
3920
3921 if (config->rti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) {
3922 if (config->rti.timer_ac_en)
3923 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
3924 else
3925 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
3926 }
3927
3928 if (config->rti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) {
3929 if (config->rti.timer_ci_en)
3930 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
3931 else
3932 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
3933 }
3934
3935 if (config->rti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) {
3936 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f);
3937 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(
3938 config->rti.urange_a);
3939 }
3940
3941 if (config->rti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) {
3942 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f);
3943 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(
3944 config->rti.urange_b);
3945 }
3946
3947 if (config->rti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) {
3948 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f);
3949 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(
3950 config->rti.urange_c);
3951 }
3952
3953 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
3954 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
3955
3956 if (config->rti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
3957 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff);
3958 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(
3959 config->rti.uec_a);
3960 }
3961
3962 if (config->rti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) {
3963 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff);
3964 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(
3965 config->rti.uec_b);
3966 }
3967
3968 if (config->rti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) {
3969 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff);
3970 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(
3971 config->rti.uec_c);
3972 }
3973
3974 if (config->rti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) {
3975 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff);
3976 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(
3977 config->rti.uec_d);
3978 }
3979
3980 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
3981 val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
3982
3983 if (config->rti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) {
3984 if (config->rti.timer_ri_en)
3985 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
3986 else
3987 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
3988 }
3989
3990 if (config->rti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
3991 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
3992 0x3ffffff);
3993 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
3994 config->rti.rtimer_val);
3995 }
3996
3997 if (config->rti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
3998 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
3999 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(
4000 config->rti.util_sel);
4001 }
4002
4003 if (config->rti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4004 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4005 0x3ffffff);
4006 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4007 config->rti.ltimer_val);
4008 }
4009
4010 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
4011 }
4012
4013 val64 = 0;
4014 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4015 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4016 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4017 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4018 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4019 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4020
4021 return status;
4022}
4023
Sreenivasa Honnureb5f10c2009-10-05 01:57:29 +00004024void
4025vxge_hw_vpath_tti_ci_set(struct __vxge_hw_device *hldev, u32 vp_id)
4026{
4027 struct __vxge_hw_virtualpath *vpath;
4028 struct vxge_hw_vpath_reg __iomem *vp_reg;
4029 struct vxge_hw_vp_config *config;
4030 u64 val64;
4031
4032 vpath = &hldev->virtual_paths[vp_id];
4033 vp_reg = vpath->vp_reg;
4034 config = vpath->vp_config;
4035
4036 if (config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4037 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
4038
4039 if (config->tti.timer_ci_en != VXGE_HW_TIM_TIMER_CI_ENABLE) {
4040 config->tti.timer_ci_en = VXGE_HW_TIM_TIMER_CI_ENABLE;
4041 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4042 writeq(val64,
4043 &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
4044 }
4045 }
Sreenivasa Honnureb5f10c2009-10-05 01:57:29 +00004046}
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004047/*
4048 * __vxge_hw_vpath_initialize
4049 * This routine is the final phase of init which initializes the
4050 * registers of the vpath using the configuration passed.
4051 */
stephen hemminger42821a52010-10-21 07:50:53 +00004052static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004053__vxge_hw_vpath_initialize(struct __vxge_hw_device *hldev, u32 vp_id)
4054{
4055 u64 val64;
4056 u32 val32;
4057 enum vxge_hw_status status = VXGE_HW_OK;
4058 struct __vxge_hw_virtualpath *vpath;
4059 struct vxge_hw_vpath_reg __iomem *vp_reg;
4060
4061 vpath = &hldev->virtual_paths[vp_id];
4062
4063 if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) {
4064 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE;
4065 goto exit;
4066 }
4067 vp_reg = vpath->vp_reg;
4068
4069 status = __vxge_hw_vpath_swapper_set(vpath->vp_reg);
4070
4071 if (status != VXGE_HW_OK)
4072 goto exit;
4073
4074 status = __vxge_hw_vpath_mac_configure(hldev, vp_id);
4075
4076 if (status != VXGE_HW_OK)
4077 goto exit;
4078
4079 status = __vxge_hw_vpath_kdfc_configure(hldev, vp_id);
4080
4081 if (status != VXGE_HW_OK)
4082 goto exit;
4083
4084 status = __vxge_hw_vpath_tim_configure(hldev, vp_id);
4085
4086 if (status != VXGE_HW_OK)
4087 goto exit;
4088
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004089 val64 = readq(&vp_reg->rtdma_rd_optimization_ctrl);
4090
4091 /* Get MRRS value from device control */
4092 status = __vxge_hw_vpath_pci_read(vpath, 1, 0x78, &val32);
4093
4094 if (status == VXGE_HW_OK) {
4095 val32 = (val32 & VXGE_HW_PCI_EXP_DEVCTL_READRQ) >> 12;
4096 val64 &=
4097 ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(7));
4098 val64 |=
4099 VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val32);
4100
4101 val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE;
4102 }
4103
4104 val64 &= ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(7));
4105 val64 |=
4106 VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(
4107 VXGE_HW_MAX_PAYLOAD_SIZE_512);
4108
4109 val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN;
4110 writeq(val64, &vp_reg->rtdma_rd_optimization_ctrl);
4111
4112exit:
4113 return status;
4114}
4115
4116/*
4117 * __vxge_hw_vp_initialize - Initialize Virtual Path structure
4118 * This routine is the initial phase of init which resets the vpath and
4119 * initializes the software support structures.
4120 */
stephen hemminger42821a52010-10-21 07:50:53 +00004121static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004122__vxge_hw_vp_initialize(struct __vxge_hw_device *hldev, u32 vp_id,
4123 struct vxge_hw_vp_config *config)
4124{
4125 struct __vxge_hw_virtualpath *vpath;
4126 enum vxge_hw_status status = VXGE_HW_OK;
4127
4128 if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) {
4129 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE;
4130 goto exit;
4131 }
4132
4133 vpath = &hldev->virtual_paths[vp_id];
4134
Jon Mason8424e002010-11-11 04:25:56 +00004135 spin_lock_init(&hldev->virtual_paths[vp_id].lock);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004136 vpath->vp_id = vp_id;
4137 vpath->vp_open = VXGE_HW_VP_OPEN;
4138 vpath->hldev = hldev;
4139 vpath->vp_config = config;
4140 vpath->vp_reg = hldev->vpath_reg[vp_id];
4141 vpath->vpmgmt_reg = hldev->vpmgmt_reg[vp_id];
4142
4143 __vxge_hw_vpath_reset(hldev, vp_id);
4144
4145 status = __vxge_hw_vpath_reset_check(vpath);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004146 if (status != VXGE_HW_OK) {
4147 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4148 goto exit;
4149 }
4150
4151 status = __vxge_hw_vpath_mgmt_read(hldev, vpath);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004152 if (status != VXGE_HW_OK) {
4153 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4154 goto exit;
4155 }
4156
4157 INIT_LIST_HEAD(&vpath->vpath_handles);
4158
4159 vpath->sw_stats = &hldev->stats.sw_dev_info_stats.vpath_info[vp_id];
4160
4161 VXGE_HW_DEVICE_TIM_INT_MASK_SET(hldev->tim_int_mask0,
4162 hldev->tim_int_mask1, vp_id);
4163
4164 status = __vxge_hw_vpath_initialize(hldev, vp_id);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004165 if (status != VXGE_HW_OK)
4166 __vxge_hw_vp_terminate(hldev, vp_id);
4167exit:
4168 return status;
4169}
4170
4171/*
4172 * __vxge_hw_vp_terminate - Terminate Virtual Path structure
4173 * This routine closes all channels it opened and freeup memory
4174 */
stephen hemminger42821a52010-10-21 07:50:53 +00004175static void
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004176__vxge_hw_vp_terminate(struct __vxge_hw_device *hldev, u32 vp_id)
4177{
4178 struct __vxge_hw_virtualpath *vpath;
4179
4180 vpath = &hldev->virtual_paths[vp_id];
4181
4182 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN)
4183 goto exit;
4184
4185 VXGE_HW_DEVICE_TIM_INT_MASK_RESET(vpath->hldev->tim_int_mask0,
4186 vpath->hldev->tim_int_mask1, vpath->vp_id);
4187 hldev->stats.hw_dev_info_stats.vpath_info[vpath->vp_id] = NULL;
4188
4189 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4190exit:
4191 return;
4192}
4193
4194/*
4195 * vxge_hw_vpath_mtu_set - Set MTU.
4196 * Set new MTU value. Example, to use jumbo frames:
4197 * vxge_hw_vpath_mtu_set(my_device, 9600);
4198 */
4199enum vxge_hw_status
4200vxge_hw_vpath_mtu_set(struct __vxge_hw_vpath_handle *vp, u32 new_mtu)
4201{
4202 u64 val64;
4203 enum vxge_hw_status status = VXGE_HW_OK;
4204 struct __vxge_hw_virtualpath *vpath;
4205
4206 if (vp == NULL) {
4207 status = VXGE_HW_ERR_INVALID_HANDLE;
4208 goto exit;
4209 }
4210 vpath = vp->vpath;
4211
4212 new_mtu += VXGE_HW_MAC_HEADER_MAX_SIZE;
4213
4214 if ((new_mtu < VXGE_HW_MIN_MTU) || (new_mtu > vpath->max_mtu))
4215 status = VXGE_HW_ERR_INVALID_MTU_SIZE;
4216
4217 val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
4218
4219 val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
4220 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(new_mtu);
4221
4222 writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
4223
4224 vpath->vp_config->mtu = new_mtu - VXGE_HW_MAC_HEADER_MAX_SIZE;
4225
4226exit:
4227 return status;
4228}
4229
4230/*
4231 * vxge_hw_vpath_open - Open a virtual path on a given adapter
4232 * This function is used to open access to virtual path of an
4233 * adapter for offload, GRO operations. This function returns
4234 * synchronously.
4235 */
4236enum vxge_hw_status
4237vxge_hw_vpath_open(struct __vxge_hw_device *hldev,
4238 struct vxge_hw_vpath_attr *attr,
4239 struct __vxge_hw_vpath_handle **vpath_handle)
4240{
4241 struct __vxge_hw_virtualpath *vpath;
4242 struct __vxge_hw_vpath_handle *vp;
4243 enum vxge_hw_status status;
4244
4245 vpath = &hldev->virtual_paths[attr->vp_id];
4246
4247 if (vpath->vp_open == VXGE_HW_VP_OPEN) {
4248 status = VXGE_HW_ERR_INVALID_STATE;
4249 goto vpath_open_exit1;
4250 }
4251
4252 status = __vxge_hw_vp_initialize(hldev, attr->vp_id,
4253 &hldev->config.vp_config[attr->vp_id]);
4254
4255 if (status != VXGE_HW_OK)
4256 goto vpath_open_exit1;
4257
Joe Perchese80be0b2010-11-27 23:05:45 +00004258 vp = vzalloc(sizeof(struct __vxge_hw_vpath_handle));
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004259 if (vp == NULL) {
4260 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4261 goto vpath_open_exit2;
4262 }
4263
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004264 vp->vpath = vpath;
4265
4266 if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4267 status = __vxge_hw_fifo_create(vp, &attr->fifo_attr);
4268 if (status != VXGE_HW_OK)
4269 goto vpath_open_exit6;
4270 }
4271
4272 if (vpath->vp_config->ring.enable == VXGE_HW_RING_ENABLE) {
4273 status = __vxge_hw_ring_create(vp, &attr->ring_attr);
4274 if (status != VXGE_HW_OK)
4275 goto vpath_open_exit7;
4276
4277 __vxge_hw_vpath_prc_configure(hldev, attr->vp_id);
4278 }
4279
4280 vpath->fifoh->tx_intr_num =
4281 (attr->vp_id * VXGE_HW_MAX_INTR_PER_VP) +
4282 VXGE_HW_VPATH_INTR_TX;
4283
4284 vpath->stats_block = __vxge_hw_blockpool_block_allocate(hldev,
4285 VXGE_HW_BLOCK_SIZE);
4286
4287 if (vpath->stats_block == NULL) {
4288 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4289 goto vpath_open_exit8;
4290 }
4291
4292 vpath->hw_stats = (struct vxge_hw_vpath_stats_hw_info *)vpath->
4293 stats_block->memblock;
4294 memset(vpath->hw_stats, 0,
4295 sizeof(struct vxge_hw_vpath_stats_hw_info));
4296
4297 hldev->stats.hw_dev_info_stats.vpath_info[attr->vp_id] =
4298 vpath->hw_stats;
4299
4300 vpath->hw_stats_sav =
4301 &hldev->stats.hw_dev_info_stats.vpath_info_sav[attr->vp_id];
4302 memset(vpath->hw_stats_sav, 0,
4303 sizeof(struct vxge_hw_vpath_stats_hw_info));
4304
4305 writeq(vpath->stats_block->dma_addr, &vpath->vp_reg->stats_cfg);
4306
4307 status = vxge_hw_vpath_stats_enable(vp);
4308 if (status != VXGE_HW_OK)
4309 goto vpath_open_exit8;
4310
4311 list_add(&vp->item, &vpath->vpath_handles);
4312
4313 hldev->vpaths_deployed |= vxge_mBIT(vpath->vp_id);
4314
4315 *vpath_handle = vp;
4316
4317 attr->fifo_attr.userdata = vpath->fifoh;
4318 attr->ring_attr.userdata = vpath->ringh;
4319
4320 return VXGE_HW_OK;
4321
4322vpath_open_exit8:
4323 if (vpath->ringh != NULL)
4324 __vxge_hw_ring_delete(vp);
4325vpath_open_exit7:
4326 if (vpath->fifoh != NULL)
4327 __vxge_hw_fifo_delete(vp);
4328vpath_open_exit6:
4329 vfree(vp);
4330vpath_open_exit2:
4331 __vxge_hw_vp_terminate(hldev, attr->vp_id);
4332vpath_open_exit1:
4333
4334 return status;
4335}
4336
4337/**
4338 * vxge_hw_vpath_rx_doorbell_post - Close the handle got from previous vpath
4339 * (vpath) open
4340 * @vp: Handle got from previous vpath open
4341 *
4342 * This function is used to close access to virtual path opened
4343 * earlier.
4344 */
4345void
4346vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_vpath_handle *vp)
4347{
Jon Masone7935c92010-11-11 04:26:00 +00004348 struct __vxge_hw_virtualpath *vpath = vp->vpath;
4349 struct __vxge_hw_ring *ring = vpath->ringh;
4350 struct vxgedev *vdev = netdev_priv(vpath->hldev->ndev);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004351 u64 new_count, val64, val164;
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004352
Jon Masone7935c92010-11-11 04:26:00 +00004353 if (vdev->titan1) {
4354 new_count = readq(&vpath->vp_reg->rxdmem_size);
4355 new_count &= 0x1fff;
4356 } else
4357 new_count = ring->config->ring_blocks * VXGE_HW_BLOCK_SIZE / 8;
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004358
Jon Masone7935c92010-11-11 04:26:00 +00004359 val164 = VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE(new_count);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004360
4361 writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val164),
4362 &vpath->vp_reg->prc_rxd_doorbell);
4363 readl(&vpath->vp_reg->prc_rxd_doorbell);
4364
4365 val164 /= 2;
4366 val64 = readq(&vpath->vp_reg->prc_cfg6);
4367 val64 = VXGE_HW_PRC_CFG6_RXD_SPAT(val64);
4368 val64 &= 0x1ff;
4369
4370 /*
4371 * Each RxD is of 4 qwords
4372 */
4373 new_count -= (val64 + 1);
4374 val64 = min(val164, new_count) / 4;
4375
4376 ring->rxds_limit = min(ring->rxds_limit, val64);
4377 if (ring->rxds_limit < 4)
4378 ring->rxds_limit = 4;
4379}
4380
4381/*
4382 * vxge_hw_vpath_close - Close the handle got from previous vpath (vpath) open
4383 * This function is used to close access to virtual path opened
4384 * earlier.
4385 */
4386enum vxge_hw_status vxge_hw_vpath_close(struct __vxge_hw_vpath_handle *vp)
4387{
4388 struct __vxge_hw_virtualpath *vpath = NULL;
4389 struct __vxge_hw_device *devh = NULL;
4390 u32 vp_id = vp->vpath->vp_id;
4391 u32 is_empty = TRUE;
4392 enum vxge_hw_status status = VXGE_HW_OK;
4393
4394 vpath = vp->vpath;
4395 devh = vpath->hldev;
4396
4397 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4398 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4399 goto vpath_close_exit;
4400 }
4401
4402 list_del(&vp->item);
4403
4404 if (!list_empty(&vpath->vpath_handles)) {
4405 list_add(&vp->item, &vpath->vpath_handles);
4406 is_empty = FALSE;
4407 }
4408
4409 if (!is_empty) {
4410 status = VXGE_HW_FAIL;
4411 goto vpath_close_exit;
4412 }
4413
4414 devh->vpaths_deployed &= ~vxge_mBIT(vp_id);
4415
4416 if (vpath->ringh != NULL)
4417 __vxge_hw_ring_delete(vp);
4418
4419 if (vpath->fifoh != NULL)
4420 __vxge_hw_fifo_delete(vp);
4421
4422 if (vpath->stats_block != NULL)
4423 __vxge_hw_blockpool_block_free(devh, vpath->stats_block);
4424
4425 vfree(vp);
4426
4427 __vxge_hw_vp_terminate(devh, vp_id);
4428
Jon Mason8424e002010-11-11 04:25:56 +00004429 spin_lock(&vpath->lock);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004430 vpath->vp_open = VXGE_HW_VP_NOT_OPEN;
Jon Mason8424e002010-11-11 04:25:56 +00004431 spin_unlock(&vpath->lock);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004432
4433vpath_close_exit:
4434 return status;
4435}
4436
4437/*
4438 * vxge_hw_vpath_reset - Resets vpath
4439 * This function is used to request a reset of vpath
4440 */
4441enum vxge_hw_status vxge_hw_vpath_reset(struct __vxge_hw_vpath_handle *vp)
4442{
4443 enum vxge_hw_status status;
4444 u32 vp_id;
4445 struct __vxge_hw_virtualpath *vpath = vp->vpath;
4446
4447 vp_id = vpath->vp_id;
4448
4449 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4450 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4451 goto exit;
4452 }
4453
4454 status = __vxge_hw_vpath_reset(vpath->hldev, vp_id);
4455 if (status == VXGE_HW_OK)
4456 vpath->sw_stats->soft_reset_cnt++;
4457exit:
4458 return status;
4459}
4460
4461/*
4462 * vxge_hw_vpath_recover_from_reset - Poll for reset complete and re-initialize.
4463 * This function poll's for the vpath reset completion and re initializes
4464 * the vpath.
4465 */
4466enum vxge_hw_status
4467vxge_hw_vpath_recover_from_reset(struct __vxge_hw_vpath_handle *vp)
4468{
4469 struct __vxge_hw_virtualpath *vpath = NULL;
4470 enum vxge_hw_status status;
4471 struct __vxge_hw_device *hldev;
4472 u32 vp_id;
4473
4474 vp_id = vp->vpath->vp_id;
4475 vpath = vp->vpath;
4476 hldev = vpath->hldev;
4477
4478 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4479 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4480 goto exit;
4481 }
4482
4483 status = __vxge_hw_vpath_reset_check(vpath);
4484 if (status != VXGE_HW_OK)
4485 goto exit;
4486
4487 status = __vxge_hw_vpath_sw_reset(hldev, vp_id);
4488 if (status != VXGE_HW_OK)
4489 goto exit;
4490
4491 status = __vxge_hw_vpath_initialize(hldev, vp_id);
4492 if (status != VXGE_HW_OK)
4493 goto exit;
4494
4495 if (vpath->ringh != NULL)
4496 __vxge_hw_vpath_prc_configure(hldev, vp_id);
4497
4498 memset(vpath->hw_stats, 0,
4499 sizeof(struct vxge_hw_vpath_stats_hw_info));
4500
4501 memset(vpath->hw_stats_sav, 0,
4502 sizeof(struct vxge_hw_vpath_stats_hw_info));
4503
4504 writeq(vpath->stats_block->dma_addr,
4505 &vpath->vp_reg->stats_cfg);
4506
4507 status = vxge_hw_vpath_stats_enable(vp);
4508
4509exit:
4510 return status;
4511}
4512
4513/*
4514 * vxge_hw_vpath_enable - Enable vpath.
4515 * This routine clears the vpath reset thereby enabling a vpath
4516 * to start forwarding frames and generating interrupts.
4517 */
4518void
4519vxge_hw_vpath_enable(struct __vxge_hw_vpath_handle *vp)
4520{
4521 struct __vxge_hw_device *hldev;
4522 u64 val64;
4523
4524 hldev = vp->vpath->hldev;
4525
4526 val64 = VXGE_HW_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(
4527 1 << (16 - vp->vpath->vp_id));
4528
4529 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
4530 &hldev->common_reg->cmn_rsthdlr_cfg1);
4531}
4532
4533/*
4534 * vxge_hw_vpath_stats_enable - Enable vpath h/wstatistics.
4535 * Enable the DMA vpath statistics. The function is to be called to re-enable
4536 * the adapter to update stats into the host memory
4537 */
stephen hemminger42821a52010-10-21 07:50:53 +00004538static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004539vxge_hw_vpath_stats_enable(struct __vxge_hw_vpath_handle *vp)
4540{
4541 enum vxge_hw_status status = VXGE_HW_OK;
4542 struct __vxge_hw_virtualpath *vpath;
4543
4544 vpath = vp->vpath;
4545
4546 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4547 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4548 goto exit;
4549 }
4550
4551 memcpy(vpath->hw_stats_sav, vpath->hw_stats,
4552 sizeof(struct vxge_hw_vpath_stats_hw_info));
4553
4554 status = __vxge_hw_vpath_stats_get(vpath, vpath->hw_stats);
4555exit:
4556 return status;
4557}
4558
4559/*
4560 * __vxge_hw_vpath_stats_access - Get the statistics from the given location
4561 * and offset and perform an operation
4562 */
stephen hemminger42821a52010-10-21 07:50:53 +00004563static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004564__vxge_hw_vpath_stats_access(struct __vxge_hw_virtualpath *vpath,
4565 u32 operation, u32 offset, u64 *stat)
4566{
4567 u64 val64;
4568 enum vxge_hw_status status = VXGE_HW_OK;
4569 struct vxge_hw_vpath_reg __iomem *vp_reg;
4570
4571 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4572 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4573 goto vpath_stats_access_exit;
4574 }
4575
4576 vp_reg = vpath->vp_reg;
4577
4578 val64 = VXGE_HW_XMAC_STATS_ACCESS_CMD_OP(operation) |
4579 VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE |
4580 VXGE_HW_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(offset);
4581
4582 status = __vxge_hw_pio_mem_write64(val64,
4583 &vp_reg->xmac_stats_access_cmd,
4584 VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE,
4585 vpath->hldev->config.device_poll_millis);
4586
4587 if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ))
4588 *stat = readq(&vp_reg->xmac_stats_access_data);
4589 else
4590 *stat = 0;
4591
4592vpath_stats_access_exit:
4593 return status;
4594}
4595
4596/*
4597 * __vxge_hw_vpath_xmac_tx_stats_get - Get the TX Statistics of a vpath
4598 */
stephen hemminger42821a52010-10-21 07:50:53 +00004599static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004600__vxge_hw_vpath_xmac_tx_stats_get(
4601 struct __vxge_hw_virtualpath *vpath,
4602 struct vxge_hw_xmac_vpath_tx_stats *vpath_tx_stats)
4603{
4604 u64 *val64;
4605 int i;
4606 u32 offset = VXGE_HW_STATS_VPATH_TX_OFFSET;
4607 enum vxge_hw_status status = VXGE_HW_OK;
4608
4609 val64 = (u64 *) vpath_tx_stats;
4610
4611 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4612 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4613 goto exit;
4614 }
4615
4616 for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_tx_stats) / 8; i++) {
4617 status = __vxge_hw_vpath_stats_access(vpath,
4618 VXGE_HW_STATS_OP_READ,
4619 offset, val64);
4620 if (status != VXGE_HW_OK)
4621 goto exit;
4622 offset++;
4623 val64++;
4624 }
4625exit:
4626 return status;
4627}
4628
4629/*
4630 * __vxge_hw_vpath_xmac_rx_stats_get - Get the RX Statistics of a vpath
4631 */
stephen hemminger42821a52010-10-21 07:50:53 +00004632static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004633__vxge_hw_vpath_xmac_rx_stats_get(struct __vxge_hw_virtualpath *vpath,
stephen hemminger42821a52010-10-21 07:50:53 +00004634 struct vxge_hw_xmac_vpath_rx_stats *vpath_rx_stats)
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004635{
4636 u64 *val64;
4637 enum vxge_hw_status status = VXGE_HW_OK;
4638 int i;
4639 u32 offset = VXGE_HW_STATS_VPATH_RX_OFFSET;
4640 val64 = (u64 *) vpath_rx_stats;
4641
4642 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4643 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4644 goto exit;
4645 }
4646 for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_rx_stats) / 8; i++) {
4647 status = __vxge_hw_vpath_stats_access(vpath,
4648 VXGE_HW_STATS_OP_READ,
4649 offset >> 3, val64);
4650 if (status != VXGE_HW_OK)
4651 goto exit;
4652
4653 offset += 8;
4654 val64++;
4655 }
4656exit:
4657 return status;
4658}
4659
4660/*
4661 * __vxge_hw_vpath_stats_get - Get the vpath hw statistics.
4662 */
stephen hemminger42821a52010-10-21 07:50:53 +00004663static enum vxge_hw_status
4664__vxge_hw_vpath_stats_get(struct __vxge_hw_virtualpath *vpath,
4665 struct vxge_hw_vpath_stats_hw_info *hw_stats)
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004666{
4667 u64 val64;
4668 enum vxge_hw_status status = VXGE_HW_OK;
4669 struct vxge_hw_vpath_reg __iomem *vp_reg;
4670
4671 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4672 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4673 goto exit;
4674 }
4675 vp_reg = vpath->vp_reg;
4676
4677 val64 = readq(&vp_reg->vpath_debug_stats0);
4678 hw_stats->ini_num_mwr_sent =
4679 (u32)VXGE_HW_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(val64);
4680
4681 val64 = readq(&vp_reg->vpath_debug_stats1);
4682 hw_stats->ini_num_mrd_sent =
4683 (u32)VXGE_HW_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(val64);
4684
4685 val64 = readq(&vp_reg->vpath_debug_stats2);
4686 hw_stats->ini_num_cpl_rcvd =
4687 (u32)VXGE_HW_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(val64);
4688
4689 val64 = readq(&vp_reg->vpath_debug_stats3);
4690 hw_stats->ini_num_mwr_byte_sent =
4691 VXGE_HW_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(val64);
4692
4693 val64 = readq(&vp_reg->vpath_debug_stats4);
4694 hw_stats->ini_num_cpl_byte_rcvd =
4695 VXGE_HW_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(val64);
4696
4697 val64 = readq(&vp_reg->vpath_debug_stats5);
4698 hw_stats->wrcrdtarb_xoff =
4699 (u32)VXGE_HW_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(val64);
4700
4701 val64 = readq(&vp_reg->vpath_debug_stats6);
4702 hw_stats->rdcrdtarb_xoff =
4703 (u32)VXGE_HW_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(val64);
4704
4705 val64 = readq(&vp_reg->vpath_genstats_count01);
4706 hw_stats->vpath_genstats_count0 =
4707 (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(
4708 val64);
4709
4710 val64 = readq(&vp_reg->vpath_genstats_count01);
4711 hw_stats->vpath_genstats_count1 =
4712 (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(
4713 val64);
4714
4715 val64 = readq(&vp_reg->vpath_genstats_count23);
4716 hw_stats->vpath_genstats_count2 =
4717 (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(
4718 val64);
4719
4720 val64 = readq(&vp_reg->vpath_genstats_count01);
4721 hw_stats->vpath_genstats_count3 =
4722 (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(
4723 val64);
4724
4725 val64 = readq(&vp_reg->vpath_genstats_count4);
4726 hw_stats->vpath_genstats_count4 =
4727 (u32)VXGE_HW_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(
4728 val64);
4729
4730 val64 = readq(&vp_reg->vpath_genstats_count5);
4731 hw_stats->vpath_genstats_count5 =
4732 (u32)VXGE_HW_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(
4733 val64);
4734
4735 status = __vxge_hw_vpath_xmac_tx_stats_get(vpath, &hw_stats->tx_stats);
4736 if (status != VXGE_HW_OK)
4737 goto exit;
4738
4739 status = __vxge_hw_vpath_xmac_rx_stats_get(vpath, &hw_stats->rx_stats);
4740 if (status != VXGE_HW_OK)
4741 goto exit;
4742
4743 VXGE_HW_VPATH_STATS_PIO_READ(
4744 VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM0_OFFSET);
4745
4746 hw_stats->prog_event_vnum0 =
4747 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM0(val64);
4748
4749 hw_stats->prog_event_vnum1 =
4750 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM1(val64);
4751
4752 VXGE_HW_VPATH_STATS_PIO_READ(
4753 VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM2_OFFSET);
4754
4755 hw_stats->prog_event_vnum2 =
4756 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM2(val64);
4757
4758 hw_stats->prog_event_vnum3 =
4759 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM3(val64);
4760
4761 val64 = readq(&vp_reg->rx_multi_cast_stats);
4762 hw_stats->rx_multi_cast_frame_discard =
4763 (u16)VXGE_HW_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(val64);
4764
4765 val64 = readq(&vp_reg->rx_frm_transferred);
4766 hw_stats->rx_frm_transferred =
4767 (u32)VXGE_HW_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(val64);
4768
4769 val64 = readq(&vp_reg->rxd_returned);
4770 hw_stats->rxd_returned =
4771 (u16)VXGE_HW_RXD_RETURNED_GET_RXD_RETURNED(val64);
4772
4773 val64 = readq(&vp_reg->dbg_stats_rx_mpa);
4774 hw_stats->rx_mpa_len_fail_frms =
4775 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(val64);
4776 hw_stats->rx_mpa_mrk_fail_frms =
4777 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(val64);
4778 hw_stats->rx_mpa_crc_fail_frms =
4779 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(val64);
4780
4781 val64 = readq(&vp_reg->dbg_stats_rx_fau);
4782 hw_stats->rx_permitted_frms =
4783 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(val64);
4784 hw_stats->rx_vp_reset_discarded_frms =
4785 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val64);
4786 hw_stats->rx_wol_frms =
4787 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(val64);
4788
4789 val64 = readq(&vp_reg->tx_vp_reset_discarded_frms);
4790 hw_stats->tx_vp_reset_discarded_frms =
4791 (u16)VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(
4792 val64);
4793exit:
4794 return status;
4795}
4796
stephen hemminger42821a52010-10-21 07:50:53 +00004797
4798static void vxge_os_dma_malloc_async(struct pci_dev *pdev, void *devh,
4799 unsigned long size)
4800{
4801 gfp_t flags;
4802 void *vaddr;
4803
4804 if (in_interrupt())
4805 flags = GFP_ATOMIC | GFP_DMA;
4806 else
4807 flags = GFP_KERNEL | GFP_DMA;
4808
4809 vaddr = kmalloc((size), flags);
4810
4811 vxge_hw_blockpool_block_add(devh, vaddr, size, pdev, pdev);
4812}
4813
4814static void vxge_os_dma_free(struct pci_dev *pdev, const void *vaddr,
4815 struct pci_dev **p_dma_acch)
4816{
4817 unsigned long misaligned = *(unsigned long *)p_dma_acch;
4818 u8 *tmp = (u8 *)vaddr;
4819 tmp -= misaligned;
4820 kfree((void *)tmp);
4821}
4822
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004823/*
4824 * __vxge_hw_blockpool_create - Create block pool
4825 */
4826
Jon Mason2c913082010-11-11 04:26:03 +00004827static enum vxge_hw_status
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004828__vxge_hw_blockpool_create(struct __vxge_hw_device *hldev,
4829 struct __vxge_hw_blockpool *blockpool,
4830 u32 pool_size,
4831 u32 pool_max)
4832{
4833 u32 i;
4834 struct __vxge_hw_blockpool_entry *entry = NULL;
4835 void *memblock;
4836 dma_addr_t dma_addr;
4837 struct pci_dev *dma_handle;
4838 struct pci_dev *acc_handle;
4839 enum vxge_hw_status status = VXGE_HW_OK;
4840
4841 if (blockpool == NULL) {
4842 status = VXGE_HW_FAIL;
4843 goto blockpool_create_exit;
4844 }
4845
4846 blockpool->hldev = hldev;
4847 blockpool->block_size = VXGE_HW_BLOCK_SIZE;
4848 blockpool->pool_size = 0;
4849 blockpool->pool_max = pool_max;
4850 blockpool->req_out = 0;
4851
4852 INIT_LIST_HEAD(&blockpool->free_block_list);
4853 INIT_LIST_HEAD(&blockpool->free_entry_list);
4854
4855 for (i = 0; i < pool_size + pool_max; i++) {
4856 entry = kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
4857 GFP_KERNEL);
4858 if (entry == NULL) {
4859 __vxge_hw_blockpool_destroy(blockpool);
4860 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4861 goto blockpool_create_exit;
4862 }
4863 list_add(&entry->item, &blockpool->free_entry_list);
4864 }
4865
4866 for (i = 0; i < pool_size; i++) {
4867
4868 memblock = vxge_os_dma_malloc(
4869 hldev->pdev,
4870 VXGE_HW_BLOCK_SIZE,
4871 &dma_handle,
4872 &acc_handle);
4873
4874 if (memblock == NULL) {
4875 __vxge_hw_blockpool_destroy(blockpool);
4876 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4877 goto blockpool_create_exit;
4878 }
4879
4880 dma_addr = pci_map_single(hldev->pdev, memblock,
4881 VXGE_HW_BLOCK_SIZE, PCI_DMA_BIDIRECTIONAL);
4882
4883 if (unlikely(pci_dma_mapping_error(hldev->pdev,
4884 dma_addr))) {
4885
4886 vxge_os_dma_free(hldev->pdev, memblock, &acc_handle);
4887 __vxge_hw_blockpool_destroy(blockpool);
4888 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4889 goto blockpool_create_exit;
4890 }
4891
4892 if (!list_empty(&blockpool->free_entry_list))
4893 entry = (struct __vxge_hw_blockpool_entry *)
4894 list_first_entry(&blockpool->free_entry_list,
4895 struct __vxge_hw_blockpool_entry,
4896 item);
4897
4898 if (entry == NULL)
4899 entry =
4900 kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
4901 GFP_KERNEL);
4902 if (entry != NULL) {
4903 list_del(&entry->item);
4904 entry->length = VXGE_HW_BLOCK_SIZE;
4905 entry->memblock = memblock;
4906 entry->dma_addr = dma_addr;
4907 entry->acc_handle = acc_handle;
4908 entry->dma_handle = dma_handle;
4909 list_add(&entry->item,
4910 &blockpool->free_block_list);
4911 blockpool->pool_size++;
4912 } else {
4913 __vxge_hw_blockpool_destroy(blockpool);
4914 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4915 goto blockpool_create_exit;
4916 }
4917 }
4918
4919blockpool_create_exit:
4920 return status;
4921}
4922
4923/*
4924 * __vxge_hw_blockpool_destroy - Deallocates the block pool
4925 */
4926
Jon Mason2c913082010-11-11 04:26:03 +00004927static void __vxge_hw_blockpool_destroy(struct __vxge_hw_blockpool *blockpool)
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00004928{
4929
4930 struct __vxge_hw_device *hldev;
4931 struct list_head *p, *n;
4932 u16 ret;
4933
4934 if (blockpool == NULL) {
4935 ret = 1;
4936 goto exit;
4937 }
4938
4939 hldev = blockpool->hldev;
4940
4941 list_for_each_safe(p, n, &blockpool->free_block_list) {
4942
4943 pci_unmap_single(hldev->pdev,
4944 ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
4945 ((struct __vxge_hw_blockpool_entry *)p)->length,
4946 PCI_DMA_BIDIRECTIONAL);
4947
4948 vxge_os_dma_free(hldev->pdev,
4949 ((struct __vxge_hw_blockpool_entry *)p)->memblock,
4950 &((struct __vxge_hw_blockpool_entry *) p)->acc_handle);
4951
4952 list_del(
4953 &((struct __vxge_hw_blockpool_entry *)p)->item);
4954 kfree(p);
4955 blockpool->pool_size--;
4956 }
4957
4958 list_for_each_safe(p, n, &blockpool->free_entry_list) {
4959 list_del(
4960 &((struct __vxge_hw_blockpool_entry *)p)->item);
4961 kfree((void *)p);
4962 }
4963 ret = 0;
4964exit:
4965 return;
4966}
4967
4968/*
4969 * __vxge_hw_blockpool_blocks_add - Request additional blocks
4970 */
4971static
4972void __vxge_hw_blockpool_blocks_add(struct __vxge_hw_blockpool *blockpool)
4973{
4974 u32 nreq = 0, i;
4975
4976 if ((blockpool->pool_size + blockpool->req_out) <
4977 VXGE_HW_MIN_DMA_BLOCK_POOL_SIZE) {
4978 nreq = VXGE_HW_INCR_DMA_BLOCK_POOL_SIZE;
4979 blockpool->req_out += nreq;
4980 }
4981
4982 for (i = 0; i < nreq; i++)
4983 vxge_os_dma_malloc_async(
4984 ((struct __vxge_hw_device *)blockpool->hldev)->pdev,
4985 blockpool->hldev, VXGE_HW_BLOCK_SIZE);
4986}
4987
4988/*
4989 * __vxge_hw_blockpool_blocks_remove - Free additional blocks
4990 */
4991static
4992void __vxge_hw_blockpool_blocks_remove(struct __vxge_hw_blockpool *blockpool)
4993{
4994 struct list_head *p, *n;
4995
4996 list_for_each_safe(p, n, &blockpool->free_block_list) {
4997
4998 if (blockpool->pool_size < blockpool->pool_max)
4999 break;
5000
5001 pci_unmap_single(
5002 ((struct __vxge_hw_device *)blockpool->hldev)->pdev,
5003 ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
5004 ((struct __vxge_hw_blockpool_entry *)p)->length,
5005 PCI_DMA_BIDIRECTIONAL);
5006
5007 vxge_os_dma_free(
5008 ((struct __vxge_hw_device *)blockpool->hldev)->pdev,
5009 ((struct __vxge_hw_blockpool_entry *)p)->memblock,
5010 &((struct __vxge_hw_blockpool_entry *)p)->acc_handle);
5011
5012 list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
5013
5014 list_add(p, &blockpool->free_entry_list);
5015
5016 blockpool->pool_size--;
5017
5018 }
5019}
5020
5021/*
5022 * vxge_hw_blockpool_block_add - callback for vxge_os_dma_malloc_async
5023 * Adds a block to block pool
5024 */
stephen hemminger42821a52010-10-21 07:50:53 +00005025static void vxge_hw_blockpool_block_add(struct __vxge_hw_device *devh,
5026 void *block_addr,
5027 u32 length,
5028 struct pci_dev *dma_h,
5029 struct pci_dev *acc_handle)
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00005030{
5031 struct __vxge_hw_blockpool *blockpool;
5032 struct __vxge_hw_blockpool_entry *entry = NULL;
5033 dma_addr_t dma_addr;
5034 enum vxge_hw_status status = VXGE_HW_OK;
5035 u32 req_out;
5036
5037 blockpool = &devh->block_pool;
5038
5039 if (block_addr == NULL) {
5040 blockpool->req_out--;
5041 status = VXGE_HW_FAIL;
5042 goto exit;
5043 }
5044
5045 dma_addr = pci_map_single(devh->pdev, block_addr, length,
5046 PCI_DMA_BIDIRECTIONAL);
5047
5048 if (unlikely(pci_dma_mapping_error(devh->pdev, dma_addr))) {
5049
5050 vxge_os_dma_free(devh->pdev, block_addr, &acc_handle);
5051 blockpool->req_out--;
5052 status = VXGE_HW_FAIL;
5053 goto exit;
5054 }
5055
5056
5057 if (!list_empty(&blockpool->free_entry_list))
5058 entry = (struct __vxge_hw_blockpool_entry *)
5059 list_first_entry(&blockpool->free_entry_list,
5060 struct __vxge_hw_blockpool_entry,
5061 item);
5062
5063 if (entry == NULL)
Joe Perchese80be0b2010-11-27 23:05:45 +00005064 entry = vmalloc(sizeof(struct __vxge_hw_blockpool_entry));
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00005065 else
5066 list_del(&entry->item);
5067
5068 if (entry != NULL) {
5069 entry->length = length;
5070 entry->memblock = block_addr;
5071 entry->dma_addr = dma_addr;
5072 entry->acc_handle = acc_handle;
5073 entry->dma_handle = dma_h;
5074 list_add(&entry->item, &blockpool->free_block_list);
5075 blockpool->pool_size++;
5076 status = VXGE_HW_OK;
5077 } else
5078 status = VXGE_HW_ERR_OUT_OF_MEMORY;
5079
5080 blockpool->req_out--;
5081
5082 req_out = blockpool->req_out;
5083exit:
5084 return;
5085}
5086
5087/*
5088 * __vxge_hw_blockpool_malloc - Allocate a memory block from pool
5089 * Allocates a block of memory of given size, either from block pool
5090 * or by calling vxge_os_dma_malloc()
5091 */
Jon Mason2c913082010-11-11 04:26:03 +00005092static void *
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00005093__vxge_hw_blockpool_malloc(struct __vxge_hw_device *devh, u32 size,
5094 struct vxge_hw_mempool_dma *dma_object)
5095{
5096 struct __vxge_hw_blockpool_entry *entry = NULL;
5097 struct __vxge_hw_blockpool *blockpool;
5098 void *memblock = NULL;
5099 enum vxge_hw_status status = VXGE_HW_OK;
5100
5101 blockpool = &devh->block_pool;
5102
5103 if (size != blockpool->block_size) {
5104
5105 memblock = vxge_os_dma_malloc(devh->pdev, size,
5106 &dma_object->handle,
5107 &dma_object->acc_handle);
5108
5109 if (memblock == NULL) {
5110 status = VXGE_HW_ERR_OUT_OF_MEMORY;
5111 goto exit;
5112 }
5113
5114 dma_object->addr = pci_map_single(devh->pdev, memblock, size,
5115 PCI_DMA_BIDIRECTIONAL);
5116
5117 if (unlikely(pci_dma_mapping_error(devh->pdev,
5118 dma_object->addr))) {
5119 vxge_os_dma_free(devh->pdev, memblock,
5120 &dma_object->acc_handle);
5121 status = VXGE_HW_ERR_OUT_OF_MEMORY;
5122 goto exit;
5123 }
5124
5125 } else {
5126
5127 if (!list_empty(&blockpool->free_block_list))
5128 entry = (struct __vxge_hw_blockpool_entry *)
5129 list_first_entry(&blockpool->free_block_list,
5130 struct __vxge_hw_blockpool_entry,
5131 item);
5132
5133 if (entry != NULL) {
5134 list_del(&entry->item);
5135 dma_object->addr = entry->dma_addr;
5136 dma_object->handle = entry->dma_handle;
5137 dma_object->acc_handle = entry->acc_handle;
5138 memblock = entry->memblock;
5139
5140 list_add(&entry->item,
5141 &blockpool->free_entry_list);
5142 blockpool->pool_size--;
5143 }
5144
5145 if (memblock != NULL)
5146 __vxge_hw_blockpool_blocks_add(blockpool);
5147 }
5148exit:
5149 return memblock;
5150}
5151
5152/*
5153 * __vxge_hw_blockpool_free - Frees the memory allcoated with
5154 __vxge_hw_blockpool_malloc
5155 */
Jon Mason2c913082010-11-11 04:26:03 +00005156static void
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00005157__vxge_hw_blockpool_free(struct __vxge_hw_device *devh,
5158 void *memblock, u32 size,
5159 struct vxge_hw_mempool_dma *dma_object)
5160{
5161 struct __vxge_hw_blockpool_entry *entry = NULL;
5162 struct __vxge_hw_blockpool *blockpool;
5163 enum vxge_hw_status status = VXGE_HW_OK;
5164
5165 blockpool = &devh->block_pool;
5166
5167 if (size != blockpool->block_size) {
5168 pci_unmap_single(devh->pdev, dma_object->addr, size,
5169 PCI_DMA_BIDIRECTIONAL);
5170 vxge_os_dma_free(devh->pdev, memblock, &dma_object->acc_handle);
5171 } else {
5172
5173 if (!list_empty(&blockpool->free_entry_list))
5174 entry = (struct __vxge_hw_blockpool_entry *)
5175 list_first_entry(&blockpool->free_entry_list,
5176 struct __vxge_hw_blockpool_entry,
5177 item);
5178
5179 if (entry == NULL)
Joe Perchese80be0b2010-11-27 23:05:45 +00005180 entry = vmalloc(sizeof(
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00005181 struct __vxge_hw_blockpool_entry));
5182 else
5183 list_del(&entry->item);
5184
5185 if (entry != NULL) {
5186 entry->length = size;
5187 entry->memblock = memblock;
5188 entry->dma_addr = dma_object->addr;
5189 entry->acc_handle = dma_object->acc_handle;
5190 entry->dma_handle = dma_object->handle;
5191 list_add(&entry->item,
5192 &blockpool->free_block_list);
5193 blockpool->pool_size++;
5194 status = VXGE_HW_OK;
5195 } else
5196 status = VXGE_HW_ERR_OUT_OF_MEMORY;
5197
5198 if (status == VXGE_HW_OK)
5199 __vxge_hw_blockpool_blocks_remove(blockpool);
5200 }
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00005201}
5202
5203/*
5204 * __vxge_hw_blockpool_block_allocate - Allocates a block from block pool
5205 * This function allocates a block from block pool or from the system
5206 */
Jon Mason2c913082010-11-11 04:26:03 +00005207static struct __vxge_hw_blockpool_entry *
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00005208__vxge_hw_blockpool_block_allocate(struct __vxge_hw_device *devh, u32 size)
5209{
5210 struct __vxge_hw_blockpool_entry *entry = NULL;
5211 struct __vxge_hw_blockpool *blockpool;
5212
5213 blockpool = &devh->block_pool;
5214
5215 if (size == blockpool->block_size) {
5216
5217 if (!list_empty(&blockpool->free_block_list))
5218 entry = (struct __vxge_hw_blockpool_entry *)
5219 list_first_entry(&blockpool->free_block_list,
5220 struct __vxge_hw_blockpool_entry,
5221 item);
5222
5223 if (entry != NULL) {
5224 list_del(&entry->item);
5225 blockpool->pool_size--;
5226 }
5227 }
5228
5229 if (entry != NULL)
5230 __vxge_hw_blockpool_blocks_add(blockpool);
5231
5232 return entry;
5233}
5234
5235/*
5236 * __vxge_hw_blockpool_block_free - Frees a block from block pool
5237 * @devh: Hal device
5238 * @entry: Entry of block to be freed
5239 *
5240 * This function frees a block from block pool
5241 */
Jon Mason2c913082010-11-11 04:26:03 +00005242static void
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00005243__vxge_hw_blockpool_block_free(struct __vxge_hw_device *devh,
5244 struct __vxge_hw_blockpool_entry *entry)
5245{
5246 struct __vxge_hw_blockpool *blockpool;
5247
5248 blockpool = &devh->block_pool;
5249
5250 if (entry->length == blockpool->block_size) {
5251 list_add(&entry->item, &blockpool->free_block_list);
5252 blockpool->pool_size++;
5253 }
5254
5255 __vxge_hw_blockpool_blocks_remove(blockpool);
Ramkrishna Vepa40a3a912009-04-01 18:14:40 +00005256}