Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm / ebee2a77ad0d25e4ccb1905d7cfe5733ce9f88ef / . / sound / soc / codecs / wcd9320.c
blob: 6f601c1d2c20df638487d8c4d8cb87a49d96d817 [file] [log] [blame]
Ravishankar Sarawadi839fcf32012-11-14 12:13:00 -0800[diff] [blame]1/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/firmware.h>
15#include <linux/slab.h>
16#include <linux/platform_device.h>
17#include <linux/device.h>
18#include <linux/printk.h>
19#include <linux/ratelimit.h>
20#include <linux/debugfs.h>
Joonwoo Park9bbb4d12012-11-09 19:58:11 -0800[diff] [blame]21#include <linux/wait.h>
22#include <linux/bitops.h>
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]23#include <linux/mfd/wcd9xxx/core.h>
24#include <linux/mfd/wcd9xxx/wcd9xxx_registers.h>
25#include <linux/mfd/wcd9xxx/wcd9320_registers.h>
26#include <linux/mfd/wcd9xxx/pdata.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/tlv.h>
32#include <linux/bitops.h>
33#include <linux/delay.h>
34#include <linux/pm_runtime.h>
35#include <linux/kernel.h>
36#include <linux/gpio.h>
37#include "wcd9320.h"
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]38#include "wcd9xxx-resmgr.h"
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]39#include "wcd9xxx-common.h"
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]40
Joonwoo Park125cd4e2012-12-11 15:16:11 -0800[diff] [blame]41static atomic_t kp_taiko_priv;
42static int spkr_drv_wrnd_param_set(const char *val,
43 const struct kernel_param *kp);
44static int spkr_drv_wrnd = 1;
45
46static struct kernel_param_ops spkr_drv_wrnd_param_ops = {
47 .set = spkr_drv_wrnd_param_set,
48 .get = param_get_int,
49};
50module_param_cb(spkr_drv_wrnd, &spkr_drv_wrnd_param_ops, &spkr_drv_wrnd, 0644);
51MODULE_PARM_DESC(spkr_drv_wrnd,
52 "Run software workaround to avoid leakage on the speaker drive");
53
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]54#define WCD9320_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
55 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
56 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
57
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]58#define NUM_DECIMATORS 10
59#define NUM_INTERPOLATORS 7
60#define BITS_PER_REG 8
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]61#define TAIKO_TX_PORT_NUMBER 16
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]62
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]63#define TAIKO_I2S_MASTER_MODE_MASK 0x08
Venkat Sudhira41630a2012-10-27 00:57:31 -0700[diff] [blame]64#define TAIKO_MCLK_CLK_12P288MHZ 12288000
65#define TAIKO_MCLK_CLK_9P6HZ 9600000
Joonwoo Park9bbb4d12012-11-09 19:58:11 -0800[diff] [blame]66
67#define TAIKO_SLIM_CLOSE_TIMEOUT 1000
68#define TAIKO_SLIM_IRQ_OVERFLOW (1 << 0)
69#define TAIKO_SLIM_IRQ_UNDERFLOW (1 << 1)
70#define TAIKO_SLIM_IRQ_PORT_CLOSED (1 << 2)
Venkat Sudhira50a3762012-11-26 12:12:15 -0800[diff] [blame]71#define TAIKO_MCLK_CLK_12P288MHZ 12288000
72#define TAIKO_MCLK_CLK_9P6HZ 9600000
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]73
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]74enum {
75 AIF1_PB = 0,
76 AIF1_CAP,
77 AIF2_PB,
78 AIF2_CAP,
79 AIF3_PB,
80 AIF3_CAP,
81 NUM_CODEC_DAIS,
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]82};
83
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]84enum {
85 RX_MIX1_INP_SEL_ZERO = 0,
86 RX_MIX1_INP_SEL_SRC1,
87 RX_MIX1_INP_SEL_SRC2,
88 RX_MIX1_INP_SEL_IIR1,
89 RX_MIX1_INP_SEL_IIR2,
90 RX_MIX1_INP_SEL_RX1,
91 RX_MIX1_INP_SEL_RX2,
92 RX_MIX1_INP_SEL_RX3,
93 RX_MIX1_INP_SEL_RX4,
94 RX_MIX1_INP_SEL_RX5,
95 RX_MIX1_INP_SEL_RX6,
96 RX_MIX1_INP_SEL_RX7,
97 RX_MIX1_INP_SEL_AUXRX,
98};
99
100#define TAIKO_COMP_DIGITAL_GAIN_OFFSET 3
101
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]102static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0);
103static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
104static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
105static struct snd_soc_dai_driver taiko_dai[];
106static const DECLARE_TLV_DB_SCALE(aux_pga_gain, 0, 2, 0);
107
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]108/* Codec supports 2 IIR filters */
109enum {
110 IIR1 = 0,
111 IIR2,
112 IIR_MAX,
113};
114/* Codec supports 5 bands */
115enum {
116 BAND1 = 0,
117 BAND2,
118 BAND3,
119 BAND4,
120 BAND5,
121 BAND_MAX,
122};
123
124enum {
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]125 COMPANDER_0,
126 COMPANDER_1,
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]127 COMPANDER_2,
128 COMPANDER_MAX,
129};
130
131enum {
132 COMPANDER_FS_8KHZ = 0,
133 COMPANDER_FS_16KHZ,
134 COMPANDER_FS_32KHZ,
135 COMPANDER_FS_48KHZ,
136 COMPANDER_FS_96KHZ,
137 COMPANDER_FS_192KHZ,
138 COMPANDER_FS_MAX,
139};
140
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]141struct comp_sample_dependent_params {
142 u32 peak_det_timeout;
143 u32 rms_meter_div_fact;
144 u32 rms_meter_resamp_fact;
145};
146
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]147struct hpf_work {
148 struct taiko_priv *taiko;
149 u32 decimator;
150 u8 tx_hpf_cut_of_freq;
151 struct delayed_work dwork;
152};
153
154static struct hpf_work tx_hpf_work[NUM_DECIMATORS];
155
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]156static const struct wcd9xxx_ch taiko_rx_chs[TAIKO_RX_MAX] = {
157 WCD9XXX_CH(16, 0),
158 WCD9XXX_CH(17, 1),
159 WCD9XXX_CH(18, 2),
160 WCD9XXX_CH(19, 3),
161 WCD9XXX_CH(20, 4),
162 WCD9XXX_CH(21, 5),
163 WCD9XXX_CH(22, 6),
164 WCD9XXX_CH(23, 7),
165 WCD9XXX_CH(24, 8),
166 WCD9XXX_CH(25, 9),
167 WCD9XXX_CH(26, 10),
168 WCD9XXX_CH(27, 11),
169 WCD9XXX_CH(28, 12),
170};
171
172static const struct wcd9xxx_ch taiko_tx_chs[TAIKO_TX_MAX] = {
173 WCD9XXX_CH(0, 0),
174 WCD9XXX_CH(1, 1),
175 WCD9XXX_CH(2, 2),
176 WCD9XXX_CH(3, 3),
177 WCD9XXX_CH(4, 4),
178 WCD9XXX_CH(5, 5),
179 WCD9XXX_CH(6, 6),
180 WCD9XXX_CH(7, 7),
181 WCD9XXX_CH(8, 8),
182 WCD9XXX_CH(9, 9),
183 WCD9XXX_CH(10, 10),
184 WCD9XXX_CH(11, 11),
185 WCD9XXX_CH(12, 12),
186 WCD9XXX_CH(13, 13),
187 WCD9XXX_CH(14, 14),
188 WCD9XXX_CH(15, 15),
189};
190
191static const u32 vport_check_table[NUM_CODEC_DAIS] = {
192 0, /* AIF1_PB */
193 (1 << AIF2_CAP) | (1 << AIF3_CAP), /* AIF1_CAP */
194 0, /* AIF2_PB */
195 (1 << AIF1_CAP) | (1 << AIF3_CAP), /* AIF2_CAP */
196 0, /* AIF2_PB */
197 (1 << AIF1_CAP) | (1 << AIF2_CAP), /* AIF2_CAP */
198};
199
Venkat Sudhir96dd28c2012-12-04 17:00:19 -0800[diff] [blame]200static const u32 vport_i2s_check_table[NUM_CODEC_DAIS] = {
201 0, /* AIF1_PB */
202 0, /* AIF1_CAP */
Venkat Sudhir994193b2012-12-17 17:30:51 -0800[diff] [blame]203 0, /* AIF2_PB */
204 0, /* AIF2_CAP */
Venkat Sudhir96dd28c2012-12-04 17:00:19 -0800[diff] [blame]205};
206
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]207struct taiko_priv {
208 struct snd_soc_codec *codec;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]209 u32 adc_count;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]210 u32 rx_bias_count;
211 s32 dmic_1_2_clk_cnt;
212 s32 dmic_3_4_clk_cnt;
213 s32 dmic_5_6_clk_cnt;
214
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]215 u32 anc_slot;
216
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]217 /*track taiko interface type*/
218 u8 intf_type;
219
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]220 /* num of slim ports required */
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]221 struct wcd9xxx_codec_dai_data dai[NUM_CODEC_DAIS];
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]222
223 /*compander*/
224 int comp_enabled[COMPANDER_MAX];
225 u32 comp_fs[COMPANDER_MAX];
226
227 /* Maintain the status of AUX PGA */
228 int aux_pga_cnt;
229 u8 aux_l_gain;
230 u8 aux_r_gain;
231
Joonwoo Park125cd4e2012-12-11 15:16:11 -0800[diff] [blame]232 bool spkr_pa_widget_on;
233
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]234 /* resmgr module */
235 struct wcd9xxx_resmgr resmgr;
236 /* mbhc module */
237 struct wcd9xxx_mbhc mbhc;
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]238
239 /* class h specific data */
240 struct wcd9xxx_clsh_cdc_data clsh_d;
241
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]242};
243
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]244static const u32 comp_shift[] = {
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]245 4, /* Compander 0's clock source is on interpolator 7 */
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]246 0,
247 2,
248};
249
250static const int comp_rx_path[] = {
251 COMPANDER_1,
252 COMPANDER_1,
253 COMPANDER_2,
254 COMPANDER_2,
255 COMPANDER_2,
256 COMPANDER_2,
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]257 COMPANDER_0,
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]258 COMPANDER_MAX,
259};
260
261static const struct comp_sample_dependent_params comp_samp_params[] = {
262 {
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]263 /* 8 Khz */
264 .peak_det_timeout = 0x02,
265 .rms_meter_div_fact = 0x09,
266 .rms_meter_resamp_fact = 0x06,
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]267 },
268 {
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]269 /* 16 Khz */
270 .peak_det_timeout = 0x03,
271 .rms_meter_div_fact = 0x0A,
272 .rms_meter_resamp_fact = 0x0C,
273 },
274 {
275 /* 32 Khz */
276 .peak_det_timeout = 0x05,
277 .rms_meter_div_fact = 0x0B,
278 .rms_meter_resamp_fact = 0x1E,
279 },
280 {
281 /* 48 Khz */
282 .peak_det_timeout = 0x05,
283 .rms_meter_div_fact = 0x0B,
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]284 .rms_meter_resamp_fact = 0x28,
285 },
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]286 {
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]287 /* 96 Khz */
288 .peak_det_timeout = 0x06,
289 .rms_meter_div_fact = 0x0C,
290 .rms_meter_resamp_fact = 0x50,
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]291 },
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]292 {
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]293 /* 192 Khz */
294 .peak_det_timeout = 0x07,
295 .rms_meter_div_fact = 0xD,
296 .rms_meter_resamp_fact = 0xA0,
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]297 },
298};
299
300static unsigned short rx_digital_gain_reg[] = {
301 TAIKO_A_CDC_RX1_VOL_CTL_B2_CTL,
302 TAIKO_A_CDC_RX2_VOL_CTL_B2_CTL,
303 TAIKO_A_CDC_RX3_VOL_CTL_B2_CTL,
304 TAIKO_A_CDC_RX4_VOL_CTL_B2_CTL,
305 TAIKO_A_CDC_RX5_VOL_CTL_B2_CTL,
306 TAIKO_A_CDC_RX6_VOL_CTL_B2_CTL,
307 TAIKO_A_CDC_RX7_VOL_CTL_B2_CTL,
308};
309
310
311static unsigned short tx_digital_gain_reg[] = {
312 TAIKO_A_CDC_TX1_VOL_CTL_GAIN,
313 TAIKO_A_CDC_TX2_VOL_CTL_GAIN,
314 TAIKO_A_CDC_TX3_VOL_CTL_GAIN,
315 TAIKO_A_CDC_TX4_VOL_CTL_GAIN,
316 TAIKO_A_CDC_TX5_VOL_CTL_GAIN,
317 TAIKO_A_CDC_TX6_VOL_CTL_GAIN,
318 TAIKO_A_CDC_TX7_VOL_CTL_GAIN,
319 TAIKO_A_CDC_TX8_VOL_CTL_GAIN,
320 TAIKO_A_CDC_TX9_VOL_CTL_GAIN,
321 TAIKO_A_CDC_TX10_VOL_CTL_GAIN,
322};
323
Joonwoo Park125cd4e2012-12-11 15:16:11 -0800[diff] [blame]324static int spkr_drv_wrnd_param_set(const char *val,
325 const struct kernel_param *kp)
326{
327 struct snd_soc_codec *codec;
328 int ret, old;
329 struct taiko_priv *priv;
330
331 priv = (struct taiko_priv *)atomic_read(&kp_taiko_priv);
332 if (!priv) {
333 pr_debug("%s: codec isn't yet registered\n", __func__);
334 return 0;
335 }
336
337 WCD9XXX_BCL_LOCK(&priv->resmgr);
338 old = spkr_drv_wrnd;
339 ret = param_set_int(val, kp);
340 if (ret) {
341 WCD9XXX_BCL_UNLOCK(&priv->resmgr);
342 return ret;
343 }
344
345 pr_debug("%s: spkr_drv_wrnd %d -> %d\n", __func__, old, spkr_drv_wrnd);
346 codec = priv->codec;
347 if (old == 0 && spkr_drv_wrnd == 1) {
348 wcd9xxx_resmgr_get_bandgap(&priv->resmgr,
349 WCD9XXX_BANDGAP_AUDIO_MODE);
350 snd_soc_update_bits(codec, TAIKO_A_SPKR_DRV_EN, 0x80, 0x80);
351 } else if (old == 1 && spkr_drv_wrnd == 0) {
352 wcd9xxx_resmgr_put_bandgap(&priv->resmgr,
353 WCD9XXX_BANDGAP_AUDIO_MODE);
354 if (!priv->spkr_pa_widget_on)
355 snd_soc_update_bits(codec, TAIKO_A_SPKR_DRV_EN, 0x80,
356 0x00);
357 }
358
359 WCD9XXX_BCL_UNLOCK(&priv->resmgr);
360 return 0;
361}
362
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]363static int taiko_get_anc_slot(struct snd_kcontrol *kcontrol,
364 struct snd_ctl_elem_value *ucontrol)
365{
366 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
367 struct taiko_priv *taiko = snd_soc_codec_get_drvdata(codec);
368 ucontrol->value.integer.value[0] = taiko->anc_slot;
369 return 0;
370}
371
372static int taiko_put_anc_slot(struct snd_kcontrol *kcontrol,
373 struct snd_ctl_elem_value *ucontrol)
374{
375 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
376 struct taiko_priv *taiko = snd_soc_codec_get_drvdata(codec);
377 taiko->anc_slot = ucontrol->value.integer.value[0];
378 return 0;
379}
380
381static int taiko_pa_gain_get(struct snd_kcontrol *kcontrol,
382 struct snd_ctl_elem_value *ucontrol)
383{
384 u8 ear_pa_gain;
385 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
386
387 ear_pa_gain = snd_soc_read(codec, TAIKO_A_RX_EAR_GAIN);
388
389 ear_pa_gain = ear_pa_gain >> 5;
390
391 if (ear_pa_gain == 0x00) {
392 ucontrol->value.integer.value[0] = 0;
393 } else if (ear_pa_gain == 0x04) {
394 ucontrol->value.integer.value[0] = 1;
395 } else {
396 pr_err("%s: ERROR: Unsupported Ear Gain = 0x%x\n",
397 __func__, ear_pa_gain);
398 return -EINVAL;
399 }
400
401 pr_debug("%s: ear_pa_gain = 0x%x\n", __func__, ear_pa_gain);
402
403 return 0;
404}
405
406static int taiko_pa_gain_put(struct snd_kcontrol *kcontrol,
407 struct snd_ctl_elem_value *ucontrol)
408{
409 u8 ear_pa_gain;
410 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
411
412 pr_debug("%s: ucontrol->value.integer.value[0] = %ld\n", __func__,
413 ucontrol->value.integer.value[0]);
414
415 switch (ucontrol->value.integer.value[0]) {
416 case 0:
417 ear_pa_gain = 0x00;
418 break;
419 case 1:
420 ear_pa_gain = 0x80;
421 break;
422 default:
423 return -EINVAL;
424 }
425
426 snd_soc_update_bits(codec, TAIKO_A_RX_EAR_GAIN, 0xE0, ear_pa_gain);
427 return 0;
428}
429
430static int taiko_get_iir_enable_audio_mixer(
431 struct snd_kcontrol *kcontrol,
432 struct snd_ctl_elem_value *ucontrol)
433{
434 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
435 int iir_idx = ((struct soc_multi_mixer_control *)
436 kcontrol->private_value)->reg;
437 int band_idx = ((struct soc_multi_mixer_control *)
438 kcontrol->private_value)->shift;
439
440 ucontrol->value.integer.value[0] =
Ben Romberger205e14d2013-02-06 12:31:53 -0800[diff] [blame]441 (snd_soc_read(codec, (TAIKO_A_CDC_IIR1_CTL + 16 * iir_idx)) &
442 (1 << band_idx)) != 0;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]443
444 pr_debug("%s: IIR #%d band #%d enable %d\n", __func__,
445 iir_idx, band_idx,
446 (uint32_t)ucontrol->value.integer.value[0]);
447 return 0;
448}
449
450static int taiko_put_iir_enable_audio_mixer(
451 struct snd_kcontrol *kcontrol,
452 struct snd_ctl_elem_value *ucontrol)
453{
454 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
455 int iir_idx = ((struct soc_multi_mixer_control *)
456 kcontrol->private_value)->reg;
457 int band_idx = ((struct soc_multi_mixer_control *)
458 kcontrol->private_value)->shift;
459 int value = ucontrol->value.integer.value[0];
460
461 /* Mask first 5 bits, 6-8 are reserved */
462 snd_soc_update_bits(codec, (TAIKO_A_CDC_IIR1_CTL + 16 * iir_idx),
463 (1 << band_idx), (value << band_idx));
464
465 pr_debug("%s: IIR #%d band #%d enable %d\n", __func__,
Ben Romberger205e14d2013-02-06 12:31:53 -0800[diff] [blame]466 iir_idx, band_idx,
467 ((snd_soc_read(codec, (TAIKO_A_CDC_IIR1_CTL + 16 * iir_idx)) &
468 (1 << band_idx)) != 0));
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]469 return 0;
470}
471static uint32_t get_iir_band_coeff(struct snd_soc_codec *codec,
472 int iir_idx, int band_idx,
473 int coeff_idx)
474{
Ben Romberger205e14d2013-02-06 12:31:53 -0800[diff] [blame]475 uint32_t value = 0;
476
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]477 /* Address does not automatically update if reading */
478 snd_soc_write(codec,
479 (TAIKO_A_CDC_IIR1_COEF_B1_CTL + 16 * iir_idx),
Ben Romberger205e14d2013-02-06 12:31:53 -0800[diff] [blame]480 ((band_idx * BAND_MAX + coeff_idx)
481 * sizeof(uint32_t)) & 0x7F);
482
483 value |= snd_soc_read(codec,
484 (TAIKO_A_CDC_IIR1_COEF_B2_CTL + 16 * iir_idx));
485
486 snd_soc_write(codec,
487 (TAIKO_A_CDC_IIR1_COEF_B1_CTL + 16 * iir_idx),
488 ((band_idx * BAND_MAX + coeff_idx)
489 * sizeof(uint32_t) + 1) & 0x7F);
490
491 value |= (snd_soc_read(codec,
492 (TAIKO_A_CDC_IIR1_COEF_B2_CTL + 16 * iir_idx)) << 8);
493
494 snd_soc_write(codec,
495 (TAIKO_A_CDC_IIR1_COEF_B1_CTL + 16 * iir_idx),
496 ((band_idx * BAND_MAX + coeff_idx)
497 * sizeof(uint32_t) + 2) & 0x7F);
498
499 value |= (snd_soc_read(codec,
500 (TAIKO_A_CDC_IIR1_COEF_B2_CTL + 16 * iir_idx)) << 16);
501
502 snd_soc_write(codec,
503 (TAIKO_A_CDC_IIR1_COEF_B1_CTL + 16 * iir_idx),
504 ((band_idx * BAND_MAX + coeff_idx)
505 * sizeof(uint32_t) + 3) & 0x7F);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]506
507 /* Mask bits top 2 bits since they are reserved */
Ben Romberger205e14d2013-02-06 12:31:53 -0800[diff] [blame]508 value |= ((snd_soc_read(codec,
509 (TAIKO_A_CDC_IIR1_COEF_B2_CTL + 16 * iir_idx)) & 0x3F) << 24);
510
511 return value;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]512}
513
514static int taiko_get_iir_band_audio_mixer(
515 struct snd_kcontrol *kcontrol,
516 struct snd_ctl_elem_value *ucontrol)
517{
518 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
519 int iir_idx = ((struct soc_multi_mixer_control *)
520 kcontrol->private_value)->reg;
521 int band_idx = ((struct soc_multi_mixer_control *)
522 kcontrol->private_value)->shift;
523
524 ucontrol->value.integer.value[0] =
525 get_iir_band_coeff(codec, iir_idx, band_idx, 0);
526 ucontrol->value.integer.value[1] =
527 get_iir_band_coeff(codec, iir_idx, band_idx, 1);
528 ucontrol->value.integer.value[2] =
529 get_iir_band_coeff(codec, iir_idx, band_idx, 2);
530 ucontrol->value.integer.value[3] =
531 get_iir_band_coeff(codec, iir_idx, band_idx, 3);
532 ucontrol->value.integer.value[4] =
533 get_iir_band_coeff(codec, iir_idx, band_idx, 4);
534
535 pr_debug("%s: IIR #%d band #%d b0 = 0x%x\n"
536 "%s: IIR #%d band #%d b1 = 0x%x\n"
537 "%s: IIR #%d band #%d b2 = 0x%x\n"
538 "%s: IIR #%d band #%d a1 = 0x%x\n"
539 "%s: IIR #%d band #%d a2 = 0x%x\n",
540 __func__, iir_idx, band_idx,
541 (uint32_t)ucontrol->value.integer.value[0],
542 __func__, iir_idx, band_idx,
543 (uint32_t)ucontrol->value.integer.value[1],
544 __func__, iir_idx, band_idx,
545 (uint32_t)ucontrol->value.integer.value[2],
546 __func__, iir_idx, band_idx,
547 (uint32_t)ucontrol->value.integer.value[3],
548 __func__, iir_idx, band_idx,
549 (uint32_t)ucontrol->value.integer.value[4]);
550 return 0;
551}
552
553static void set_iir_band_coeff(struct snd_soc_codec *codec,
554 int iir_idx, int band_idx,
Ben Romberger205e14d2013-02-06 12:31:53 -0800[diff] [blame]555 uint32_t value)
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]556{
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]557 snd_soc_write(codec,
Ben Romberger205e14d2013-02-06 12:31:53 -0800[diff] [blame]558 (TAIKO_A_CDC_IIR1_COEF_B2_CTL + 16 * iir_idx),
559 (value & 0xFF));
560
561 snd_soc_write(codec,
562 (TAIKO_A_CDC_IIR1_COEF_B2_CTL + 16 * iir_idx),
563 (value >> 8) & 0xFF);
564
565 snd_soc_write(codec,
566 (TAIKO_A_CDC_IIR1_COEF_B2_CTL + 16 * iir_idx),
567 (value >> 16) & 0xFF);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]568
569 /* Mask top 2 bits, 7-8 are reserved */
570 snd_soc_write(codec,
571 (TAIKO_A_CDC_IIR1_COEF_B2_CTL + 16 * iir_idx),
572 (value >> 24) & 0x3F);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]573}
574
575static int taiko_put_iir_band_audio_mixer(
576 struct snd_kcontrol *kcontrol,
577 struct snd_ctl_elem_value *ucontrol)
578{
579 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
580 int iir_idx = ((struct soc_multi_mixer_control *)
581 kcontrol->private_value)->reg;
582 int band_idx = ((struct soc_multi_mixer_control *)
583 kcontrol->private_value)->shift;
584
Ben Romberger205e14d2013-02-06 12:31:53 -0800[diff] [blame]585 /* Mask top bit it is reserved */
586 /* Updates addr automatically for each B2 write */
587 snd_soc_write(codec,
588 (TAIKO_A_CDC_IIR1_COEF_B1_CTL + 16 * iir_idx),
589 (band_idx * BAND_MAX * sizeof(uint32_t)) & 0x7F);
590
591 set_iir_band_coeff(codec, iir_idx, band_idx,
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]592 ucontrol->value.integer.value[0]);
Ben Romberger205e14d2013-02-06 12:31:53 -0800[diff] [blame]593 set_iir_band_coeff(codec, iir_idx, band_idx,
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]594 ucontrol->value.integer.value[1]);
Ben Romberger205e14d2013-02-06 12:31:53 -0800[diff] [blame]595 set_iir_band_coeff(codec, iir_idx, band_idx,
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]596 ucontrol->value.integer.value[2]);
Ben Romberger205e14d2013-02-06 12:31:53 -0800[diff] [blame]597 set_iir_band_coeff(codec, iir_idx, band_idx,
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]598 ucontrol->value.integer.value[3]);
Ben Romberger205e14d2013-02-06 12:31:53 -0800[diff] [blame]599 set_iir_band_coeff(codec, iir_idx, band_idx,
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]600 ucontrol->value.integer.value[4]);
601
602 pr_debug("%s: IIR #%d band #%d b0 = 0x%x\n"
603 "%s: IIR #%d band #%d b1 = 0x%x\n"
604 "%s: IIR #%d band #%d b2 = 0x%x\n"
605 "%s: IIR #%d band #%d a1 = 0x%x\n"
606 "%s: IIR #%d band #%d a2 = 0x%x\n",
607 __func__, iir_idx, band_idx,
608 get_iir_band_coeff(codec, iir_idx, band_idx, 0),
609 __func__, iir_idx, band_idx,
610 get_iir_band_coeff(codec, iir_idx, band_idx, 1),
611 __func__, iir_idx, band_idx,
612 get_iir_band_coeff(codec, iir_idx, band_idx, 2),
613 __func__, iir_idx, band_idx,
614 get_iir_band_coeff(codec, iir_idx, band_idx, 3),
615 __func__, iir_idx, band_idx,
616 get_iir_band_coeff(codec, iir_idx, band_idx, 4));
617 return 0;
618}
619
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]620static int taiko_get_compander(struct snd_kcontrol *kcontrol,
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]621 struct snd_ctl_elem_value *ucontrol)
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]622{
623
624 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
625 int comp = ((struct soc_multi_mixer_control *)
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]626 kcontrol->private_value)->shift;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]627 struct taiko_priv *taiko = snd_soc_codec_get_drvdata(codec);
628
629 ucontrol->value.integer.value[0] = taiko->comp_enabled[comp];
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]630 return 0;
631}
632
633static int taiko_set_compander(struct snd_kcontrol *kcontrol,
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]634 struct snd_ctl_elem_value *ucontrol)
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]635{
636 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
637 struct taiko_priv *taiko = snd_soc_codec_get_drvdata(codec);
638 int comp = ((struct soc_multi_mixer_control *)
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]639 kcontrol->private_value)->shift;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]640 int value = ucontrol->value.integer.value[0];
641
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]642 pr_debug("%s: Compander %d enable current %d, new %d\n",
643 __func__, comp, taiko->comp_enabled[comp], value);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]644 taiko->comp_enabled[comp] = value;
645 return 0;
646}
647
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]648static int taiko_config_gain_compander(struct snd_soc_codec *codec,
649 int comp, bool enable)
650{
651 int ret = 0;
652
653 switch (comp) {
654 case COMPANDER_0:
655 snd_soc_update_bits(codec, TAIKO_A_SPKR_DRV_GAIN,
656 1 << 2, !enable << 2);
657 break;
658 case COMPANDER_1:
659 snd_soc_update_bits(codec, TAIKO_A_RX_HPH_L_GAIN,
660 1 << 5, !enable << 5);
661 snd_soc_update_bits(codec, TAIKO_A_RX_HPH_R_GAIN,
662 1 << 5, !enable << 5);
663 break;
664 case COMPANDER_2:
665 snd_soc_update_bits(codec, TAIKO_A_RX_LINE_1_GAIN,
666 1 << 5, !enable << 5);
667 snd_soc_update_bits(codec, TAIKO_A_RX_LINE_3_GAIN,
668 1 << 5, !enable << 5);
669 snd_soc_update_bits(codec, TAIKO_A_RX_LINE_2_GAIN,
670 1 << 5, !enable << 5);
671 snd_soc_update_bits(codec, TAIKO_A_RX_LINE_4_GAIN,
672 1 << 5, !enable << 5);
673 break;
674 default:
675 WARN_ON(1);
676 ret = -EINVAL;
677 }
678
679 return ret;
680}
681
682static void taiko_discharge_comp(struct snd_soc_codec *codec, int comp)
683{
684 /* Update RSM to 1, DIVF to 5 */
685 snd_soc_write(codec, TAIKO_A_CDC_COMP0_B3_CTL + (comp * 8), 1);
686 snd_soc_update_bits(codec, TAIKO_A_CDC_COMP0_B2_CTL + (comp * 8), 0xF0,
687 1 << 5);
688 /* Wait for 1ms */
689 usleep_range(1000, 1000);
690}
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]691
692static int taiko_config_compander(struct snd_soc_dapm_widget *w,
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]693 struct snd_kcontrol *kcontrol, int event)
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]694{
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]695 int mask, emask;
696 bool timedout;
697 unsigned long timeout;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]698 struct snd_soc_codec *codec = w->codec;
699 struct taiko_priv *taiko = snd_soc_codec_get_drvdata(codec);
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]700 const int comp = w->shift;
701 const u32 rate = taiko->comp_fs[comp];
702 const struct comp_sample_dependent_params *comp_params =
703 &comp_samp_params[rate];
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]704
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]705 pr_debug("%s: %s event %d compander %d, enabled %d", __func__,
706 w->name, event, comp, taiko->comp_enabled[comp]);
707
708 if (!taiko->comp_enabled[comp])
709 return 0;
710
711 /* Compander 0 has single channel */
712 mask = (comp == COMPANDER_0 ? 0x01 : 0x03);
713 emask = (comp == COMPANDER_0 ? 0x02 : 0x03);
Kiran Kandid2b46332012-10-05 12:04:00 -0700[diff] [blame]714
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]715 switch (event) {
716 case SND_SOC_DAPM_PRE_PMU:
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]717 /* Set gain source to compander */
718 taiko_config_gain_compander(codec, comp, true);
719 /* Enable RX interpolation path clocks */
720 snd_soc_update_bits(codec, TAIKO_A_CDC_CLK_RX_B2_CTL,
721 mask << comp_shift[comp],
722 mask << comp_shift[comp]);
723
724 taiko_discharge_comp(codec, comp);
725
726 /* Clear compander halt */
727 snd_soc_update_bits(codec, TAIKO_A_CDC_COMP0_B1_CTL +
728 (comp * 8),
729 1 << 2, 0);
730 /* Toggle compander reset bits */
731 snd_soc_update_bits(codec, TAIKO_A_CDC_CLK_OTHR_RESET_B2_CTL,
732 mask << comp_shift[comp],
733 mask << comp_shift[comp]);
734 snd_soc_update_bits(codec, TAIKO_A_CDC_CLK_OTHR_RESET_B2_CTL,
735 mask << comp_shift[comp], 0);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]736 break;
737 case SND_SOC_DAPM_POST_PMU:
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]738 /* Set sample rate dependent paramater */
739 snd_soc_update_bits(codec,
740 TAIKO_A_CDC_COMP0_FS_CFG + (comp * 8),
741 0x07, rate);
742 snd_soc_write(codec, TAIKO_A_CDC_COMP0_B3_CTL + (comp * 8),
743 comp_params->rms_meter_resamp_fact);
744 snd_soc_update_bits(codec,
745 TAIKO_A_CDC_COMP0_B2_CTL + (comp * 8),
746 0x0F, comp_params->peak_det_timeout);
747 snd_soc_update_bits(codec,
748 TAIKO_A_CDC_COMP0_B2_CTL + (comp * 8),
749 0xF0, comp_params->rms_meter_div_fact << 4);
750 /* Compander enable */
751 snd_soc_update_bits(codec, TAIKO_A_CDC_COMP0_B1_CTL +
752 (comp * 8), emask, emask);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]753 break;
754 case SND_SOC_DAPM_PRE_PMD:
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]755 /* Halt compander */
756 snd_soc_update_bits(codec,
757 TAIKO_A_CDC_COMP0_B1_CTL + (comp * 8),
758 1 << 2, 1 << 2);
759 /* Wait up to a second for shutdown complete */
760 timeout = jiffies + HZ;
761 do {
762 if ((snd_soc_read(codec,
763 TAIKO_A_CDC_COMP0_SHUT_DOWN_STATUS +
764 (comp * 8)) & mask) == mask)
765 break;
766 } while (!(timedout = time_after(jiffies, timeout)));
767 pr_debug("%s: Compander %d shutdown %s in %dms\n", __func__,
768 comp, timedout ? "timedout" : "completed",
769 jiffies_to_msecs(timeout - HZ - jiffies));
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]770 break;
771 case SND_SOC_DAPM_POST_PMD:
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]772 /* Disable compander */
773 snd_soc_update_bits(codec,
774 TAIKO_A_CDC_COMP0_B1_CTL + (comp * 8),
775 emask, 0x00);
776 /* Turn off the clock for compander in pair */
777 snd_soc_update_bits(codec, TAIKO_A_CDC_CLK_RX_B2_CTL,
778 mask << comp_shift[comp], 0);
779 /* Set gain source to register */
780 taiko_config_gain_compander(codec, comp, false);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]781 break;
782 }
783 return 0;
784}
785
786static const char * const taiko_ear_pa_gain_text[] = {"POS_6_DB", "POS_2_DB"};
787static const struct soc_enum taiko_ear_pa_gain_enum[] = {
788 SOC_ENUM_SINGLE_EXT(2, taiko_ear_pa_gain_text),
789};
790
791/*cut of frequency for high pass filter*/
792static const char * const cf_text[] = {
793 "MIN_3DB_4Hz", "MIN_3DB_75Hz", "MIN_3DB_150Hz"
794};
795
796static const struct soc_enum cf_dec1_enum =
797 SOC_ENUM_SINGLE(TAIKO_A_CDC_TX1_MUX_CTL, 4, 3, cf_text);
798
799static const struct soc_enum cf_dec2_enum =
800 SOC_ENUM_SINGLE(TAIKO_A_CDC_TX2_MUX_CTL, 4, 3, cf_text);
801
802static const struct soc_enum cf_dec3_enum =
803 SOC_ENUM_SINGLE(TAIKO_A_CDC_TX3_MUX_CTL, 4, 3, cf_text);
804
805static const struct soc_enum cf_dec4_enum =
806 SOC_ENUM_SINGLE(TAIKO_A_CDC_TX4_MUX_CTL, 4, 3, cf_text);
807
808static const struct soc_enum cf_dec5_enum =
809 SOC_ENUM_SINGLE(TAIKO_A_CDC_TX5_MUX_CTL, 4, 3, cf_text);
810
811static const struct soc_enum cf_dec6_enum =
812 SOC_ENUM_SINGLE(TAIKO_A_CDC_TX6_MUX_CTL, 4, 3, cf_text);
813
814static const struct soc_enum cf_dec7_enum =
815 SOC_ENUM_SINGLE(TAIKO_A_CDC_TX7_MUX_CTL, 4, 3, cf_text);
816
817static const struct soc_enum cf_dec8_enum =
818 SOC_ENUM_SINGLE(TAIKO_A_CDC_TX8_MUX_CTL, 4, 3, cf_text);
819
820static const struct soc_enum cf_dec9_enum =
821 SOC_ENUM_SINGLE(TAIKO_A_CDC_TX9_MUX_CTL, 4, 3, cf_text);
822
823static const struct soc_enum cf_dec10_enum =
824 SOC_ENUM_SINGLE(TAIKO_A_CDC_TX10_MUX_CTL, 4, 3, cf_text);
825
826static const struct soc_enum cf_rxmix1_enum =
827 SOC_ENUM_SINGLE(TAIKO_A_CDC_RX1_B4_CTL, 1, 3, cf_text);
828
829static const struct soc_enum cf_rxmix2_enum =
830 SOC_ENUM_SINGLE(TAIKO_A_CDC_RX2_B4_CTL, 1, 3, cf_text);
831
832static const struct soc_enum cf_rxmix3_enum =
833 SOC_ENUM_SINGLE(TAIKO_A_CDC_RX3_B4_CTL, 1, 3, cf_text);
834
835static const struct soc_enum cf_rxmix4_enum =
836 SOC_ENUM_SINGLE(TAIKO_A_CDC_RX4_B4_CTL, 1, 3, cf_text);
837
838static const struct soc_enum cf_rxmix5_enum =
839 SOC_ENUM_SINGLE(TAIKO_A_CDC_RX5_B4_CTL, 1, 3, cf_text)
840;
841static const struct soc_enum cf_rxmix6_enum =
842 SOC_ENUM_SINGLE(TAIKO_A_CDC_RX6_B4_CTL, 1, 3, cf_text);
843
844static const struct soc_enum cf_rxmix7_enum =
845 SOC_ENUM_SINGLE(TAIKO_A_CDC_RX7_B4_CTL, 1, 3, cf_text);
846
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]847static const char * const class_h_dsm_text[] = {
848 "ZERO", "DSM_HPHL_RX1", "DSM_SPKR_RX7"
849};
850
851static const struct soc_enum class_h_dsm_enum =
852 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_CLSH_CTL, 4, 3, class_h_dsm_text);
853
854static const struct snd_kcontrol_new class_h_dsm_mux =
855 SOC_DAPM_ENUM("CLASS_H_DSM MUX Mux", class_h_dsm_enum);
856
857
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]858static const struct snd_kcontrol_new taiko_snd_controls[] = {
859
860 SOC_ENUM_EXT("EAR PA Gain", taiko_ear_pa_gain_enum[0],
861 taiko_pa_gain_get, taiko_pa_gain_put),
862
863 SOC_SINGLE_TLV("LINEOUT1 Volume", TAIKO_A_RX_LINE_1_GAIN, 0, 12, 1,
864 line_gain),
865 SOC_SINGLE_TLV("LINEOUT2 Volume", TAIKO_A_RX_LINE_2_GAIN, 0, 12, 1,
866 line_gain),
867 SOC_SINGLE_TLV("LINEOUT3 Volume", TAIKO_A_RX_LINE_3_GAIN, 0, 12, 1,
868 line_gain),
869 SOC_SINGLE_TLV("LINEOUT4 Volume", TAIKO_A_RX_LINE_4_GAIN, 0, 12, 1,
870 line_gain),
871
872 SOC_SINGLE_TLV("HPHL Volume", TAIKO_A_RX_HPH_L_GAIN, 0, 12, 1,
873 line_gain),
874 SOC_SINGLE_TLV("HPHR Volume", TAIKO_A_RX_HPH_R_GAIN, 0, 12, 1,
875 line_gain),
876
Kiran Kandifd0a1da2013-01-21 09:58:45 -0800[diff] [blame]877 SOC_SINGLE_TLV("SPK DRV Volume", TAIKO_A_SPKR_DRV_GAIN, 3, 7, 1,
878 line_gain),
879
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]880 SOC_SINGLE_S8_TLV("RX1 Digital Volume", TAIKO_A_CDC_RX1_VOL_CTL_B2_CTL,
881 -84, 40, digital_gain),
882 SOC_SINGLE_S8_TLV("RX2 Digital Volume", TAIKO_A_CDC_RX2_VOL_CTL_B2_CTL,
883 -84, 40, digital_gain),
884 SOC_SINGLE_S8_TLV("RX3 Digital Volume", TAIKO_A_CDC_RX3_VOL_CTL_B2_CTL,
885 -84, 40, digital_gain),
886 SOC_SINGLE_S8_TLV("RX4 Digital Volume", TAIKO_A_CDC_RX4_VOL_CTL_B2_CTL,
887 -84, 40, digital_gain),
888 SOC_SINGLE_S8_TLV("RX5 Digital Volume", TAIKO_A_CDC_RX5_VOL_CTL_B2_CTL,
889 -84, 40, digital_gain),
890 SOC_SINGLE_S8_TLV("RX6 Digital Volume", TAIKO_A_CDC_RX6_VOL_CTL_B2_CTL,
891 -84, 40, digital_gain),
892 SOC_SINGLE_S8_TLV("RX7 Digital Volume", TAIKO_A_CDC_RX7_VOL_CTL_B2_CTL,
893 -84, 40, digital_gain),
894
895 SOC_SINGLE_S8_TLV("DEC1 Volume", TAIKO_A_CDC_TX1_VOL_CTL_GAIN, -84, 40,
896 digital_gain),
897 SOC_SINGLE_S8_TLV("DEC2 Volume", TAIKO_A_CDC_TX2_VOL_CTL_GAIN, -84, 40,
898 digital_gain),
899 SOC_SINGLE_S8_TLV("DEC3 Volume", TAIKO_A_CDC_TX3_VOL_CTL_GAIN, -84, 40,
900 digital_gain),
901 SOC_SINGLE_S8_TLV("DEC4 Volume", TAIKO_A_CDC_TX4_VOL_CTL_GAIN, -84, 40,
902 digital_gain),
903 SOC_SINGLE_S8_TLV("DEC5 Volume", TAIKO_A_CDC_TX5_VOL_CTL_GAIN, -84, 40,
904 digital_gain),
905 SOC_SINGLE_S8_TLV("DEC6 Volume", TAIKO_A_CDC_TX6_VOL_CTL_GAIN, -84, 40,
906 digital_gain),
907 SOC_SINGLE_S8_TLV("DEC7 Volume", TAIKO_A_CDC_TX7_VOL_CTL_GAIN, -84, 40,
908 digital_gain),
909 SOC_SINGLE_S8_TLV("DEC8 Volume", TAIKO_A_CDC_TX8_VOL_CTL_GAIN, -84, 40,
910 digital_gain),
911 SOC_SINGLE_S8_TLV("DEC9 Volume", TAIKO_A_CDC_TX9_VOL_CTL_GAIN, -84, 40,
912 digital_gain),
913 SOC_SINGLE_S8_TLV("DEC10 Volume", TAIKO_A_CDC_TX10_VOL_CTL_GAIN, -84,
914 40, digital_gain),
915 SOC_SINGLE_S8_TLV("IIR1 INP1 Volume", TAIKO_A_CDC_IIR1_GAIN_B1_CTL, -84,
916 40, digital_gain),
917 SOC_SINGLE_S8_TLV("IIR1 INP2 Volume", TAIKO_A_CDC_IIR1_GAIN_B2_CTL, -84,
918 40, digital_gain),
919 SOC_SINGLE_S8_TLV("IIR1 INP3 Volume", TAIKO_A_CDC_IIR1_GAIN_B3_CTL, -84,
920 40, digital_gain),
921 SOC_SINGLE_S8_TLV("IIR1 INP4 Volume", TAIKO_A_CDC_IIR1_GAIN_B4_CTL, -84,
922 40, digital_gain),
923 SOC_SINGLE_TLV("ADC1 Volume", TAIKO_A_TX_1_2_EN, 5, 3, 0, analog_gain),
924 SOC_SINGLE_TLV("ADC2 Volume", TAIKO_A_TX_1_2_EN, 1, 3, 0, analog_gain),
925 SOC_SINGLE_TLV("ADC3 Volume", TAIKO_A_TX_3_4_EN, 5, 3, 0, analog_gain),
926 SOC_SINGLE_TLV("ADC4 Volume", TAIKO_A_TX_3_4_EN, 1, 3, 0, analog_gain),
927 SOC_SINGLE_TLV("ADC5 Volume", TAIKO_A_TX_5_6_EN, 5, 3, 0, analog_gain),
928 SOC_SINGLE_TLV("ADC6 Volume", TAIKO_A_TX_5_6_EN, 1, 3, 0, analog_gain),
929
930
931 SOC_SINGLE("MICBIAS1 CAPLESS Switch", TAIKO_A_MICB_1_CTL, 4, 1, 1),
932 SOC_SINGLE("MICBIAS2 CAPLESS Switch", TAIKO_A_MICB_2_CTL, 4, 1, 1),
933 SOC_SINGLE("MICBIAS3 CAPLESS Switch", TAIKO_A_MICB_3_CTL, 4, 1, 1),
934 SOC_SINGLE("MICBIAS4 CAPLESS Switch", TAIKO_A_MICB_4_CTL, 4, 1, 1),
935
936 SOC_SINGLE_EXT("ANC Slot", SND_SOC_NOPM, 0, 0, 100, taiko_get_anc_slot,
937 taiko_put_anc_slot),
938 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
939 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
940 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
941 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
942 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
943 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
944 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
945 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
946 SOC_ENUM("TX9 HPF cut off", cf_dec9_enum),
947 SOC_ENUM("TX10 HPF cut off", cf_dec10_enum),
948
949 SOC_SINGLE("TX1 HPF Switch", TAIKO_A_CDC_TX1_MUX_CTL, 3, 1, 0),
950 SOC_SINGLE("TX2 HPF Switch", TAIKO_A_CDC_TX2_MUX_CTL, 3, 1, 0),
951 SOC_SINGLE("TX3 HPF Switch", TAIKO_A_CDC_TX3_MUX_CTL, 3, 1, 0),
952 SOC_SINGLE("TX4 HPF Switch", TAIKO_A_CDC_TX4_MUX_CTL, 3, 1, 0),
953 SOC_SINGLE("TX5 HPF Switch", TAIKO_A_CDC_TX5_MUX_CTL, 3, 1, 0),
954 SOC_SINGLE("TX6 HPF Switch", TAIKO_A_CDC_TX6_MUX_CTL, 3, 1, 0),
955 SOC_SINGLE("TX7 HPF Switch", TAIKO_A_CDC_TX7_MUX_CTL, 3, 1, 0),
956 SOC_SINGLE("TX8 HPF Switch", TAIKO_A_CDC_TX8_MUX_CTL, 3, 1, 0),
957 SOC_SINGLE("TX9 HPF Switch", TAIKO_A_CDC_TX9_MUX_CTL, 3, 1, 0),
958 SOC_SINGLE("TX10 HPF Switch", TAIKO_A_CDC_TX10_MUX_CTL, 3, 1, 0),
959
960 SOC_SINGLE("RX1 HPF Switch", TAIKO_A_CDC_RX1_B5_CTL, 2, 1, 0),
961 SOC_SINGLE("RX2 HPF Switch", TAIKO_A_CDC_RX2_B5_CTL, 2, 1, 0),
962 SOC_SINGLE("RX3 HPF Switch", TAIKO_A_CDC_RX3_B5_CTL, 2, 1, 0),
963 SOC_SINGLE("RX4 HPF Switch", TAIKO_A_CDC_RX4_B5_CTL, 2, 1, 0),
964 SOC_SINGLE("RX5 HPF Switch", TAIKO_A_CDC_RX5_B5_CTL, 2, 1, 0),
965 SOC_SINGLE("RX6 HPF Switch", TAIKO_A_CDC_RX6_B5_CTL, 2, 1, 0),
966 SOC_SINGLE("RX7 HPF Switch", TAIKO_A_CDC_RX7_B5_CTL, 2, 1, 0),
967
968 SOC_ENUM("RX1 HPF cut off", cf_rxmix1_enum),
969 SOC_ENUM("RX2 HPF cut off", cf_rxmix2_enum),
970 SOC_ENUM("RX3 HPF cut off", cf_rxmix3_enum),
971 SOC_ENUM("RX4 HPF cut off", cf_rxmix4_enum),
972 SOC_ENUM("RX5 HPF cut off", cf_rxmix5_enum),
973 SOC_ENUM("RX6 HPF cut off", cf_rxmix6_enum),
974 SOC_ENUM("RX7 HPF cut off", cf_rxmix7_enum),
975
976 SOC_SINGLE_EXT("IIR1 Enable Band1", IIR1, BAND1, 1, 0,
977 taiko_get_iir_enable_audio_mixer, taiko_put_iir_enable_audio_mixer),
978 SOC_SINGLE_EXT("IIR1 Enable Band2", IIR1, BAND2, 1, 0,
979 taiko_get_iir_enable_audio_mixer, taiko_put_iir_enable_audio_mixer),
980 SOC_SINGLE_EXT("IIR1 Enable Band3", IIR1, BAND3, 1, 0,
981 taiko_get_iir_enable_audio_mixer, taiko_put_iir_enable_audio_mixer),
982 SOC_SINGLE_EXT("IIR1 Enable Band4", IIR1, BAND4, 1, 0,
983 taiko_get_iir_enable_audio_mixer, taiko_put_iir_enable_audio_mixer),
984 SOC_SINGLE_EXT("IIR1 Enable Band5", IIR1, BAND5, 1, 0,
985 taiko_get_iir_enable_audio_mixer, taiko_put_iir_enable_audio_mixer),
986 SOC_SINGLE_EXT("IIR2 Enable Band1", IIR2, BAND1, 1, 0,
987 taiko_get_iir_enable_audio_mixer, taiko_put_iir_enable_audio_mixer),
988 SOC_SINGLE_EXT("IIR2 Enable Band2", IIR2, BAND2, 1, 0,
989 taiko_get_iir_enable_audio_mixer, taiko_put_iir_enable_audio_mixer),
990 SOC_SINGLE_EXT("IIR2 Enable Band3", IIR2, BAND3, 1, 0,
991 taiko_get_iir_enable_audio_mixer, taiko_put_iir_enable_audio_mixer),
992 SOC_SINGLE_EXT("IIR2 Enable Band4", IIR2, BAND4, 1, 0,
993 taiko_get_iir_enable_audio_mixer, taiko_put_iir_enable_audio_mixer),
994 SOC_SINGLE_EXT("IIR2 Enable Band5", IIR2, BAND5, 1, 0,
995 taiko_get_iir_enable_audio_mixer, taiko_put_iir_enable_audio_mixer),
996
997 SOC_SINGLE_MULTI_EXT("IIR1 Band1", IIR1, BAND1, 255, 0, 5,
998 taiko_get_iir_band_audio_mixer, taiko_put_iir_band_audio_mixer),
999 SOC_SINGLE_MULTI_EXT("IIR1 Band2", IIR1, BAND2, 255, 0, 5,
1000 taiko_get_iir_band_audio_mixer, taiko_put_iir_band_audio_mixer),
1001 SOC_SINGLE_MULTI_EXT("IIR1 Band3", IIR1, BAND3, 255, 0, 5,
1002 taiko_get_iir_band_audio_mixer, taiko_put_iir_band_audio_mixer),
1003 SOC_SINGLE_MULTI_EXT("IIR1 Band4", IIR1, BAND4, 255, 0, 5,
1004 taiko_get_iir_band_audio_mixer, taiko_put_iir_band_audio_mixer),
1005 SOC_SINGLE_MULTI_EXT("IIR1 Band5", IIR1, BAND5, 255, 0, 5,
1006 taiko_get_iir_band_audio_mixer, taiko_put_iir_band_audio_mixer),
1007 SOC_SINGLE_MULTI_EXT("IIR2 Band1", IIR2, BAND1, 255, 0, 5,
1008 taiko_get_iir_band_audio_mixer, taiko_put_iir_band_audio_mixer),
1009 SOC_SINGLE_MULTI_EXT("IIR2 Band2", IIR2, BAND2, 255, 0, 5,
1010 taiko_get_iir_band_audio_mixer, taiko_put_iir_band_audio_mixer),
1011 SOC_SINGLE_MULTI_EXT("IIR2 Band3", IIR2, BAND3, 255, 0, 5,
1012 taiko_get_iir_band_audio_mixer, taiko_put_iir_band_audio_mixer),
1013 SOC_SINGLE_MULTI_EXT("IIR2 Band4", IIR2, BAND4, 255, 0, 5,
1014 taiko_get_iir_band_audio_mixer, taiko_put_iir_band_audio_mixer),
1015 SOC_SINGLE_MULTI_EXT("IIR2 Band5", IIR2, BAND5, 255, 0, 5,
1016 taiko_get_iir_band_audio_mixer, taiko_put_iir_band_audio_mixer),
1017
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]1018 SOC_SINGLE_EXT("COMP0 Switch", SND_SOC_NOPM, COMPANDER_0, 1, 0,
1019 taiko_get_compander, taiko_set_compander),
1020 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
1021 taiko_get_compander, taiko_set_compander),
1022 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
1023 taiko_get_compander, taiko_set_compander),
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]1024
1025};
1026
1027static const char * const rx_mix1_text[] = {
1028 "ZERO", "SRC1", "SRC2", "IIR1", "IIR2", "RX1", "RX2", "RX3", "RX4",
1029 "RX5", "RX6", "RX7"
1030};
1031
1032static const char * const rx_mix2_text[] = {
1033 "ZERO", "SRC1", "SRC2", "IIR1", "IIR2"
1034};
1035
Tanya Finkeldaaa6d12012-10-25 11:22:48 +0200[diff] [blame]1036static const char * const rx_rdac5_text[] = {
1037 "DEM4", "DEM3_INV"
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]1038};
1039
Tanya Finkeldaaa6d12012-10-25 11:22:48 +0200[diff] [blame]1040static const char * const rx_rdac7_text[] = {
1041 "DEM6", "DEM5_INV"
1042};
1043
1044
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]1045static const char * const sb_tx1_mux_text[] = {
1046 "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
1047 "DEC1"
1048};
1049
1050static const char * const sb_tx2_mux_text[] = {
1051 "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
1052 "DEC2"
1053};
1054
1055static const char * const sb_tx3_mux_text[] = {
1056 "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
1057 "DEC3"
1058};
1059
1060static const char * const sb_tx4_mux_text[] = {
1061 "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
1062 "DEC4"
1063};
1064
1065static const char * const sb_tx5_mux_text[] = {
1066 "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
1067 "DEC5"
1068};
1069
1070static const char * const sb_tx6_mux_text[] = {
1071 "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
1072 "DEC6"
1073};
1074
1075static const char * const sb_tx7_to_tx10_mux_text[] = {
1076 "ZERO", "RMIX1", "RMIX2", "RMIX3", "RMIX4", "RMIX5", "RMIX6", "RMIX7",
1077 "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6", "DEC7", "DEC8",
1078 "DEC9", "DEC10"
1079};
1080
1081static const char * const dec1_mux_text[] = {
1082 "ZERO", "DMIC1", "ADC6",
1083};
1084
1085static const char * const dec2_mux_text[] = {
1086 "ZERO", "DMIC2", "ADC5",
1087};
1088
1089static const char * const dec3_mux_text[] = {
1090 "ZERO", "DMIC3", "ADC4",
1091};
1092
1093static const char * const dec4_mux_text[] = {
1094 "ZERO", "DMIC4", "ADC3",
1095};
1096
1097static const char * const dec5_mux_text[] = {
1098 "ZERO", "DMIC5", "ADC2",
1099};
1100
1101static const char * const dec6_mux_text[] = {
1102 "ZERO", "DMIC6", "ADC1",
1103};
1104
1105static const char * const dec7_mux_text[] = {
1106 "ZERO", "DMIC1", "DMIC6", "ADC1", "ADC6", "ANC1_FB", "ANC2_FB",
1107};
1108
1109static const char * const dec8_mux_text[] = {
1110 "ZERO", "DMIC2", "DMIC5", "ADC2", "ADC5",
1111};
1112
1113static const char * const dec9_mux_text[] = {
1114 "ZERO", "DMIC4", "DMIC5", "ADC2", "ADC3", "ADCMB", "ANC1_FB", "ANC2_FB",
1115};
1116
1117static const char * const dec10_mux_text[] = {
1118 "ZERO", "DMIC3", "DMIC6", "ADC1", "ADC4", "ADCMB", "ANC1_FB", "ANC2_FB",
1119};
1120
1121static const char * const anc_mux_text[] = {
1122 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6", "ADC_MB",
1123 "RSVD_1", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5", "DMIC6"
1124};
1125
1126static const char * const anc1_fb_mux_text[] = {
1127 "ZERO", "EAR_HPH_L", "EAR_LINE_1",
1128};
1129
1130static const char * const iir1_inp1_text[] = {
1131 "ZERO", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6", "DEC7", "DEC8",
1132 "DEC9", "DEC10", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7"
1133};
1134
1135static const struct soc_enum rx_mix1_inp1_chain_enum =
1136 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_RX1_B1_CTL, 0, 12, rx_mix1_text);
1137
1138static const struct soc_enum rx_mix1_inp2_chain_enum =
1139 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_RX1_B1_CTL, 4, 12, rx_mix1_text);
1140
1141static const struct soc_enum rx_mix1_inp3_chain_enum =
1142 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_RX1_B2_CTL, 0, 12, rx_mix1_text);
1143
1144static const struct soc_enum rx2_mix1_inp1_chain_enum =
1145 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_RX2_B1_CTL, 0, 12, rx_mix1_text);
1146
1147static const struct soc_enum rx2_mix1_inp2_chain_enum =
1148 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_RX2_B1_CTL, 4, 12, rx_mix1_text);
1149
1150static const struct soc_enum rx3_mix1_inp1_chain_enum =
1151 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_RX3_B1_CTL, 0, 12, rx_mix1_text);
1152
1153static const struct soc_enum rx3_mix1_inp2_chain_enum =
1154 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_RX3_B1_CTL, 4, 12, rx_mix1_text);
1155
1156static const struct soc_enum rx4_mix1_inp1_chain_enum =
1157 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_RX4_B1_CTL, 0, 12, rx_mix1_text);
1158
1159static const struct soc_enum rx4_mix1_inp2_chain_enum =
1160 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_RX4_B1_CTL, 4, 12, rx_mix1_text);
1161
1162static const struct soc_enum rx5_mix1_inp1_chain_enum =
1163 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_RX5_B1_CTL, 0, 12, rx_mix1_text);
1164
1165static const struct soc_enum rx5_mix1_inp2_chain_enum =
1166 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_RX5_B1_CTL, 4, 12, rx_mix1_text);
1167
1168static const struct soc_enum rx6_mix1_inp1_chain_enum =
1169 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_RX6_B1_CTL, 0, 12, rx_mix1_text);
1170
1171static const struct soc_enum rx6_mix1_inp2_chain_enum =
1172 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_RX6_B1_CTL, 4, 12, rx_mix1_text);
1173
1174static const struct soc_enum rx7_mix1_inp1_chain_enum =
1175 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_RX7_B1_CTL, 0, 12, rx_mix1_text);
1176
1177static const struct soc_enum rx7_mix1_inp2_chain_enum =
1178 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_RX7_B1_CTL, 4, 12, rx_mix1_text);
1179
1180static const struct soc_enum rx1_mix2_inp1_chain_enum =
1181 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_RX1_B3_CTL, 0, 5, rx_mix2_text);
1182
1183static const struct soc_enum rx1_mix2_inp2_chain_enum =
1184 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_RX1_B3_CTL, 3, 5, rx_mix2_text);
1185
1186static const struct soc_enum rx2_mix2_inp1_chain_enum =
1187 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_RX2_B3_CTL, 0, 5, rx_mix2_text);
1188
1189static const struct soc_enum rx2_mix2_inp2_chain_enum =
1190 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_RX2_B3_CTL, 3, 5, rx_mix2_text);
1191
1192static const struct soc_enum rx7_mix2_inp1_chain_enum =
1193 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_RX7_B3_CTL, 0, 5, rx_mix2_text);
1194
1195static const struct soc_enum rx7_mix2_inp2_chain_enum =
1196 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_RX7_B3_CTL, 3, 5, rx_mix2_text);
1197
Tanya Finkeldaaa6d12012-10-25 11:22:48 +0200[diff] [blame]1198static const struct soc_enum rx_rdac5_enum =
1199 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_MISC, 2, 2, rx_rdac5_text);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]1200
Tanya Finkeldaaa6d12012-10-25 11:22:48 +0200[diff] [blame]1201static const struct soc_enum rx_rdac7_enum =
1202 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_MISC, 1, 2, rx_rdac7_text);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]1203
1204static const struct soc_enum sb_tx1_mux_enum =
1205 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_TX_SB_B1_CTL, 0, 9, sb_tx1_mux_text);
1206
1207static const struct soc_enum sb_tx2_mux_enum =
1208 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_TX_SB_B2_CTL, 0, 9, sb_tx2_mux_text);
1209
1210static const struct soc_enum sb_tx3_mux_enum =
1211 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_TX_SB_B3_CTL, 0, 9, sb_tx3_mux_text);
1212
1213static const struct soc_enum sb_tx4_mux_enum =
1214 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_TX_SB_B4_CTL, 0, 9, sb_tx4_mux_text);
1215
1216static const struct soc_enum sb_tx5_mux_enum =
1217 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_TX_SB_B5_CTL, 0, 9, sb_tx5_mux_text);
1218
1219static const struct soc_enum sb_tx6_mux_enum =
1220 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_TX_SB_B6_CTL, 0, 9, sb_tx6_mux_text);
1221
1222static const struct soc_enum sb_tx7_mux_enum =
1223 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_TX_SB_B7_CTL, 0, 18,
1224 sb_tx7_to_tx10_mux_text);
1225
1226static const struct soc_enum sb_tx8_mux_enum =
1227 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_TX_SB_B8_CTL, 0, 18,
1228 sb_tx7_to_tx10_mux_text);
1229
1230static const struct soc_enum sb_tx9_mux_enum =
1231 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_TX_SB_B9_CTL, 0, 18,
1232 sb_tx7_to_tx10_mux_text);
1233
1234static const struct soc_enum sb_tx10_mux_enum =
1235 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_TX_SB_B10_CTL, 0, 18,
1236 sb_tx7_to_tx10_mux_text);
1237
1238static const struct soc_enum dec1_mux_enum =
1239 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_TX_B1_CTL, 0, 3, dec1_mux_text);
1240
1241static const struct soc_enum dec2_mux_enum =
1242 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_TX_B1_CTL, 2, 3, dec2_mux_text);
1243
1244static const struct soc_enum dec3_mux_enum =
1245 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_TX_B1_CTL, 4, 3, dec3_mux_text);
1246
1247static const struct soc_enum dec4_mux_enum =
1248 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_TX_B1_CTL, 6, 3, dec4_mux_text);
1249
1250static const struct soc_enum dec5_mux_enum =
1251 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_TX_B2_CTL, 0, 3, dec5_mux_text);
1252
1253static const struct soc_enum dec6_mux_enum =
1254 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_TX_B2_CTL, 2, 3, dec6_mux_text);
1255
1256static const struct soc_enum dec7_mux_enum =
1257 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_TX_B2_CTL, 4, 7, dec7_mux_text);
1258
1259static const struct soc_enum dec8_mux_enum =
1260 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_TX_B3_CTL, 0, 7, dec8_mux_text);
1261
1262static const struct soc_enum dec9_mux_enum =
1263 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_TX_B3_CTL, 3, 8, dec9_mux_text);
1264
1265static const struct soc_enum dec10_mux_enum =
1266 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_TX_B4_CTL, 0, 8, dec10_mux_text);
1267
1268static const struct soc_enum anc1_mux_enum =
1269 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_ANC_B1_CTL, 0, 16, anc_mux_text);
1270
1271static const struct soc_enum anc2_mux_enum =
1272 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_ANC_B1_CTL, 4, 16, anc_mux_text);
1273
1274static const struct soc_enum anc1_fb_mux_enum =
1275 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_ANC_B2_CTL, 0, 3, anc1_fb_mux_text);
1276
1277static const struct soc_enum iir1_inp1_mux_enum =
1278 SOC_ENUM_SINGLE(TAIKO_A_CDC_CONN_EQ1_B1_CTL, 0, 18, iir1_inp1_text);
1279
1280static const struct snd_kcontrol_new rx_mix1_inp1_mux =
1281 SOC_DAPM_ENUM("RX1 MIX1 INP1 Mux", rx_mix1_inp1_chain_enum);
1282
1283static const struct snd_kcontrol_new rx_mix1_inp2_mux =
1284 SOC_DAPM_ENUM("RX1 MIX1 INP2 Mux", rx_mix1_inp2_chain_enum);
1285
1286static const struct snd_kcontrol_new rx_mix1_inp3_mux =
1287 SOC_DAPM_ENUM("RX1 MIX1 INP3 Mux", rx_mix1_inp3_chain_enum);
1288
1289static const struct snd_kcontrol_new rx2_mix1_inp1_mux =
1290 SOC_DAPM_ENUM("RX2 MIX1 INP1 Mux", rx2_mix1_inp1_chain_enum);
1291
1292static const struct snd_kcontrol_new rx2_mix1_inp2_mux =
1293 SOC_DAPM_ENUM("RX2 MIX1 INP2 Mux", rx2_mix1_inp2_chain_enum);
1294
1295static const struct snd_kcontrol_new rx3_mix1_inp1_mux =
1296 SOC_DAPM_ENUM("RX3 MIX1 INP1 Mux", rx3_mix1_inp1_chain_enum);
1297
1298static const struct snd_kcontrol_new rx3_mix1_inp2_mux =
1299 SOC_DAPM_ENUM("RX3 MIX1 INP2 Mux", rx3_mix1_inp2_chain_enum);
1300
1301static const struct snd_kcontrol_new rx4_mix1_inp1_mux =
1302 SOC_DAPM_ENUM("RX4 MIX1 INP1 Mux", rx4_mix1_inp1_chain_enum);
1303
1304static const struct snd_kcontrol_new rx4_mix1_inp2_mux =
1305 SOC_DAPM_ENUM("RX4 MIX1 INP2 Mux", rx4_mix1_inp2_chain_enum);
1306
1307static const struct snd_kcontrol_new rx5_mix1_inp1_mux =
1308 SOC_DAPM_ENUM("RX5 MIX1 INP1 Mux", rx5_mix1_inp1_chain_enum);
1309
1310static const struct snd_kcontrol_new rx5_mix1_inp2_mux =
1311 SOC_DAPM_ENUM("RX5 MIX1 INP2 Mux", rx5_mix1_inp2_chain_enum);
1312
1313static const struct snd_kcontrol_new rx6_mix1_inp1_mux =
1314 SOC_DAPM_ENUM("RX6 MIX1 INP1 Mux", rx6_mix1_inp1_chain_enum);
1315
1316static const struct snd_kcontrol_new rx6_mix1_inp2_mux =
1317 SOC_DAPM_ENUM("RX6 MIX1 INP2 Mux", rx6_mix1_inp2_chain_enum);
1318
1319static const struct snd_kcontrol_new rx7_mix1_inp1_mux =
1320 SOC_DAPM_ENUM("RX7 MIX1 INP1 Mux", rx7_mix1_inp1_chain_enum);
1321
1322static const struct snd_kcontrol_new rx7_mix1_inp2_mux =
1323 SOC_DAPM_ENUM("RX7 MIX1 INP2 Mux", rx7_mix1_inp2_chain_enum);
1324
1325static const struct snd_kcontrol_new rx1_mix2_inp1_mux =
1326 SOC_DAPM_ENUM("RX1 MIX2 INP1 Mux", rx1_mix2_inp1_chain_enum);
1327
1328static const struct snd_kcontrol_new rx1_mix2_inp2_mux =
1329 SOC_DAPM_ENUM("RX1 MIX2 INP2 Mux", rx1_mix2_inp2_chain_enum);
1330
1331static const struct snd_kcontrol_new rx2_mix2_inp1_mux =
1332 SOC_DAPM_ENUM("RX2 MIX2 INP1 Mux", rx2_mix2_inp1_chain_enum);
1333
1334static const struct snd_kcontrol_new rx2_mix2_inp2_mux =
1335 SOC_DAPM_ENUM("RX2 MIX2 INP2 Mux", rx2_mix2_inp2_chain_enum);
1336
1337static const struct snd_kcontrol_new rx7_mix2_inp1_mux =
1338 SOC_DAPM_ENUM("RX7 MIX2 INP1 Mux", rx7_mix2_inp1_chain_enum);
1339
1340static const struct snd_kcontrol_new rx7_mix2_inp2_mux =
1341 SOC_DAPM_ENUM("RX7 MIX2 INP2 Mux", rx7_mix2_inp2_chain_enum);
1342
Tanya Finkeldaaa6d12012-10-25 11:22:48 +0200[diff] [blame]1343static const struct snd_kcontrol_new rx_dac5_mux =
1344 SOC_DAPM_ENUM("RDAC5 MUX Mux", rx_rdac5_enum);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]1345
Tanya Finkeldaaa6d12012-10-25 11:22:48 +0200[diff] [blame]1346static const struct snd_kcontrol_new rx_dac7_mux =
1347 SOC_DAPM_ENUM("RDAC7 MUX Mux", rx_rdac7_enum);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]1348
1349static const struct snd_kcontrol_new sb_tx1_mux =
1350 SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum);
1351
1352static const struct snd_kcontrol_new sb_tx2_mux =
1353 SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum);
1354
1355static const struct snd_kcontrol_new sb_tx3_mux =
1356 SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum);
1357
1358static const struct snd_kcontrol_new sb_tx4_mux =
1359 SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum);
1360
1361static const struct snd_kcontrol_new sb_tx5_mux =
1362 SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum);
1363
1364static const struct snd_kcontrol_new sb_tx6_mux =
1365 SOC_DAPM_ENUM("SLIM TX6 MUX Mux", sb_tx6_mux_enum);
1366
1367static const struct snd_kcontrol_new sb_tx7_mux =
1368 SOC_DAPM_ENUM("SLIM TX7 MUX Mux", sb_tx7_mux_enum);
1369
1370static const struct snd_kcontrol_new sb_tx8_mux =
1371 SOC_DAPM_ENUM("SLIM TX8 MUX Mux", sb_tx8_mux_enum);
1372
1373static const struct snd_kcontrol_new sb_tx9_mux =
1374 SOC_DAPM_ENUM("SLIM TX9 MUX Mux", sb_tx9_mux_enum);
1375
1376static const struct snd_kcontrol_new sb_tx10_mux =
1377 SOC_DAPM_ENUM("SLIM TX10 MUX Mux", sb_tx10_mux_enum);
1378
1379
1380static int wcd9320_put_dec_enum(struct snd_kcontrol *kcontrol,
1381 struct snd_ctl_elem_value *ucontrol)
1382{
1383 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1384 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1385 struct snd_soc_codec *codec = w->codec;
1386 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1387 unsigned int dec_mux, decimator;
1388 char *dec_name = NULL;
1389 char *widget_name = NULL;
1390 char *temp;
1391 u16 tx_mux_ctl_reg;
1392 u8 adc_dmic_sel = 0x0;
1393 int ret = 0;
1394
1395 if (ucontrol->value.enumerated.item[0] > e->max - 1)
1396 return -EINVAL;
1397
1398 dec_mux = ucontrol->value.enumerated.item[0];
1399
1400 widget_name = kstrndup(w->name, 15, GFP_KERNEL);
1401 if (!widget_name)
1402 return -ENOMEM;
1403 temp = widget_name;
1404
1405 dec_name = strsep(&widget_name, " ");
1406 widget_name = temp;
1407 if (!dec_name) {
1408 pr_err("%s: Invalid decimator = %s\n", __func__, w->name);
1409 ret = -EINVAL;
1410 goto out;
1411 }
1412
1413 ret = kstrtouint(strpbrk(dec_name, "123456789"), 10, &decimator);
1414 if (ret < 0) {
1415 pr_err("%s: Invalid decimator = %s\n", __func__, dec_name);
1416 ret = -EINVAL;
1417 goto out;
1418 }
1419
1420 dev_dbg(w->dapm->dev, "%s(): widget = %s decimator = %u dec_mux = %u\n"
1421 , __func__, w->name, decimator, dec_mux);
1422
1423
1424 switch (decimator) {
1425 case 1:
1426 case 2:
1427 case 3:
1428 case 4:
1429 case 5:
1430 case 6:
1431 if (dec_mux == 1)
1432 adc_dmic_sel = 0x1;
1433 else
1434 adc_dmic_sel = 0x0;
1435 break;
1436 case 7:
1437 case 8:
1438 case 9:
1439 case 10:
1440 if ((dec_mux == 1) || (dec_mux == 2))
1441 adc_dmic_sel = 0x1;
1442 else
1443 adc_dmic_sel = 0x0;
1444 break;
1445 default:
1446 pr_err("%s: Invalid Decimator = %u\n", __func__, decimator);
1447 ret = -EINVAL;
1448 goto out;
1449 }
1450
1451 tx_mux_ctl_reg = TAIKO_A_CDC_TX1_MUX_CTL + 8 * (decimator - 1);
1452
1453 snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x1, adc_dmic_sel);
1454
1455 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1456
1457out:
1458 kfree(widget_name);
1459 return ret;
1460}
1461
1462#define WCD9320_DEC_ENUM(xname, xenum) \
1463{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1464 .info = snd_soc_info_enum_double, \
1465 .get = snd_soc_dapm_get_enum_double, \
1466 .put = wcd9320_put_dec_enum, \
1467 .private_value = (unsigned long)&xenum }
1468
1469static const struct snd_kcontrol_new dec1_mux =
1470 WCD9320_DEC_ENUM("DEC1 MUX Mux", dec1_mux_enum);
1471
1472static const struct snd_kcontrol_new dec2_mux =
1473 WCD9320_DEC_ENUM("DEC2 MUX Mux", dec2_mux_enum);
1474
1475static const struct snd_kcontrol_new dec3_mux =
1476 WCD9320_DEC_ENUM("DEC3 MUX Mux", dec3_mux_enum);
1477
1478static const struct snd_kcontrol_new dec4_mux =
1479 WCD9320_DEC_ENUM("DEC4 MUX Mux", dec4_mux_enum);
1480
1481static const struct snd_kcontrol_new dec5_mux =
1482 WCD9320_DEC_ENUM("DEC5 MUX Mux", dec5_mux_enum);
1483
1484static const struct snd_kcontrol_new dec6_mux =
1485 WCD9320_DEC_ENUM("DEC6 MUX Mux", dec6_mux_enum);
1486
1487static const struct snd_kcontrol_new dec7_mux =
1488 WCD9320_DEC_ENUM("DEC7 MUX Mux", dec7_mux_enum);
1489
1490static const struct snd_kcontrol_new dec8_mux =
1491 WCD9320_DEC_ENUM("DEC8 MUX Mux", dec8_mux_enum);
1492
1493static const struct snd_kcontrol_new dec9_mux =
1494 WCD9320_DEC_ENUM("DEC9 MUX Mux", dec9_mux_enum);
1495
1496static const struct snd_kcontrol_new dec10_mux =
1497 WCD9320_DEC_ENUM("DEC10 MUX Mux", dec10_mux_enum);
1498
1499static const struct snd_kcontrol_new iir1_inp1_mux =
1500 SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
1501
1502static const struct snd_kcontrol_new anc1_mux =
1503 SOC_DAPM_ENUM("ANC1 MUX Mux", anc1_mux_enum);
1504
1505static const struct snd_kcontrol_new anc2_mux =
1506 SOC_DAPM_ENUM("ANC2 MUX Mux", anc2_mux_enum);
1507
1508static const struct snd_kcontrol_new anc1_fb_mux =
1509 SOC_DAPM_ENUM("ANC1 FB MUX Mux", anc1_fb_mux_enum);
1510
1511static const struct snd_kcontrol_new dac1_switch[] = {
1512 SOC_DAPM_SINGLE("Switch", TAIKO_A_RX_EAR_EN, 5, 1, 0)
1513};
1514static const struct snd_kcontrol_new hphl_switch[] = {
1515 SOC_DAPM_SINGLE("Switch", TAIKO_A_RX_HPH_L_DAC_CTL, 6, 1, 0)
1516};
1517
1518static const struct snd_kcontrol_new hphl_pa_mix[] = {
1519 SOC_DAPM_SINGLE("AUX_PGA_L Switch", TAIKO_A_RX_PA_AUX_IN_CONN,
1520 7, 1, 0),
1521};
1522
1523static const struct snd_kcontrol_new hphr_pa_mix[] = {
1524 SOC_DAPM_SINGLE("AUX_PGA_R Switch", TAIKO_A_RX_PA_AUX_IN_CONN,
1525 6, 1, 0),
1526};
1527
1528static const struct snd_kcontrol_new ear_pa_mix[] = {
1529 SOC_DAPM_SINGLE("AUX_PGA_L Switch", TAIKO_A_RX_PA_AUX_IN_CONN,
1530 5, 1, 0),
1531};
1532static const struct snd_kcontrol_new lineout1_pa_mix[] = {
1533 SOC_DAPM_SINGLE("AUX_PGA_L Switch", TAIKO_A_RX_PA_AUX_IN_CONN,
1534 4, 1, 0),
1535};
1536
1537static const struct snd_kcontrol_new lineout2_pa_mix[] = {
1538 SOC_DAPM_SINGLE("AUX_PGA_R Switch", TAIKO_A_RX_PA_AUX_IN_CONN,
1539 3, 1, 0),
1540};
1541
1542static const struct snd_kcontrol_new lineout3_pa_mix[] = {
1543 SOC_DAPM_SINGLE("AUX_PGA_L Switch", TAIKO_A_RX_PA_AUX_IN_CONN,
1544 2, 1, 0),
1545};
1546
1547static const struct snd_kcontrol_new lineout4_pa_mix[] = {
1548 SOC_DAPM_SINGLE("AUX_PGA_R Switch", TAIKO_A_RX_PA_AUX_IN_CONN,
1549 1, 1, 0),
1550};
1551
1552static const struct snd_kcontrol_new lineout3_ground_switch =
1553 SOC_DAPM_SINGLE("Switch", TAIKO_A_RX_LINE_3_DAC_CTL, 6, 1, 0);
1554
1555static const struct snd_kcontrol_new lineout4_ground_switch =
1556 SOC_DAPM_SINGLE("Switch", TAIKO_A_RX_LINE_4_DAC_CTL, 6, 1, 0);
1557
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]1558/* virtual port entries */
1559static int slim_tx_mixer_get(struct snd_kcontrol *kcontrol,
1560 struct snd_ctl_elem_value *ucontrol)
1561{
1562 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1563 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
1564
1565 ucontrol->value.integer.value[0] = widget->value;
1566 return 0;
1567}
1568
1569static int slim_tx_mixer_put(struct snd_kcontrol *kcontrol,
1570 struct snd_ctl_elem_value *ucontrol)
1571{
1572 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1573 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
1574 struct snd_soc_codec *codec = widget->codec;
1575 struct taiko_priv *taiko_p = snd_soc_codec_get_drvdata(codec);
1576 struct wcd9xxx *core = dev_get_drvdata(codec->dev->parent);
1577 struct soc_multi_mixer_control *mixer =
1578 ((struct soc_multi_mixer_control *)kcontrol->private_value);
1579 u32 dai_id = widget->shift;
1580 u32 port_id = mixer->shift;
1581 u32 enable = ucontrol->value.integer.value[0];
Venkat Sudhir96dd28c2012-12-04 17:00:19 -0800[diff] [blame]1582 u32 vtable = vport_check_table[dai_id];
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]1583
1584
1585 pr_debug("%s: wname %s cname %s value %u shift %d item %ld\n", __func__,
1586 widget->name, ucontrol->id.name, widget->value, widget->shift,
1587 ucontrol->value.integer.value[0]);
1588
1589 mutex_lock(&codec->mutex);
1590
1591 if (taiko_p->intf_type != WCD9XXX_INTERFACE_TYPE_SLIMBUS) {
1592 if (dai_id != AIF1_CAP) {
1593 dev_err(codec->dev, "%s: invalid AIF for I2C mode\n",
1594 __func__);
1595 mutex_unlock(&codec->mutex);
1596 return -EINVAL;
1597 }
1598 }
Venkat Sudhira41630a2012-10-27 00:57:31 -0700[diff] [blame]1599 switch (dai_id) {
1600 case AIF1_CAP:
1601 case AIF2_CAP:
1602 case AIF3_CAP:
1603 /* only add to the list if value not set
1604 */
1605 if (enable && !(widget->value & 1 << port_id)) {
Venkat Sudhir96dd28c2012-12-04 17:00:19 -0800[diff] [blame]1606
1607 if (taiko_p->intf_type ==
1608 WCD9XXX_INTERFACE_TYPE_SLIMBUS)
1609 vtable = vport_check_table[dai_id];
1610 if (taiko_p->intf_type ==
1611 WCD9XXX_INTERFACE_TYPE_I2C)
1612 vtable = vport_i2s_check_table[dai_id];
1613
Venkat Sudhira41630a2012-10-27 00:57:31 -0700[diff] [blame]1614 if (wcd9xxx_tx_vport_validation(
Venkat Sudhir96dd28c2012-12-04 17:00:19 -0800[diff] [blame]1615 vtable,
Kuirong Wangdcc392e2012-10-19 00:33:38 -0700[diff] [blame]1616 port_id,
1617 taiko_p->dai)) {
Venkat Sudhira41630a2012-10-27 00:57:31 -0700[diff] [blame]1618 pr_debug("%s: TX%u is used by other\n"
1619 "virtual port\n",
1620 __func__, port_id + 1);
1621 mutex_unlock(&codec->mutex);
1622 return -EINVAL;
1623 }
1624 widget->value |= 1 << port_id;
1625 list_add_tail(&core->tx_chs[port_id].list,
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]1626 &taiko_p->dai[dai_id].wcd9xxx_ch_list
Venkat Sudhira41630a2012-10-27 00:57:31 -0700[diff] [blame]1627 );
1628 } else if (!enable && (widget->value & 1 << port_id)) {
1629 widget->value &= ~(1 << port_id);
1630 list_del_init(&core->tx_chs[port_id].list);
1631 } else {
1632 if (enable)
1633 pr_debug("%s: TX%u port is used by\n"
1634 "this virtual port\n",
1635 __func__, port_id + 1);
1636 else
1637 pr_debug("%s: TX%u port is not used by\n"
1638 "this virtual port\n",
1639 __func__, port_id + 1);
1640 /* avoid update power function */
1641 mutex_unlock(&codec->mutex);
1642 return 0;
1643 }
1644 break;
1645 default:
1646 pr_err("Unknown AIF %d\n", dai_id);
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]1647 mutex_unlock(&codec->mutex);
Venkat Sudhira41630a2012-10-27 00:57:31 -0700[diff] [blame]1648 return -EINVAL;
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]1649 }
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]1650 pr_debug("%s: name %s sname %s updated value %u shift %d\n", __func__,
1651 widget->name, widget->sname, widget->value, widget->shift);
1652
1653 snd_soc_dapm_mixer_update_power(widget, kcontrol, enable);
1654
1655 mutex_unlock(&codec->mutex);
1656 return 0;
1657}
1658
1659static int slim_rx_mux_get(struct snd_kcontrol *kcontrol,
1660 struct snd_ctl_elem_value *ucontrol)
1661{
1662 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1663 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
1664
1665 ucontrol->value.enumerated.item[0] = widget->value;
1666 return 0;
1667}
1668
1669static const char *const slim_rx_mux_text[] = {
1670 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB"
1671};
1672
1673static int slim_rx_mux_put(struct snd_kcontrol *kcontrol,
1674 struct snd_ctl_elem_value *ucontrol)
1675{
1676 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1677 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
1678 struct snd_soc_codec *codec = widget->codec;
1679 struct taiko_priv *taiko_p = snd_soc_codec_get_drvdata(codec);
1680 struct wcd9xxx *core = dev_get_drvdata(codec->dev->parent);
1681 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1682 u32 port_id = widget->shift;
1683
1684 pr_debug("%s: wname %s cname %s value %u shift %d item %ld\n", __func__,
1685 widget->name, ucontrol->id.name, widget->value, widget->shift,
1686 ucontrol->value.integer.value[0]);
1687
1688 widget->value = ucontrol->value.enumerated.item[0];
1689
1690 mutex_lock(&codec->mutex);
1691
1692 if (taiko_p->intf_type != WCD9XXX_INTERFACE_TYPE_SLIMBUS) {
Venkat Sudhir994193b2012-12-17 17:30:51 -0800[diff] [blame]1693 if (widget->value > 2) {
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]1694 dev_err(codec->dev, "%s: invalid AIF for I2C mode\n",
1695 __func__);
Kuirong Wangdcc392e2012-10-19 00:33:38 -0700[diff] [blame]1696 goto err;
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]1697 }
1698 }
1699 /* value need to match the Virtual port and AIF number
1700 */
1701 switch (widget->value) {
1702 case 0:
1703 list_del_init(&core->rx_chs[port_id].list);
1704 break;
1705 case 1:
Kuirong Wangdcc392e2012-10-19 00:33:38 -0700[diff] [blame]1706 if (wcd9xxx_rx_vport_validation(port_id + core->num_tx_port,
1707 &taiko_p->dai[AIF1_PB].wcd9xxx_ch_list))
1708 goto pr_err;
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]1709 list_add_tail(&core->rx_chs[port_id].list,
1710 &taiko_p->dai[AIF1_PB].wcd9xxx_ch_list);
1711 break;
1712 case 2:
Kuirong Wangdcc392e2012-10-19 00:33:38 -0700[diff] [blame]1713 if (wcd9xxx_rx_vport_validation(port_id + core->num_tx_port,
Gopikrishnaiah Anandana8aec1f2013-01-23 14:26:27 -0500[diff] [blame]1714 &taiko_p->dai[AIF2_PB].wcd9xxx_ch_list))
Kuirong Wangdcc392e2012-10-19 00:33:38 -0700[diff] [blame]1715 goto pr_err;
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]1716 list_add_tail(&core->rx_chs[port_id].list,
1717 &taiko_p->dai[AIF2_PB].wcd9xxx_ch_list);
1718 break;
1719 case 3:
Kuirong Wangdcc392e2012-10-19 00:33:38 -0700[diff] [blame]1720 if (wcd9xxx_rx_vport_validation(port_id + core->num_tx_port,
Gopikrishnaiah Anandana8aec1f2013-01-23 14:26:27 -0500[diff] [blame]1721 &taiko_p->dai[AIF3_PB].wcd9xxx_ch_list))
Kuirong Wangdcc392e2012-10-19 00:33:38 -0700[diff] [blame]1722 goto pr_err;
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]1723 list_add_tail(&core->rx_chs[port_id].list,
1724 &taiko_p->dai[AIF3_PB].wcd9xxx_ch_list);
1725 break;
1726 default:
1727 pr_err("Unknown AIF %d\n", widget->value);
Kuirong Wangdcc392e2012-10-19 00:33:38 -0700[diff] [blame]1728 goto err;
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]1729 }
1730
1731 snd_soc_dapm_mux_update_power(widget, kcontrol, 1, widget->value, e);
1732
1733 mutex_unlock(&codec->mutex);
1734 return 0;
Kuirong Wangdcc392e2012-10-19 00:33:38 -0700[diff] [blame]1735pr_err:
1736 pr_err("%s: RX%u is used by current requesting AIF_PB itself\n",
1737 __func__, port_id + 1);
1738err:
1739 mutex_unlock(&codec->mutex);
1740 return -EINVAL;
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]1741}
1742
1743static const struct soc_enum slim_rx_mux_enum =
1744 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
1745
1746static const struct snd_kcontrol_new slim_rx_mux[TAIKO_RX_MAX] = {
1747 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
1748 slim_rx_mux_get, slim_rx_mux_put),
1749 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
1750 slim_rx_mux_get, slim_rx_mux_put),
1751 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
1752 slim_rx_mux_get, slim_rx_mux_put),
1753 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
1754 slim_rx_mux_get, slim_rx_mux_put),
1755 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
1756 slim_rx_mux_get, slim_rx_mux_put),
1757 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
1758 slim_rx_mux_get, slim_rx_mux_put),
1759 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
1760 slim_rx_mux_get, slim_rx_mux_put),
1761};
1762
1763static const struct snd_kcontrol_new aif_cap_mixer[] = {
1764 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, TAIKO_TX1, 1, 0,
1765 slim_tx_mixer_get, slim_tx_mixer_put),
1766 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, TAIKO_TX2, 1, 0,
1767 slim_tx_mixer_get, slim_tx_mixer_put),
1768 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, TAIKO_TX3, 1, 0,
1769 slim_tx_mixer_get, slim_tx_mixer_put),
1770 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, TAIKO_TX4, 1, 0,
1771 slim_tx_mixer_get, slim_tx_mixer_put),
1772 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, TAIKO_TX5, 1, 0,
1773 slim_tx_mixer_get, slim_tx_mixer_put),
1774 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, TAIKO_TX6, 1, 0,
1775 slim_tx_mixer_get, slim_tx_mixer_put),
1776 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, TAIKO_TX7, 1, 0,
1777 slim_tx_mixer_get, slim_tx_mixer_put),
1778 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, TAIKO_TX8, 1, 0,
1779 slim_tx_mixer_get, slim_tx_mixer_put),
1780 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, TAIKO_TX9, 1, 0,
1781 slim_tx_mixer_get, slim_tx_mixer_put),
1782 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, TAIKO_TX10, 1, 0,
1783 slim_tx_mixer_get, slim_tx_mixer_put),
1784};
1785
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]1786static void taiko_codec_enable_adc_block(struct snd_soc_codec *codec,
1787 int enable)
1788{
1789 struct taiko_priv *taiko = snd_soc_codec_get_drvdata(codec);
1790
1791 pr_debug("%s %d\n", __func__, enable);
1792
1793 if (enable) {
1794 taiko->adc_count++;
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]1795 snd_soc_update_bits(codec, WCD9XXX_A_CDC_CLK_OTHR_CTL,
1796 0x2, 0x2);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]1797 } else {
1798 taiko->adc_count--;
1799 if (!taiko->adc_count)
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]1800 snd_soc_update_bits(codec, WCD9XXX_A_CDC_CLK_OTHR_CTL,
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]1801 0x2, 0x0);
1802 }
1803}
1804
1805static int taiko_codec_enable_adc(struct snd_soc_dapm_widget *w,
1806 struct snd_kcontrol *kcontrol, int event)
1807{
1808 struct snd_soc_codec *codec = w->codec;
1809 u16 adc_reg;
1810 u8 init_bit_shift;
1811
1812 pr_debug("%s %d\n", __func__, event);
1813
1814 if (w->reg == TAIKO_A_TX_1_2_EN)
1815 adc_reg = TAIKO_A_TX_1_2_TEST_CTL;
1816 else if (w->reg == TAIKO_A_TX_3_4_EN)
1817 adc_reg = TAIKO_A_TX_3_4_TEST_CTL;
1818 else if (w->reg == TAIKO_A_TX_5_6_EN)
1819 adc_reg = TAIKO_A_TX_5_6_TEST_CTL;
1820 else {
1821 pr_err("%s: Error, invalid adc register\n", __func__);
1822 return -EINVAL;
1823 }
1824
1825 if (w->shift == 3)
1826 init_bit_shift = 6;
1827 else if (w->shift == 7)
1828 init_bit_shift = 7;
1829 else {
1830 pr_err("%s: Error, invalid init bit postion adc register\n",
1831 __func__);
1832 return -EINVAL;
1833 }
1834
1835 switch (event) {
1836 case SND_SOC_DAPM_PRE_PMU:
1837 taiko_codec_enable_adc_block(codec, 1);
1838 snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift,
1839 1 << init_bit_shift);
1840 break;
1841 case SND_SOC_DAPM_POST_PMU:
1842
1843 snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift, 0x00);
1844
1845 break;
1846 case SND_SOC_DAPM_POST_PMD:
1847 taiko_codec_enable_adc_block(codec, 0);
1848 break;
1849 }
1850 return 0;
1851}
1852
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]1853static int taiko_codec_enable_aux_pga(struct snd_soc_dapm_widget *w,
1854 struct snd_kcontrol *kcontrol, int event)
1855{
1856 struct snd_soc_codec *codec = w->codec;
1857 struct taiko_priv *taiko = snd_soc_codec_get_drvdata(codec);
1858
1859 pr_debug("%s: %d\n", __func__, event);
1860
1861 switch (event) {
1862 case SND_SOC_DAPM_PRE_PMU:
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]1863 WCD9XXX_BCL_LOCK(&taiko->resmgr);
1864 wcd9xxx_resmgr_get_bandgap(&taiko->resmgr,
1865 WCD9XXX_BANDGAP_AUDIO_MODE);
1866 /* AUX PGA requires RCO or MCLK */
1867 wcd9xxx_resmgr_get_clk_block(&taiko->resmgr, WCD9XXX_CLK_RCO);
1868 wcd9xxx_resmgr_enable_rx_bias(&taiko->resmgr, 1);
1869 WCD9XXX_BCL_UNLOCK(&taiko->resmgr);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]1870 break;
1871
1872 case SND_SOC_DAPM_POST_PMD:
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]1873 WCD9XXX_BCL_LOCK(&taiko->resmgr);
1874 wcd9xxx_resmgr_enable_rx_bias(&taiko->resmgr, 0);
1875 wcd9xxx_resmgr_put_bandgap(&taiko->resmgr,
1876 WCD9XXX_BANDGAP_AUDIO_MODE);
1877 wcd9xxx_resmgr_put_clk_block(&taiko->resmgr, WCD9XXX_CLK_RCO);
1878 WCD9XXX_BCL_UNLOCK(&taiko->resmgr);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]1879 break;
1880 }
1881 return 0;
1882}
1883
1884static int taiko_codec_enable_lineout(struct snd_soc_dapm_widget *w,
1885 struct snd_kcontrol *kcontrol, int event)
1886{
1887 struct snd_soc_codec *codec = w->codec;
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]1888 struct taiko_priv *taiko = snd_soc_codec_get_drvdata(codec);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]1889 u16 lineout_gain_reg;
1890
1891 pr_debug("%s %d %s\n", __func__, event, w->name);
1892
1893 switch (w->shift) {
1894 case 0:
1895 lineout_gain_reg = TAIKO_A_RX_LINE_1_GAIN;
1896 break;
1897 case 1:
1898 lineout_gain_reg = TAIKO_A_RX_LINE_2_GAIN;
1899 break;
1900 case 2:
1901 lineout_gain_reg = TAIKO_A_RX_LINE_3_GAIN;
1902 break;
1903 case 3:
1904 lineout_gain_reg = TAIKO_A_RX_LINE_4_GAIN;
1905 break;
1906 default:
1907 pr_err("%s: Error, incorrect lineout register value\n",
1908 __func__);
1909 return -EINVAL;
1910 }
1911
1912 switch (event) {
1913 case SND_SOC_DAPM_PRE_PMU:
1914 snd_soc_update_bits(codec, lineout_gain_reg, 0x40, 0x40);
1915 break;
1916 case SND_SOC_DAPM_POST_PMU:
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]1917 wcd9xxx_clsh_fsm(codec, &taiko->clsh_d,
1918 WCD9XXX_CLSH_STATE_LO,
1919 WCD9XXX_CLSH_REQ_ENABLE,
1920 WCD9XXX_CLSH_EVENT_POST_PA);
1921 pr_debug("%s: sleeping 3 ms after %s PA turn on\n",
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]1922 __func__, w->name);
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]1923 usleep_range(3000, 3000);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]1924 break;
1925 case SND_SOC_DAPM_POST_PMD:
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]1926 wcd9xxx_clsh_fsm(codec, &taiko->clsh_d,
1927 WCD9XXX_CLSH_STATE_LO,
1928 WCD9XXX_CLSH_REQ_DISABLE,
1929 WCD9XXX_CLSH_EVENT_POST_PA);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]1930 snd_soc_update_bits(codec, lineout_gain_reg, 0x40, 0x00);
1931 break;
1932 }
1933 return 0;
1934}
1935
Joonwoo Park7680b9f2012-07-13 11:36:48 -0700[diff] [blame]1936static int taiko_codec_enable_spk_pa(struct snd_soc_dapm_widget *w,
1937 struct snd_kcontrol *kcontrol, int event)
1938{
Joonwoo Park125cd4e2012-12-11 15:16:11 -0800[diff] [blame]1939 struct snd_soc_codec *codec = w->codec;
1940 struct taiko_priv *taiko = snd_soc_codec_get_drvdata(codec);
1941
1942 pr_debug("%s: %d %s\n", __func__, event, w->name);
1943 WCD9XXX_BCL_LOCK(&taiko->resmgr);
1944 switch (event) {
1945 case SND_SOC_DAPM_PRE_PMU:
1946 taiko->spkr_pa_widget_on = true;
1947 snd_soc_update_bits(codec, TAIKO_A_SPKR_DRV_EN, 0x80, 0x80);
1948 break;
1949 case SND_SOC_DAPM_POST_PMD:
1950 taiko->spkr_pa_widget_on = false;
1951 snd_soc_update_bits(codec, TAIKO_A_SPKR_DRV_EN, 0x80, 0x00);
1952 break;
1953 }
1954 WCD9XXX_BCL_UNLOCK(&taiko->resmgr);
Joonwoo Park7680b9f2012-07-13 11:36:48 -0700[diff] [blame]1955 return 0;
1956}
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]1957
1958static int taiko_codec_enable_dmic(struct snd_soc_dapm_widget *w,
1959 struct snd_kcontrol *kcontrol, int event)
1960{
1961 struct snd_soc_codec *codec = w->codec;
1962 struct taiko_priv *taiko = snd_soc_codec_get_drvdata(codec);
1963 u8 dmic_clk_en;
1964 u16 dmic_clk_reg;
1965 s32 *dmic_clk_cnt;
1966 unsigned int dmic;
1967 int ret;
1968
1969 ret = kstrtouint(strpbrk(w->name, "123456"), 10, &dmic);
1970 if (ret < 0) {
1971 pr_err("%s: Invalid DMIC line on the codec\n", __func__);
1972 return -EINVAL;
1973 }
1974
1975 switch (dmic) {
1976 case 1:
1977 case 2:
1978 dmic_clk_en = 0x01;
1979 dmic_clk_cnt = &(taiko->dmic_1_2_clk_cnt);
1980 dmic_clk_reg = TAIKO_A_CDC_CLK_DMIC_B1_CTL;
1981 pr_debug("%s() event %d DMIC%d dmic_1_2_clk_cnt %d\n",
1982 __func__, event, dmic, *dmic_clk_cnt);
1983
1984 break;
1985
1986 case 3:
1987 case 4:
1988 dmic_clk_en = 0x10;
1989 dmic_clk_cnt = &(taiko->dmic_3_4_clk_cnt);
1990 dmic_clk_reg = TAIKO_A_CDC_CLK_DMIC_B1_CTL;
1991
1992 pr_debug("%s() event %d DMIC%d dmic_3_4_clk_cnt %d\n",
1993 __func__, event, dmic, *dmic_clk_cnt);
1994 break;
1995
1996 case 5:
1997 case 6:
1998 dmic_clk_en = 0x01;
1999 dmic_clk_cnt = &(taiko->dmic_5_6_clk_cnt);
2000 dmic_clk_reg = TAIKO_A_CDC_CLK_DMIC_B2_CTL;
2001
2002 pr_debug("%s() event %d DMIC%d dmic_5_6_clk_cnt %d\n",
2003 __func__, event, dmic, *dmic_clk_cnt);
2004
2005 break;
2006
2007 default:
2008 pr_err("%s: Invalid DMIC Selection\n", __func__);
2009 return -EINVAL;
2010 }
2011
2012 switch (event) {
2013 case SND_SOC_DAPM_PRE_PMU:
2014
2015 (*dmic_clk_cnt)++;
2016 if (*dmic_clk_cnt == 1)
2017 snd_soc_update_bits(codec, dmic_clk_reg,
2018 dmic_clk_en, dmic_clk_en);
2019
2020 break;
2021 case SND_SOC_DAPM_POST_PMD:
2022
2023 (*dmic_clk_cnt)--;
2024 if (*dmic_clk_cnt == 0)
2025 snd_soc_update_bits(codec, dmic_clk_reg,
2026 dmic_clk_en, 0);
2027 break;
2028 }
2029 return 0;
2030}
2031
2032static int taiko_codec_enable_anc(struct snd_soc_dapm_widget *w,
2033 struct snd_kcontrol *kcontrol, int event)
2034{
2035 struct snd_soc_codec *codec = w->codec;
2036 const char *filename;
2037 const struct firmware *fw;
2038 int i;
2039 int ret;
2040 int num_anc_slots;
2041 struct anc_header *anc_head;
2042 struct taiko_priv *taiko = snd_soc_codec_get_drvdata(codec);
2043 u32 anc_writes_size = 0;
2044 int anc_size_remaining;
2045 u32 *anc_ptr;
2046 u16 reg;
Kiran Kandi1b2d1ef2012-10-23 15:29:00 -0700[diff] [blame]2047 u8 mask, val;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2048
2049 pr_debug("%s %d\n", __func__, event);
2050 switch (event) {
2051 case SND_SOC_DAPM_PRE_PMU:
2052
2053 filename = "wcd9320/wcd9320_anc.bin";
2054
2055 ret = request_firmware(&fw, filename, codec->dev);
2056 if (ret != 0) {
2057 dev_err(codec->dev, "Failed to acquire ANC data: %d\n",
2058 ret);
2059 return -ENODEV;
2060 }
2061
2062 if (fw->size < sizeof(struct anc_header)) {
2063 dev_err(codec->dev, "Not enough data\n");
2064 release_firmware(fw);
2065 return -ENOMEM;
2066 }
2067
2068 /* First number is the number of register writes */
2069 anc_head = (struct anc_header *)(fw->data);
2070 anc_ptr = (u32 *)((u32)fw->data + sizeof(struct anc_header));
2071 anc_size_remaining = fw->size - sizeof(struct anc_header);
2072 num_anc_slots = anc_head->num_anc_slots;
2073
2074 if (taiko->anc_slot >= num_anc_slots) {
2075 dev_err(codec->dev, "Invalid ANC slot selected\n");
2076 release_firmware(fw);
2077 return -EINVAL;
2078 }
2079
2080 for (i = 0; i < num_anc_slots; i++) {
2081
2082 if (anc_size_remaining < TAIKO_PACKED_REG_SIZE) {
2083 dev_err(codec->dev, "Invalid register format\n");
2084 release_firmware(fw);
2085 return -EINVAL;
2086 }
2087 anc_writes_size = (u32)(*anc_ptr);
2088 anc_size_remaining -= sizeof(u32);
2089 anc_ptr += 1;
2090
2091 if (anc_writes_size * TAIKO_PACKED_REG_SIZE
2092 > anc_size_remaining) {
2093 dev_err(codec->dev, "Invalid register format\n");
2094 release_firmware(fw);
2095 return -ENOMEM;
2096 }
2097
2098 if (taiko->anc_slot == i)
2099 break;
2100
2101 anc_size_remaining -= (anc_writes_size *
2102 TAIKO_PACKED_REG_SIZE);
2103 anc_ptr += anc_writes_size;
2104 }
2105 if (i == num_anc_slots) {
2106 dev_err(codec->dev, "Selected ANC slot not present\n");
2107 release_firmware(fw);
2108 return -ENOMEM;
2109 }
2110
2111 for (i = 0; i < anc_writes_size; i++) {
2112 TAIKO_CODEC_UNPACK_ENTRY(anc_ptr[i], reg,
2113 mask, val);
Kiran Kandi1b2d1ef2012-10-23 15:29:00 -0700[diff] [blame]2114 snd_soc_write(codec, reg, val);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2115 }
2116 release_firmware(fw);
2117
2118 break;
2119 case SND_SOC_DAPM_POST_PMD:
2120 snd_soc_write(codec, TAIKO_A_CDC_CLK_ANC_RESET_CTL, 0xFF);
2121 snd_soc_write(codec, TAIKO_A_CDC_CLK_ANC_CLK_EN_CTL, 0);
2122 break;
2123 }
2124 return 0;
2125}
2126
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2127static int taiko_codec_enable_micbias(struct snd_soc_dapm_widget *w,
2128 struct snd_kcontrol *kcontrol, int event)
2129{
2130 struct snd_soc_codec *codec = w->codec;
2131 struct taiko_priv *taiko = snd_soc_codec_get_drvdata(codec);
Joonwoo Park3699ca32013-02-08 12:06:15 -0800[diff] [blame]2132 u16 micb_int_reg = 0, micb_ctl_reg = 0;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2133 u8 cfilt_sel_val = 0;
2134 char *internal1_text = "Internal1";
2135 char *internal2_text = "Internal2";
2136 char *internal3_text = "Internal3";
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]2137 enum wcd9xxx_notify_event e_post_off, e_pre_on, e_post_on;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2138
Joonwoo Park3699ca32013-02-08 12:06:15 -0800[diff] [blame]2139 pr_debug("%s: w->name %s event %d\n", __func__, w->name, event);
2140 if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1"))) {
2141 micb_ctl_reg = TAIKO_A_MICB_1_CTL;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2142 micb_int_reg = TAIKO_A_MICB_1_INT_RBIAS;
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]2143 cfilt_sel_val = taiko->resmgr.pdata->micbias.bias1_cfilt_sel;
2144 e_pre_on = WCD9XXX_EVENT_PRE_MICBIAS_1_ON;
2145 e_post_on = WCD9XXX_EVENT_POST_MICBIAS_1_ON;
2146 e_post_off = WCD9XXX_EVENT_POST_MICBIAS_1_OFF;
Joonwoo Park3699ca32013-02-08 12:06:15 -0800[diff] [blame]2147 } else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2"))) {
2148 micb_ctl_reg = TAIKO_A_MICB_2_CTL;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2149 micb_int_reg = TAIKO_A_MICB_2_INT_RBIAS;
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]2150 cfilt_sel_val = taiko->resmgr.pdata->micbias.bias2_cfilt_sel;
2151 e_pre_on = WCD9XXX_EVENT_PRE_MICBIAS_2_ON;
2152 e_post_on = WCD9XXX_EVENT_POST_MICBIAS_2_ON;
2153 e_post_off = WCD9XXX_EVENT_POST_MICBIAS_2_OFF;
Joonwoo Park3699ca32013-02-08 12:06:15 -0800[diff] [blame]2154 } else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3"))) {
2155 micb_ctl_reg = TAIKO_A_MICB_2_CTL;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2156 micb_int_reg = TAIKO_A_MICB_3_INT_RBIAS;
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]2157 cfilt_sel_val = taiko->resmgr.pdata->micbias.bias3_cfilt_sel;
2158 e_pre_on = WCD9XXX_EVENT_PRE_MICBIAS_3_ON;
2159 e_post_on = WCD9XXX_EVENT_POST_MICBIAS_3_ON;
2160 e_post_off = WCD9XXX_EVENT_POST_MICBIAS_3_OFF;
Joonwoo Park3699ca32013-02-08 12:06:15 -0800[diff] [blame]2161 } else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4"))) {
2162 micb_ctl_reg = TAIKO_A_MICB_2_CTL;
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]2163 micb_int_reg = taiko->resmgr.reg_addr->micb_4_int_rbias;
2164 cfilt_sel_val = taiko->resmgr.pdata->micbias.bias4_cfilt_sel;
2165 e_pre_on = WCD9XXX_EVENT_PRE_MICBIAS_4_ON;
2166 e_post_on = WCD9XXX_EVENT_POST_MICBIAS_4_ON;
2167 e_post_off = WCD9XXX_EVENT_POST_MICBIAS_4_OFF;
Joonwoo Park3699ca32013-02-08 12:06:15 -0800[diff] [blame]2168 } else {
2169 pr_err("%s: Error, invalid micbias %s\n", __func__, w->name);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2170 return -EINVAL;
2171 }
2172
2173 switch (event) {
2174 case SND_SOC_DAPM_PRE_PMU:
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]2175 /* Let MBHC module know so micbias switch to be off */
2176 wcd9xxx_resmgr_notifier_call(&taiko->resmgr, e_pre_on);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2177
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]2178 /* Get cfilt */
2179 wcd9xxx_resmgr_cfilt_get(&taiko->resmgr, cfilt_sel_val);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2180
2181 if (strnstr(w->name, internal1_text, 30))
2182 snd_soc_update_bits(codec, micb_int_reg, 0xE0, 0xE0);
2183 else if (strnstr(w->name, internal2_text, 30))
2184 snd_soc_update_bits(codec, micb_int_reg, 0x1C, 0x1C);
2185 else if (strnstr(w->name, internal3_text, 30))
2186 snd_soc_update_bits(codec, micb_int_reg, 0x3, 0x3);
2187
Joonwoo Park3699ca32013-02-08 12:06:15 -0800[diff] [blame]2188 if (micb_ctl_reg == TAIKO_A_MICB_2_CTL) {
2189 WCD9XXX_BCL_LOCK(&taiko->resmgr);
2190 wcd9xxx_resmgr_add_cond_update_bits(&taiko->resmgr,
2191 WCD9XXX_COND_HPH_MIC,
2192 micb_ctl_reg, w->shift,
2193 false);
2194 WCD9XXX_BCL_UNLOCK(&taiko->resmgr);
2195 } else
2196 snd_soc_update_bits(codec, micb_ctl_reg, 1 << w->shift,
2197 1 << w->shift);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2198 break;
2199 case SND_SOC_DAPM_POST_PMU:
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2200 usleep_range(20000, 20000);
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]2201 /* Let MBHC module know so micbias is on */
2202 wcd9xxx_resmgr_notifier_call(&taiko->resmgr, e_post_on);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2203 break;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2204 case SND_SOC_DAPM_POST_PMD:
Joonwoo Park3699ca32013-02-08 12:06:15 -0800[diff] [blame]2205 if (micb_ctl_reg == TAIKO_A_MICB_2_CTL) {
2206 WCD9XXX_BCL_LOCK(&taiko->resmgr);
2207 wcd9xxx_resmgr_rm_cond_update_bits(&taiko->resmgr,
2208 WCD9XXX_COND_HPH_MIC,
2209 micb_ctl_reg, 7, false);
2210 WCD9XXX_BCL_UNLOCK(&taiko->resmgr);
2211 } else
2212 snd_soc_update_bits(codec, micb_ctl_reg, 1 << w->shift,
2213 0);
2214
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]2215 /* Let MBHC module know so micbias switch to be off */
2216 wcd9xxx_resmgr_notifier_call(&taiko->resmgr, e_post_off);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2217
2218 if (strnstr(w->name, internal1_text, 30))
2219 snd_soc_update_bits(codec, micb_int_reg, 0x80, 0x00);
2220 else if (strnstr(w->name, internal2_text, 30))
2221 snd_soc_update_bits(codec, micb_int_reg, 0x10, 0x00);
2222 else if (strnstr(w->name, internal3_text, 30))
2223 snd_soc_update_bits(codec, micb_int_reg, 0x2, 0x0);
2224
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]2225 /* Put cfilt */
2226 wcd9xxx_resmgr_cfilt_put(&taiko->resmgr, cfilt_sel_val);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2227 break;
2228 }
2229
2230 return 0;
2231}
2232
2233
2234static void tx_hpf_corner_freq_callback(struct work_struct *work)
2235{
2236 struct delayed_work *hpf_delayed_work;
2237 struct hpf_work *hpf_work;
2238 struct taiko_priv *taiko;
2239 struct snd_soc_codec *codec;
2240 u16 tx_mux_ctl_reg;
2241 u8 hpf_cut_of_freq;
2242
2243 hpf_delayed_work = to_delayed_work(work);
2244 hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork);
2245 taiko = hpf_work->taiko;
2246 codec = hpf_work->taiko->codec;
2247 hpf_cut_of_freq = hpf_work->tx_hpf_cut_of_freq;
2248
2249 tx_mux_ctl_reg = TAIKO_A_CDC_TX1_MUX_CTL +
2250 (hpf_work->decimator - 1) * 8;
2251
2252 pr_debug("%s(): decimator %u hpf_cut_of_freq 0x%x\n", __func__,
2253 hpf_work->decimator, (unsigned int)hpf_cut_of_freq);
2254
2255 snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x30, hpf_cut_of_freq << 4);
2256}
2257
2258#define TX_MUX_CTL_CUT_OFF_FREQ_MASK 0x30
2259#define CF_MIN_3DB_4HZ 0x0
2260#define CF_MIN_3DB_75HZ 0x1
2261#define CF_MIN_3DB_150HZ 0x2
2262
2263static int taiko_codec_enable_dec(struct snd_soc_dapm_widget *w,
2264 struct snd_kcontrol *kcontrol, int event)
2265{
2266 struct snd_soc_codec *codec = w->codec;
2267 unsigned int decimator;
2268 char *dec_name = NULL;
2269 char *widget_name = NULL;
2270 char *temp;
2271 int ret = 0;
2272 u16 dec_reset_reg, tx_vol_ctl_reg, tx_mux_ctl_reg;
2273 u8 dec_hpf_cut_of_freq;
2274 int offset;
2275
2276
2277 pr_debug("%s %d\n", __func__, event);
2278
2279 widget_name = kstrndup(w->name, 15, GFP_KERNEL);
2280 if (!widget_name)
2281 return -ENOMEM;
2282 temp = widget_name;
2283
2284 dec_name = strsep(&widget_name, " ");
2285 widget_name = temp;
2286 if (!dec_name) {
2287 pr_err("%s: Invalid decimator = %s\n", __func__, w->name);
2288 ret = -EINVAL;
2289 goto out;
2290 }
2291
2292 ret = kstrtouint(strpbrk(dec_name, "123456789"), 10, &decimator);
2293 if (ret < 0) {
2294 pr_err("%s: Invalid decimator = %s\n", __func__, dec_name);
2295 ret = -EINVAL;
2296 goto out;
2297 }
2298
2299 pr_debug("%s(): widget = %s dec_name = %s decimator = %u\n", __func__,
2300 w->name, dec_name, decimator);
2301
2302 if (w->reg == TAIKO_A_CDC_CLK_TX_CLK_EN_B1_CTL) {
2303 dec_reset_reg = TAIKO_A_CDC_CLK_TX_RESET_B1_CTL;
2304 offset = 0;
2305 } else if (w->reg == TAIKO_A_CDC_CLK_TX_CLK_EN_B2_CTL) {
2306 dec_reset_reg = TAIKO_A_CDC_CLK_TX_RESET_B2_CTL;
2307 offset = 8;
2308 } else {
2309 pr_err("%s: Error, incorrect dec\n", __func__);
2310 return -EINVAL;
2311 }
2312
2313 tx_vol_ctl_reg = TAIKO_A_CDC_TX1_VOL_CTL_CFG + 8 * (decimator - 1);
2314 tx_mux_ctl_reg = TAIKO_A_CDC_TX1_MUX_CTL + 8 * (decimator - 1);
2315
2316 switch (event) {
2317 case SND_SOC_DAPM_PRE_PMU:
2318
2319 /* Enableable TX digital mute */
2320 snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x01);
2321
2322 snd_soc_update_bits(codec, dec_reset_reg, 1 << w->shift,
2323 1 << w->shift);
2324 snd_soc_update_bits(codec, dec_reset_reg, 1 << w->shift, 0x0);
2325
2326 dec_hpf_cut_of_freq = snd_soc_read(codec, tx_mux_ctl_reg);
2327
2328 dec_hpf_cut_of_freq = (dec_hpf_cut_of_freq & 0x30) >> 4;
2329
2330 tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq =
2331 dec_hpf_cut_of_freq;
2332
2333 if ((dec_hpf_cut_of_freq != CF_MIN_3DB_150HZ)) {
2334
2335 /* set cut of freq to CF_MIN_3DB_150HZ (0x1); */
2336 snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x30,
2337 CF_MIN_3DB_150HZ << 4);
2338 }
2339
2340 /* enable HPF */
2341 snd_soc_update_bits(codec, tx_mux_ctl_reg , 0x08, 0x00);
2342
2343 break;
2344
2345 case SND_SOC_DAPM_POST_PMU:
2346
2347 /* Disable TX digital mute */
2348 snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x00);
2349
2350 if (tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq !=
2351 CF_MIN_3DB_150HZ) {
2352
2353 schedule_delayed_work(&tx_hpf_work[decimator - 1].dwork,
2354 msecs_to_jiffies(300));
2355 }
2356 /* apply the digital gain after the decimator is enabled*/
Damir Didjustoed406e22012-11-16 15:44:57 -0800[diff] [blame]2357 if ((w->shift + offset) < ARRAY_SIZE(tx_digital_gain_reg))
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2358 snd_soc_write(codec,
2359 tx_digital_gain_reg[w->shift + offset],
2360 snd_soc_read(codec,
2361 tx_digital_gain_reg[w->shift + offset])
2362 );
2363
2364 break;
2365
2366 case SND_SOC_DAPM_PRE_PMD:
2367
2368 snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x01);
2369 cancel_delayed_work_sync(&tx_hpf_work[decimator - 1].dwork);
2370 break;
2371
2372 case SND_SOC_DAPM_POST_PMD:
2373
2374 snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x08, 0x08);
2375 snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x30,
2376 (tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq) << 4);
2377
2378 break;
2379 }
2380out:
2381 kfree(widget_name);
2382 return ret;
2383}
2384
Joonwoo Park125cd4e2012-12-11 15:16:11 -0800[diff] [blame]2385static int taiko_codec_enable_vdd_spkr(struct snd_soc_dapm_widget *w,
2386 struct snd_kcontrol *kcontrol, int event)
2387{
2388 int ret = 0;
2389 struct snd_soc_codec *codec = w->codec;
2390 struct wcd9xxx *core = dev_get_drvdata(codec->dev->parent);
2391
2392 pr_debug("%s: %d %s\n", __func__, event, w->name);
2393 switch (event) {
2394 case SND_SOC_DAPM_PRE_PMU:
2395 if (spkr_drv_wrnd > 0) {
2396 WARN_ON(!(snd_soc_read(codec, TAIKO_A_SPKR_DRV_EN) &
2397 0x80));
2398 snd_soc_update_bits(codec, TAIKO_A_SPKR_DRV_EN, 0x80,
2399 0x00);
2400 }
2401 if (TAIKO_IS_1_0(core->version))
2402 snd_soc_update_bits(codec, TAIKO_A_SPKR_DRV_DBG_PWRSTG,
2403 0x24, 0x00);
2404 break;
2405 case SND_SOC_DAPM_POST_PMD:
2406 if (TAIKO_IS_1_0(core->version))
2407 snd_soc_update_bits(codec, TAIKO_A_SPKR_DRV_DBG_PWRSTG,
2408 0x24, 0x24);
2409 if (spkr_drv_wrnd > 0) {
2410 WARN_ON(!!(snd_soc_read(codec, TAIKO_A_SPKR_DRV_EN) &
2411 0x80));
2412 snd_soc_update_bits(codec, TAIKO_A_SPKR_DRV_EN, 0x80,
2413 0x80);
2414 }
2415 break;
2416 }
2417
2418 return ret;
2419}
2420
Kiran Kandi7b7d2ff2012-09-14 14:52:14 -0700[diff] [blame]2421static int taiko_codec_enable_interpolator(struct snd_soc_dapm_widget *w,
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2422 struct snd_kcontrol *kcontrol, int event)
2423{
2424 struct snd_soc_codec *codec = w->codec;
2425
2426 pr_debug("%s %d %s\n", __func__, event, w->name);
2427
2428 switch (event) {
2429 case SND_SOC_DAPM_PRE_PMU:
2430 snd_soc_update_bits(codec, TAIKO_A_CDC_CLK_RX_RESET_CTL,
2431 1 << w->shift, 1 << w->shift);
2432 snd_soc_update_bits(codec, TAIKO_A_CDC_CLK_RX_RESET_CTL,
2433 1 << w->shift, 0x0);
2434 break;
2435 case SND_SOC_DAPM_POST_PMU:
2436 /* apply the digital gain after the interpolator is enabled*/
2437 if ((w->shift) < ARRAY_SIZE(rx_digital_gain_reg))
2438 snd_soc_write(codec,
2439 rx_digital_gain_reg[w->shift],
2440 snd_soc_read(codec,
2441 rx_digital_gain_reg[w->shift])
2442 );
2443 break;
2444 }
2445 return 0;
2446}
2447
2448static int taiko_codec_enable_ldo_h(struct snd_soc_dapm_widget *w,
2449 struct snd_kcontrol *kcontrol, int event)
2450{
2451 switch (event) {
2452 case SND_SOC_DAPM_POST_PMU:
2453 case SND_SOC_DAPM_POST_PMD:
2454 usleep_range(1000, 1000);
2455 break;
2456 }
2457 return 0;
2458}
2459
2460static int taiko_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
2461 struct snd_kcontrol *kcontrol, int event)
2462{
2463 struct snd_soc_codec *codec = w->codec;
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]2464 struct taiko_priv *taiko = snd_soc_codec_get_drvdata(codec);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2465
2466 pr_debug("%s %d\n", __func__, event);
2467
2468 switch (event) {
2469 case SND_SOC_DAPM_PRE_PMU:
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]2470 wcd9xxx_resmgr_enable_rx_bias(&taiko->resmgr, 1);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2471 break;
2472 case SND_SOC_DAPM_POST_PMD:
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]2473 wcd9xxx_resmgr_enable_rx_bias(&taiko->resmgr, 0);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2474 break;
2475 }
2476 return 0;
2477}
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]2478
2479static int taiko_hphl_dac_event(struct snd_soc_dapm_widget *w,
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2480 struct snd_kcontrol *kcontrol, int event)
2481{
2482 struct snd_soc_codec *codec = w->codec;
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]2483 struct taiko_priv *taiko_p = snd_soc_codec_get_drvdata(codec);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2484
2485 pr_debug("%s %s %d\n", __func__, w->name, event);
2486
2487 switch (event) {
2488 case SND_SOC_DAPM_PRE_PMU:
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]2489 snd_soc_update_bits(codec, TAIKO_A_CDC_CLK_RDAC_CLK_EN_CTL,
2490 0x02, 0x02);
2491 wcd9xxx_clsh_fsm(codec, &taiko_p->clsh_d,
2492 WCD9XXX_CLSH_STATE_HPHL,
2493 WCD9XXX_CLSH_REQ_ENABLE,
2494 WCD9XXX_CLSH_EVENT_PRE_DAC);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2495 break;
2496 case SND_SOC_DAPM_POST_PMD:
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]2497 snd_soc_update_bits(codec, TAIKO_A_CDC_CLK_RDAC_CLK_EN_CTL,
2498 0x02, 0x00);
2499 }
2500 return 0;
2501}
2502
2503static int taiko_hphr_dac_event(struct snd_soc_dapm_widget *w,
2504 struct snd_kcontrol *kcontrol, int event)
2505{
2506 struct snd_soc_codec *codec = w->codec;
2507 struct taiko_priv *taiko_p = snd_soc_codec_get_drvdata(codec);
2508
2509 pr_debug("%s %s %d\n", __func__, w->name, event);
2510
2511 switch (event) {
2512 case SND_SOC_DAPM_PRE_PMU:
2513 snd_soc_update_bits(codec, TAIKO_A_CDC_CLK_RDAC_CLK_EN_CTL,
2514 0x04, 0x04);
2515 snd_soc_update_bits(codec, w->reg, 0x40, 0x40);
2516 wcd9xxx_clsh_fsm(codec, &taiko_p->clsh_d,
2517 WCD9XXX_CLSH_STATE_HPHR,
2518 WCD9XXX_CLSH_REQ_ENABLE,
2519 WCD9XXX_CLSH_EVENT_PRE_DAC);
2520 break;
2521 case SND_SOC_DAPM_POST_PMD:
2522 snd_soc_update_bits(codec, TAIKO_A_CDC_CLK_RDAC_CLK_EN_CTL,
2523 0x04, 0x00);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2524 snd_soc_update_bits(codec, w->reg, 0x40, 0x00);
2525 break;
2526 }
2527 return 0;
2528}
2529
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2530static int taiko_hph_pa_event(struct snd_soc_dapm_widget *w,
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]2531 struct snd_kcontrol *kcontrol, int event)
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2532{
2533 struct snd_soc_codec *codec = w->codec;
2534 struct taiko_priv *taiko = snd_soc_codec_get_drvdata(codec);
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]2535 enum wcd9xxx_notify_event e_pre_on, e_post_off;
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]2536 u8 req_clsh_state;
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]2537
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]2538 pr_debug("%s: %s event = %d\n", __func__, w->name, event);
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]2539 if (w->shift == 5) {
2540 e_pre_on = WCD9XXX_EVENT_PRE_HPHR_PA_ON;
2541 e_post_off = WCD9XXX_EVENT_POST_HPHR_PA_OFF;
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]2542 req_clsh_state = WCD9XXX_CLSH_STATE_HPHL;
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]2543 } else if (w->shift == 4) {
2544 e_pre_on = WCD9XXX_EVENT_PRE_HPHL_PA_ON;
2545 e_post_off = WCD9XXX_EVENT_POST_HPHL_PA_OFF;
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]2546 req_clsh_state = WCD9XXX_CLSH_STATE_HPHR;
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]2547 } else {
2548 pr_err("%s: Invalid w->shift %d\n", __func__, w->shift);
2549 return -EINVAL;
2550 }
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2551
2552 switch (event) {
2553 case SND_SOC_DAPM_PRE_PMU:
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]2554 /* Let MBHC module know PA is turning on */
2555 wcd9xxx_resmgr_notifier_call(&taiko->resmgr, e_pre_on);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2556 break;
2557
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]2558 case SND_SOC_DAPM_POST_PMU:
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]2559 wcd9xxx_clsh_fsm(codec, &taiko->clsh_d,
2560 req_clsh_state,
2561 WCD9XXX_CLSH_REQ_ENABLE,
2562 WCD9XXX_CLSH_EVENT_POST_PA);
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]2563
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]2564
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]2565 usleep_range(5000, 5000);
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]2566 break;
2567
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2568 case SND_SOC_DAPM_POST_PMD:
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]2569 /* Let MBHC module know PA turned off */
2570 wcd9xxx_resmgr_notifier_call(&taiko->resmgr, e_post_off);
2571
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]2572 wcd9xxx_clsh_fsm(codec, &taiko->clsh_d,
2573 req_clsh_state,
2574 WCD9XXX_CLSH_REQ_DISABLE,
2575 WCD9XXX_CLSH_EVENT_POST_PA);
2576
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2577 pr_debug("%s: sleep 10 ms after %s PA disable.\n", __func__,
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]2578 w->name);
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]2579 usleep_range(5000, 5000);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2580 break;
2581 }
2582 return 0;
2583}
2584
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2585static const struct snd_soc_dapm_widget taiko_dapm_i2s_widgets[] = {
2586 SND_SOC_DAPM_SUPPLY("RX_I2S_CLK", TAIKO_A_CDC_CLK_RX_I2S_CTL,
2587 4, 0, NULL, 0),
2588 SND_SOC_DAPM_SUPPLY("TX_I2S_CLK", TAIKO_A_CDC_CLK_TX_I2S_CTL, 4,
2589 0, NULL, 0),
2590};
2591
2592static int taiko_lineout_dac_event(struct snd_soc_dapm_widget *w,
2593 struct snd_kcontrol *kcontrol, int event)
2594{
2595 struct snd_soc_codec *codec = w->codec;
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]2596 struct taiko_priv *taiko = snd_soc_codec_get_drvdata(codec);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2597
2598 pr_debug("%s %s %d\n", __func__, w->name, event);
2599
2600 switch (event) {
2601 case SND_SOC_DAPM_PRE_PMU:
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]2602 wcd9xxx_clsh_fsm(codec, &taiko->clsh_d,
2603 WCD9XXX_CLSH_STATE_LO,
2604 WCD9XXX_CLSH_REQ_ENABLE,
2605 WCD9XXX_CLSH_EVENT_PRE_DAC);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2606 snd_soc_update_bits(codec, w->reg, 0x40, 0x40);
2607 break;
2608
2609 case SND_SOC_DAPM_POST_PMD:
2610 snd_soc_update_bits(codec, w->reg, 0x40, 0x00);
2611 break;
2612 }
2613 return 0;
2614}
2615
Joonwoo Park7680b9f2012-07-13 11:36:48 -0700[diff] [blame]2616static int taiko_spk_dac_event(struct snd_soc_dapm_widget *w,
2617 struct snd_kcontrol *kcontrol, int event)
2618{
2619 pr_debug("%s %s %d\n", __func__, w->name, event);
2620 return 0;
2621}
2622
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2623static const struct snd_soc_dapm_route audio_i2s_map[] = {
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2624 {"SLIM RX1", NULL, "RX_I2S_CLK"},
2625 {"SLIM RX2", NULL, "RX_I2S_CLK"},
2626 {"SLIM RX3", NULL, "RX_I2S_CLK"},
2627 {"SLIM RX4", NULL, "RX_I2S_CLK"},
2628
Venkat Sudhira41630a2012-10-27 00:57:31 -0700[diff] [blame]2629 {"SLIM TX7 MUX", NULL, "TX_I2S_CLK"},
2630 {"SLIM TX8 MUX", NULL, "TX_I2S_CLK"},
2631 {"SLIM TX9 MUX", NULL, "TX_I2S_CLK"},
2632 {"SLIM TX10 MUX", NULL, "TX_I2S_CLK"},
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2633};
2634
Joonwoo Park559a5bf2013-02-15 14:46:36 -0800[diff] [blame]2635static const struct snd_soc_dapm_route audio_i2s_map_1_0[] = {
2636 {"RX_I2S_CLK", NULL, "CDC_CONN"},
2637};
2638
2639static const struct snd_soc_dapm_route audio_i2s_map_2_0[] = {
2640 {"RX_I2S_CLK", NULL, "CDC_I2S_RX_CONN"},
2641};
2642
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2643static const struct snd_soc_dapm_route audio_map[] = {
2644 /* SLIMBUS Connections */
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]2645 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
2646 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
2647 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2648
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]2649 /* SLIM_MIXER("AIF1_CAP Mixer"),*/
2650 {"AIF1_CAP Mixer", "SLIM TX1", "SLIM TX1 MUX"},
2651 {"AIF1_CAP Mixer", "SLIM TX2", "SLIM TX2 MUX"},
2652 {"AIF1_CAP Mixer", "SLIM TX3", "SLIM TX3 MUX"},
2653 {"AIF1_CAP Mixer", "SLIM TX4", "SLIM TX4 MUX"},
2654 {"AIF1_CAP Mixer", "SLIM TX5", "SLIM TX5 MUX"},
2655 {"AIF1_CAP Mixer", "SLIM TX6", "SLIM TX6 MUX"},
2656 {"AIF1_CAP Mixer", "SLIM TX7", "SLIM TX7 MUX"},
2657 {"AIF1_CAP Mixer", "SLIM TX8", "SLIM TX8 MUX"},
2658 {"AIF1_CAP Mixer", "SLIM TX9", "SLIM TX9 MUX"},
2659 {"AIF1_CAP Mixer", "SLIM TX10", "SLIM TX10 MUX"},
2660 /* SLIM_MIXER("AIF2_CAP Mixer"),*/
2661 {"AIF2_CAP Mixer", "SLIM TX1", "SLIM TX1 MUX"},
2662 {"AIF2_CAP Mixer", "SLIM TX2", "SLIM TX2 MUX"},
2663 {"AIF2_CAP Mixer", "SLIM TX3", "SLIM TX3 MUX"},
2664 {"AIF2_CAP Mixer", "SLIM TX4", "SLIM TX4 MUX"},
2665 {"AIF2_CAP Mixer", "SLIM TX5", "SLIM TX5 MUX"},
2666 {"AIF2_CAP Mixer", "SLIM TX6", "SLIM TX6 MUX"},
2667 {"AIF2_CAP Mixer", "SLIM TX7", "SLIM TX7 MUX"},
2668 {"AIF2_CAP Mixer", "SLIM TX8", "SLIM TX8 MUX"},
2669 {"AIF2_CAP Mixer", "SLIM TX9", "SLIM TX9 MUX"},
2670 {"AIF2_CAP Mixer", "SLIM TX10", "SLIM TX10 MUX"},
2671 /* SLIM_MIXER("AIF3_CAP Mixer"),*/
2672 {"AIF3_CAP Mixer", "SLIM TX1", "SLIM TX1 MUX"},
2673 {"AIF3_CAP Mixer", "SLIM TX2", "SLIM TX2 MUX"},
2674 {"AIF3_CAP Mixer", "SLIM TX3", "SLIM TX3 MUX"},
2675 {"AIF3_CAP Mixer", "SLIM TX4", "SLIM TX4 MUX"},
2676 {"AIF3_CAP Mixer", "SLIM TX5", "SLIM TX5 MUX"},
2677 {"AIF3_CAP Mixer", "SLIM TX6", "SLIM TX6 MUX"},
2678 {"AIF3_CAP Mixer", "SLIM TX7", "SLIM TX7 MUX"},
2679 {"AIF3_CAP Mixer", "SLIM TX8", "SLIM TX8 MUX"},
2680 {"AIF3_CAP Mixer", "SLIM TX9", "SLIM TX9 MUX"},
2681 {"AIF3_CAP Mixer", "SLIM TX10", "SLIM TX10 MUX"},
2682
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2683 {"SLIM TX1 MUX", "DEC1", "DEC1 MUX"},
2684
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2685 {"SLIM TX2 MUX", "DEC2", "DEC2 MUX"},
2686
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2687 {"SLIM TX3 MUX", "DEC3", "DEC3 MUX"},
2688 {"SLIM TX3 MUX", "RMIX1", "RX1 MIX1"},
2689 {"SLIM TX3 MUX", "RMIX2", "RX2 MIX1"},
2690 {"SLIM TX3 MUX", "RMIX3", "RX3 MIX1"},
2691 {"SLIM TX3 MUX", "RMIX4", "RX4 MIX1"},
2692 {"SLIM TX3 MUX", "RMIX5", "RX5 MIX1"},
2693 {"SLIM TX3 MUX", "RMIX6", "RX6 MIX1"},
2694 {"SLIM TX3 MUX", "RMIX7", "RX7 MIX1"},
2695
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2696 {"SLIM TX4 MUX", "DEC4", "DEC4 MUX"},
2697
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2698 {"SLIM TX5 MUX", "DEC5", "DEC5 MUX"},
2699 {"SLIM TX5 MUX", "RMIX1", "RX1 MIX1"},
2700 {"SLIM TX5 MUX", "RMIX2", "RX2 MIX1"},
2701 {"SLIM TX5 MUX", "RMIX3", "RX3 MIX1"},
2702 {"SLIM TX5 MUX", "RMIX4", "RX4 MIX1"},
2703 {"SLIM TX5 MUX", "RMIX5", "RX5 MIX1"},
2704 {"SLIM TX5 MUX", "RMIX6", "RX6 MIX1"},
2705 {"SLIM TX5 MUX", "RMIX7", "RX7 MIX1"},
2706
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2707 {"SLIM TX6 MUX", "DEC6", "DEC6 MUX"},
2708
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2709 {"SLIM TX7 MUX", "DEC1", "DEC1 MUX"},
2710 {"SLIM TX7 MUX", "DEC2", "DEC2 MUX"},
2711 {"SLIM TX7 MUX", "DEC3", "DEC3 MUX"},
2712 {"SLIM TX7 MUX", "DEC4", "DEC4 MUX"},
2713 {"SLIM TX7 MUX", "DEC5", "DEC5 MUX"},
2714 {"SLIM TX7 MUX", "DEC6", "DEC6 MUX"},
2715 {"SLIM TX7 MUX", "DEC7", "DEC7 MUX"},
2716 {"SLIM TX7 MUX", "DEC8", "DEC8 MUX"},
2717 {"SLIM TX7 MUX", "DEC9", "DEC9 MUX"},
2718 {"SLIM TX7 MUX", "DEC10", "DEC10 MUX"},
2719 {"SLIM TX7 MUX", "RMIX1", "RX1 MIX1"},
2720 {"SLIM TX7 MUX", "RMIX2", "RX2 MIX1"},
2721 {"SLIM TX7 MUX", "RMIX3", "RX3 MIX1"},
2722 {"SLIM TX7 MUX", "RMIX4", "RX4 MIX1"},
2723 {"SLIM TX7 MUX", "RMIX5", "RX5 MIX1"},
2724 {"SLIM TX7 MUX", "RMIX6", "RX6 MIX1"},
2725 {"SLIM TX7 MUX", "RMIX7", "RX7 MIX1"},
2726
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2727 {"SLIM TX8 MUX", "DEC1", "DEC1 MUX"},
2728 {"SLIM TX8 MUX", "DEC2", "DEC2 MUX"},
2729 {"SLIM TX8 MUX", "DEC3", "DEC3 MUX"},
2730 {"SLIM TX8 MUX", "DEC4", "DEC4 MUX"},
2731 {"SLIM TX8 MUX", "DEC5", "DEC5 MUX"},
2732 {"SLIM TX8 MUX", "DEC6", "DEC6 MUX"},
2733 {"SLIM TX8 MUX", "DEC7", "DEC7 MUX"},
2734 {"SLIM TX8 MUX", "DEC8", "DEC8 MUX"},
2735 {"SLIM TX8 MUX", "DEC9", "DEC9 MUX"},
2736 {"SLIM TX8 MUX", "DEC10", "DEC10 MUX"},
2737
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2738 {"SLIM TX9 MUX", "DEC1", "DEC1 MUX"},
2739 {"SLIM TX9 MUX", "DEC2", "DEC2 MUX"},
2740 {"SLIM TX9 MUX", "DEC3", "DEC3 MUX"},
2741 {"SLIM TX9 MUX", "DEC4", "DEC4 MUX"},
2742 {"SLIM TX9 MUX", "DEC5", "DEC5 MUX"},
2743 {"SLIM TX9 MUX", "DEC6", "DEC6 MUX"},
2744 {"SLIM TX9 MUX", "DEC7", "DEC7 MUX"},
2745 {"SLIM TX9 MUX", "DEC8", "DEC8 MUX"},
2746 {"SLIM TX9 MUX", "DEC9", "DEC9 MUX"},
2747 {"SLIM TX9 MUX", "DEC10", "DEC10 MUX"},
2748
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2749 {"SLIM TX10 MUX", "DEC1", "DEC1 MUX"},
2750 {"SLIM TX10 MUX", "DEC2", "DEC2 MUX"},
2751 {"SLIM TX10 MUX", "DEC3", "DEC3 MUX"},
2752 {"SLIM TX10 MUX", "DEC4", "DEC4 MUX"},
2753 {"SLIM TX10 MUX", "DEC5", "DEC5 MUX"},
2754 {"SLIM TX10 MUX", "DEC6", "DEC6 MUX"},
2755 {"SLIM TX10 MUX", "DEC7", "DEC7 MUX"},
2756 {"SLIM TX10 MUX", "DEC8", "DEC8 MUX"},
2757 {"SLIM TX10 MUX", "DEC9", "DEC9 MUX"},
2758 {"SLIM TX10 MUX", "DEC10", "DEC10 MUX"},
2759
2760 /* Earpiece (RX MIX1) */
2761 {"EAR", NULL, "EAR PA"},
2762 {"EAR PA", NULL, "EAR_PA_MIXER"},
2763 {"EAR_PA_MIXER", NULL, "DAC1"},
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]2764 {"DAC1", NULL, "RX_BIAS"},
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2765
2766 {"ANC1 FB MUX", "EAR_HPH_L", "RX1 MIX2"},
2767 {"ANC1 FB MUX", "EAR_LINE_1", "RX2 MIX2"},
2768 {"ANC", NULL, "ANC1 FB MUX"},
2769
2770 /* Headset (RX MIX1 and RX MIX2) */
2771 {"HEADPHONE", NULL, "HPHL"},
2772 {"HEADPHONE", NULL, "HPHR"},
2773
2774 {"HPHL", NULL, "HPHL_PA_MIXER"},
2775 {"HPHL_PA_MIXER", NULL, "HPHL DAC"},
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]2776 {"HPHL DAC", NULL, "RX_BIAS"},
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2777
2778 {"HPHR", NULL, "HPHR_PA_MIXER"},
2779 {"HPHR_PA_MIXER", NULL, "HPHR DAC"},
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]2780 {"HPHR DAC", NULL, "RX_BIAS"},
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2781
2782 {"ANC", NULL, "ANC1 MUX"},
2783 {"ANC", NULL, "ANC2 MUX"},
2784 {"ANC1 MUX", "ADC1", "ADC1"},
2785 {"ANC1 MUX", "ADC2", "ADC2"},
2786 {"ANC1 MUX", "ADC3", "ADC3"},
2787 {"ANC1 MUX", "ADC4", "ADC4"},
2788 {"ANC2 MUX", "ADC1", "ADC1"},
2789 {"ANC2 MUX", "ADC2", "ADC2"},
2790 {"ANC2 MUX", "ADC3", "ADC3"},
2791 {"ANC2 MUX", "ADC4", "ADC4"},
2792
2793 {"ANC", NULL, "CDC_CONN"},
2794
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]2795 {"DAC1", "Switch", "CLASS_H_DSM MUX"},
2796 {"HPHL DAC", "Switch", "CLASS_H_DSM MUX"},
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2797 {"HPHR DAC", NULL, "RX2 CHAIN"},
2798
2799 {"LINEOUT1", NULL, "LINEOUT1 PA"},
2800 {"LINEOUT2", NULL, "LINEOUT2 PA"},
2801 {"LINEOUT3", NULL, "LINEOUT3 PA"},
2802 {"LINEOUT4", NULL, "LINEOUT4 PA"},
Joonwoo Park7680b9f2012-07-13 11:36:48 -0700[diff] [blame]2803 {"SPK_OUT", NULL, "SPK PA"},
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2804
2805 {"LINEOUT1 PA", NULL, "LINEOUT1_PA_MIXER"},
2806 {"LINEOUT1_PA_MIXER", NULL, "LINEOUT1 DAC"},
Tanya Finkelfe634462012-10-23 22:12:07 +0200[diff] [blame]2807
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2808 {"LINEOUT2 PA", NULL, "LINEOUT2_PA_MIXER"},
2809 {"LINEOUT2_PA_MIXER", NULL, "LINEOUT2 DAC"},
Tanya Finkelfe634462012-10-23 22:12:07 +0200[diff] [blame]2810
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2811 {"LINEOUT3 PA", NULL, "LINEOUT3_PA_MIXER"},
2812 {"LINEOUT3_PA_MIXER", NULL, "LINEOUT3 DAC"},
Tanya Finkelfe634462012-10-23 22:12:07 +0200[diff] [blame]2813
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2814 {"LINEOUT4 PA", NULL, "LINEOUT4_PA_MIXER"},
2815 {"LINEOUT4_PA_MIXER", NULL, "LINEOUT4 DAC"},
2816
2817 {"LINEOUT1 DAC", NULL, "RX3 MIX1"},
2818
Tanya Finkeldaaa6d12012-10-25 11:22:48 +0200[diff] [blame]2819 {"RDAC5 MUX", "DEM3_INV", "RX3 MIX1"},
2820 {"RDAC5 MUX", "DEM4", "RX4 MIX1"},
2821
2822 {"LINEOUT3 DAC", NULL, "RDAC5 MUX"},
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2823
2824 {"LINEOUT2 DAC", NULL, "RX5 MIX1"},
2825
Tanya Finkeldaaa6d12012-10-25 11:22:48 +0200[diff] [blame]2826 {"RDAC7 MUX", "DEM5_INV", "RX5 MIX1"},
2827 {"RDAC7 MUX", "DEM6", "RX6 MIX1"},
2828
2829 {"LINEOUT4 DAC", NULL, "RDAC7 MUX"},
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2830
Joonwoo Park7680b9f2012-07-13 11:36:48 -0700[diff] [blame]2831 {"SPK PA", NULL, "SPK DAC"},
Kiran Kandid2b46332012-10-05 12:04:00 -0700[diff] [blame]2832 {"SPK DAC", NULL, "RX7 MIX2"},
Joonwoo Park125cd4e2012-12-11 15:16:11 -0800[diff] [blame]2833 {"SPK DAC", NULL, "VDD_SPKDRV"},
Joonwoo Park7680b9f2012-07-13 11:36:48 -0700[diff] [blame]2834
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]2835 {"CLASS_H_DSM MUX", "DSM_HPHL_RX1", "RX1 CHAIN"},
2836
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2837 {"RX1 CHAIN", NULL, "RX1 MIX2"},
2838 {"RX2 CHAIN", NULL, "RX2 MIX2"},
2839 {"RX1 CHAIN", NULL, "ANC"},
2840 {"RX2 CHAIN", NULL, "ANC"},
2841
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2842 {"LINEOUT1 DAC", NULL, "RX_BIAS"},
2843 {"LINEOUT2 DAC", NULL, "RX_BIAS"},
2844 {"LINEOUT3 DAC", NULL, "RX_BIAS"},
2845 {"LINEOUT4 DAC", NULL, "RX_BIAS"},
Joonwoo Park7680b9f2012-07-13 11:36:48 -0700[diff] [blame]2846 {"SPK DAC", NULL, "RX_BIAS"},
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2847
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]2848 {"RX7 MIX1", NULL, "COMP0_CLK"},
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2849 {"RX1 MIX1", NULL, "COMP1_CLK"},
2850 {"RX2 MIX1", NULL, "COMP1_CLK"},
2851 {"RX3 MIX1", NULL, "COMP2_CLK"},
2852 {"RX5 MIX1", NULL, "COMP2_CLK"},
2853
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2854 {"RX1 MIX1", NULL, "RX1 MIX1 INP1"},
2855 {"RX1 MIX1", NULL, "RX1 MIX1 INP2"},
2856 {"RX1 MIX1", NULL, "RX1 MIX1 INP3"},
2857 {"RX2 MIX1", NULL, "RX2 MIX1 INP1"},
2858 {"RX2 MIX1", NULL, "RX2 MIX1 INP2"},
2859 {"RX3 MIX1", NULL, "RX3 MIX1 INP1"},
2860 {"RX3 MIX1", NULL, "RX3 MIX1 INP2"},
2861 {"RX4 MIX1", NULL, "RX4 MIX1 INP1"},
2862 {"RX4 MIX1", NULL, "RX4 MIX1 INP2"},
2863 {"RX5 MIX1", NULL, "RX5 MIX1 INP1"},
2864 {"RX5 MIX1", NULL, "RX5 MIX1 INP2"},
2865 {"RX6 MIX1", NULL, "RX6 MIX1 INP1"},
2866 {"RX6 MIX1", NULL, "RX6 MIX1 INP2"},
2867 {"RX7 MIX1", NULL, "RX7 MIX1 INP1"},
2868 {"RX7 MIX1", NULL, "RX7 MIX1 INP2"},
2869 {"RX1 MIX2", NULL, "RX1 MIX1"},
2870 {"RX1 MIX2", NULL, "RX1 MIX2 INP1"},
2871 {"RX1 MIX2", NULL, "RX1 MIX2 INP2"},
2872 {"RX2 MIX2", NULL, "RX2 MIX1"},
2873 {"RX2 MIX2", NULL, "RX2 MIX2 INP1"},
2874 {"RX2 MIX2", NULL, "RX2 MIX2 INP2"},
2875 {"RX7 MIX2", NULL, "RX7 MIX1"},
2876 {"RX7 MIX2", NULL, "RX7 MIX2 INP1"},
2877 {"RX7 MIX2", NULL, "RX7 MIX2 INP2"},
2878
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]2879 /* SLIM_MUX("AIF1_PB", "AIF1 PB"),*/
2880 {"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"},
2881 {"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"},
2882 {"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"},
2883 {"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"},
2884 {"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"},
2885 {"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"},
2886 {"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"},
2887 /* SLIM_MUX("AIF2_PB", "AIF2 PB"),*/
2888 {"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"},
2889 {"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"},
2890 {"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"},
2891 {"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"},
2892 {"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"},
2893 {"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"},
2894 {"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"},
2895 /* SLIM_MUX("AIF3_PB", "AIF3 PB"),*/
2896 {"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"},
2897 {"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"},
2898 {"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"},
2899 {"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"},
2900 {"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"},
2901 {"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"},
2902 {"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"},
2903
2904 {"SLIM RX1", NULL, "SLIM RX1 MUX"},
2905 {"SLIM RX2", NULL, "SLIM RX2 MUX"},
2906 {"SLIM RX3", NULL, "SLIM RX3 MUX"},
2907 {"SLIM RX4", NULL, "SLIM RX4 MUX"},
2908 {"SLIM RX5", NULL, "SLIM RX5 MUX"},
2909 {"SLIM RX6", NULL, "SLIM RX6 MUX"},
2910 {"SLIM RX7", NULL, "SLIM RX7 MUX"},
2911
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]2912 {"RX1 MIX1 INP1", "RX1", "SLIM RX1"},
2913 {"RX1 MIX1 INP1", "RX2", "SLIM RX2"},
2914 {"RX1 MIX1 INP1", "RX3", "SLIM RX3"},
2915 {"RX1 MIX1 INP1", "RX4", "SLIM RX4"},
2916 {"RX1 MIX1 INP1", "RX5", "SLIM RX5"},
2917 {"RX1 MIX1 INP1", "RX6", "SLIM RX6"},
2918 {"RX1 MIX1 INP1", "RX7", "SLIM RX7"},
2919 {"RX1 MIX1 INP1", "IIR1", "IIR1"},
2920 {"RX1 MIX1 INP2", "RX1", "SLIM RX1"},
2921 {"RX1 MIX1 INP2", "RX2", "SLIM RX2"},
2922 {"RX1 MIX1 INP2", "RX3", "SLIM RX3"},
2923 {"RX1 MIX1 INP2", "RX4", "SLIM RX4"},
2924 {"RX1 MIX1 INP2", "RX5", "SLIM RX5"},
2925 {"RX1 MIX1 INP2", "RX6", "SLIM RX6"},
2926 {"RX1 MIX1 INP2", "RX7", "SLIM RX7"},
2927 {"RX1 MIX1 INP2", "IIR1", "IIR1"},
2928 {"RX1 MIX1 INP3", "RX1", "SLIM RX1"},
2929 {"RX1 MIX1 INP3", "RX2", "SLIM RX2"},
2930 {"RX1 MIX1 INP3", "RX3", "SLIM RX3"},
2931 {"RX1 MIX1 INP3", "RX4", "SLIM RX4"},
2932 {"RX1 MIX1 INP3", "RX5", "SLIM RX5"},
2933 {"RX1 MIX1 INP3", "RX6", "SLIM RX6"},
2934 {"RX1 MIX1 INP3", "RX7", "SLIM RX7"},
2935 {"RX2 MIX1 INP1", "RX1", "SLIM RX1"},
2936 {"RX2 MIX1 INP1", "RX2", "SLIM RX2"},
2937 {"RX2 MIX1 INP1", "RX3", "SLIM RX3"},
2938 {"RX2 MIX1 INP1", "RX4", "SLIM RX4"},
2939 {"RX2 MIX1 INP1", "RX5", "SLIM RX5"},
2940 {"RX2 MIX1 INP1", "RX6", "SLIM RX6"},
2941 {"RX2 MIX1 INP1", "RX7", "SLIM RX7"},
2942 {"RX2 MIX1 INP1", "IIR1", "IIR1"},
2943 {"RX2 MIX1 INP2", "RX1", "SLIM RX1"},
2944 {"RX2 MIX1 INP2", "RX2", "SLIM RX2"},
2945 {"RX2 MIX1 INP2", "RX3", "SLIM RX3"},
2946 {"RX2 MIX1 INP2", "RX4", "SLIM RX4"},
2947 {"RX2 MIX1 INP2", "RX5", "SLIM RX5"},
2948 {"RX2 MIX1 INP2", "RX6", "SLIM RX6"},
2949 {"RX2 MIX1 INP2", "RX7", "SLIM RX7"},
2950 {"RX2 MIX1 INP2", "IIR1", "IIR1"},
2951 {"RX3 MIX1 INP1", "RX1", "SLIM RX1"},
2952 {"RX3 MIX1 INP1", "RX2", "SLIM RX2"},
2953 {"RX3 MIX1 INP1", "RX3", "SLIM RX3"},
2954 {"RX3 MIX1 INP1", "RX4", "SLIM RX4"},
2955 {"RX3 MIX1 INP1", "RX5", "SLIM RX5"},
2956 {"RX3 MIX1 INP1", "RX6", "SLIM RX6"},
2957 {"RX3 MIX1 INP1", "RX7", "SLIM RX7"},
2958 {"RX3 MIX1 INP1", "IIR1", "IIR1"},
2959 {"RX3 MIX1 INP2", "RX1", "SLIM RX1"},
2960 {"RX3 MIX1 INP2", "RX2", "SLIM RX2"},
2961 {"RX3 MIX1 INP2", "RX3", "SLIM RX3"},
2962 {"RX3 MIX1 INP2", "RX4", "SLIM RX4"},
2963 {"RX3 MIX1 INP2", "RX5", "SLIM RX5"},
2964 {"RX3 MIX1 INP2", "RX6", "SLIM RX6"},
2965 {"RX3 MIX1 INP2", "RX7", "SLIM RX7"},
2966 {"RX3 MIX1 INP2", "IIR1", "IIR1"},
2967 {"RX4 MIX1 INP1", "RX1", "SLIM RX1"},
2968 {"RX4 MIX1 INP1", "RX2", "SLIM RX2"},
2969 {"RX4 MIX1 INP1", "RX3", "SLIM RX3"},
2970 {"RX4 MIX1 INP1", "RX4", "SLIM RX4"},
2971 {"RX4 MIX1 INP1", "RX5", "SLIM RX5"},
2972 {"RX4 MIX1 INP1", "RX6", "SLIM RX6"},
2973 {"RX4 MIX1 INP1", "RX7", "SLIM RX7"},
2974 {"RX4 MIX1 INP1", "IIR1", "IIR1"},
2975 {"RX4 MIX1 INP2", "RX1", "SLIM RX1"},
2976 {"RX4 MIX1 INP2", "RX2", "SLIM RX2"},
2977 {"RX4 MIX1 INP2", "RX3", "SLIM RX3"},
2978 {"RX4 MIX1 INP2", "RX5", "SLIM RX5"},
2979 {"RX4 MIX1 INP2", "RX4", "SLIM RX4"},
2980 {"RX4 MIX1 INP2", "RX6", "SLIM RX6"},
2981 {"RX4 MIX1 INP2", "RX7", "SLIM RX7"},
2982 {"RX4 MIX1 INP2", "IIR1", "IIR1"},
2983 {"RX5 MIX1 INP1", "RX1", "SLIM RX1"},
2984 {"RX5 MIX1 INP1", "RX2", "SLIM RX2"},
2985 {"RX5 MIX1 INP1", "RX3", "SLIM RX3"},
2986 {"RX5 MIX1 INP1", "RX4", "SLIM RX4"},
2987 {"RX5 MIX1 INP1", "RX5", "SLIM RX5"},
2988 {"RX5 MIX1 INP1", "RX6", "SLIM RX6"},
2989 {"RX5 MIX1 INP1", "RX7", "SLIM RX7"},
2990 {"RX5 MIX1 INP1", "IIR1", "IIR1"},
2991 {"RX5 MIX1 INP2", "RX1", "SLIM RX1"},
2992 {"RX5 MIX1 INP2", "RX2", "SLIM RX2"},
2993 {"RX5 MIX1 INP2", "RX3", "SLIM RX3"},
2994 {"RX5 MIX1 INP2", "RX4", "SLIM RX4"},
2995 {"RX5 MIX1 INP2", "RX5", "SLIM RX5"},
2996 {"RX5 MIX1 INP2", "RX6", "SLIM RX6"},
2997 {"RX5 MIX1 INP2", "RX7", "SLIM RX7"},
2998 {"RX5 MIX1 INP2", "IIR1", "IIR1"},
2999 {"RX6 MIX1 INP1", "RX1", "SLIM RX1"},
3000 {"RX6 MIX1 INP1", "RX2", "SLIM RX2"},
3001 {"RX6 MIX1 INP1", "RX3", "SLIM RX3"},
3002 {"RX6 MIX1 INP1", "RX4", "SLIM RX4"},
3003 {"RX6 MIX1 INP1", "RX5", "SLIM RX5"},
3004 {"RX6 MIX1 INP1", "RX6", "SLIM RX6"},
3005 {"RX6 MIX1 INP1", "RX7", "SLIM RX7"},
3006 {"RX6 MIX1 INP1", "IIR1", "IIR1"},
3007 {"RX6 MIX1 INP2", "RX1", "SLIM RX1"},
3008 {"RX6 MIX1 INP2", "RX2", "SLIM RX2"},
3009 {"RX6 MIX1 INP2", "RX3", "SLIM RX3"},
3010 {"RX6 MIX1 INP2", "RX4", "SLIM RX4"},
3011 {"RX6 MIX1 INP2", "RX5", "SLIM RX5"},
3012 {"RX6 MIX1 INP2", "RX6", "SLIM RX6"},
3013 {"RX6 MIX1 INP2", "RX7", "SLIM RX7"},
3014 {"RX6 MIX1 INP2", "IIR1", "IIR1"},
3015 {"RX7 MIX1 INP1", "RX1", "SLIM RX1"},
3016 {"RX7 MIX1 INP1", "RX2", "SLIM RX2"},
3017 {"RX7 MIX1 INP1", "RX3", "SLIM RX3"},
3018 {"RX7 MIX1 INP1", "RX4", "SLIM RX4"},
3019 {"RX7 MIX1 INP1", "RX5", "SLIM RX5"},
3020 {"RX7 MIX1 INP1", "RX6", "SLIM RX6"},
3021 {"RX7 MIX1 INP1", "RX7", "SLIM RX7"},
3022 {"RX7 MIX1 INP1", "IIR1", "IIR1"},
3023 {"RX7 MIX1 INP2", "RX1", "SLIM RX1"},
3024 {"RX7 MIX1 INP2", "RX2", "SLIM RX2"},
3025 {"RX7 MIX1 INP2", "RX3", "SLIM RX3"},
3026 {"RX7 MIX1 INP2", "RX4", "SLIM RX4"},
3027 {"RX7 MIX1 INP2", "RX5", "SLIM RX5"},
3028 {"RX7 MIX1 INP2", "RX6", "SLIM RX6"},
3029 {"RX7 MIX1 INP2", "RX7", "SLIM RX7"},
3030 {"RX7 MIX1 INP2", "IIR1", "IIR1"},
3031 {"RX1 MIX2 INP1", "IIR1", "IIR1"},
3032 {"RX1 MIX2 INP2", "IIR1", "IIR1"},
3033 {"RX2 MIX2 INP1", "IIR1", "IIR1"},
3034 {"RX2 MIX2 INP2", "IIR1", "IIR1"},
3035 {"RX7 MIX2 INP1", "IIR1", "IIR1"},
3036 {"RX7 MIX2 INP2", "IIR1", "IIR1"},
3037
3038 /* Decimator Inputs */
3039 {"DEC1 MUX", "DMIC1", "DMIC1"},
3040 {"DEC1 MUX", "ADC6", "ADC6"},
3041 {"DEC1 MUX", NULL, "CDC_CONN"},
3042 {"DEC2 MUX", "DMIC2", "DMIC2"},
3043 {"DEC2 MUX", "ADC5", "ADC5"},
3044 {"DEC2 MUX", NULL, "CDC_CONN"},
3045 {"DEC3 MUX", "DMIC3", "DMIC3"},
3046 {"DEC3 MUX", "ADC4", "ADC4"},
3047 {"DEC3 MUX", NULL, "CDC_CONN"},
3048 {"DEC4 MUX", "DMIC4", "DMIC4"},
3049 {"DEC4 MUX", "ADC3", "ADC3"},
3050 {"DEC4 MUX", NULL, "CDC_CONN"},
3051 {"DEC5 MUX", "DMIC5", "DMIC5"},
3052 {"DEC5 MUX", "ADC2", "ADC2"},
3053 {"DEC5 MUX", NULL, "CDC_CONN"},
3054 {"DEC6 MUX", "DMIC6", "DMIC6"},
3055 {"DEC6 MUX", "ADC1", "ADC1"},
3056 {"DEC6 MUX", NULL, "CDC_CONN"},
3057 {"DEC7 MUX", "DMIC1", "DMIC1"},
3058 {"DEC7 MUX", "DMIC6", "DMIC6"},
3059 {"DEC7 MUX", "ADC1", "ADC1"},
3060 {"DEC7 MUX", "ADC6", "ADC6"},
3061 {"DEC7 MUX", NULL, "CDC_CONN"},
3062 {"DEC8 MUX", "DMIC2", "DMIC2"},
3063 {"DEC8 MUX", "DMIC5", "DMIC5"},
3064 {"DEC8 MUX", "ADC2", "ADC2"},
3065 {"DEC8 MUX", "ADC5", "ADC5"},
3066 {"DEC8 MUX", NULL, "CDC_CONN"},
3067 {"DEC9 MUX", "DMIC4", "DMIC4"},
3068 {"DEC9 MUX", "DMIC5", "DMIC5"},
3069 {"DEC9 MUX", "ADC2", "ADC2"},
3070 {"DEC9 MUX", "ADC3", "ADC3"},
3071 {"DEC9 MUX", NULL, "CDC_CONN"},
3072 {"DEC10 MUX", "DMIC3", "DMIC3"},
3073 {"DEC10 MUX", "DMIC6", "DMIC6"},
3074 {"DEC10 MUX", "ADC1", "ADC1"},
3075 {"DEC10 MUX", "ADC4", "ADC4"},
3076 {"DEC10 MUX", NULL, "CDC_CONN"},
3077
3078 /* ADC Connections */
3079 {"ADC1", NULL, "AMIC1"},
3080 {"ADC2", NULL, "AMIC2"},
3081 {"ADC3", NULL, "AMIC3"},
3082 {"ADC4", NULL, "AMIC4"},
3083 {"ADC5", NULL, "AMIC5"},
3084 {"ADC6", NULL, "AMIC6"},
3085
3086 /* AUX PGA Connections */
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3087 {"EAR_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]3088 {"HPHL_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
3089 {"HPHR_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
3090 {"LINEOUT1_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
3091 {"LINEOUT2_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
3092 {"LINEOUT3_PA_MIXER", "AUX_PGA_L Switch", "AUX_PGA_Left"},
3093 {"LINEOUT4_PA_MIXER", "AUX_PGA_R Switch", "AUX_PGA_Right"},
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3094 {"AUX_PGA_Left", NULL, "AMIC5"},
3095 {"AUX_PGA_Right", NULL, "AMIC6"},
3096
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3097 {"IIR1", NULL, "IIR1 INP1 MUX"},
3098 {"IIR1 INP1 MUX", "DEC1", "DEC1 MUX"},
3099 {"IIR1 INP1 MUX", "DEC2", "DEC2 MUX"},
3100 {"IIR1 INP1 MUX", "DEC3", "DEC3 MUX"},
3101 {"IIR1 INP1 MUX", "DEC4", "DEC4 MUX"},
3102 {"IIR1 INP1 MUX", "DEC5", "DEC5 MUX"},
3103 {"IIR1 INP1 MUX", "DEC6", "DEC6 MUX"},
3104 {"IIR1 INP1 MUX", "DEC7", "DEC7 MUX"},
3105 {"IIR1 INP1 MUX", "DEC8", "DEC8 MUX"},
3106 {"IIR1 INP1 MUX", "DEC9", "DEC9 MUX"},
3107 {"IIR1 INP1 MUX", "DEC10", "DEC10 MUX"},
3108
3109 {"MIC BIAS1 Internal1", NULL, "LDO_H"},
3110 {"MIC BIAS1 Internal2", NULL, "LDO_H"},
3111 {"MIC BIAS1 External", NULL, "LDO_H"},
3112 {"MIC BIAS2 Internal1", NULL, "LDO_H"},
3113 {"MIC BIAS2 Internal2", NULL, "LDO_H"},
3114 {"MIC BIAS2 Internal3", NULL, "LDO_H"},
3115 {"MIC BIAS2 External", NULL, "LDO_H"},
3116 {"MIC BIAS3 Internal1", NULL, "LDO_H"},
3117 {"MIC BIAS3 Internal2", NULL, "LDO_H"},
3118 {"MIC BIAS3 External", NULL, "LDO_H"},
3119 {"MIC BIAS4 External", NULL, "LDO_H"},
3120};
3121
3122static int taiko_readable(struct snd_soc_codec *ssc, unsigned int reg)
3123{
3124 return taiko_reg_readable[reg];
3125}
3126
3127static bool taiko_is_digital_gain_register(unsigned int reg)
3128{
3129 bool rtn = false;
3130 switch (reg) {
3131 case TAIKO_A_CDC_RX1_VOL_CTL_B2_CTL:
3132 case TAIKO_A_CDC_RX2_VOL_CTL_B2_CTL:
3133 case TAIKO_A_CDC_RX3_VOL_CTL_B2_CTL:
3134 case TAIKO_A_CDC_RX4_VOL_CTL_B2_CTL:
3135 case TAIKO_A_CDC_RX5_VOL_CTL_B2_CTL:
3136 case TAIKO_A_CDC_RX6_VOL_CTL_B2_CTL:
3137 case TAIKO_A_CDC_RX7_VOL_CTL_B2_CTL:
3138 case TAIKO_A_CDC_TX1_VOL_CTL_GAIN:
3139 case TAIKO_A_CDC_TX2_VOL_CTL_GAIN:
3140 case TAIKO_A_CDC_TX3_VOL_CTL_GAIN:
3141 case TAIKO_A_CDC_TX4_VOL_CTL_GAIN:
3142 case TAIKO_A_CDC_TX5_VOL_CTL_GAIN:
3143 case TAIKO_A_CDC_TX6_VOL_CTL_GAIN:
3144 case TAIKO_A_CDC_TX7_VOL_CTL_GAIN:
3145 case TAIKO_A_CDC_TX8_VOL_CTL_GAIN:
3146 case TAIKO_A_CDC_TX9_VOL_CTL_GAIN:
3147 case TAIKO_A_CDC_TX10_VOL_CTL_GAIN:
3148 rtn = true;
3149 break;
3150 default:
3151 break;
3152 }
3153 return rtn;
3154}
3155
3156static int taiko_volatile(struct snd_soc_codec *ssc, unsigned int reg)
3157{
3158 /* Registers lower than 0x100 are top level registers which can be
3159 * written by the Taiko core driver.
3160 */
3161
3162 if ((reg >= TAIKO_A_CDC_MBHC_EN_CTL) || (reg < 0x100))
3163 return 1;
3164
3165 /* IIR Coeff registers are not cacheable */
3166 if ((reg >= TAIKO_A_CDC_IIR1_COEF_B1_CTL) &&
3167 (reg <= TAIKO_A_CDC_IIR2_COEF_B2_CTL))
3168 return 1;
3169
3170 /* Digital gain register is not cacheable so we have to write
3171 * the setting even it is the same
3172 */
3173 if (taiko_is_digital_gain_register(reg))
3174 return 1;
3175
3176 /* HPH status registers */
3177 if (reg == TAIKO_A_RX_HPH_L_STATUS || reg == TAIKO_A_RX_HPH_R_STATUS)
3178 return 1;
3179
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]3180 if (reg == TAIKO_A_MBHC_INSERT_DET_STATUS)
3181 return 1;
3182
Joonwoo Park559a5bf2013-02-15 14:46:36 -0800[diff] [blame]3183 switch (reg) {
3184 case TAIKO_A_CDC_SPKR_CLIPDET_VAL0:
3185 case TAIKO_A_CDC_SPKR_CLIPDET_VAL1:
3186 case TAIKO_A_CDC_SPKR_CLIPDET_VAL2:
3187 case TAIKO_A_CDC_SPKR_CLIPDET_VAL3:
3188 case TAIKO_A_CDC_SPKR_CLIPDET_VAL4:
3189 case TAIKO_A_CDC_SPKR_CLIPDET_VAL5:
3190 case TAIKO_A_CDC_SPKR_CLIPDET_VAL6:
3191 case TAIKO_A_CDC_SPKR_CLIPDET_VAL7:
3192 case TAIKO_A_CDC_VBAT_GAIN_MON_VAL:
3193 return 1;
3194 }
3195
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3196 return 0;
3197}
3198
3199#define TAIKO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
3200static int taiko_write(struct snd_soc_codec *codec, unsigned int reg,
3201 unsigned int value)
3202{
3203 int ret;
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3204
3205 if (reg == SND_SOC_NOPM)
3206 return 0;
3207
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3208 BUG_ON(reg > TAIKO_MAX_REGISTER);
3209
3210 if (!taiko_volatile(codec, reg)) {
3211 ret = snd_soc_cache_write(codec, reg, value);
3212 if (ret != 0)
3213 dev_err(codec->dev, "Cache write to %x failed: %d\n",
3214 reg, ret);
3215 }
3216
3217 return wcd9xxx_reg_write(codec->control_data, reg, value);
3218}
3219static unsigned int taiko_read(struct snd_soc_codec *codec,
3220 unsigned int reg)
3221{
3222 unsigned int val;
3223 int ret;
3224
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3225 if (reg == SND_SOC_NOPM)
3226 return 0;
3227
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3228 BUG_ON(reg > TAIKO_MAX_REGISTER);
3229
3230 if (!taiko_volatile(codec, reg) && taiko_readable(codec, reg) &&
3231 reg < codec->driver->reg_cache_size) {
3232 ret = snd_soc_cache_read(codec, reg, &val);
3233 if (ret >= 0) {
3234 return val;
3235 } else
3236 dev_err(codec->dev, "Cache read from %x failed: %d\n",
3237 reg, ret);
3238 }
3239
3240 val = wcd9xxx_reg_read(codec->control_data, reg);
3241 return val;
3242}
3243
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3244static int taiko_startup(struct snd_pcm_substream *substream,
3245 struct snd_soc_dai *dai)
3246{
3247 struct wcd9xxx *taiko_core = dev_get_drvdata(dai->codec->dev->parent);
3248 pr_debug("%s(): substream = %s stream = %d\n" , __func__,
3249 substream->name, substream->stream);
3250 if ((taiko_core != NULL) &&
3251 (taiko_core->dev != NULL) &&
3252 (taiko_core->dev->parent != NULL))
3253 pm_runtime_get_sync(taiko_core->dev->parent);
3254
3255 return 0;
3256}
3257
3258static void taiko_shutdown(struct snd_pcm_substream *substream,
3259 struct snd_soc_dai *dai)
3260{
3261 struct wcd9xxx *taiko_core = dev_get_drvdata(dai->codec->dev->parent);
3262 pr_debug("%s(): substream = %s stream = %d\n" , __func__,
3263 substream->name, substream->stream);
3264 if ((taiko_core != NULL) &&
3265 (taiko_core->dev != NULL) &&
3266 (taiko_core->dev->parent != NULL)) {
3267 pm_runtime_mark_last_busy(taiko_core->dev->parent);
3268 pm_runtime_put(taiko_core->dev->parent);
3269 }
3270}
3271
3272int taiko_mclk_enable(struct snd_soc_codec *codec, int mclk_enable, bool dapm)
3273{
3274 struct taiko_priv *taiko = snd_soc_codec_get_drvdata(codec);
3275
3276 pr_debug("%s: mclk_enable = %u, dapm = %d\n", __func__, mclk_enable,
3277 dapm);
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]3278
3279 WCD9XXX_BCL_LOCK(&taiko->resmgr);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3280 if (mclk_enable) {
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]3281 wcd9xxx_resmgr_get_bandgap(&taiko->resmgr,
3282 WCD9XXX_BANDGAP_AUDIO_MODE);
3283 wcd9xxx_resmgr_get_clk_block(&taiko->resmgr, WCD9XXX_CLK_MCLK);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3284 } else {
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]3285 /* Put clock and BG */
3286 wcd9xxx_resmgr_put_clk_block(&taiko->resmgr, WCD9XXX_CLK_MCLK);
3287 wcd9xxx_resmgr_put_bandgap(&taiko->resmgr,
3288 WCD9XXX_BANDGAP_AUDIO_MODE);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3289 }
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]3290 WCD9XXX_BCL_UNLOCK(&taiko->resmgr);
3291
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3292 return 0;
3293}
3294
3295static int taiko_set_dai_sysclk(struct snd_soc_dai *dai,
3296 int clk_id, unsigned int freq, int dir)
3297{
Venkat Sudhira50a3762012-11-26 12:12:15 -0800[diff] [blame]3298 pr_debug("%s\n", __func__);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3299 return 0;
3300}
3301
3302static int taiko_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3303{
3304 u8 val = 0;
3305 struct taiko_priv *taiko = snd_soc_codec_get_drvdata(dai->codec);
3306
3307 pr_debug("%s\n", __func__);
3308 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
3309 case SND_SOC_DAIFMT_CBS_CFS:
3310 /* CPU is master */
3311 if (taiko->intf_type == WCD9XXX_INTERFACE_TYPE_I2C) {
3312 if (dai->id == AIF1_CAP)
3313 snd_soc_update_bits(dai->codec,
3314 TAIKO_A_CDC_CLK_TX_I2S_CTL,
3315 TAIKO_I2S_MASTER_MODE_MASK, 0);
3316 else if (dai->id == AIF1_PB)
3317 snd_soc_update_bits(dai->codec,
3318 TAIKO_A_CDC_CLK_RX_I2S_CTL,
3319 TAIKO_I2S_MASTER_MODE_MASK, 0);
3320 }
3321 break;
3322 case SND_SOC_DAIFMT_CBM_CFM:
3323 /* CPU is slave */
3324 if (taiko->intf_type == WCD9XXX_INTERFACE_TYPE_I2C) {
3325 val = TAIKO_I2S_MASTER_MODE_MASK;
3326 if (dai->id == AIF1_CAP)
3327 snd_soc_update_bits(dai->codec,
3328 TAIKO_A_CDC_CLK_TX_I2S_CTL, val, val);
3329 else if (dai->id == AIF1_PB)
3330 snd_soc_update_bits(dai->codec,
3331 TAIKO_A_CDC_CLK_RX_I2S_CTL, val, val);
3332 }
3333 break;
3334 default:
3335 return -EINVAL;
3336 }
3337 return 0;
3338}
3339
3340static int taiko_set_channel_map(struct snd_soc_dai *dai,
3341 unsigned int tx_num, unsigned int *tx_slot,
3342 unsigned int rx_num, unsigned int *rx_slot)
3343
3344{
3345 struct taiko_priv *taiko = snd_soc_codec_get_drvdata(dai->codec);
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3346 struct wcd9xxx *core = dev_get_drvdata(dai->codec->dev->parent);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3347 if (!tx_slot && !rx_slot) {
3348 pr_err("%s: Invalid\n", __func__);
3349 return -EINVAL;
3350 }
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3351 pr_debug("%s(): dai_name = %s DAI-ID %x tx_ch %d rx_ch %d\n"
3352 "taiko->intf_type %d\n",
3353 __func__, dai->name, dai->id, tx_num, rx_num,
3354 taiko->intf_type);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3355
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3356 if (taiko->intf_type == WCD9XXX_INTERFACE_TYPE_SLIMBUS)
3357 wcd9xxx_init_slimslave(core, core->slim->laddr,
3358 tx_num, tx_slot, rx_num, rx_slot);
3359 return 0;
3360}
3361
3362static int taiko_get_channel_map(struct snd_soc_dai *dai,
3363 unsigned int *tx_num, unsigned int *tx_slot,
3364 unsigned int *rx_num, unsigned int *rx_slot)
3365
3366{
3367 struct taiko_priv *taiko_p = snd_soc_codec_get_drvdata(dai->codec);
3368 u32 i = 0;
3369 struct wcd9xxx_ch *ch;
3370
3371 switch (dai->id) {
3372 case AIF1_PB:
3373 case AIF2_PB:
3374 case AIF3_PB:
3375 if (!rx_slot || !rx_num) {
3376 pr_err("%s: Invalid rx_slot %d or rx_num %d\n",
3377 __func__, (u32) rx_slot, (u32) rx_num);
3378 return -EINVAL;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3379 }
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3380 list_for_each_entry(ch, &taiko_p->dai[dai->id].wcd9xxx_ch_list,
3381 list) {
Gopikrishnaiah Anandana8aec1f2013-01-23 14:26:27 -0500[diff] [blame]3382 pr_debug("%s: slot_num %u ch->ch_num %d\n",
3383 __func__, i, ch->ch_num);
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3384 rx_slot[i++] = ch->ch_num;
3385 }
3386 pr_debug("%s: rx_num %d\n", __func__, i);
3387 *rx_num = i;
3388 break;
3389 case AIF1_CAP:
3390 case AIF2_CAP:
3391 case AIF3_CAP:
3392 if (!tx_slot || !tx_num) {
3393 pr_err("%s: Invalid tx_slot %d or tx_num %d\n",
3394 __func__, (u32) tx_slot, (u32) tx_num);
3395 return -EINVAL;
3396 }
3397 list_for_each_entry(ch, &taiko_p->dai[dai->id].wcd9xxx_ch_list,
3398 list) {
Gopikrishnaiah Anandana8aec1f2013-01-23 14:26:27 -0500[diff] [blame]3399 pr_debug("%s: slot_num %u ch->ch_num %d\n",
3400 __func__, i, ch->ch_num);
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3401 tx_slot[i++] = ch->ch_num;
3402 }
3403 pr_debug("%s: tx_num %d\n", __func__, i);
3404 *tx_num = i;
3405 break;
3406
3407 default:
3408 pr_err("%s: Invalid DAI ID %x\n", __func__, dai->id);
3409 break;
3410 }
3411
3412 return 0;
3413}
3414
3415static int taiko_set_interpolator_rate(struct snd_soc_dai *dai,
3416 u8 rx_fs_rate_reg_val, u32 compander_fs, u32 sample_rate)
3417{
3418 u32 j;
3419 u8 rx_mix1_inp;
3420 u16 rx_mix_1_reg_1, rx_mix_1_reg_2;
3421 u16 rx_fs_reg;
3422 u8 rx_mix_1_reg_1_val, rx_mix_1_reg_2_val;
3423 struct snd_soc_codec *codec = dai->codec;
3424 struct wcd9xxx_ch *ch;
3425 struct taiko_priv *taiko = snd_soc_codec_get_drvdata(codec);
3426
3427 list_for_each_entry(ch, &taiko->dai[dai->id].wcd9xxx_ch_list, list) {
3428 /* for RX port starting from 16 instead of 10 like tabla */
3429 rx_mix1_inp = ch->port + RX_MIX1_INP_SEL_RX1 -
3430 TAIKO_TX_PORT_NUMBER;
3431 if ((rx_mix1_inp < RX_MIX1_INP_SEL_RX1) ||
3432 (rx_mix1_inp > RX_MIX1_INP_SEL_RX7)) {
3433 pr_err("%s: Invalid TAIKO_RX%u port. Dai ID is %d\n",
3434 __func__, rx_mix1_inp - 5 , dai->id);
3435 return -EINVAL;
3436 }
3437
3438 rx_mix_1_reg_1 = TAIKO_A_CDC_CONN_RX1_B1_CTL;
3439
3440 for (j = 0; j < NUM_INTERPOLATORS; j++) {
3441 rx_mix_1_reg_2 = rx_mix_1_reg_1 + 1;
3442
3443 rx_mix_1_reg_1_val = snd_soc_read(codec,
3444 rx_mix_1_reg_1);
3445 rx_mix_1_reg_2_val = snd_soc_read(codec,
3446 rx_mix_1_reg_2);
3447
3448 if (((rx_mix_1_reg_1_val & 0x0F) == rx_mix1_inp) ||
3449 (((rx_mix_1_reg_1_val >> 4) & 0x0F)
3450 == rx_mix1_inp) ||
3451 ((rx_mix_1_reg_2_val & 0x0F) == rx_mix1_inp)) {
3452
3453 rx_fs_reg = TAIKO_A_CDC_RX1_B5_CTL + 8 * j;
3454
3455 pr_debug("%s: AIF_PB DAI(%d) connected to RX%u\n",
3456 __func__, dai->id, j + 1);
3457
3458 pr_debug("%s: set RX%u sample rate to %u\n",
3459 __func__, j + 1, sample_rate);
3460
3461 snd_soc_update_bits(codec, rx_fs_reg,
3462 0xE0, rx_fs_rate_reg_val);
3463
3464 if (comp_rx_path[j] < COMPANDER_MAX)
3465 taiko->comp_fs[comp_rx_path[j]]
3466 = compander_fs;
3467 }
3468 if (j <= 2)
3469 rx_mix_1_reg_1 += 3;
3470 else
3471 rx_mix_1_reg_1 += 2;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3472 }
3473 }
3474 return 0;
3475}
3476
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3477static int taiko_set_decimator_rate(struct snd_soc_dai *dai,
3478 u8 tx_fs_rate_reg_val, u32 sample_rate)
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3479{
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3480 struct snd_soc_codec *codec = dai->codec;
3481 struct wcd9xxx_ch *ch;
3482 struct taiko_priv *taiko = snd_soc_codec_get_drvdata(codec);
3483 u32 tx_port;
3484 u16 tx_port_reg, tx_fs_reg;
3485 u8 tx_port_reg_val;
3486 s8 decimator;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3487
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3488 list_for_each_entry(ch, &taiko->dai[dai->id].wcd9xxx_ch_list, list) {
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3489
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3490 tx_port = ch->port + 1;
3491 pr_debug("%s: dai->id = %d, tx_port = %d",
3492 __func__, dai->id, tx_port);
3493
3494 if ((tx_port < 1) || (tx_port > NUM_DECIMATORS)) {
3495 pr_err("%s: Invalid SLIM TX%u port. DAI ID is %d\n",
3496 __func__, tx_port, dai->id);
3497 return -EINVAL;
3498 }
3499
3500 tx_port_reg = TAIKO_A_CDC_CONN_TX_SB_B1_CTL + (tx_port - 1);
3501 tx_port_reg_val = snd_soc_read(codec, tx_port_reg);
3502
3503 decimator = 0;
3504
3505 if ((tx_port >= 1) && (tx_port <= 6)) {
3506
3507 tx_port_reg_val = tx_port_reg_val & 0x0F;
3508 if (tx_port_reg_val == 0x8)
3509 decimator = tx_port;
3510
3511 } else if ((tx_port >= 7) && (tx_port <= NUM_DECIMATORS)) {
3512
3513 tx_port_reg_val = tx_port_reg_val & 0x1F;
3514
3515 if ((tx_port_reg_val >= 0x8) &&
3516 (tx_port_reg_val <= 0x11)) {
3517
3518 decimator = (tx_port_reg_val - 0x8) + 1;
3519 }
3520 }
3521
3522 if (decimator) { /* SLIM_TX port has a DEC as input */
3523
3524 tx_fs_reg = TAIKO_A_CDC_TX1_CLK_FS_CTL +
3525 8 * (decimator - 1);
3526
3527 pr_debug("%s: set DEC%u (-> SLIM_TX%u) rate to %u\n",
3528 __func__, decimator, tx_port, sample_rate);
3529
3530 snd_soc_update_bits(codec, tx_fs_reg, 0x07,
3531 tx_fs_rate_reg_val);
3532
3533 } else {
3534 if ((tx_port_reg_val >= 0x1) &&
3535 (tx_port_reg_val <= 0x7)) {
3536
3537 pr_debug("%s: RMIX%u going to SLIM TX%u\n",
3538 __func__, tx_port_reg_val, tx_port);
3539
3540 } else if ((tx_port_reg_val >= 0x8) &&
3541 (tx_port_reg_val <= 0x11)) {
3542
3543 pr_err("%s: ERROR: Should not be here\n",
3544 __func__);
3545 pr_err("%s: ERROR: DEC connected to SLIM TX%u\n",
3546 __func__, tx_port);
3547 return -EINVAL;
3548
3549 } else if (tx_port_reg_val == 0) {
3550 pr_debug("%s: no signal to SLIM TX%u\n",
3551 __func__, tx_port);
3552 } else {
3553 pr_err("%s: ERROR: wrong signal to SLIM TX%u\n",
3554 __func__, tx_port);
3555 pr_err("%s: ERROR: wrong signal = %u\n",
3556 __func__, tx_port_reg_val);
3557 return -EINVAL;
3558 }
3559 }
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3560 }
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3561 return 0;
3562}
3563
3564static int taiko_hw_params(struct snd_pcm_substream *substream,
3565 struct snd_pcm_hw_params *params,
3566 struct snd_soc_dai *dai)
3567{
3568 struct snd_soc_codec *codec = dai->codec;
3569 struct taiko_priv *taiko = snd_soc_codec_get_drvdata(dai->codec);
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3570 u8 tx_fs_rate, rx_fs_rate;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3571 u32 compander_fs;
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3572 int ret;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3573
3574 pr_debug("%s: dai_name = %s DAI-ID %x rate %d num_ch %d\n", __func__,
3575 dai->name, dai->id, params_rate(params),
3576 params_channels(params));
3577
3578 switch (params_rate(params)) {
3579 case 8000:
3580 tx_fs_rate = 0x00;
3581 rx_fs_rate = 0x00;
3582 compander_fs = COMPANDER_FS_8KHZ;
3583 break;
3584 case 16000:
3585 tx_fs_rate = 0x01;
3586 rx_fs_rate = 0x20;
3587 compander_fs = COMPANDER_FS_16KHZ;
3588 break;
3589 case 32000:
3590 tx_fs_rate = 0x02;
3591 rx_fs_rate = 0x40;
3592 compander_fs = COMPANDER_FS_32KHZ;
3593 break;
3594 case 48000:
3595 tx_fs_rate = 0x03;
3596 rx_fs_rate = 0x60;
3597 compander_fs = COMPANDER_FS_48KHZ;
3598 break;
3599 case 96000:
3600 tx_fs_rate = 0x04;
3601 rx_fs_rate = 0x80;
3602 compander_fs = COMPANDER_FS_96KHZ;
3603 break;
3604 case 192000:
3605 tx_fs_rate = 0x05;
3606 rx_fs_rate = 0xA0;
3607 compander_fs = COMPANDER_FS_192KHZ;
3608 break;
3609 default:
3610 pr_err("%s: Invalid sampling rate %d\n", __func__,
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3611 params_rate(params));
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3612 return -EINVAL;
3613 }
3614
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3615 switch (substream->stream) {
3616 case SNDRV_PCM_STREAM_CAPTURE:
3617 ret = taiko_set_decimator_rate(dai, tx_fs_rate,
3618 params_rate(params));
3619 if (ret < 0) {
3620 pr_err("%s: set decimator rate failed %d\n", __func__,
3621 ret);
3622 return ret;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3623 }
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3624
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3625 if (taiko->intf_type == WCD9XXX_INTERFACE_TYPE_I2C) {
3626 switch (params_format(params)) {
3627 case SNDRV_PCM_FORMAT_S16_LE:
3628 snd_soc_update_bits(codec,
3629 TAIKO_A_CDC_CLK_TX_I2S_CTL,
3630 0x20, 0x20);
3631 break;
3632 case SNDRV_PCM_FORMAT_S32_LE:
3633 snd_soc_update_bits(codec,
3634 TAIKO_A_CDC_CLK_TX_I2S_CTL,
3635 0x20, 0x00);
3636 break;
3637 default:
3638 pr_err("invalid format\n");
3639 break;
3640 }
3641 snd_soc_update_bits(codec, TAIKO_A_CDC_CLK_TX_I2S_CTL,
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3642 0x07, tx_fs_rate);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3643 } else {
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3644 taiko->dai[dai->id].rate = params_rate(params);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3645 }
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3646 break;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3647
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3648 case SNDRV_PCM_STREAM_PLAYBACK:
3649 ret = taiko_set_interpolator_rate(dai, rx_fs_rate,
3650 compander_fs,
3651 params_rate(params));
3652 if (ret < 0) {
3653 pr_err("%s: set decimator rate failed %d\n", __func__,
3654 ret);
3655 return ret;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3656 }
3657 if (taiko->intf_type == WCD9XXX_INTERFACE_TYPE_I2C) {
3658 switch (params_format(params)) {
3659 case SNDRV_PCM_FORMAT_S16_LE:
3660 snd_soc_update_bits(codec,
3661 TAIKO_A_CDC_CLK_RX_I2S_CTL,
3662 0x20, 0x20);
3663 break;
3664 case SNDRV_PCM_FORMAT_S32_LE:
3665 snd_soc_update_bits(codec,
3666 TAIKO_A_CDC_CLK_RX_I2S_CTL,
3667 0x20, 0x00);
3668 break;
3669 default:
3670 pr_err("invalid format\n");
3671 break;
3672 }
3673 snd_soc_update_bits(codec, TAIKO_A_CDC_CLK_RX_I2S_CTL,
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3674 0x03, (rx_fs_rate >> 0x05));
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3675 } else {
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3676 taiko->dai[dai->id].rate = params_rate(params);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3677 }
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3678 break;
3679 default:
3680 pr_err("%s: Invalid stream type %d\n", __func__,
3681 substream->stream);
3682 return -EINVAL;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3683 }
3684
3685 return 0;
3686}
3687
3688static struct snd_soc_dai_ops taiko_dai_ops = {
3689 .startup = taiko_startup,
3690 .shutdown = taiko_shutdown,
3691 .hw_params = taiko_hw_params,
3692 .set_sysclk = taiko_set_dai_sysclk,
3693 .set_fmt = taiko_set_dai_fmt,
3694 .set_channel_map = taiko_set_channel_map,
3695 .get_channel_map = taiko_get_channel_map,
3696};
3697
3698static struct snd_soc_dai_driver taiko_dai[] = {
3699 {
3700 .name = "taiko_rx1",
3701 .id = AIF1_PB,
3702 .playback = {
3703 .stream_name = "AIF1 Playback",
3704 .rates = WCD9320_RATES,
3705 .formats = TAIKO_FORMATS,
3706 .rate_max = 192000,
3707 .rate_min = 8000,
3708 .channels_min = 1,
3709 .channels_max = 2,
3710 },
3711 .ops = &taiko_dai_ops,
3712 },
3713 {
3714 .name = "taiko_tx1",
3715 .id = AIF1_CAP,
3716 .capture = {
3717 .stream_name = "AIF1 Capture",
3718 .rates = WCD9320_RATES,
3719 .formats = TAIKO_FORMATS,
3720 .rate_max = 192000,
3721 .rate_min = 8000,
3722 .channels_min = 1,
3723 .channels_max = 4,
3724 },
3725 .ops = &taiko_dai_ops,
3726 },
3727 {
3728 .name = "taiko_rx2",
3729 .id = AIF2_PB,
3730 .playback = {
3731 .stream_name = "AIF2 Playback",
3732 .rates = WCD9320_RATES,
3733 .formats = TAIKO_FORMATS,
3734 .rate_min = 8000,
3735 .rate_max = 192000,
3736 .channels_min = 1,
3737 .channels_max = 2,
3738 },
3739 .ops = &taiko_dai_ops,
3740 },
3741 {
3742 .name = "taiko_tx2",
3743 .id = AIF2_CAP,
3744 .capture = {
3745 .stream_name = "AIF2 Capture",
3746 .rates = WCD9320_RATES,
3747 .formats = TAIKO_FORMATS,
3748 .rate_max = 192000,
3749 .rate_min = 8000,
3750 .channels_min = 1,
3751 .channels_max = 4,
3752 },
3753 .ops = &taiko_dai_ops,
3754 },
3755 {
3756 .name = "taiko_tx3",
3757 .id = AIF3_CAP,
3758 .capture = {
3759 .stream_name = "AIF3 Capture",
3760 .rates = WCD9320_RATES,
3761 .formats = TAIKO_FORMATS,
3762 .rate_max = 48000,
3763 .rate_min = 8000,
3764 .channels_min = 1,
3765 .channels_max = 2,
3766 },
3767 .ops = &taiko_dai_ops,
3768 },
3769 {
3770 .name = "taiko_rx3",
3771 .id = AIF3_PB,
3772 .playback = {
3773 .stream_name = "AIF3 Playback",
3774 .rates = WCD9320_RATES,
3775 .formats = TAIKO_FORMATS,
3776 .rate_min = 8000,
3777 .rate_max = 192000,
3778 .channels_min = 1,
3779 .channels_max = 2,
3780 },
3781 .ops = &taiko_dai_ops,
3782 },
3783};
3784
3785static struct snd_soc_dai_driver taiko_i2s_dai[] = {
3786 {
3787 .name = "taiko_i2s_rx1",
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3788 .id = AIF1_PB,
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3789 .playback = {
3790 .stream_name = "AIF1 Playback",
3791 .rates = WCD9320_RATES,
3792 .formats = TAIKO_FORMATS,
3793 .rate_max = 192000,
3794 .rate_min = 8000,
3795 .channels_min = 1,
3796 .channels_max = 4,
3797 },
3798 .ops = &taiko_dai_ops,
3799 },
3800 {
3801 .name = "taiko_i2s_tx1",
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3802 .id = AIF1_CAP,
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3803 .capture = {
3804 .stream_name = "AIF1 Capture",
3805 .rates = WCD9320_RATES,
3806 .formats = TAIKO_FORMATS,
3807 .rate_max = 192000,
3808 .rate_min = 8000,
3809 .channels_min = 1,
3810 .channels_max = 4,
3811 },
3812 .ops = &taiko_dai_ops,
3813 },
Venkat Sudhir994193b2012-12-17 17:30:51 -0800[diff] [blame]3814 {
3815 .name = "taiko_i2s_rx2",
3816 .id = AIF1_PB,
3817 .playback = {
3818 .stream_name = "AIF2 Playback",
3819 .rates = WCD9320_RATES,
3820 .formats = TAIKO_FORMATS,
3821 .rate_max = 192000,
3822 .rate_min = 8000,
3823 .channels_min = 1,
3824 .channels_max = 4,
3825 },
3826 .ops = &taiko_dai_ops,
3827 },
3828 {
3829 .name = "taiko_i2s_tx2",
3830 .id = AIF1_CAP,
3831 .capture = {
3832 .stream_name = "AIF2 Capture",
3833 .rates = WCD9320_RATES,
3834 .formats = TAIKO_FORMATS,
3835 .rate_max = 192000,
3836 .rate_min = 8000,
3837 .channels_min = 1,
3838 .channels_max = 4,
3839 },
3840 .ops = &taiko_dai_ops,
3841 },
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3842};
3843
Joonwoo Park9bbb4d12012-11-09 19:58:11 -0800[diff] [blame]3844static int taiko_codec_enable_slim_chmask(struct wcd9xxx_codec_dai_data *dai,
3845 bool up)
3846{
3847 int ret = 0;
3848 struct wcd9xxx_ch *ch;
3849
3850 if (up) {
3851 list_for_each_entry(ch, &dai->wcd9xxx_ch_list, list) {
3852 ret = wcd9xxx_get_slave_port(ch->ch_num);
3853 if (ret < 0) {
3854 pr_err("%s: Invalid slave port ID: %d\n",
3855 __func__, ret);
3856 ret = -EINVAL;
3857 } else {
3858 set_bit(ret, &dai->ch_mask);
3859 }
3860 }
3861 } else {
3862 ret = wait_event_timeout(dai->dai_wait, (dai->ch_mask == 0),
3863 msecs_to_jiffies(
3864 TAIKO_SLIM_CLOSE_TIMEOUT));
3865 if (!ret) {
3866 pr_err("%s: Slim close tx/rx wait timeout\n", __func__);
3867 ret = -ETIMEDOUT;
3868 } else {
3869 ret = 0;
3870 }
3871 }
3872 return ret;
3873}
3874
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3875static int taiko_codec_enable_slimrx(struct snd_soc_dapm_widget *w,
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3876 struct snd_kcontrol *kcontrol,
3877 int event)
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3878{
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3879 struct wcd9xxx *core;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3880 struct snd_soc_codec *codec = w->codec;
3881 struct taiko_priv *taiko_p = snd_soc_codec_get_drvdata(codec);
Joonwoo Park9bbb4d12012-11-09 19:58:11 -0800[diff] [blame]3882 int ret = 0;
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3883 struct wcd9xxx_codec_dai_data *dai;
3884
3885 core = dev_get_drvdata(codec->dev->parent);
3886
3887 pr_debug("%s: event called! codec name %s num_dai %d\n"
3888 "stream name %s event %d\n",
3889 __func__, w->codec->name, w->codec->num_dai, w->sname, event);
3890
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3891 /* Execute the callback only if interface type is slimbus */
3892 if (taiko_p->intf_type != WCD9XXX_INTERFACE_TYPE_SLIMBUS)
3893 return 0;
3894
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3895 dai = &taiko_p->dai[w->shift];
3896 pr_debug("%s: w->name %s w->shift %d event %d\n",
3897 __func__, w->name, w->shift, event);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3898
3899 switch (event) {
3900 case SND_SOC_DAPM_POST_PMU:
Joonwoo Park9bbb4d12012-11-09 19:58:11 -0800[diff] [blame]3901 (void) taiko_codec_enable_slim_chmask(dai, true);
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3902 ret = wcd9xxx_cfg_slim_sch_rx(core, &dai->wcd9xxx_ch_list,
3903 dai->rate, dai->bit_width,
3904 &dai->grph);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3905 break;
3906 case SND_SOC_DAPM_POST_PMD:
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3907 ret = wcd9xxx_close_slim_sch_rx(core, &dai->wcd9xxx_ch_list,
3908 dai->grph);
Joonwoo Park9bbb4d12012-11-09 19:58:11 -0800[diff] [blame]3909 ret = taiko_codec_enable_slim_chmask(dai, false);
3910 if (ret < 0) {
3911 ret = wcd9xxx_disconnect_port(core,
3912 &dai->wcd9xxx_ch_list,
3913 dai->grph);
3914 pr_debug("%s: Disconnect RX port, ret = %d\n",
3915 __func__, ret);
3916 }
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3917 break;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3918 }
3919 return ret;
3920}
3921
3922static int taiko_codec_enable_slimtx(struct snd_soc_dapm_widget *w,
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3923 struct snd_kcontrol *kcontrol,
3924 int event)
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3925{
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3926 struct wcd9xxx *core;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3927 struct snd_soc_codec *codec = w->codec;
3928 struct taiko_priv *taiko_p = snd_soc_codec_get_drvdata(codec);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3929 u32 ret = 0;
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3930 struct wcd9xxx_codec_dai_data *dai;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3931
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3932 core = dev_get_drvdata(codec->dev->parent);
3933
3934 pr_debug("%s: event called! codec name %s num_dai %d stream name %s\n",
3935 __func__, w->codec->name, w->codec->num_dai, w->sname);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3936
3937 /* Execute the callback only if interface type is slimbus */
3938 if (taiko_p->intf_type != WCD9XXX_INTERFACE_TYPE_SLIMBUS)
3939 return 0;
3940
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3941 pr_debug("%s(): w->name %s event %d w->shift %d\n",
3942 __func__, w->name, event, w->shift);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3943
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3944 dai = &taiko_p->dai[w->shift];
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3945 switch (event) {
3946 case SND_SOC_DAPM_POST_PMU:
Joonwoo Park9bbb4d12012-11-09 19:58:11 -0800[diff] [blame]3947 (void) taiko_codec_enable_slim_chmask(dai, true);
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3948 ret = wcd9xxx_cfg_slim_sch_tx(core, &dai->wcd9xxx_ch_list,
3949 dai->rate, dai->bit_width,
3950 &dai->grph);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3951 break;
3952 case SND_SOC_DAPM_POST_PMD:
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3953 ret = wcd9xxx_close_slim_sch_tx(core, &dai->wcd9xxx_ch_list,
3954 dai->grph);
Joonwoo Park9bbb4d12012-11-09 19:58:11 -0800[diff] [blame]3955 ret = taiko_codec_enable_slim_chmask(dai, false);
3956 if (ret < 0) {
3957 ret = wcd9xxx_disconnect_port(core,
3958 &dai->wcd9xxx_ch_list,
3959 dai->grph);
3960 pr_debug("%s: Disconnect RX port, ret = %d\n",
3961 __func__, ret);
3962 }
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]3963 break;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]3964 }
3965 return ret;
3966}
3967
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]3968static int taiko_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
3969 struct snd_kcontrol *kcontrol, int event)
3970{
3971 struct snd_soc_codec *codec = w->codec;
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]3972 struct taiko_priv *taiko_p = snd_soc_codec_get_drvdata(codec);
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]3973
3974 pr_debug("%s %s %d\n", __func__, w->name, event);
3975
3976 switch (event) {
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]3977 case SND_SOC_DAPM_POST_PMU:
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]3978 wcd9xxx_clsh_fsm(codec, &taiko_p->clsh_d,
3979 WCD9XXX_CLSH_STATE_EAR,
3980 WCD9XXX_CLSH_REQ_ENABLE,
3981 WCD9XXX_CLSH_EVENT_POST_PA);
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]3982
3983 usleep_range(5000, 5000);
3984 break;
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]3985 case SND_SOC_DAPM_POST_PMD:
3986 wcd9xxx_clsh_fsm(codec, &taiko_p->clsh_d,
3987 WCD9XXX_CLSH_STATE_EAR,
3988 WCD9XXX_CLSH_REQ_DISABLE,
3989 WCD9XXX_CLSH_EVENT_POST_PA);
3990 usleep_range(5000, 5000);
3991 }
3992 return 0;
3993}
3994
3995static int taiko_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
3996 struct snd_kcontrol *kcontrol, int event)
3997{
3998 struct snd_soc_codec *codec = w->codec;
3999 struct taiko_priv *taiko_p = snd_soc_codec_get_drvdata(codec);
4000
4001 pr_debug("%s %s %d\n", __func__, w->name, event);
4002
4003 switch (event) {
4004 case SND_SOC_DAPM_PRE_PMU:
4005 wcd9xxx_clsh_fsm(codec, &taiko_p->clsh_d,
4006 WCD9XXX_CLSH_STATE_EAR,
4007 WCD9XXX_CLSH_REQ_ENABLE,
4008 WCD9XXX_CLSH_EVENT_PRE_DAC);
4009 break;
4010 }
4011
4012 return 0;
4013}
4014
4015static int taiko_codec_dsm_mux_event(struct snd_soc_dapm_widget *w,
4016 struct snd_kcontrol *kcontrol, int event)
4017{
4018 struct snd_soc_codec *codec = w->codec;
4019 u8 reg_val, zoh_mux_val = 0x00;
4020
4021 pr_debug("%s: event = %d\n", __func__, event);
4022
4023 switch (event) {
4024 case SND_SOC_DAPM_POST_PMU:
4025 reg_val = snd_soc_read(codec, TAIKO_A_CDC_CONN_CLSH_CTL);
4026
4027 if ((reg_val & 0x30) == 0x10)
4028 zoh_mux_val = 0x04;
4029 else if ((reg_val & 0x30) == 0x20)
4030 zoh_mux_val = 0x08;
4031
4032 if (zoh_mux_val != 0x00)
4033 snd_soc_update_bits(codec,
4034 TAIKO_A_CDC_CONN_CLSH_CTL,
4035 0x0C, zoh_mux_val);
4036 break;
4037
4038 case SND_SOC_DAPM_POST_PMD:
4039 snd_soc_update_bits(codec, TAIKO_A_CDC_CONN_CLSH_CTL,
4040 0x0C, 0x00);
4041 break;
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]4042 }
4043 return 0;
4044}
4045
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]4046
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4047/* Todo: Have seperate dapm widgets for I2S and Slimbus.
4048 * Might Need to have callbacks registered only for slimbus
4049 */
4050static const struct snd_soc_dapm_widget taiko_dapm_widgets[] = {
4051 /*RX stuff */
4052 SND_SOC_DAPM_OUTPUT("EAR"),
4053
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]4054 SND_SOC_DAPM_PGA_E("EAR PA", TAIKO_A_RX_EAR_EN, 4, 0, NULL, 0,
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]4055 taiko_codec_enable_ear_pa, SND_SOC_DAPM_POST_PMU |
4056 SND_SOC_DAPM_POST_PMD),
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4057
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]4058 SND_SOC_DAPM_MIXER_E("DAC1", TAIKO_A_RX_EAR_EN, 6, 0, dac1_switch,
4059 ARRAY_SIZE(dac1_switch), taiko_codec_ear_dac_event,
4060 SND_SOC_DAPM_PRE_PMU),
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4061
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]4062 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
4063 AIF1_PB, 0, taiko_codec_enable_slimrx,
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4064 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]4065 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
4066 AIF2_PB, 0, taiko_codec_enable_slimrx,
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4067 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]4068 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
4069 AIF3_PB, 0, taiko_codec_enable_slimrx,
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4070 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4071
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]4072 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, TAIKO_RX1, 0,
4073 &slim_rx_mux[TAIKO_RX1]),
4074 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, TAIKO_RX2, 0,
4075 &slim_rx_mux[TAIKO_RX2]),
4076 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, TAIKO_RX3, 0,
4077 &slim_rx_mux[TAIKO_RX3]),
4078 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, TAIKO_RX4, 0,
4079 &slim_rx_mux[TAIKO_RX4]),
4080 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, TAIKO_RX5, 0,
4081 &slim_rx_mux[TAIKO_RX5]),
4082 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, TAIKO_RX6, 0,
4083 &slim_rx_mux[TAIKO_RX6]),
4084 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, TAIKO_RX7, 0,
4085 &slim_rx_mux[TAIKO_RX7]),
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4086
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]4087 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4088 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4089 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4090 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
4091 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
4092 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
4093 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4094
4095 /* Headphone */
4096 SND_SOC_DAPM_OUTPUT("HEADPHONE"),
4097 SND_SOC_DAPM_PGA_E("HPHL", TAIKO_A_RX_HPH_CNP_EN, 5, 0, NULL, 0,
4098 taiko_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]4099 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]4100 SND_SOC_DAPM_MIXER_E("HPHL DAC", TAIKO_A_RX_HPH_L_DAC_CTL, 7, 0,
4101 hphl_switch, ARRAY_SIZE(hphl_switch), taiko_hphl_dac_event,
4102 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4103
4104 SND_SOC_DAPM_PGA_E("HPHR", TAIKO_A_RX_HPH_CNP_EN, 4, 0, NULL, 0,
4105 taiko_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]4106 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4107
4108 SND_SOC_DAPM_DAC_E("HPHR DAC", NULL, TAIKO_A_RX_HPH_R_DAC_CTL, 7, 0,
4109 taiko_hphr_dac_event,
4110 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4111
4112 /* Speaker */
4113 SND_SOC_DAPM_OUTPUT("LINEOUT1"),
4114 SND_SOC_DAPM_OUTPUT("LINEOUT2"),
4115 SND_SOC_DAPM_OUTPUT("LINEOUT3"),
4116 SND_SOC_DAPM_OUTPUT("LINEOUT4"),
Joonwoo Park7680b9f2012-07-13 11:36:48 -0700[diff] [blame]4117 SND_SOC_DAPM_OUTPUT("SPK_OUT"),
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4118
4119 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", TAIKO_A_RX_LINE_CNP_EN, 0, 0, NULL,
4120 0, taiko_codec_enable_lineout, SND_SOC_DAPM_PRE_PMU |
4121 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4122 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", TAIKO_A_RX_LINE_CNP_EN, 1, 0, NULL,
4123 0, taiko_codec_enable_lineout, SND_SOC_DAPM_PRE_PMU |
4124 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4125 SND_SOC_DAPM_PGA_E("LINEOUT3 PA", TAIKO_A_RX_LINE_CNP_EN, 2, 0, NULL,
4126 0, taiko_codec_enable_lineout, SND_SOC_DAPM_PRE_PMU |
4127 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4128 SND_SOC_DAPM_PGA_E("LINEOUT4 PA", TAIKO_A_RX_LINE_CNP_EN, 3, 0, NULL,
4129 0, taiko_codec_enable_lineout, SND_SOC_DAPM_PRE_PMU |
4130 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
Joonwoo Park125cd4e2012-12-11 15:16:11 -0800[diff] [blame]4131 SND_SOC_DAPM_PGA_E("SPK PA", SND_SOC_NOPM, 0, 0 , NULL,
4132 0, taiko_codec_enable_spk_pa,
4133 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4134
4135 SND_SOC_DAPM_DAC_E("LINEOUT1 DAC", NULL, TAIKO_A_RX_LINE_1_DAC_CTL, 7, 0
4136 , taiko_lineout_dac_event,
4137 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4138 SND_SOC_DAPM_DAC_E("LINEOUT2 DAC", NULL, TAIKO_A_RX_LINE_2_DAC_CTL, 7, 0
4139 , taiko_lineout_dac_event,
4140 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4141 SND_SOC_DAPM_DAC_E("LINEOUT3 DAC", NULL, TAIKO_A_RX_LINE_3_DAC_CTL, 7, 0
4142 , taiko_lineout_dac_event,
4143 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4144 SND_SOC_DAPM_SWITCH("LINEOUT3 DAC GROUND", SND_SOC_NOPM, 0, 0,
4145 &lineout3_ground_switch),
4146 SND_SOC_DAPM_DAC_E("LINEOUT4 DAC", NULL, TAIKO_A_RX_LINE_4_DAC_CTL, 7, 0
4147 , taiko_lineout_dac_event,
4148 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4149 SND_SOC_DAPM_SWITCH("LINEOUT4 DAC GROUND", SND_SOC_NOPM, 0, 0,
4150 &lineout4_ground_switch),
4151
Joonwoo Park7680b9f2012-07-13 11:36:48 -0700[diff] [blame]4152 SND_SOC_DAPM_DAC_E("SPK DAC", NULL, SND_SOC_NOPM, 0, 0,
4153 taiko_spk_dac_event,
4154 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4155
Joonwoo Park125cd4e2012-12-11 15:16:11 -0800[diff] [blame]4156 SND_SOC_DAPM_SUPPLY("VDD_SPKDRV", SND_SOC_NOPM, 0, 0,
4157 taiko_codec_enable_vdd_spkr,
4158 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4159
Kiran Kandid2b46332012-10-05 12:04:00 -0700[diff] [blame]4160 SND_SOC_DAPM_MIXER("RX1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4161 SND_SOC_DAPM_MIXER("RX2 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4162 SND_SOC_DAPM_MIXER("RX7 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4163
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4164 SND_SOC_DAPM_MIXER_E("RX1 MIX2", TAIKO_A_CDC_CLK_RX_B1_CTL, 0, 0, NULL,
Kiran Kandi7b7d2ff2012-09-14 14:52:14 -0700[diff] [blame]4165 0, taiko_codec_enable_interpolator, SND_SOC_DAPM_PRE_PMU |
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4166 SND_SOC_DAPM_POST_PMU),
4167 SND_SOC_DAPM_MIXER_E("RX2 MIX2", TAIKO_A_CDC_CLK_RX_B1_CTL, 1, 0, NULL,
Kiran Kandi7b7d2ff2012-09-14 14:52:14 -0700[diff] [blame]4168 0, taiko_codec_enable_interpolator, SND_SOC_DAPM_PRE_PMU |
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4169 SND_SOC_DAPM_POST_PMU),
Kiran Kandid2b46332012-10-05 12:04:00 -0700[diff] [blame]4170 SND_SOC_DAPM_MIXER_E("RX3 MIX1", TAIKO_A_CDC_CLK_RX_B1_CTL, 2, 0, NULL,
Kiran Kandi7b7d2ff2012-09-14 14:52:14 -0700[diff] [blame]4171 0, taiko_codec_enable_interpolator, SND_SOC_DAPM_PRE_PMU |
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4172 SND_SOC_DAPM_POST_PMU),
4173 SND_SOC_DAPM_MIXER_E("RX4 MIX1", TAIKO_A_CDC_CLK_RX_B1_CTL, 3, 0, NULL,
Kiran Kandi7b7d2ff2012-09-14 14:52:14 -0700[diff] [blame]4174 0, taiko_codec_enable_interpolator, SND_SOC_DAPM_PRE_PMU |
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4175 SND_SOC_DAPM_POST_PMU),
4176 SND_SOC_DAPM_MIXER_E("RX5 MIX1", TAIKO_A_CDC_CLK_RX_B1_CTL, 4, 0, NULL,
Kiran Kandi7b7d2ff2012-09-14 14:52:14 -0700[diff] [blame]4177 0, taiko_codec_enable_interpolator, SND_SOC_DAPM_PRE_PMU |
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4178 SND_SOC_DAPM_POST_PMU),
4179 SND_SOC_DAPM_MIXER_E("RX6 MIX1", TAIKO_A_CDC_CLK_RX_B1_CTL, 5, 0, NULL,
Kiran Kandi7b7d2ff2012-09-14 14:52:14 -0700[diff] [blame]4180 0, taiko_codec_enable_interpolator, SND_SOC_DAPM_PRE_PMU |
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4181 SND_SOC_DAPM_POST_PMU),
Kiran Kandid2b46332012-10-05 12:04:00 -0700[diff] [blame]4182 SND_SOC_DAPM_MIXER_E("RX7 MIX2", TAIKO_A_CDC_CLK_RX_B1_CTL, 6, 0, NULL,
Kiran Kandi7b7d2ff2012-09-14 14:52:14 -0700[diff] [blame]4183 0, taiko_codec_enable_interpolator, SND_SOC_DAPM_PRE_PMU |
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4184 SND_SOC_DAPM_POST_PMU),
4185
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4186
4187 SND_SOC_DAPM_MIXER("RX1 CHAIN", TAIKO_A_CDC_RX1_B6_CTL, 5, 0, NULL, 0),
4188 SND_SOC_DAPM_MIXER("RX2 CHAIN", TAIKO_A_CDC_RX2_B6_CTL, 5, 0, NULL, 0),
4189
4190 SND_SOC_DAPM_MUX("RX1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4191 &rx_mix1_inp1_mux),
4192 SND_SOC_DAPM_MUX("RX1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4193 &rx_mix1_inp2_mux),
4194 SND_SOC_DAPM_MUX("RX1 MIX1 INP3", SND_SOC_NOPM, 0, 0,
4195 &rx_mix1_inp3_mux),
4196 SND_SOC_DAPM_MUX("RX2 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4197 &rx2_mix1_inp1_mux),
4198 SND_SOC_DAPM_MUX("RX2 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4199 &rx2_mix1_inp2_mux),
4200 SND_SOC_DAPM_MUX("RX3 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4201 &rx3_mix1_inp1_mux),
4202 SND_SOC_DAPM_MUX("RX3 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4203 &rx3_mix1_inp2_mux),
4204 SND_SOC_DAPM_MUX("RX4 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4205 &rx4_mix1_inp1_mux),
4206 SND_SOC_DAPM_MUX("RX4 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4207 &rx4_mix1_inp2_mux),
4208 SND_SOC_DAPM_MUX("RX5 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4209 &rx5_mix1_inp1_mux),
4210 SND_SOC_DAPM_MUX("RX5 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4211 &rx5_mix1_inp2_mux),
4212 SND_SOC_DAPM_MUX("RX6 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4213 &rx6_mix1_inp1_mux),
4214 SND_SOC_DAPM_MUX("RX6 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4215 &rx6_mix1_inp2_mux),
4216 SND_SOC_DAPM_MUX("RX7 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4217 &rx7_mix1_inp1_mux),
4218 SND_SOC_DAPM_MUX("RX7 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4219 &rx7_mix1_inp2_mux),
4220 SND_SOC_DAPM_MUX("RX1 MIX2 INP1", SND_SOC_NOPM, 0, 0,
4221 &rx1_mix2_inp1_mux),
4222 SND_SOC_DAPM_MUX("RX1 MIX2 INP2", SND_SOC_NOPM, 0, 0,
4223 &rx1_mix2_inp2_mux),
4224 SND_SOC_DAPM_MUX("RX2 MIX2 INP1", SND_SOC_NOPM, 0, 0,
4225 &rx2_mix2_inp1_mux),
4226 SND_SOC_DAPM_MUX("RX2 MIX2 INP2", SND_SOC_NOPM, 0, 0,
4227 &rx2_mix2_inp2_mux),
4228 SND_SOC_DAPM_MUX("RX7 MIX2 INP1", SND_SOC_NOPM, 0, 0,
4229 &rx7_mix2_inp1_mux),
4230 SND_SOC_DAPM_MUX("RX7 MIX2 INP2", SND_SOC_NOPM, 0, 0,
4231 &rx7_mix2_inp2_mux),
4232
Tanya Finkeldaaa6d12012-10-25 11:22:48 +0200[diff] [blame]4233 SND_SOC_DAPM_MUX("RDAC5 MUX", SND_SOC_NOPM, 0, 0,
4234 &rx_dac5_mux),
4235 SND_SOC_DAPM_MUX("RDAC7 MUX", SND_SOC_NOPM, 0, 0,
4236 &rx_dac7_mux),
4237
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]4238 SND_SOC_DAPM_MUX_E("CLASS_H_DSM MUX", SND_SOC_NOPM, 0, 0,
4239 &class_h_dsm_mux, taiko_codec_dsm_mux_event,
4240 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]4241
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4242 SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0,
4243 taiko_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU |
4244 SND_SOC_DAPM_POST_PMD),
4245
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]4246 SND_SOC_DAPM_SUPPLY("CDC_I2S_RX_CONN", WCD9XXX_A_CDC_CLK_OTHR_CTL, 5, 0,
Joonwoo Park559a5bf2013-02-15 14:46:36 -0800[diff] [blame]4247 NULL, 0),
4248
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4249 /* TX */
4250
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]4251 SND_SOC_DAPM_SUPPLY("CDC_CONN", WCD9XXX_A_CDC_CLK_OTHR_CTL, 2, 0, NULL,
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4252 0),
4253
4254 SND_SOC_DAPM_SUPPLY("LDO_H", TAIKO_A_LDO_H_MODE_1, 7, 0,
4255 taiko_codec_enable_ldo_h, SND_SOC_DAPM_POST_PMU),
4256
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]4257 SND_SOC_DAPM_SUPPLY("COMP0_CLK", SND_SOC_NOPM, 0, 0,
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4258 taiko_config_compander, SND_SOC_DAPM_PRE_PMU |
4259 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]4260 SND_SOC_DAPM_SUPPLY("COMP1_CLK", SND_SOC_NOPM, 1, 0,
4261 taiko_config_compander, SND_SOC_DAPM_PRE_PMU |
4262 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
4263 SND_SOC_DAPM_SUPPLY("COMP2_CLK", SND_SOC_NOPM, 2, 0,
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4264 taiko_config_compander, SND_SOC_DAPM_PRE_PMU |
4265 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
4266
4267
4268 SND_SOC_DAPM_INPUT("AMIC1"),
Joonwoo Park3699ca32013-02-08 12:06:15 -0800[diff] [blame]4269 SND_SOC_DAPM_MICBIAS_E("MIC BIAS1 External", SND_SOC_NOPM, 7, 0,
4270 taiko_codec_enable_micbias,
4271 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4272 SND_SOC_DAPM_POST_PMD),
4273 SND_SOC_DAPM_MICBIAS_E("MIC BIAS1 Internal1", SND_SOC_NOPM, 7, 0,
4274 taiko_codec_enable_micbias,
4275 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4276 SND_SOC_DAPM_POST_PMD),
4277 SND_SOC_DAPM_MICBIAS_E("MIC BIAS1 Internal2", SND_SOC_NOPM, 7, 0,
4278 taiko_codec_enable_micbias,
4279 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4280 SND_SOC_DAPM_POST_PMD),
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4281 SND_SOC_DAPM_ADC_E("ADC1", NULL, TAIKO_A_TX_1_2_EN, 7, 0,
4282 taiko_codec_enable_adc, SND_SOC_DAPM_PRE_PMU |
4283 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4284
4285 SND_SOC_DAPM_INPUT("AMIC3"),
4286 SND_SOC_DAPM_ADC_E("ADC3", NULL, TAIKO_A_TX_3_4_EN, 7, 0,
4287 taiko_codec_enable_adc, SND_SOC_DAPM_PRE_PMU |
4288 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4289
4290 SND_SOC_DAPM_INPUT("AMIC4"),
4291 SND_SOC_DAPM_ADC_E("ADC4", NULL, TAIKO_A_TX_3_4_EN, 3, 0,
4292 taiko_codec_enable_adc, SND_SOC_DAPM_PRE_PMU |
4293 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4294
4295 SND_SOC_DAPM_INPUT("AMIC5"),
4296 SND_SOC_DAPM_ADC_E("ADC5", NULL, TAIKO_A_TX_5_6_EN, 7, 0,
4297 taiko_codec_enable_adc, SND_SOC_DAPM_POST_PMU),
4298
4299 SND_SOC_DAPM_INPUT("AMIC6"),
4300 SND_SOC_DAPM_ADC_E("ADC6", NULL, TAIKO_A_TX_5_6_EN, 3, 0,
4301 taiko_codec_enable_adc, SND_SOC_DAPM_POST_PMU),
4302
4303 SND_SOC_DAPM_MUX_E("DEC1 MUX", TAIKO_A_CDC_CLK_TX_CLK_EN_B1_CTL, 0, 0,
4304 &dec1_mux, taiko_codec_enable_dec,
4305 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4306 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4307
4308 SND_SOC_DAPM_MUX_E("DEC2 MUX", TAIKO_A_CDC_CLK_TX_CLK_EN_B1_CTL, 1, 0,
4309 &dec2_mux, taiko_codec_enable_dec,
4310 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4311 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4312
4313 SND_SOC_DAPM_MUX_E("DEC3 MUX", TAIKO_A_CDC_CLK_TX_CLK_EN_B1_CTL, 2, 0,
4314 &dec3_mux, taiko_codec_enable_dec,
4315 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4316 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4317
4318 SND_SOC_DAPM_MUX_E("DEC4 MUX", TAIKO_A_CDC_CLK_TX_CLK_EN_B1_CTL, 3, 0,
4319 &dec4_mux, taiko_codec_enable_dec,
4320 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4321 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4322
4323 SND_SOC_DAPM_MUX_E("DEC5 MUX", TAIKO_A_CDC_CLK_TX_CLK_EN_B1_CTL, 4, 0,
4324 &dec5_mux, taiko_codec_enable_dec,
4325 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4326 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4327
4328 SND_SOC_DAPM_MUX_E("DEC6 MUX", TAIKO_A_CDC_CLK_TX_CLK_EN_B1_CTL, 5, 0,
4329 &dec6_mux, taiko_codec_enable_dec,
4330 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4331 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4332
4333 SND_SOC_DAPM_MUX_E("DEC7 MUX", TAIKO_A_CDC_CLK_TX_CLK_EN_B1_CTL, 6, 0,
4334 &dec7_mux, taiko_codec_enable_dec,
4335 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4336 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4337
4338 SND_SOC_DAPM_MUX_E("DEC8 MUX", TAIKO_A_CDC_CLK_TX_CLK_EN_B1_CTL, 7, 0,
4339 &dec8_mux, taiko_codec_enable_dec,
4340 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4341 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4342
4343 SND_SOC_DAPM_MUX_E("DEC9 MUX", TAIKO_A_CDC_CLK_TX_CLK_EN_B2_CTL, 0, 0,
4344 &dec9_mux, taiko_codec_enable_dec,
4345 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4346 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4347
4348 SND_SOC_DAPM_MUX_E("DEC10 MUX", TAIKO_A_CDC_CLK_TX_CLK_EN_B2_CTL, 1, 0,
4349 &dec10_mux, taiko_codec_enable_dec,
4350 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4351 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4352
4353 SND_SOC_DAPM_MUX("ANC1 MUX", SND_SOC_NOPM, 0, 0, &anc1_mux),
4354 SND_SOC_DAPM_MUX("ANC2 MUX", SND_SOC_NOPM, 0, 0, &anc2_mux),
4355
4356 SND_SOC_DAPM_MIXER_E("ANC", SND_SOC_NOPM, 0, 0, NULL, 0,
4357 taiko_codec_enable_anc, SND_SOC_DAPM_PRE_PMU |
4358 SND_SOC_DAPM_POST_PMD),
4359
4360 SND_SOC_DAPM_MUX("ANC1 FB MUX", SND_SOC_NOPM, 0, 0, &anc1_fb_mux),
4361
4362 SND_SOC_DAPM_INPUT("AMIC2"),
Joonwoo Park3699ca32013-02-08 12:06:15 -0800[diff] [blame]4363 SND_SOC_DAPM_MICBIAS_E("MIC BIAS2 External", SND_SOC_NOPM, 7, 0,
4364 taiko_codec_enable_micbias,
4365 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4366 SND_SOC_DAPM_POST_PMD),
4367 SND_SOC_DAPM_MICBIAS_E("MIC BIAS2 Internal1", SND_SOC_NOPM, 7, 0,
4368 taiko_codec_enable_micbias,
4369 SND_SOC_DAPM_PRE_PMU |
4370 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4371 SND_SOC_DAPM_MICBIAS_E("MIC BIAS2 Internal2", SND_SOC_NOPM, 7, 0,
4372 taiko_codec_enable_micbias,
4373 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4374 SND_SOC_DAPM_POST_PMD),
4375 SND_SOC_DAPM_MICBIAS_E("MIC BIAS2 Internal3", SND_SOC_NOPM, 7, 0,
4376 taiko_codec_enable_micbias,
4377 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4378 SND_SOC_DAPM_POST_PMD),
4379 SND_SOC_DAPM_MICBIAS_E("MIC BIAS3 External", SND_SOC_NOPM, 7, 0,
4380 taiko_codec_enable_micbias,
4381 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4382 SND_SOC_DAPM_POST_PMD),
4383 SND_SOC_DAPM_MICBIAS_E("MIC BIAS3 Internal1", SND_SOC_NOPM, 7, 0,
4384 taiko_codec_enable_micbias,
4385 SND_SOC_DAPM_PRE_PMU |
4386 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4387 SND_SOC_DAPM_MICBIAS_E("MIC BIAS3 Internal2", SND_SOC_NOPM, 7, 0,
4388 taiko_codec_enable_micbias,
4389 SND_SOC_DAPM_PRE_PMU |
4390 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4391 SND_SOC_DAPM_MICBIAS_E("MIC BIAS4 External", SND_SOC_NOPM, 7,
4392 0, taiko_codec_enable_micbias,
4393 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4394 SND_SOC_DAPM_POST_PMD),
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4395
4396 SND_SOC_DAPM_ADC_E("ADC2", NULL, TAIKO_A_TX_1_2_EN, 3, 0,
4397 taiko_codec_enable_adc, SND_SOC_DAPM_PRE_PMU |
4398 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4399
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]4400 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
4401 AIF1_CAP, 0, taiko_codec_enable_slimtx,
4402 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4403
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]4404 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
4405 AIF2_CAP, 0, taiko_codec_enable_slimtx,
4406 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4407
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]4408 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
4409 AIF3_CAP, 0, taiko_codec_enable_slimtx,
4410 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4411
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]4412 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
4413 aif_cap_mixer, ARRAY_SIZE(aif_cap_mixer)),
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4414
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]4415 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
4416 aif_cap_mixer, ARRAY_SIZE(aif_cap_mixer)),
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4417
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]4418 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
4419 aif_cap_mixer, ARRAY_SIZE(aif_cap_mixer)),
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4420
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]4421 SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, TAIKO_TX1, 0,
4422 &sb_tx1_mux),
4423 SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, TAIKO_TX2, 0,
4424 &sb_tx2_mux),
4425 SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, TAIKO_TX3, 0,
4426 &sb_tx3_mux),
4427 SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, TAIKO_TX4, 0,
4428 &sb_tx4_mux),
4429 SND_SOC_DAPM_MUX("SLIM TX5 MUX", SND_SOC_NOPM, TAIKO_TX5, 0,
4430 &sb_tx5_mux),
4431 SND_SOC_DAPM_MUX("SLIM TX6 MUX", SND_SOC_NOPM, TAIKO_TX6, 0,
4432 &sb_tx6_mux),
4433 SND_SOC_DAPM_MUX("SLIM TX7 MUX", SND_SOC_NOPM, TAIKO_TX7, 0,
4434 &sb_tx7_mux),
4435 SND_SOC_DAPM_MUX("SLIM TX8 MUX", SND_SOC_NOPM, TAIKO_TX8, 0,
4436 &sb_tx8_mux),
4437 SND_SOC_DAPM_MUX("SLIM TX9 MUX", SND_SOC_NOPM, TAIKO_TX9, 0,
4438 &sb_tx9_mux),
4439 SND_SOC_DAPM_MUX("SLIM TX10 MUX", SND_SOC_NOPM, TAIKO_TX10, 0,
4440 &sb_tx10_mux),
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4441
4442 /* Digital Mic Inputs */
4443 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
4444 taiko_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4445 SND_SOC_DAPM_POST_PMD),
4446
4447 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
4448 taiko_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4449 SND_SOC_DAPM_POST_PMD),
4450
4451 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
4452 taiko_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4453 SND_SOC_DAPM_POST_PMD),
4454
4455 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
4456 taiko_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4457 SND_SOC_DAPM_POST_PMD),
4458
4459 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
4460 taiko_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4461 SND_SOC_DAPM_POST_PMD),
4462 SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 0, 0,
4463 taiko_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4464 SND_SOC_DAPM_POST_PMD),
4465
4466 /* Sidetone */
4467 SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
4468 SND_SOC_DAPM_PGA("IIR1", TAIKO_A_CDC_CLK_SD_CTL, 0, 0, NULL, 0),
4469
4470 /* AUX PGA */
4471 SND_SOC_DAPM_ADC_E("AUX_PGA_Left", NULL, TAIKO_A_RX_AUX_SW_CTL, 7, 0,
4472 taiko_codec_enable_aux_pga, SND_SOC_DAPM_PRE_PMU |
4473 SND_SOC_DAPM_POST_PMD),
4474
4475 SND_SOC_DAPM_ADC_E("AUX_PGA_Right", NULL, TAIKO_A_RX_AUX_SW_CTL, 6, 0,
4476 taiko_codec_enable_aux_pga, SND_SOC_DAPM_PRE_PMU |
4477 SND_SOC_DAPM_POST_PMD),
4478
4479 /* Lineout, ear and HPH PA Mixers */
4480
4481 SND_SOC_DAPM_MIXER("EAR_PA_MIXER", SND_SOC_NOPM, 0, 0,
4482 ear_pa_mix, ARRAY_SIZE(ear_pa_mix)),
4483
4484 SND_SOC_DAPM_MIXER("HPHL_PA_MIXER", SND_SOC_NOPM, 0, 0,
4485 hphl_pa_mix, ARRAY_SIZE(hphl_pa_mix)),
4486
4487 SND_SOC_DAPM_MIXER("HPHR_PA_MIXER", SND_SOC_NOPM, 0, 0,
4488 hphr_pa_mix, ARRAY_SIZE(hphr_pa_mix)),
4489
4490 SND_SOC_DAPM_MIXER("LINEOUT1_PA_MIXER", SND_SOC_NOPM, 0, 0,
4491 lineout1_pa_mix, ARRAY_SIZE(lineout1_pa_mix)),
4492
4493 SND_SOC_DAPM_MIXER("LINEOUT2_PA_MIXER", SND_SOC_NOPM, 0, 0,
4494 lineout2_pa_mix, ARRAY_SIZE(lineout2_pa_mix)),
4495
4496 SND_SOC_DAPM_MIXER("LINEOUT3_PA_MIXER", SND_SOC_NOPM, 0, 0,
4497 lineout3_pa_mix, ARRAY_SIZE(lineout3_pa_mix)),
4498
4499 SND_SOC_DAPM_MIXER("LINEOUT4_PA_MIXER", SND_SOC_NOPM, 0, 0,
4500 lineout4_pa_mix, ARRAY_SIZE(lineout4_pa_mix)),
4501
4502};
4503
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4504static irqreturn_t taiko_slimbus_irq(int irq, void *data)
4505{
4506 struct taiko_priv *priv = data;
4507 struct snd_soc_codec *codec = priv->codec;
Joonwoo Park9bbb4d12012-11-09 19:58:11 -0800[diff] [blame]4508 unsigned long status = 0;
4509 int i, j, port_id, k;
4510 u32 bit;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4511 u8 val;
Joonwoo Park9bbb4d12012-11-09 19:58:11 -0800[diff] [blame]4512 bool tx, cleared;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4513
Joonwoo Park9bbb4d12012-11-09 19:58:11 -0800[diff] [blame]4514 for (i = TAIKO_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
4515 i <= TAIKO_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
4516 val = wcd9xxx_interface_reg_read(codec->control_data, i);
4517 status |= ((u32)val << (8 * j));
4518 }
4519
4520 for_each_set_bit(j, &status, 32) {
4521 tx = (j >= 16 ? true : false);
4522 port_id = (tx ? j - 16 : j);
4523 val = wcd9xxx_interface_reg_read(codec->control_data,
4524 TAIKO_SLIM_PGD_PORT_INT_RX_SOURCE0 + j);
4525 if (val & TAIKO_SLIM_IRQ_OVERFLOW)
4526 pr_err_ratelimited(
4527 "%s: overflow error on %s port %d, value %x\n",
4528 __func__, (tx ? "TX" : "RX"), port_id, val);
4529 if (val & TAIKO_SLIM_IRQ_UNDERFLOW)
4530 pr_err_ratelimited(
4531 "%s: underflow error on %s port %d, value %x\n",
4532 __func__, (tx ? "TX" : "RX"), port_id, val);
4533 if (val & TAIKO_SLIM_IRQ_PORT_CLOSED) {
4534 /*
4535 * INT SOURCE register starts from RX to TX
4536 * but port number in the ch_mask is in opposite way
4537 */
4538 bit = (tx ? j - 16 : j + 16);
4539 pr_debug("%s: %s port %d closed value %x, bit %u\n",
4540 __func__, (tx ? "TX" : "RX"), port_id, val,
4541 bit);
4542 for (k = 0, cleared = false; k < NUM_CODEC_DAIS; k++) {
4543 pr_debug("%s: priv->dai[%d].ch_mask = 0x%lx\n",
4544 __func__, k, priv->dai[k].ch_mask);
4545 if (test_and_clear_bit(bit,
4546 &priv->dai[k].ch_mask)) {
4547 cleared = true;
4548 if (!priv->dai[k].ch_mask)
4549 wake_up(&priv->dai[k].dai_wait);
4550 /*
4551 * There are cases when multiple DAIs
4552 * might be using the same slimbus
4553 * channel. Hence don't break here.
4554 */
4555 }
4556 }
4557 WARN(!cleared,
4558 "Couldn't find slimbus %s port %d for closing\n",
4559 (tx ? "TX" : "RX"), port_id);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4560 }
4561 wcd9xxx_interface_reg_write(codec->control_data,
Joonwoo Park9bbb4d12012-11-09 19:58:11 -0800[diff] [blame]4562 TAIKO_SLIM_PGD_PORT_INT_CLR_RX_0 +
4563 (j / 8),
4564 1 << (j % 8));
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]4565 }
Joonwoo Park9bbb4d12012-11-09 19:58:11 -0800[diff] [blame]4566
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4567 return IRQ_HANDLED;
4568}
4569
4570static int taiko_handle_pdata(struct taiko_priv *taiko)
4571{
4572 struct snd_soc_codec *codec = taiko->codec;
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]4573 struct wcd9xxx_pdata *pdata = taiko->resmgr.pdata;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4574 int k1, k2, k3, rc = 0;
Kiran Kandi725f8492012-08-06 13:45:16 -0700[diff] [blame]4575 u8 leg_mode, txfe_bypass, txfe_buff, flag;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4576 u8 i = 0, j = 0;
4577 u8 val_txfe = 0, value = 0;
4578
4579 if (!pdata) {
Kiran Kandi725f8492012-08-06 13:45:16 -0700[diff] [blame]4580 pr_err("%s: NULL pdata\n", __func__);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4581 rc = -ENODEV;
4582 goto done;
4583 }
4584
Kiran Kandi725f8492012-08-06 13:45:16 -0700[diff] [blame]4585 leg_mode = pdata->amic_settings.legacy_mode;
4586 txfe_bypass = pdata->amic_settings.txfe_enable;
4587 txfe_buff = pdata->amic_settings.txfe_buff;
4588 flag = pdata->amic_settings.use_pdata;
4589
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4590 /* Make sure settings are correct */
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]4591 if ((pdata->micbias.ldoh_v > WCD9XXX_LDOH_3P0_V) ||
4592 (pdata->micbias.bias1_cfilt_sel > WCD9XXX_CFILT3_SEL) ||
4593 (pdata->micbias.bias2_cfilt_sel > WCD9XXX_CFILT3_SEL) ||
4594 (pdata->micbias.bias3_cfilt_sel > WCD9XXX_CFILT3_SEL) ||
4595 (pdata->micbias.bias4_cfilt_sel > WCD9XXX_CFILT3_SEL)) {
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4596 rc = -EINVAL;
4597 goto done;
4598 }
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4599 /* figure out k value */
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]4600 k1 = wcd9xxx_resmgr_get_k_val(&taiko->resmgr, pdata->micbias.cfilt1_mv);
4601 k2 = wcd9xxx_resmgr_get_k_val(&taiko->resmgr, pdata->micbias.cfilt2_mv);
4602 k3 = wcd9xxx_resmgr_get_k_val(&taiko->resmgr, pdata->micbias.cfilt3_mv);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4603
4604 if (IS_ERR_VALUE(k1) || IS_ERR_VALUE(k2) || IS_ERR_VALUE(k3)) {
4605 rc = -EINVAL;
4606 goto done;
4607 }
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4608 /* Set voltage level and always use LDO */
4609 snd_soc_update_bits(codec, TAIKO_A_LDO_H_MODE_1, 0x0C,
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]4610 (pdata->micbias.ldoh_v << 2));
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4611
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]4612 snd_soc_update_bits(codec, TAIKO_A_MICB_CFILT_1_VAL, 0xFC, (k1 << 2));
4613 snd_soc_update_bits(codec, TAIKO_A_MICB_CFILT_2_VAL, 0xFC, (k2 << 2));
4614 snd_soc_update_bits(codec, TAIKO_A_MICB_CFILT_3_VAL, 0xFC, (k3 << 2));
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4615
4616 snd_soc_update_bits(codec, TAIKO_A_MICB_1_CTL, 0x60,
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]4617 (pdata->micbias.bias1_cfilt_sel << 5));
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4618 snd_soc_update_bits(codec, TAIKO_A_MICB_2_CTL, 0x60,
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]4619 (pdata->micbias.bias2_cfilt_sel << 5));
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4620 snd_soc_update_bits(codec, TAIKO_A_MICB_3_CTL, 0x60,
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]4621 (pdata->micbias.bias3_cfilt_sel << 5));
4622 snd_soc_update_bits(codec, taiko->resmgr.reg_addr->micb_4_ctl, 0x60,
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4623 (pdata->micbias.bias4_cfilt_sel << 5));
4624
4625 for (i = 0; i < 6; j++, i += 2) {
4626 if (flag & (0x01 << i)) {
4627 value = (leg_mode & (0x01 << i)) ? 0x10 : 0x00;
4628 val_txfe = (txfe_bypass & (0x01 << i)) ? 0x20 : 0x00;
4629 val_txfe = val_txfe |
4630 ((txfe_buff & (0x01 << i)) ? 0x10 : 0x00);
4631 snd_soc_update_bits(codec, TAIKO_A_TX_1_2_EN + j * 10,
4632 0x10, value);
4633 snd_soc_update_bits(codec,
4634 TAIKO_A_TX_1_2_TEST_EN + j * 10,
4635 0x30, val_txfe);
4636 }
4637 if (flag & (0x01 << (i + 1))) {
4638 value = (leg_mode & (0x01 << (i + 1))) ? 0x01 : 0x00;
4639 val_txfe = (txfe_bypass &
4640 (0x01 << (i + 1))) ? 0x02 : 0x00;
4641 val_txfe |= (txfe_buff &
4642 (0x01 << (i + 1))) ? 0x01 : 0x00;
4643 snd_soc_update_bits(codec, TAIKO_A_TX_1_2_EN + j * 10,
4644 0x01, value);
4645 snd_soc_update_bits(codec,
4646 TAIKO_A_TX_1_2_TEST_EN + j * 10,
4647 0x03, val_txfe);
4648 }
4649 }
4650 if (flag & 0x40) {
4651 value = (leg_mode & 0x40) ? 0x10 : 0x00;
4652 value = value | ((txfe_bypass & 0x40) ? 0x02 : 0x00);
4653 value = value | ((txfe_buff & 0x40) ? 0x01 : 0x00);
4654 snd_soc_update_bits(codec, TAIKO_A_TX_7_MBHC_EN,
4655 0x13, value);
4656 }
4657
4658 if (pdata->ocp.use_pdata) {
4659 /* not defined in CODEC specification */
4660 if (pdata->ocp.hph_ocp_limit == 1 ||
4661 pdata->ocp.hph_ocp_limit == 5) {
4662 rc = -EINVAL;
4663 goto done;
4664 }
4665 snd_soc_update_bits(codec, TAIKO_A_RX_COM_OCP_CTL,
4666 0x0F, pdata->ocp.num_attempts);
4667 snd_soc_write(codec, TAIKO_A_RX_COM_OCP_COUNT,
4668 ((pdata->ocp.run_time << 4) | pdata->ocp.wait_time));
4669 snd_soc_update_bits(codec, TAIKO_A_RX_HPH_OCP_CTL,
4670 0xE0, (pdata->ocp.hph_ocp_limit << 5));
4671 }
4672
4673 for (i = 0; i < ARRAY_SIZE(pdata->regulator); i++) {
4674 if (!strncmp(pdata->regulator[i].name, "CDC_VDDA_RX", 11)) {
4675 if (pdata->regulator[i].min_uV == 1800000 &&
4676 pdata->regulator[i].max_uV == 1800000) {
4677 snd_soc_write(codec, TAIKO_A_BIAS_REF_CTL,
4678 0x1C);
4679 } else if (pdata->regulator[i].min_uV == 2200000 &&
4680 pdata->regulator[i].max_uV == 2200000) {
4681 snd_soc_write(codec, TAIKO_A_BIAS_REF_CTL,
4682 0x1E);
4683 } else {
4684 pr_err("%s: unsupported CDC_VDDA_RX voltage\n"
4685 "min %d, max %d\n", __func__,
4686 pdata->regulator[i].min_uV,
4687 pdata->regulator[i].max_uV);
4688 rc = -EINVAL;
4689 }
4690 break;
4691 }
4692 }
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]4693
Joonwoo Park1848c762012-10-18 13:16:01 -0700[diff] [blame]4694 /* Set micbias capless mode with tail current */
4695 value = (pdata->micbias.bias1_cap_mode == MICBIAS_EXT_BYP_CAP ?
4696 0x00 : 0x16);
4697 snd_soc_update_bits(codec, TAIKO_A_MICB_1_CTL, 0x1E, value);
4698 value = (pdata->micbias.bias2_cap_mode == MICBIAS_EXT_BYP_CAP ?
4699 0x00 : 0x16);
4700 snd_soc_update_bits(codec, TAIKO_A_MICB_2_CTL, 0x1E, value);
4701 value = (pdata->micbias.bias3_cap_mode == MICBIAS_EXT_BYP_CAP ?
4702 0x00 : 0x16);
4703 snd_soc_update_bits(codec, TAIKO_A_MICB_3_CTL, 0x1E, value);
4704 value = (pdata->micbias.bias4_cap_mode == MICBIAS_EXT_BYP_CAP ?
4705 0x00 : 0x16);
4706 snd_soc_update_bits(codec, TAIKO_A_MICB_4_CTL, 0x1E, value);
4707
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4708done:
4709 return rc;
4710}
4711
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]4712static const struct wcd9xxx_reg_mask_val taiko_reg_defaults[] = {
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4713
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]4714 /* set MCLk to 9.6 */
Gopikrishnaiah Anandana8aec1f2013-01-23 14:26:27 -0500[diff] [blame]4715 TAIKO_REG_VAL(TAIKO_A_CHIP_CTL, 0x02),
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]4716 TAIKO_REG_VAL(TAIKO_A_CDC_CLK_POWER_CTL, 0x03),
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4717
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]4718 /* EAR PA deafults */
4719 TAIKO_REG_VAL(TAIKO_A_RX_EAR_CMBUFF, 0x05),
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4720
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]4721 /* RX deafults */
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4722 TAIKO_REG_VAL(TAIKO_A_CDC_RX1_B5_CTL, 0x78),
4723 TAIKO_REG_VAL(TAIKO_A_CDC_RX2_B5_CTL, 0x78),
4724 TAIKO_REG_VAL(TAIKO_A_CDC_RX3_B5_CTL, 0x78),
4725 TAIKO_REG_VAL(TAIKO_A_CDC_RX4_B5_CTL, 0x78),
4726 TAIKO_REG_VAL(TAIKO_A_CDC_RX5_B5_CTL, 0x78),
4727 TAIKO_REG_VAL(TAIKO_A_CDC_RX6_B5_CTL, 0x78),
4728 TAIKO_REG_VAL(TAIKO_A_CDC_RX7_B5_CTL, 0x78),
4729
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]4730 /* RX1 and RX2 defaults */
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4731 TAIKO_REG_VAL(TAIKO_A_CDC_RX1_B6_CTL, 0xA0),
4732 TAIKO_REG_VAL(TAIKO_A_CDC_RX2_B6_CTL, 0xA0),
4733
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]4734 /* RX3 to RX7 defaults */
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4735 TAIKO_REG_VAL(TAIKO_A_CDC_RX3_B6_CTL, 0x80),
4736 TAIKO_REG_VAL(TAIKO_A_CDC_RX4_B6_CTL, 0x80),
4737 TAIKO_REG_VAL(TAIKO_A_CDC_RX5_B6_CTL, 0x80),
4738 TAIKO_REG_VAL(TAIKO_A_CDC_RX6_B6_CTL, 0x80),
4739 TAIKO_REG_VAL(TAIKO_A_CDC_RX7_B6_CTL, 0x80),
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4740};
4741
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]4742static const struct wcd9xxx_reg_mask_val taiko_1_0_reg_defaults[] = {
Kiran Kandi7b7d2ff2012-09-14 14:52:14 -0700[diff] [blame]4743 /*
4744 * The following only need to be written for Taiko 1.0 parts.
4745 * Taiko 2.0 will have appropriate defaults for these registers.
4746 */
Joonwoo Park559a5bf2013-02-15 14:46:36 -0800[diff] [blame]4747
4748 /* BUCK default */
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]4749 TAIKO_REG_VAL(WCD9XXX_A_BUCK_CTRL_CCL_4, 0x50),
4750
4751 /* Required defaults for class H operation */
4752 TAIKO_REG_VAL(TAIKO_A_RX_HPH_CHOP_CTL, 0xF4),
4753 TAIKO_REG_VAL(TAIKO_A_BIAS_CURR_CTL_2, 0x08),
4754 TAIKO_REG_VAL(WCD9XXX_A_BUCK_CTRL_CCL_1, 0x5B),
4755 TAIKO_REG_VAL(WCD9XXX_A_BUCK_CTRL_CCL_3, 0x60),
Joonwoo Park559a5bf2013-02-15 14:46:36 -0800[diff] [blame]4756
Kiran Kandi7b7d2ff2012-09-14 14:52:14 -0700[diff] [blame]4757 /* Choose max non-overlap time for NCP */
4758 TAIKO_REG_VAL(TAIKO_A_NCP_CLK, 0xFC),
4759 /* Use 25mV/50mV for deltap/m to reduce ripple */
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]4760 TAIKO_REG_VAL(WCD9XXX_A_BUCK_CTRL_VCL_1, 0x08),
Kiran Kandi7b7d2ff2012-09-14 14:52:14 -0700[diff] [blame]4761 /*
4762 * Set DISABLE_MODE_SEL<1:0> to 0b10 (disable PWM in auto mode).
4763 * Note that the other bits of this register will be changed during
4764 * Rx PA bring up.
4765 */
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]4766 TAIKO_REG_VAL(WCD9XXX_A_BUCK_MODE_3, 0xCE),
Kiran Kandi7b7d2ff2012-09-14 14:52:14 -0700[diff] [blame]4767 /* Reduce HPH DAC bias to 70% */
4768 TAIKO_REG_VAL(TAIKO_A_RX_HPH_BIAS_PA, 0x7A),
4769 /*Reduce EAR DAC bias to 70% */
4770 TAIKO_REG_VAL(TAIKO_A_RX_EAR_BIAS_PA, 0x76),
4771 /* Reduce LINE DAC bias to 70% */
4772 TAIKO_REG_VAL(TAIKO_A_RX_LINE_BIAS_PA, 0x78),
Joonwoo Parkd87ec4c2012-10-30 15:44:18 -0700[diff] [blame]4773
4774 /*
4775 * There is a diode to pull down the micbias while doing
4776 * insertion detection. This diode can cause leakage.
4777 * Set bit 0 to 1 to prevent leakage.
4778 * Setting this bit of micbias 2 prevents leakage for all other micbias.
4779 */
4780 TAIKO_REG_VAL(TAIKO_A_MICB_2_MBHC, 0x41),
Joonwoo Park3c7bca62012-10-31 12:44:23 -0700[diff] [blame]4781
4782 /* Disable TX7 internal biasing path which can cause leakage */
4783 TAIKO_REG_VAL(TAIKO_A_TX_SUP_SWITCH_CTRL_1, 0xBF),
Joonwoo Park03604052012-11-06 18:40:25 -0800[diff] [blame]4784 /* Enable MICB 4 VDDIO switch to prevent leakage */
4785 TAIKO_REG_VAL(TAIKO_A_MICB_4_MBHC, 0x81),
Joonwoo Park125cd4e2012-12-11 15:16:11 -0800[diff] [blame]4786
4787 /* Close leakage on the spkdrv */
4788 TAIKO_REG_VAL(TAIKO_A_SPKR_DRV_DBG_PWRSTG, 0x24),
Kiran Kandi7b7d2ff2012-09-14 14:52:14 -0700[diff] [blame]4789};
4790
Joonwoo Park559a5bf2013-02-15 14:46:36 -0800[diff] [blame]4791/*
4792 * Don't update TAIKO_A_CHIP_CTL, TAIKO_A_BUCK_CTRL_CCL_1 and
4793 * TAIKO_A_RX_EAR_CMBUFF as those are updated in taiko_reg_defaults
4794 */
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]4795static const struct wcd9xxx_reg_mask_val taiko_2_0_reg_defaults[] = {
Joonwoo Park559a5bf2013-02-15 14:46:36 -0800[diff] [blame]4796 TAIKO_REG_VAL(TAIKO_A_CDC_TX_1_GAIN, 0x2),
4797 TAIKO_REG_VAL(TAIKO_A_CDC_TX_2_GAIN, 0x2),
4798 TAIKO_REG_VAL(TAIKO_A_CDC_TX_1_2_ADC_IB, 0x44),
4799 TAIKO_REG_VAL(TAIKO_A_CDC_TX_3_GAIN, 0x2),
4800 TAIKO_REG_VAL(TAIKO_A_CDC_TX_4_GAIN, 0x2),
4801 TAIKO_REG_VAL(TAIKO_A_CDC_TX_3_4_ADC_IB, 0x44),
4802 TAIKO_REG_VAL(TAIKO_A_CDC_TX_5_GAIN, 0x2),
4803 TAIKO_REG_VAL(TAIKO_A_CDC_TX_6_GAIN, 0x2),
4804 TAIKO_REG_VAL(TAIKO_A_CDC_TX_5_6_ADC_IB, 0x44),
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]4805 TAIKO_REG_VAL(WCD9XXX_A_BUCK_MODE_3, 0xCE),
4806 TAIKO_REG_VAL(WCD9XXX_A_BUCK_CTRL_VCL_1, 0x8),
4807 TAIKO_REG_VAL(WCD9XXX_A_BUCK_CTRL_CCL_4, 0x51),
Joonwoo Park559a5bf2013-02-15 14:46:36 -0800[diff] [blame]4808 TAIKO_REG_VAL(TAIKO_A_NCP_DTEST, 0x10),
4809 TAIKO_REG_VAL(TAIKO_A_RX_HPH_CHOP_CTL, 0xA4),
4810 TAIKO_REG_VAL(TAIKO_A_RX_HPH_BIAS_PA, 0x7A),
4811 TAIKO_REG_VAL(TAIKO_A_RX_HPH_OCP_CTL, 0x69),
4812 TAIKO_REG_VAL(TAIKO_A_RX_HPH_CNP_WG_CTL, 0xDA),
4813 TAIKO_REG_VAL(TAIKO_A_RX_HPH_CNP_WG_TIME, 0x15),
4814 TAIKO_REG_VAL(TAIKO_A_RX_EAR_BIAS_PA, 0x76),
4815 TAIKO_REG_VAL(TAIKO_A_RX_EAR_CNP, 0xC0),
4816 TAIKO_REG_VAL(TAIKO_A_RX_LINE_BIAS_PA, 0x78),
4817 TAIKO_REG_VAL(TAIKO_A_RX_LINE_1_TEST, 0x2),
4818 TAIKO_REG_VAL(TAIKO_A_RX_LINE_2_TEST, 0x2),
4819 TAIKO_REG_VAL(TAIKO_A_RX_LINE_3_TEST, 0x2),
4820 TAIKO_REG_VAL(TAIKO_A_RX_LINE_4_TEST, 0x2),
4821 TAIKO_REG_VAL(TAIKO_A_SPKR_DRV_OCP_CTL, 0x97),
4822 TAIKO_REG_VAL(TAIKO_A_SPKR_DRV_CLIP_DET, 0x1),
4823 TAIKO_REG_VAL(TAIKO_A_SPKR_DRV_IEC, 0x0),
4824 TAIKO_REG_VAL(TAIKO_A_CDC_TX1_MUX_CTL, 0x48),
4825 TAIKO_REG_VAL(TAIKO_A_CDC_TX2_MUX_CTL, 0x48),
4826 TAIKO_REG_VAL(TAIKO_A_CDC_TX3_MUX_CTL, 0x48),
4827 TAIKO_REG_VAL(TAIKO_A_CDC_TX4_MUX_CTL, 0x48),
4828 TAIKO_REG_VAL(TAIKO_A_CDC_TX5_MUX_CTL, 0x48),
4829 TAIKO_REG_VAL(TAIKO_A_CDC_TX6_MUX_CTL, 0x48),
4830 TAIKO_REG_VAL(TAIKO_A_CDC_TX7_MUX_CTL, 0x48),
4831 TAIKO_REG_VAL(TAIKO_A_CDC_TX8_MUX_CTL, 0x48),
4832 TAIKO_REG_VAL(TAIKO_A_CDC_TX9_MUX_CTL, 0x48),
4833 TAIKO_REG_VAL(TAIKO_A_CDC_TX10_MUX_CTL, 0x48),
4834 TAIKO_REG_VAL(TAIKO_A_CDC_RX1_B4_CTL, 0x8),
4835 TAIKO_REG_VAL(TAIKO_A_CDC_VBAT_GAIN_UPD_MON, 0x0),
4836 TAIKO_REG_VAL(TAIKO_A_CDC_PA_RAMP_B1_CTL, 0x0),
4837 TAIKO_REG_VAL(TAIKO_A_CDC_PA_RAMP_B2_CTL, 0x0),
4838 TAIKO_REG_VAL(TAIKO_A_CDC_PA_RAMP_B3_CTL, 0x0),
4839 TAIKO_REG_VAL(TAIKO_A_CDC_PA_RAMP_B4_CTL, 0x0),
4840 TAIKO_REG_VAL(TAIKO_A_CDC_SPKR_CLIPDET_B1_CTL, 0x0),
4841 TAIKO_REG_VAL(TAIKO_A_CDC_COMP0_B4_CTL, 0x37),
4842 TAIKO_REG_VAL(TAIKO_A_CDC_COMP0_B5_CTL, 0x7f),
4843};
4844
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4845static void taiko_update_reg_defaults(struct snd_soc_codec *codec)
4846{
4847 u32 i;
Kiran Kandi7b7d2ff2012-09-14 14:52:14 -0700[diff] [blame]4848 struct wcd9xxx *taiko_core = dev_get_drvdata(codec->dev->parent);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4849
Kiran Kandi7b7d2ff2012-09-14 14:52:14 -0700[diff] [blame]4850 for (i = 0; i < ARRAY_SIZE(taiko_reg_defaults); i++)
4851 snd_soc_write(codec, taiko_reg_defaults[i].reg,
Joonwoo Park559a5bf2013-02-15 14:46:36 -0800[diff] [blame]4852 taiko_reg_defaults[i].val);
Kiran Kandi7b7d2ff2012-09-14 14:52:14 -0700[diff] [blame]4853
4854 if (TAIKO_IS_1_0(taiko_core->version)) {
4855 for (i = 0; i < ARRAY_SIZE(taiko_1_0_reg_defaults); i++)
4856 snd_soc_write(codec, taiko_1_0_reg_defaults[i].reg,
Joonwoo Park559a5bf2013-02-15 14:46:36 -0800[diff] [blame]4857 taiko_1_0_reg_defaults[i].val);
4858 if (spkr_drv_wrnd == 1)
4859 snd_soc_write(codec, TAIKO_A_SPKR_DRV_EN, 0xEF);
4860 } else {
4861 for (i = 0; i < ARRAY_SIZE(taiko_2_0_reg_defaults); i++)
4862 snd_soc_write(codec, taiko_2_0_reg_defaults[i].reg,
4863 taiko_2_0_reg_defaults[i].val);
Joonwoo Park125cd4e2012-12-11 15:16:11 -0800[diff] [blame]4864 spkr_drv_wrnd = -1;
Joonwoo Park559a5bf2013-02-15 14:46:36 -0800[diff] [blame]4865 }
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4866}
4867
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]4868static const struct wcd9xxx_reg_mask_val taiko_codec_reg_init_val[] = {
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4869 /* Initialize current threshold to 350MA
4870 * number of wait and run cycles to 4096
4871 */
Kiran Kandi7b7d2ff2012-09-14 14:52:14 -0700[diff] [blame]4872 {TAIKO_A_RX_HPH_OCP_CTL, 0xE1, 0x61},
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4873 {TAIKO_A_RX_COM_OCP_COUNT, 0xFF, 0xFF},
Patrick Lai92833bf2012-12-01 10:31:35 -0800[diff] [blame]4874 {TAIKO_A_RX_HPH_L_TEST, 0x01, 0x01},
4875 {TAIKO_A_RX_HPH_R_TEST, 0x01, 0x01},
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4876
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4877 /* Initialize gain registers to use register gain */
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]4878 {TAIKO_A_RX_HPH_L_GAIN, 0x20, 0x20},
4879 {TAIKO_A_RX_HPH_R_GAIN, 0x20, 0x20},
4880 {TAIKO_A_RX_LINE_1_GAIN, 0x20, 0x20},
4881 {TAIKO_A_RX_LINE_2_GAIN, 0x20, 0x20},
4882 {TAIKO_A_RX_LINE_3_GAIN, 0x20, 0x20},
4883 {TAIKO_A_RX_LINE_4_GAIN, 0x20, 0x20},
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]4884 {TAIKO_A_SPKR_DRV_GAIN, 0x04, 0x04},
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4885
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4886 /* Use 16 bit sample size for TX1 to TX6 */
4887 {TAIKO_A_CDC_CONN_TX_SB_B1_CTL, 0x30, 0x20},
4888 {TAIKO_A_CDC_CONN_TX_SB_B2_CTL, 0x30, 0x20},
4889 {TAIKO_A_CDC_CONN_TX_SB_B3_CTL, 0x30, 0x20},
4890 {TAIKO_A_CDC_CONN_TX_SB_B4_CTL, 0x30, 0x20},
4891 {TAIKO_A_CDC_CONN_TX_SB_B5_CTL, 0x30, 0x20},
4892 {TAIKO_A_CDC_CONN_TX_SB_B6_CTL, 0x30, 0x20},
4893
4894 /* Use 16 bit sample size for TX7 to TX10 */
4895 {TAIKO_A_CDC_CONN_TX_SB_B7_CTL, 0x60, 0x40},
4896 {TAIKO_A_CDC_CONN_TX_SB_B8_CTL, 0x60, 0x40},
4897 {TAIKO_A_CDC_CONN_TX_SB_B9_CTL, 0x60, 0x40},
4898 {TAIKO_A_CDC_CONN_TX_SB_B10_CTL, 0x60, 0x40},
4899
4900 /* Use 16 bit sample size for RX */
4901 {TAIKO_A_CDC_CONN_RX_SB_B1_CTL, 0xFF, 0xAA},
Kiran Kandi7b7d2ff2012-09-14 14:52:14 -0700[diff] [blame]4902 {TAIKO_A_CDC_CONN_RX_SB_B2_CTL, 0xFF, 0x2A},
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4903
4904 /*enable HPF filter for TX paths */
4905 {TAIKO_A_CDC_TX1_MUX_CTL, 0x8, 0x0},
4906 {TAIKO_A_CDC_TX2_MUX_CTL, 0x8, 0x0},
4907 {TAIKO_A_CDC_TX3_MUX_CTL, 0x8, 0x0},
4908 {TAIKO_A_CDC_TX4_MUX_CTL, 0x8, 0x0},
4909 {TAIKO_A_CDC_TX5_MUX_CTL, 0x8, 0x0},
4910 {TAIKO_A_CDC_TX6_MUX_CTL, 0x8, 0x0},
4911 {TAIKO_A_CDC_TX7_MUX_CTL, 0x8, 0x0},
4912 {TAIKO_A_CDC_TX8_MUX_CTL, 0x8, 0x0},
4913 {TAIKO_A_CDC_TX9_MUX_CTL, 0x8, 0x0},
4914 {TAIKO_A_CDC_TX10_MUX_CTL, 0x8, 0x0},
4915
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]4916 /* config Decimator for DMIC CLK_MODE_1(3.2Mhz@9.6Mhz mclk) */
4917 {TAIKO_A_CDC_TX1_DMIC_CTL, 0x7, 0x1},
4918 {TAIKO_A_CDC_TX2_DMIC_CTL, 0x7, 0x1},
4919 {TAIKO_A_CDC_TX3_DMIC_CTL, 0x7, 0x1},
4920 {TAIKO_A_CDC_TX4_DMIC_CTL, 0x7, 0x1},
4921 {TAIKO_A_CDC_TX5_DMIC_CTL, 0x7, 0x1},
4922 {TAIKO_A_CDC_TX6_DMIC_CTL, 0x7, 0x1},
4923 {TAIKO_A_CDC_TX7_DMIC_CTL, 0x7, 0x1},
4924 {TAIKO_A_CDC_TX8_DMIC_CTL, 0x7, 0x1},
4925 {TAIKO_A_CDC_TX9_DMIC_CTL, 0x7, 0x1},
4926 {TAIKO_A_CDC_TX10_DMIC_CTL, 0x7, 0x1},
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4927
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]4928 /* config DMIC clk to CLK_MODE_1 (3.2Mhz@9.6Mhz mclk) */
4929 {TAIKO_A_CDC_CLK_DMIC_B1_CTL, 0xEE, 0x22},
4930 {TAIKO_A_CDC_CLK_DMIC_B2_CTL, 0x0E, 0x02},
4931
Joonwoo Parkc7731432012-10-17 12:41:44 -0700[diff] [blame]4932 /* Compander zone selection */
4933 {TAIKO_A_CDC_COMP0_B4_CTL, 0x3F, 0x37},
4934 {TAIKO_A_CDC_COMP1_B4_CTL, 0x3F, 0x37},
4935 {TAIKO_A_CDC_COMP2_B4_CTL, 0x3F, 0x37},
4936 {TAIKO_A_CDC_COMP0_B5_CTL, 0x7F, 0x7F},
4937 {TAIKO_A_CDC_COMP1_B5_CTL, 0x7F, 0x7F},
4938 {TAIKO_A_CDC_COMP2_B5_CTL, 0x7F, 0x7F},
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]4939};
4940
4941static void taiko_codec_init_reg(struct snd_soc_codec *codec)
4942{
4943 u32 i;
4944
4945 for (i = 0; i < ARRAY_SIZE(taiko_codec_reg_init_val); i++)
4946 snd_soc_update_bits(codec, taiko_codec_reg_init_val[i].reg,
4947 taiko_codec_reg_init_val[i].mask,
4948 taiko_codec_reg_init_val[i].val);
4949}
4950
Joonwoo Park7680b9f2012-07-13 11:36:48 -0700[diff] [blame]4951static int taiko_setup_irqs(struct taiko_priv *taiko)
4952{
Joonwoo Park7680b9f2012-07-13 11:36:48 -0700[diff] [blame]4953 int i;
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]4954 int ret = 0;
Joonwoo Park7680b9f2012-07-13 11:36:48 -0700[diff] [blame]4955 struct snd_soc_codec *codec = taiko->codec;
4956
Joonwoo Parkf6574c72012-10-10 17:29:57 -0700[diff] [blame]4957 ret = wcd9xxx_request_irq(codec->control_data, WCD9XXX_IRQ_SLIMBUS,
Joonwoo Park7680b9f2012-07-13 11:36:48 -0700[diff] [blame]4958 taiko_slimbus_irq, "SLIMBUS Slave", taiko);
4959 if (ret) {
4960 pr_err("%s: Failed to request irq %d\n", __func__,
Joonwoo Parkf6574c72012-10-10 17:29:57 -0700[diff] [blame]4961 WCD9XXX_IRQ_SLIMBUS);
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]4962 goto exit;
Joonwoo Park7680b9f2012-07-13 11:36:48 -0700[diff] [blame]4963 }
4964
4965 for (i = 0; i < WCD9XXX_SLIM_NUM_PORT_REG; i++)
4966 wcd9xxx_interface_reg_write(codec->control_data,
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]4967 TAIKO_SLIM_PGD_PORT_INT_EN0 + i,
4968 0xFF);
4969exit:
Joonwoo Park7680b9f2012-07-13 11:36:48 -0700[diff] [blame]4970 return ret;
4971}
4972
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]4973int taiko_hs_detect(struct snd_soc_codec *codec,
4974 struct wcd9xxx_mbhc_config *mbhc_cfg)
4975{
4976 struct taiko_priv *taiko = snd_soc_codec_get_drvdata(codec);
4977 return wcd9xxx_mbhc_start(&taiko->mbhc, mbhc_cfg);
4978}
4979EXPORT_SYMBOL_GPL(taiko_hs_detect);
4980
Ravishankar Sarawadi839fcf32012-11-14 12:13:00 -0800[diff] [blame]4981static int taiko_post_reset_cb(struct wcd9xxx *wcd9xxx)
4982{
4983 int ret = 0;
4984 struct snd_soc_codec *codec;
4985 struct taiko_priv *taiko;
4986
4987 codec = (struct snd_soc_codec *)(wcd9xxx->ssr_priv);
4988 taiko = snd_soc_codec_get_drvdata(codec);
4989 mutex_lock(&codec->mutex);
4990 WCD9XXX_BCL_LOCK(&taiko->resmgr);
Ravishankar Sarawadi839fcf32012-11-14 12:13:00 -0800[diff] [blame]4991
4992 if (codec->reg_def_copy) {
4993 pr_debug("%s: Update ASOC cache", __func__);
4994 kfree(codec->reg_cache);
4995 codec->reg_cache = kmemdup(codec->reg_def_copy,
4996 codec->reg_size, GFP_KERNEL);
4997 }
4998
Ravishankar Sarawadi2293efe2013-01-11 16:37:23 -0800[diff] [blame]4999 wcd9xxx_resmgr_post_ssr(&taiko->resmgr);
5000 if (spkr_drv_wrnd == 1)
5001 snd_soc_update_bits(codec, TAIKO_A_SPKR_DRV_EN, 0x80, 0x80);
5002 WCD9XXX_BCL_UNLOCK(&taiko->resmgr);
5003
Ravishankar Sarawadi839fcf32012-11-14 12:13:00 -0800[diff] [blame]5004 taiko_update_reg_defaults(codec);
5005 taiko_codec_init_reg(codec);
5006 ret = taiko_handle_pdata(taiko);
5007 if (IS_ERR_VALUE(ret))
5008 pr_err("%s: bad pdata\n", __func__);
Ravishankar Sarawadi2293efe2013-01-11 16:37:23 -0800[diff] [blame]5009
5010 wcd9xxx_mbhc_deinit(&taiko->mbhc);
5011 ret = wcd9xxx_mbhc_init(&taiko->mbhc, &taiko->resmgr, codec);
5012 if (ret)
5013 pr_err("%s: mbhc init failed %d\n", __func__, ret);
5014 else
5015 wcd9xxx_mbhc_start(&taiko->mbhc, taiko->mbhc.mbhc_cfg);
Ravishankar Sarawadi839fcf32012-11-14 12:13:00 -0800[diff] [blame]5016 mutex_unlock(&codec->mutex);
5017 return ret;
5018}
5019
5020
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]5021static struct wcd9xxx_reg_address taiko_reg_address = {
5022 .micb_4_mbhc = TAIKO_A_MICB_4_MBHC,
5023 .micb_4_int_rbias = TAIKO_A_MICB_4_INT_RBIAS,
5024 .micb_4_ctl = TAIKO_A_MICB_4_CTL,
5025};
5026
Ravishankar Sarawadi839fcf32012-11-14 12:13:00 -0800[diff] [blame]5027static int wcd9xxx_ssr_register(struct wcd9xxx *control,
5028 int (*post_reset_cb)(struct wcd9xxx *wcd9xxx), void *priv)
5029{
5030 control->post_reset = post_reset_cb;
5031 control->ssr_priv = priv;
5032 return 0;
5033}
5034
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]5035static int taiko_codec_get_buck_mv(struct snd_soc_codec *codec)
5036{
5037 int buck_volt = WCD9XXX_CDC_BUCK_UNSUPPORTED;
5038 struct taiko_priv *taiko = snd_soc_codec_get_drvdata(codec);
5039 struct wcd9xxx_pdata *pdata = taiko->resmgr.pdata;
5040 int i;
5041
5042 for (i = 0; i < ARRAY_SIZE(pdata->regulator); i++) {
5043 if (!strncmp(pdata->regulator[i].name,
5044 WCD9XXX_SUPPLY_BUCK_NAME,
5045 sizeof(WCD9XXX_SUPPLY_BUCK_NAME))) {
5046 buck_volt = pdata->regulator[i].min_uV;
5047 break;
5048 }
5049 }
5050 return buck_volt;
5051}
5052
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]5053static int taiko_codec_probe(struct snd_soc_codec *codec)
5054{
5055 struct wcd9xxx *control;
5056 struct taiko_priv *taiko;
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]5057 struct wcd9xxx_pdata *pdata;
5058 struct wcd9xxx *wcd9xxx;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]5059 struct snd_soc_dapm_context *dapm = &codec->dapm;
5060 int ret = 0;
5061 int i;
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]5062 void *ptr = NULL;
Joonwoo Park559a5bf2013-02-15 14:46:36 -0800[diff] [blame]5063 struct wcd9xxx *core = dev_get_drvdata(codec->dev->parent);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]5064
5065 codec->control_data = dev_get_drvdata(codec->dev->parent);
5066 control = codec->control_data;
5067
Ravishankar Sarawadi839fcf32012-11-14 12:13:00 -0800[diff] [blame]5068 wcd9xxx_ssr_register(control, taiko_post_reset_cb, (void *)codec);
5069
Kiran Kandi4c56c592012-07-25 11:04:55 -0700[diff] [blame]5070 dev_info(codec->dev, "%s()\n", __func__);
5071
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]5072 taiko = kzalloc(sizeof(struct taiko_priv), GFP_KERNEL);
5073 if (!taiko) {
5074 dev_err(codec->dev, "Failed to allocate private data\n");
5075 return -ENOMEM;
5076 }
5077 for (i = 0 ; i < NUM_DECIMATORS; i++) {
5078 tx_hpf_work[i].taiko = taiko;
5079 tx_hpf_work[i].decimator = i + 1;
5080 INIT_DELAYED_WORK(&tx_hpf_work[i].dwork,
5081 tx_hpf_corner_freq_callback);
5082 }
5083
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]5084
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]5085 snd_soc_codec_set_drvdata(codec, taiko);
5086
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]5087
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]5088 /* codec resmgr module init */
5089 wcd9xxx = codec->control_data;
5090 pdata = dev_get_platdata(codec->dev->parent);
5091 ret = wcd9xxx_resmgr_init(&taiko->resmgr, codec, wcd9xxx, pdata,
5092 &taiko_reg_address);
5093 if (ret) {
5094 pr_err("%s: wcd9xxx init failed %d\n", __func__, ret);
5095 return ret;
5096 }
5097
Bhalchandra Gajare87fef4c2013-02-19 14:57:03 -0800[diff] [blame]5098 taiko->clsh_d.buck_mv = taiko_codec_get_buck_mv(codec);
5099 wcd9xxx_clsh_init(&taiko->clsh_d);
5100
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]5101 /* init and start mbhc */
5102 ret = wcd9xxx_mbhc_init(&taiko->mbhc, &taiko->resmgr, codec);
5103 if (ret) {
5104 pr_err("%s: mbhc init failed %d\n", __func__, ret);
5105 return ret;
5106 }
5107
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]5108 taiko->codec = codec;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]5109 for (i = 0; i < COMPANDER_MAX; i++) {
5110 taiko->comp_enabled[i] = 0;
5111 taiko->comp_fs[i] = COMPANDER_FS_48KHZ;
5112 }
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]5113 taiko->intf_type = wcd9xxx_get_intf_type();
5114 taiko->aux_pga_cnt = 0;
5115 taiko->aux_l_gain = 0x1F;
5116 taiko->aux_r_gain = 0x1F;
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]5117 taiko_update_reg_defaults(codec);
Venkat Sudhira50a3762012-11-26 12:12:15 -0800[diff] [blame]5118 pr_debug("%s: MCLK Rate = %x\n", __func__, wcd9xxx->mclk_rate);
5119 if (wcd9xxx->mclk_rate == TAIKO_MCLK_CLK_12P288MHZ)
Venkat Sudhir16d95e62013-02-04 16:57:33 -0800[diff] [blame]5120 snd_soc_update_bits(codec, TAIKO_A_CHIP_CTL, 0x06, 0x0);
Venkat Sudhira50a3762012-11-26 12:12:15 -0800[diff] [blame]5121 else if (wcd9xxx->mclk_rate == TAIKO_MCLK_CLK_9P6HZ)
Venkat Sudhir16d95e62013-02-04 16:57:33 -0800[diff] [blame]5122 snd_soc_update_bits(codec, TAIKO_A_CHIP_CTL, 0x06, 0x2);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]5123 taiko_codec_init_reg(codec);
5124 ret = taiko_handle_pdata(taiko);
5125 if (IS_ERR_VALUE(ret)) {
5126 pr_err("%s: bad pdata\n", __func__);
5127 goto err_pdata;
5128 }
5129
Joonwoo Park125cd4e2012-12-11 15:16:11 -0800[diff] [blame]5130 if (spkr_drv_wrnd > 0) {
5131 WCD9XXX_BCL_LOCK(&taiko->resmgr);
5132 wcd9xxx_resmgr_get_bandgap(&taiko->resmgr,
5133 WCD9XXX_BANDGAP_AUDIO_MODE);
5134 WCD9XXX_BCL_UNLOCK(&taiko->resmgr);
5135 }
5136
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]5137 ptr = kmalloc((sizeof(taiko_rx_chs) +
5138 sizeof(taiko_tx_chs)), GFP_KERNEL);
5139 if (!ptr) {
5140 pr_err("%s: no mem for slim chan ctl data\n", __func__);
5141 ret = -ENOMEM;
5142 goto err_nomem_slimch;
5143 }
5144
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]5145 if (taiko->intf_type == WCD9XXX_INTERFACE_TYPE_I2C) {
5146 snd_soc_dapm_new_controls(dapm, taiko_dapm_i2s_widgets,
5147 ARRAY_SIZE(taiko_dapm_i2s_widgets));
5148 snd_soc_dapm_add_routes(dapm, audio_i2s_map,
5149 ARRAY_SIZE(audio_i2s_map));
Joonwoo Park559a5bf2013-02-15 14:46:36 -0800[diff] [blame]5150 if (TAIKO_IS_1_0(core->version))
5151 snd_soc_dapm_add_routes(dapm, audio_i2s_map_1_0,
5152 ARRAY_SIZE(audio_i2s_map_1_0));
5153 else
5154 snd_soc_dapm_add_routes(dapm, audio_i2s_map_2_0,
5155 ARRAY_SIZE(audio_i2s_map_2_0));
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]5156 for (i = 0; i < ARRAY_SIZE(taiko_i2s_dai); i++)
5157 INIT_LIST_HEAD(&taiko->dai[i].wcd9xxx_ch_list);
5158 } else if (taiko->intf_type == WCD9XXX_INTERFACE_TYPE_SLIMBUS) {
5159 for (i = 0; i < NUM_CODEC_DAIS; i++) {
5160 INIT_LIST_HEAD(&taiko->dai[i].wcd9xxx_ch_list);
5161 init_waitqueue_head(&taiko->dai[i].dai_wait);
5162 }
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]5163 }
5164
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]5165 control->num_rx_port = TAIKO_RX_MAX;
5166 control->rx_chs = ptr;
5167 memcpy(control->rx_chs, taiko_rx_chs, sizeof(taiko_rx_chs));
5168 control->num_tx_port = TAIKO_TX_MAX;
5169 control->tx_chs = ptr + sizeof(taiko_rx_chs);
5170 memcpy(control->tx_chs, taiko_tx_chs, sizeof(taiko_tx_chs));
5171
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]5172 snd_soc_dapm_sync(dapm);
5173
Joonwoo Park7680b9f2012-07-13 11:36:48 -0700[diff] [blame]5174 (void) taiko_setup_irqs(taiko);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]5175
Joonwoo Park125cd4e2012-12-11 15:16:11 -0800[diff] [blame]5176 atomic_set(&kp_taiko_priv, (unsigned long)taiko);
5177
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]5178 codec->ignore_pmdown_time = 1;
5179 return ret;
5180
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]5181err_pdata:
Kuirong Wang906ac472012-07-09 12:54:44 -0700[diff] [blame]5182 kfree(ptr);
5183err_nomem_slimch:
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]5184 kfree(taiko);
5185 return ret;
5186}
5187static int taiko_codec_remove(struct snd_soc_codec *codec)
5188{
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]5189 struct taiko_priv *taiko = snd_soc_codec_get_drvdata(codec);
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]5190
Joonwoo Park125cd4e2012-12-11 15:16:11 -0800[diff] [blame]5191 WCD9XXX_BCL_LOCK(&taiko->resmgr);
5192 atomic_set(&kp_taiko_priv, 0);
5193
5194 if (spkr_drv_wrnd > 0)
5195 wcd9xxx_resmgr_put_bandgap(&taiko->resmgr,
5196 WCD9XXX_BANDGAP_AUDIO_MODE);
5197 WCD9XXX_BCL_UNLOCK(&taiko->resmgr);
5198
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]5199 /* cleanup MBHC */
5200 wcd9xxx_mbhc_deinit(&taiko->mbhc);
5201 /* cleanup resmgr */
5202 wcd9xxx_resmgr_deinit(&taiko->resmgr);
5203
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]5204 kfree(taiko);
5205 return 0;
5206}
5207static struct snd_soc_codec_driver soc_codec_dev_taiko = {
5208 .probe = taiko_codec_probe,
5209 .remove = taiko_codec_remove,
5210
5211 .read = taiko_read,
5212 .write = taiko_write,
5213
5214 .readable_register = taiko_readable,
5215 .volatile_register = taiko_volatile,
5216
5217 .reg_cache_size = TAIKO_CACHE_SIZE,
Kiran Kandi7b7d2ff2012-09-14 14:52:14 -0700[diff] [blame]5218 .reg_cache_default = taiko_reset_reg_defaults,
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]5219 .reg_word_size = 1,
5220
5221 .controls = taiko_snd_controls,
5222 .num_controls = ARRAY_SIZE(taiko_snd_controls),
5223 .dapm_widgets = taiko_dapm_widgets,
5224 .num_dapm_widgets = ARRAY_SIZE(taiko_dapm_widgets),
5225 .dapm_routes = audio_map,
5226 .num_dapm_routes = ARRAY_SIZE(audio_map),
5227};
5228
5229#ifdef CONFIG_PM
5230static int taiko_suspend(struct device *dev)
5231{
5232 dev_dbg(dev, "%s: system suspend\n", __func__);
5233 return 0;
5234}
5235
5236static int taiko_resume(struct device *dev)
5237{
5238 struct platform_device *pdev = to_platform_device(dev);
5239 struct taiko_priv *taiko = platform_get_drvdata(pdev);
5240 dev_dbg(dev, "%s: system resume\n", __func__);
Joonwoo Parka8890262012-10-15 12:04:27 -0700[diff] [blame]5241 /* Notify */
5242 wcd9xxx_resmgr_notifier_call(&taiko->resmgr, WCD9XXX_EVENT_POST_RESUME);
Kiran Kandic3b24402012-06-11 00:05:59 -0700[diff] [blame]5243 return 0;
5244}
5245
5246static const struct dev_pm_ops taiko_pm_ops = {
5247 .suspend = taiko_suspend,
5248 .resume = taiko_resume,
5249};
5250#endif
5251
5252static int __devinit taiko_probe(struct platform_device *pdev)
5253{
5254 int ret = 0;
5255 if (wcd9xxx_get_intf_type() == WCD9XXX_INTERFACE_TYPE_SLIMBUS)
5256 ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_taiko,
5257 taiko_dai, ARRAY_SIZE(taiko_dai));
5258 else if (wcd9xxx_get_intf_type() == WCD9XXX_INTERFACE_TYPE_I2C)
5259 ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_taiko,
5260 taiko_i2s_dai, ARRAY_SIZE(taiko_i2s_dai));
5261 return ret;
5262}
5263static int __devexit taiko_remove(struct platform_device *pdev)
5264{
5265 snd_soc_unregister_codec(&pdev->dev);
5266 return 0;
5267}
5268static struct platform_driver taiko_codec_driver = {
5269 .probe = taiko_probe,
5270 .remove = taiko_remove,
5271 .driver = {
5272 .name = "taiko_codec",
5273 .owner = THIS_MODULE,
5274#ifdef CONFIG_PM
5275 .pm = &taiko_pm_ops,
5276#endif
5277 },
5278};
5279
5280static int __init taiko_codec_init(void)
5281{
5282 return platform_driver_register(&taiko_codec_driver);
5283}
5284
5285static void __exit taiko_codec_exit(void)
5286{
5287 platform_driver_unregister(&taiko_codec_driver);
5288}
5289
5290module_init(taiko_codec_init);
5291module_exit(taiko_codec_exit);
5292
5293MODULE_DESCRIPTION("Taiko codec driver");
5294MODULE_LICENSE("GPL v2");