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gerrit-public.fairphone.software / kernel / msm / a4c8ea2ddaed2f461606c2828b19786524b551ac / . / arch / arm / mach-davinci / include / mach / asp.h
blob: 834725f1e81d93504936b32abf0f88180c101d32 [file] [log] [blame]
David Brownellf492ec92009-05-14 13:01:59 -0700[diff] [blame]1/*
2 * <mach/asp.h> - DaVinci Audio Serial Port support
3 */
4#ifndef __ASM_ARCH_DAVINCI_ASP_H
5#define __ASM_ARCH_DAVINCI_ASP_H
6
7#include <mach/irqs.h>
Chaithrika U S25acf552009-06-05 06:28:08 -0400[diff] [blame]8#include <mach/edma.h>
David Brownellf492ec92009-05-14 13:01:59 -0700[diff] [blame]9
Chaithrika U S25acf552009-06-05 06:28:08 -0400[diff] [blame]10/* Bases of dm644x and dm355 register banks */
David Brownellf492ec92009-05-14 13:01:59 -0700[diff] [blame]11#define DAVINCI_ASP0_BASE 0x01E02000
12#define DAVINCI_ASP1_BASE 0x01E04000
13
Miguel Aguilare9ab3212009-09-02 15:33:29 -0600[diff] [blame]14/* Bases of dm365 register banks */
15#define DAVINCI_DM365_ASP0_BASE 0x01D02000
16
Chaithrika U S25acf552009-06-05 06:28:08 -0400[diff] [blame]17/* Bases of dm646x register banks */
18#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000
19#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800
20
Chaithrika U S491214e2009-08-11 17:03:25 -0400[diff] [blame]21/* Bases of da850/da830 McASP0 register banks */
22#define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000
23
Chaithrika U Se33ef5e2009-08-11 17:01:59 -0400[diff] [blame]24/* Bases of da830 McASP1 register banks */
25#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000
26
Chaithrika U S25acf552009-06-05 06:28:08 -0400[diff] [blame]27/* EDMA channels of dm644x and dm355 */
David Brownellf492ec92009-05-14 13:01:59 -0700[diff] [blame]28#define DAVINCI_DMA_ASP0_TX 2
29#define DAVINCI_DMA_ASP0_RX 3
30#define DAVINCI_DMA_ASP1_TX 8
31#define DAVINCI_DMA_ASP1_RX 9
32
Chaithrika U S25acf552009-06-05 06:28:08 -0400[diff] [blame]33/* EDMA channels of dm646x */
34#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6
35#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9
36#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12
37
Chaithrika U S491214e2009-08-11 17:03:25 -0400[diff] [blame]38/* EDMA channels of da850/da830 McASP0 */
39#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0
40#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1
41
Chaithrika U Se33ef5e2009-08-11 17:01:59 -0400[diff] [blame]42/* EDMA channels of da830 McASP1 */
43#define DAVINCI_DA830_DMA_MCASP1_AREVT 2
44#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3
45
David Brownellf492ec92009-05-14 13:01:59 -0700[diff] [blame]46/* Interrupts */
47#define DAVINCI_ASP0_RX_INT IRQ_MBRINT
48#define DAVINCI_ASP0_TX_INT IRQ_MBXINT
49#define DAVINCI_ASP1_RX_INT IRQ_MBRINT
50#define DAVINCI_ASP1_TX_INT IRQ_MBXINT
51
Chaithrika U S25acf552009-06-05 06:28:08 -0400[diff] [blame]52struct snd_platform_data {
Chaithrika U S25acf552009-06-05 06:28:08 -0400[diff] [blame]53 u32 tx_dma_offset;
54 u32 rx_dma_offset;
55 enum dma_event_q eventq_no; /* event queue number */
56 unsigned int codec_fmt;
Troy Kisky0d6c9772009-11-18 17:49:51 -0700[diff] [blame]57 /*
58 * Allowing this is more efficient and eliminates left and right swaps
59 * caused by underruns, but will swap the left and right channels
60 * when compared to previous behavior.
61 */
62 unsigned enable_channel_combine:1;
Troy Kisky1e224f32009-11-18 17:49:53 -0700[diff] [blame]63 unsigned sram_size_playback;
64 unsigned sram_size_capture;
Chaithrika U S25acf552009-06-05 06:28:08 -0400[diff] [blame]65
66 /* McASP specific fields */
67 int tdm_slots;
68 u8 op_mode;
69 u8 num_serializer;
70 u8 *serial_dir;
Chaithrika U Se33ef5e2009-08-11 17:01:59 -0400[diff] [blame]71 u8 version;
72 u8 txnumevt;
73 u8 rxnumevt;
74};
75
76enum {
77 MCASP_VERSION_1 = 0, /* DM646x */
78 MCASP_VERSION_2, /* DA8xx/OMAPL1x */
Chaithrika U S25acf552009-06-05 06:28:08 -0400[diff] [blame]79};
80
81#define INACTIVE_MODE 0
82#define TX_MODE 1
83#define RX_MODE 2
84
85#define DAVINCI_MCASP_IIS_MODE 0
86#define DAVINCI_MCASP_DIT_MODE 1
87
David Brownellf492ec92009-05-14 13:01:59 -0700[diff] [blame]88#endif /* __ASM_ARCH_DAVINCI_ASP_H */