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Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/*
2 * Idle processing for ARMv7-based Qualcomm SoCs.
3 *
4 * Copyright (C) 2007 Google, Inc.
Pratik Patel17f3b822011-11-21 12:41:47 -08005 * Copyright (c) 2007-2009, 2011-2012 Code Aurora Forum. All rights reserved.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include <linux/linkage.h>
19#include <linux/threads.h>
20#include <asm/assembler.h>
21
Steve Mucklefcece052012-02-18 20:09:58 -080022#include "idle.h"
Murali Nalajala73c13332012-05-15 11:30:59 +053023#include "idle-macros.S"
Steve Mucklefcece052012-02-18 20:09:58 -080024
Maheshkumar Sivasubramanianfa1d0dd2011-07-26 16:02:55 -060025#ifdef CONFIG_ARCH_MSM_KRAIT
26#define SCM_SVC_BOOT 0x1
27#define SCM_CMD_TERMINATE_PC 0x2
28#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070029
30ENTRY(msm_arch_idle)
Stepan Moskovchenkoae920e72012-07-03 19:10:44 -070031#ifdef CONFIG_ARCH_MSM_KRAIT
32 mrc p15, 0, r0, c0, c0, 0
33 bic r1, r0, #0xff
34 movw r2, #0x0400
35 movt r2, #0x511F
36 movw r3, #0x0600
37 movt r3, #0x510F
38 cmp r2, r1
39 cmpne r3, r1
40 bne go_wfi
41
42 mrs r0, cpsr
43 cpsid if
44
45 mrc p15, 7, r1, c15, c0, 5
46 bic r2, r1, #0x20000
47 mcr p15, 7, r2, c15, c0, 5
48 isb
49
50go_wfi:
51 wfi
52 bne wfi_done
53 mcr p15, 7, r1, c15, c0, 5
54 isb
55 msr cpsr_c, r0
56
57wfi_done:
58 bx lr
59#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070060 wfi
Pratik Patelcbcc1f02011-11-08 12:58:00 -080061#ifdef CONFIG_ARCH_MSM8X60
62 mrc p14, 1, r1, c1, c5, 4 /* read ETM PDSR to clear sticky bit */
63 mrc p14, 0, r1, c1, c5, 4 /* read DBG PRSR to clear sticky bit */
64 isb
65#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070066 bx lr
Stepan Moskovchenkoae920e72012-07-03 19:10:44 -070067#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070068
69ENTRY(msm_pm_collapse)
70#if defined(CONFIG_MSM_FIQ_SUPPORT)
71 cpsid f
72#endif
73
Steve Mucklefcece052012-02-18 20:09:58 -080074 ldr r0, =msm_saved_state /* address of msm_saved_state ptr */
75 ldr r0, [r0] /* load ptr */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070076#if (NR_CPUS >= 2)
77 mrc p15, 0, r1, c0, c0, 5 /* MPIDR */
78 ands r1, r1, #15 /* What CPU am I */
Mahesh Sivasubramanian0ff37e72011-12-15 14:12:31 -070079 mov r2, #CPU_SAVED_STATE_SIZE
80 mul r1, r1, r2
81 add r0, r0, r1
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070082#endif
83
84 stmia r0!, {r4-r14}
85 mrc p15, 0, r1, c1, c0, 0 /* MMU control */
86 mrc p15, 0, r2, c2, c0, 0 /* TTBR0 */
87 mrc p15, 0, r3, c3, c0, 0 /* dacr */
88#ifdef CONFIG_ARCH_MSM_SCORPION
89 /* This instruction is not valid for non scorpion processors */
90 mrc p15, 3, r4, c15, c0, 3 /* L2CR1 is the L2 cache control reg 1 */
91#endif
92 mrc p15, 0, r5, c10, c2, 0 /* PRRR */
93 mrc p15, 0, r6, c10, c2, 1 /* NMRR */
94 mrc p15, 0, r7, c1, c0, 1 /* ACTLR */
95 mrc p15, 0, r8, c2, c0, 1 /* TTBR1 */
96 mrc p15, 0, r9, c13, c0, 3 /* TPIDRURO */
97 mrc p15, 0, ip, c13, c0, 1 /* context ID */
98 stmia r0!, {r1-r9, ip}
99#ifdef CONFIG_MSM_CPU_AVS
100 mrc p15, 7, r1, c15, c1, 7 /* AVSCSR is the Adaptive Voltage Scaling
101 * Control and Status Register */
102 mrc p15, 7, r2, c15, c0, 6 /* AVSDSCR is the Adaptive Voltage
103 * Scaling Delay Synthesizer Control
104 * Register */
105#ifndef CONFIG_ARCH_MSM_KRAIT
106 mrc p15, 7, r3, c15, c1, 0 /* TSCSR is the Temperature Status and
107 * Control Register
108 */
109#endif
110
111 stmia r0!, {r1-r3}
112#endif
113
Pratik Patel17f3b822011-11-21 12:41:47 -0800114#ifdef CONFIG_MSM_JTAG
115 bl msm_jtag_save_state
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700116#endif
Maheshkumar Sivasubramaniana012e092011-08-18 10:13:03 -0600117
118 ldr r0, =msm_pm_flush_l2_flag
119 ldr r0, [r0]
120 mov r1, #0
121 mcr p15, 2, r1, c0, c0, 0 /*CCSELR*/
Maheshkumar Sivasubramanian1d2b69c2011-11-17 10:26:09 -0700122 isb
Maheshkumar Sivasubramaniana012e092011-08-18 10:13:03 -0600123 mrc p15, 1, r1, c0, c0, 0 /*CCSIDR*/
124 mov r2, #1
125 and r1, r2, r1, ASR #30 /* Check if the cache is write back */
126 orr r1, r0, r1
127 cmp r1, #1
128 bne skip
129 bl v7_flush_dcache_all
Steve Mucklefcece052012-02-18 20:09:58 -0800130skip:
Mahesh Sivasubramaniancb396622012-03-14 14:50:37 -0600131 mrc p15, 0, r0, c0, c0, 5 /* MPIDR */
132 and r0, r0, #15 /* what CPU am I */
133
134 ldr r1, =msm_pc_debug_counters /*load the IMEM debug location */
135 ldr r1, [r1]
136 cmp r1, #0
137 beq skip_pc_debug1
138 add r1, r1, r0, LSL #4 /* debug location for this CPU */
139 ldr r2, [r1]
140 add r2, #1
141 str r2, [r1]
142skip_pc_debug1:
143
Maheshkumar Sivasubramanianfa1d0dd2011-07-26 16:02:55 -0600144#ifdef CONFIG_ARCH_MSM_KRAIT
145 ldr r0, =SCM_SVC_BOOT
146 ldr r1, =SCM_CMD_TERMINATE_PC
Maheshkumar Sivasubramanian16588412011-10-13 12:16:23 -0600147 ldr r2, =msm_pm_flush_l2_flag
148 ldr r2, [r2]
Maheshkumar Sivasubramanianfa1d0dd2011-07-26 16:02:55 -0600149 bl scm_call_atomic1
150#else
Stepan Moskovchenko34dc00f2012-01-28 19:31:41 -0800151 mrc p15, 0, r4, c1, c0, 0 /* read current CR */
152 bic r0, r4, #(1 << 2) /* clear dcache bit */
153 bic r0, r0, #(1 << 12) /* clear icache bit */
154 mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */
Murali Nalajala73c13332012-05-15 11:30:59 +0530155 isb
Stepan Moskovchenko34dc00f2012-01-28 19:31:41 -0800156
Murali Nalajala73c13332012-05-15 11:30:59 +0530157 SUSPEND_8x25_L2
Murali Nalajala93f29992012-03-21 15:59:27 +0530158 SET_SMP_COHERENCY OFF
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700159 wfi
Murali Nalajala3a6de242012-05-11 15:05:35 +0530160 DELAY_8x25 300
Stepan Moskovchenko34dc00f2012-01-28 19:31:41 -0800161
Maheshkumar Sivasubramanianfa1d0dd2011-07-26 16:02:55 -0600162 mcr p15, 0, r4, c1, c0, 0 /* restore d/i cache */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700163 isb
Murali Nalajala73c13332012-05-15 11:30:59 +0530164 ENABLE_8x25_L2 /* enable only l2, no need to restore the reg back */
Murali Nalajala93f29992012-03-21 15:59:27 +0530165 SET_SMP_COHERENCY ON
Murali Nalajala73c13332012-05-15 11:30:59 +0530166#endif
167
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700168#if defined(CONFIG_MSM_FIQ_SUPPORT)
169 cpsie f
170#endif
Mahesh Sivasubramaniancb396622012-03-14 14:50:37 -0600171 mrc p15, 0, r0, c0, c0, 5 /* MPIDR */
172 and r0, r0, #15 /* what CPU am I */
173
174 ldr r1, =msm_pc_debug_counters /*load the IMEM debug location */
175 ldr r1, [r1]
176 cmp r1, #0
177 beq skip_pc_debug2
178 add r1, r1, r0, LSL #4 /* debug location for this CPU */
179 add r1, #8
180 ldr r2, [r1]
181 add r2, #1
182 str r2, [r1]
183
184skip_pc_debug2:
185
Pratik Patel17f3b822011-11-21 12:41:47 -0800186#ifdef CONFIG_MSM_JTAG
187 bl msm_jtag_restore_state
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700188#endif
Steve Mucklefcece052012-02-18 20:09:58 -0800189 ldr r0, =msm_saved_state /* address of msm_saved_state ptr */
190 ldr r0, [r0] /* load ptr */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700191#if (NR_CPUS >= 2)
192 mrc p15, 0, r1, c0, c0, 5 /* MPIDR */
193 ands r1, r1, #15 /* What CPU am I */
Praveen Chidambaram4b1e6f02012-02-11 16:17:30 -0700194 mov r2, #CPU_SAVED_STATE_SIZE
195 mul r2, r2, r1
196 add r0, r0, r2
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700197#endif
Steve Mucklefcece052012-02-18 20:09:58 -0800198 ldmfd r0, {r4-r14} /* restore registers */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700199 mov r0, #0 /* return power collapse failed */
200 bx lr
201
202ENTRY(msm_pm_collapse_exit)
203#if 0 /* serial debug */
204 mov r0, #0x80000016
205 mcr p15, 0, r0, c15, c2, 4
206 mov r0, #0xA9000000
207 add r0, r0, #0x00A00000 /* UART1 */
208 /*add r0, r0, #0x00C00000*/ /* UART3 */
209 mov r1, #'A'
210 str r1, [r0, #0x00C]
211#endif
Steve Mucklefcece052012-02-18 20:09:58 -0800212 ldr r1, =msm_saved_state_phys
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700213 ldr r2, =msm_pm_collapse_exit
214 adr r3, msm_pm_collapse_exit
215 add r1, r1, r3
216 sub r1, r1, r2
Steve Mucklefcece052012-02-18 20:09:58 -0800217 ldr r1, [r1]
Mahesh Sivasubramanian0ff37e72011-12-15 14:12:31 -0700218 add r1, r1, #CPU_SAVED_STATE_SIZE
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700219#if (NR_CPUS >= 2)
220 mrc p15, 0, r2, c0, c0, 5 /* MPIDR */
221 ands r2, r2, #15 /* What CPU am I */
Mahesh Sivasubramanian0ff37e72011-12-15 14:12:31 -0700222 mov r3, #CPU_SAVED_STATE_SIZE
223 mul r2, r2, r3
224 add r1, r1, r2
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700225#endif
226
227#ifdef CONFIG_MSM_CPU_AVS
228 ldmdb r1!, {r2-r4}
229#ifndef CONFIG_ARCH_MSM_KRAIT
230 mcr p15, 7, r4, c15, c1, 0 /* TSCSR */
231#endif
232 mcr p15, 7, r3, c15, c0, 6 /* AVSDSCR */
233 mcr p15, 7, r2, c15, c1, 7 /* AVSCSR */
234#endif
235 ldmdb r1!, {r2-r11}
236 mcr p15, 0, r4, c3, c0, 0 /* dacr */
237 mcr p15, 0, r3, c2, c0, 0 /* TTBR0 */
238#ifdef CONFIG_ARCH_MSM_SCORPION
239 /* This instruction is not valid for non scorpion processors */
240 mcr p15, 3, r5, c15, c0, 3 /* L2CR1 */
241#endif
242 mcr p15, 0, r6, c10, c2, 0 /* PRRR */
243 mcr p15, 0, r7, c10, c2, 1 /* NMRR */
244 mcr p15, 0, r8, c1, c0, 1 /* ACTLR */
245 mcr p15, 0, r9, c2, c0, 1 /* TTBR1 */
246 mcr p15, 0, r10, c13, c0, 3 /* TPIDRURO */
247 mcr p15, 0, r11, c13, c0, 1 /* context ID */
248 isb
249 ldmdb r1!, {r4-r14}
250 ldr r0, =msm_pm_pc_pgd
251 ldr r1, =msm_pm_collapse_exit
252 adr r3, msm_pm_collapse_exit
253 add r0, r0, r3
254 sub r0, r0, r1
255 ldr r0, [r0]
256 mrc p15, 0, r1, c2, c0, 0 /* save current TTBR0 */
257 and r3, r1, #0x7f /* mask to get TTB flags */
258 orr r0, r0, r3 /* add TTB flags to switch TTBR value */
259 mcr p15, 0, r0, c2, c0, 0 /* temporary switch TTBR0 */
260 isb
261 mcr p15, 0, r2, c1, c0, 0 /* MMU control */
262 isb
263msm_pm_mapped_pa:
264 /* Switch to virtual */
265 ldr r0, =msm_pm_pa_to_va
266 mov pc, r0
267msm_pm_pa_to_va:
268 mcr p15, 0, r1, c2, c0, 0 /* restore TTBR0 */
269 isb
270 mcr p15, 0, r3, c8, c7, 0 /* UTLBIALL */
271 mcr p15, 0, r3, c7, c5, 6 /* BPIALL */
272 dsb
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700273 isb
Murali Nalajala93f29992012-03-21 15:59:27 +0530274
Stepan Moskovchenko6fd9c922011-12-08 18:15:05 -0800275#ifdef CONFIG_ARCH_MSM_KRAIT
276 mrc p15, 0, r1, c0, c0, 0
277 ldr r3, =0xff00fc00
278 and r3, r1, r3
279 ldr r1, =0x51000400
280 cmp r3, r1
281 mrceq p15, 7, r3, c15, c0, 2
282 biceq r3, r3, #0x400
283 mcreq p15, 7, r3, c15, c0, 2
Murali Nalajala73c13332012-05-15 11:30:59 +0530284#else
285 RESUME_8x25_L2
286 SET_SMP_COHERENCY ON
Stepan Moskovchenko6fd9c922011-12-08 18:15:05 -0800287#endif
Murali Nalajala73c13332012-05-15 11:30:59 +0530288
Pratik Patel17f3b822011-11-21 12:41:47 -0800289#ifdef CONFIG_MSM_JTAG
Steve Mucklec1421e32012-03-26 11:05:06 -0700290 stmfd sp!, {lr}
Pratik Patel17f3b822011-11-21 12:41:47 -0800291 bl msm_jtag_restore_state
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700292 ldmfd sp!, {lr}
Steve Mucklec1421e32012-03-26 11:05:06 -0700293#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700294 mov r0, #1
295 bx lr
296 nop
297 nop
298 nop
299 nop
300 nop
3011: b 1b
302
303ENTRY(msm_pm_boot_entry)
304 mrc p15, 0, r0, c0, c0, 5 /* MPIDR */
305 and r0, r0, #15 /* what CPU am I */
306
Mahesh Sivasubramaniancb396622012-03-14 14:50:37 -0600307 ldr r1, =msm_pc_debug_counters_phys /*phys addr for IMEM reg */
308 ldr r2, =msm_pm_boot_entry
309 adr r3, msm_pm_boot_entry
310 add r1, r1, r3 /* translate virt to phys addr */
311 sub r1, r1, r2
312 ldr r1,[r1]
313
314 cmp r1, #0
315 beq skip_pc_debug3
316 add r1, r1, r0, LSL #4 /* debug location for this CPU */
317 add r1, #4 /* warmboot entry counter*/
318 ldr r2, [r1]
319 add r2, #1
320 str r2, [r1]
321
322skip_pc_debug3:
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700323 ldr r1, =msm_pm_boot_vector
324 ldr r2, =msm_pm_boot_entry
325 adr r3, msm_pm_boot_entry
326 add r1, r1, r3 /* translate virt to phys addr */
327 sub r1, r1, r2
328
329 add r1, r1, r0, LSL #2 /* locate boot vector for our cpu */
330 ldr pc, [r1] /* jump */
331
Maheshkumar Sivasubramaniana012e092011-08-18 10:13:03 -0600332ENTRY(msm_pm_set_l2_flush_flag)
Praveen Chidambaramc594a092012-09-18 19:48:29 -0600333 ldr r1, =msm_pm_flush_l2_flag
334 str r0, [r1]
335 bx lr
336
337ENTRY(msm_pm_get_l2_flush_flag)
338 ldr r1, =msm_pm_flush_l2_flag
339 ldr r0, [r1]
340 bx lr
Maheshkumar Sivasubramaniana012e092011-08-18 10:13:03 -0600341
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700342 .data
343
344 .globl msm_pm_pc_pgd
345msm_pm_pc_pgd:
346 .long 0x0
347
Steve Mucklefcece052012-02-18 20:09:58 -0800348 .globl msm_saved_state
349msm_saved_state:
350 .long 0x0
351
352 .globl msm_saved_state_phys
353msm_saved_state_phys:
354 .long 0x0
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700355
Steve Mucklec25a9362012-03-22 16:40:01 -0700356 .globl msm_pm_boot_vector
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700357msm_pm_boot_vector:
358 .space 4 * NR_CPUS
Maheshkumar Sivasubramaniana012e092011-08-18 10:13:03 -0600359
Murali Nalajala93f29992012-03-21 15:59:27 +0530360 .globl target_type
361target_type:
362 .long 0x0
363
Murali Nalajala73c13332012-05-15 11:30:59 +0530364 .globl apps_power_collapse
365apps_power_collapse:
366 .long 0x0
367
368 .globl l2x0_base_addr
369l2x0_base_addr:
370 .long 0x0
371
Mahesh Sivasubramaniancb396622012-03-14 14:50:37 -0600372 .globl msm_pc_debug_counters_phys
373msm_pc_debug_counters_phys:
374 .long 0x0
375
376 .globl msm_pc_debug_counters
377msm_pc_debug_counters:
378 .long 0x0
379
Maheshkumar Sivasubramaniana012e092011-08-18 10:13:03 -0600380/*
381 * Default the l2 flush flag to 1 so that caches are flushed during power
382 * collapse unless the L2 driver decides to flush them only during L2
383 * Power collapse.
384 */
385msm_pm_flush_l2_flag:
386 .long 0x1
Murali Nalajala73c13332012-05-15 11:30:59 +0530387
388/*
389 * Save & restore l2x0 registers while system is entering and resuming
390 * from Power Collapse.
391 * 1. aux_ctrl_save (0x0)
392 * 2. data_latency_ctrl (0x4)
393 * 3. prefetch control (0x8)
394 */
395l2x0_saved_ctrl_reg_val:
396 .space 4 * 3