Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | /* This file contains register alloction support. */ |
| 18 | |
| 19 | #include "dex/compiler_ir.h" |
| 20 | #include "dex/compiler_internals.h" |
| 21 | #include "mir_to_lir-inl.h" |
| 22 | |
| 23 | namespace art { |
| 24 | |
| 25 | /* |
| 26 | * Free all allocated temps in the temp pools. Note that this does |
| 27 | * not affect the "liveness" of a temp register, which will stay |
| 28 | * live until it is either explicitly killed or reallocated. |
| 29 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 30 | void Mir2Lir::ResetRegPool() { |
buzbee | bd663de | 2013-09-10 15:41:31 -0700 | [diff] [blame] | 31 | GrowableArray<RegisterInfo*>::Iterator iter(&tempreg_info_); |
| 32 | for (RegisterInfo* info = iter.Next(); info != NULL; info = iter.Next()) { |
| 33 | info->in_use = false; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 34 | } |
| 35 | // Reset temp tracking sanity check. |
| 36 | if (kIsDebugBuild) { |
| 37 | live_sreg_ = INVALID_SREG; |
| 38 | } |
| 39 | } |
| 40 | |
| 41 | /* |
| 42 | * Set up temp & preserved register pools specialized by target. |
| 43 | * Note: num_regs may be zero. |
| 44 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 45 | void Mir2Lir::CompilerInitPool(RegisterInfo* regs, int* reg_nums, int num) { |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 46 | for (int i = 0; i < num; i++) { |
buzbee | bd663de | 2013-09-10 15:41:31 -0700 | [diff] [blame] | 47 | uint32_t reg_number = reg_nums[i]; |
| 48 | regs[i].reg = reg_number; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 49 | regs[i].in_use = false; |
| 50 | regs[i].is_temp = false; |
| 51 | regs[i].pair = false; |
| 52 | regs[i].live = false; |
| 53 | regs[i].dirty = false; |
| 54 | regs[i].s_reg = INVALID_SREG; |
buzbee | bd663de | 2013-09-10 15:41:31 -0700 | [diff] [blame] | 55 | size_t map_size = reginfo_map_.Size(); |
| 56 | if (reg_number >= map_size) { |
| 57 | for (uint32_t i = 0; i < ((reg_number - map_size) + 1); i++) { |
| 58 | reginfo_map_.Insert(NULL); |
| 59 | } |
| 60 | } |
| 61 | reginfo_map_.Put(reg_number, ®s[i]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 62 | } |
| 63 | } |
| 64 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 65 | void Mir2Lir::DumpRegPool(RegisterInfo* p, int num_regs) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 66 | LOG(INFO) << "================================================"; |
| 67 | for (int i = 0; i < num_regs; i++) { |
| 68 | LOG(INFO) << StringPrintf( |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 69 | "R[%d]: T:%d, U:%d, P:%d, p:%d, LV:%d, D:%d, SR:%d", |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 70 | p[i].reg, p[i].is_temp, p[i].in_use, p[i].pair, p[i].partner, |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 71 | p[i].live, p[i].dirty, p[i].s_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 72 | } |
| 73 | LOG(INFO) << "================================================"; |
| 74 | } |
| 75 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 76 | void Mir2Lir::DumpCoreRegPool() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 77 | DumpRegPool(reg_pool_->core_regs, reg_pool_->num_core_regs); |
| 78 | } |
| 79 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 80 | void Mir2Lir::DumpFpRegPool() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 81 | DumpRegPool(reg_pool_->FPRegs, reg_pool_->num_fp_regs); |
| 82 | } |
| 83 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 84 | void Mir2Lir::Clobber(RegStorage reg) { |
| 85 | if (reg.IsPair()) { |
| 86 | ClobberBody(GetRegInfo(reg.GetLowReg())); |
| 87 | ClobberBody(GetRegInfo(reg.GetHighReg())); |
| 88 | } else { |
| 89 | ClobberBody(GetRegInfo(reg.GetReg())); |
| 90 | } |
| 91 | } |
| 92 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 93 | void Mir2Lir::ClobberSRegBody(RegisterInfo* p, int num_regs, int s_reg) { |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 94 | for (int i = 0; i< num_regs; i++) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 95 | if (p[i].s_reg == s_reg) { |
| 96 | if (p[i].is_temp) { |
| 97 | p[i].live = false; |
| 98 | } |
| 99 | p[i].def_start = NULL; |
| 100 | p[i].def_end = NULL; |
| 101 | } |
| 102 | } |
| 103 | } |
| 104 | |
| 105 | /* |
| 106 | * Break the association between a Dalvik vreg and a physical temp register of either register |
| 107 | * class. |
| 108 | * TODO: Ideally, the public version of this code should not exist. Besides its local usage |
| 109 | * in the register utilities, is is also used by code gen routines to work around a deficiency in |
| 110 | * local register allocation, which fails to distinguish between the "in" and "out" identities |
| 111 | * of Dalvik vregs. This can result in useless register copies when the same Dalvik vreg |
| 112 | * is used both as the source and destination register of an operation in which the type |
| 113 | * changes (for example: INT_TO_FLOAT v1, v1). Revisit when improved register allocation is |
| 114 | * addressed. |
| 115 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 116 | void Mir2Lir::ClobberSReg(int s_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 117 | /* Reset live temp tracking sanity checker */ |
| 118 | if (kIsDebugBuild) { |
| 119 | if (s_reg == live_sreg_) { |
| 120 | live_sreg_ = INVALID_SREG; |
| 121 | } |
| 122 | } |
| 123 | ClobberSRegBody(reg_pool_->core_regs, reg_pool_->num_core_regs, s_reg); |
| 124 | ClobberSRegBody(reg_pool_->FPRegs, reg_pool_->num_fp_regs, s_reg); |
| 125 | } |
| 126 | |
| 127 | /* |
| 128 | * SSA names associated with the initial definitions of Dalvik |
| 129 | * registers are the same as the Dalvik register number (and |
| 130 | * thus take the same position in the promotion_map. However, |
| 131 | * the special Method* and compiler temp resisters use negative |
| 132 | * v_reg numbers to distinguish them and can have an arbitrary |
| 133 | * ssa name (above the last original Dalvik register). This function |
| 134 | * maps SSA names to positions in the promotion_map array. |
| 135 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 136 | int Mir2Lir::SRegToPMap(int s_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 137 | DCHECK_LT(s_reg, mir_graph_->GetNumSSARegs()); |
| 138 | DCHECK_GE(s_reg, 0); |
| 139 | int v_reg = mir_graph_->SRegToVReg(s_reg); |
| 140 | if (v_reg >= 0) { |
| 141 | DCHECK_LT(v_reg, cu_->num_dalvik_registers); |
| 142 | return v_reg; |
| 143 | } else { |
Razvan A Lupusoru | da7a69b | 2014-01-08 15:09:50 -0800 | [diff] [blame] | 144 | /* |
| 145 | * It must be the case that the v_reg for temporary is less than or equal to the |
| 146 | * base reg for temps. For that reason, "position" must be zero or positive. |
| 147 | */ |
| 148 | unsigned int position = std::abs(v_reg) - std::abs(static_cast<int>(kVRegTempBaseReg)); |
| 149 | |
| 150 | // The temporaries are placed after dalvik registers in the promotion map |
| 151 | DCHECK_LT(position, mir_graph_->GetNumUsedCompilerTemps()); |
| 152 | return cu_->num_dalvik_registers + position; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 153 | } |
| 154 | } |
| 155 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 156 | void Mir2Lir::RecordCorePromotion(RegStorage reg, int s_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 157 | int p_map_idx = SRegToPMap(s_reg); |
| 158 | int v_reg = mir_graph_->SRegToVReg(s_reg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 159 | int reg_num = reg.GetReg(); |
| 160 | GetRegInfo(reg_num)->in_use = true; |
| 161 | core_spill_mask_ |= (1 << reg_num); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 162 | // Include reg for later sort |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 163 | core_vmap_table_.push_back(reg_num << VREG_NUM_WIDTH | (v_reg & ((1 << VREG_NUM_WIDTH) - 1))); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 164 | num_core_spills_++; |
| 165 | promotion_map_[p_map_idx].core_location = kLocPhysReg; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 166 | promotion_map_[p_map_idx].core_reg = reg_num; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 167 | } |
| 168 | |
| 169 | /* Reserve a callee-save register. Return -1 if none available */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 170 | RegStorage Mir2Lir::AllocPreservedCoreReg(int s_reg) { |
| 171 | RegStorage res; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 172 | RegisterInfo* core_regs = reg_pool_->core_regs; |
| 173 | for (int i = 0; i < reg_pool_->num_core_regs; i++) { |
| 174 | if (!core_regs[i].is_temp && !core_regs[i].in_use) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 175 | res = RegStorage::Solo32(core_regs[i].reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 176 | RecordCorePromotion(res, s_reg); |
| 177 | break; |
| 178 | } |
| 179 | } |
| 180 | return res; |
| 181 | } |
| 182 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 183 | void Mir2Lir::RecordFpPromotion(RegStorage reg, int s_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 184 | int p_map_idx = SRegToPMap(s_reg); |
| 185 | int v_reg = mir_graph_->SRegToVReg(s_reg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 186 | int reg_num = reg.GetReg(); |
| 187 | GetRegInfo(reg_num)->in_use = true; |
| 188 | MarkPreservedSingle(v_reg, reg_num); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 189 | promotion_map_[p_map_idx].fp_location = kLocPhysReg; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 190 | promotion_map_[p_map_idx].FpReg = reg_num; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 191 | } |
| 192 | |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 193 | // Reserve a callee-save fp single register. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 194 | RegStorage Mir2Lir::AllocPreservedSingle(int s_reg) { |
| 195 | RegStorage res; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 196 | RegisterInfo* FPRegs = reg_pool_->FPRegs; |
| 197 | for (int i = 0; i < reg_pool_->num_fp_regs; i++) { |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 198 | if (!FPRegs[i].is_temp && !FPRegs[i].in_use) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 199 | res = RegStorage::Solo32(FPRegs[i].reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 200 | RecordFpPromotion(res, s_reg); |
| 201 | break; |
| 202 | } |
| 203 | } |
| 204 | return res; |
| 205 | } |
| 206 | |
| 207 | /* |
| 208 | * Somewhat messy code here. We want to allocate a pair of contiguous |
| 209 | * physical single-precision floating point registers starting with |
| 210 | * an even numbered reg. It is possible that the paired s_reg (s_reg+1) |
| 211 | * has already been allocated - try to fit if possible. Fail to |
| 212 | * allocate if we can't meet the requirements for the pair of |
| 213 | * s_reg<=sX[even] & (s_reg+1)<= sX+1. |
| 214 | */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 215 | // TODO: needs rewrite to support non-backed 64-bit float regs. |
| 216 | RegStorage Mir2Lir::AllocPreservedDouble(int s_reg) { |
| 217 | RegStorage res; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 218 | int v_reg = mir_graph_->SRegToVReg(s_reg); |
| 219 | int p_map_idx = SRegToPMap(s_reg); |
| 220 | if (promotion_map_[p_map_idx+1].fp_location == kLocPhysReg) { |
| 221 | // Upper reg is already allocated. Can we fit? |
| 222 | int high_reg = promotion_map_[p_map_idx+1].FpReg; |
| 223 | if ((high_reg & 1) == 0) { |
| 224 | // High reg is even - fail. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 225 | return res; // Invalid. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 226 | } |
| 227 | // Is the low reg of the pair free? |
| 228 | RegisterInfo* p = GetRegInfo(high_reg-1); |
| 229 | if (p->in_use || p->is_temp) { |
| 230 | // Already allocated or not preserved - fail. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 231 | return res; // Invalid. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 232 | } |
| 233 | // OK - good to go. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 234 | res = RegStorage(RegStorage::k64BitPair, p->reg, p->reg + 1); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 235 | p->in_use = true; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 236 | DCHECK_EQ((res.GetReg() & 1), 0); |
| 237 | MarkPreservedSingle(v_reg, res.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 238 | } else { |
| 239 | RegisterInfo* FPRegs = reg_pool_->FPRegs; |
| 240 | for (int i = 0; i < reg_pool_->num_fp_regs; i++) { |
| 241 | if (!FPRegs[i].is_temp && !FPRegs[i].in_use && |
| 242 | ((FPRegs[i].reg & 0x1) == 0x0) && |
| 243 | !FPRegs[i+1].is_temp && !FPRegs[i+1].in_use && |
| 244 | ((FPRegs[i+1].reg & 0x1) == 0x1) && |
| 245 | (FPRegs[i].reg + 1) == FPRegs[i+1].reg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 246 | res = RegStorage(RegStorage::k64BitPair, FPRegs[i].reg, FPRegs[i].reg+1); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 247 | FPRegs[i].in_use = true; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 248 | MarkPreservedSingle(v_reg, res.GetLowReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 249 | FPRegs[i+1].in_use = true; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 250 | DCHECK_EQ(res.GetLowReg() + 1, FPRegs[i+1].reg); |
| 251 | MarkPreservedSingle(v_reg+1, res.GetLowReg() + 1); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 252 | break; |
| 253 | } |
| 254 | } |
| 255 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 256 | if (res.Valid()) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 257 | promotion_map_[p_map_idx].fp_location = kLocPhysReg; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 258 | promotion_map_[p_map_idx].FpReg = res.GetLowReg(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 259 | promotion_map_[p_map_idx+1].fp_location = kLocPhysReg; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 260 | promotion_map_[p_map_idx+1].FpReg = res.GetLowReg() + 1; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 261 | } |
| 262 | return res; |
| 263 | } |
| 264 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 265 | RegStorage Mir2Lir::AllocTempBody(RegisterInfo* p, int num_regs, int* next_temp, |
| 266 | bool required) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 267 | int next = *next_temp; |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 268 | for (int i = 0; i< num_regs; i++) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 269 | if (next >= num_regs) |
| 270 | next = 0; |
| 271 | if (p[next].is_temp && !p[next].in_use && !p[next].live) { |
| 272 | Clobber(p[next].reg); |
| 273 | p[next].in_use = true; |
| 274 | p[next].pair = false; |
| 275 | *next_temp = next + 1; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 276 | return RegStorage::Solo32(p[next].reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 277 | } |
| 278 | next++; |
| 279 | } |
| 280 | next = *next_temp; |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 281 | for (int i = 0; i< num_regs; i++) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 282 | if (next >= num_regs) |
| 283 | next = 0; |
| 284 | if (p[next].is_temp && !p[next].in_use) { |
| 285 | Clobber(p[next].reg); |
| 286 | p[next].in_use = true; |
| 287 | p[next].pair = false; |
| 288 | *next_temp = next + 1; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 289 | return RegStorage::Solo32(p[next].reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 290 | } |
| 291 | next++; |
| 292 | } |
| 293 | if (required) { |
| 294 | CodegenDump(); |
| 295 | DumpRegPool(reg_pool_->core_regs, |
| 296 | reg_pool_->num_core_regs); |
| 297 | LOG(FATAL) << "No free temp registers"; |
| 298 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 299 | return RegStorage::InvalidReg(); // No register available |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 300 | } |
| 301 | |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 302 | // REDO: too many assumptions. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 303 | // Virtualize - this is target dependent. |
| 304 | RegStorage Mir2Lir::AllocTempDouble() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 305 | RegisterInfo* p = reg_pool_->FPRegs; |
| 306 | int num_regs = reg_pool_->num_fp_regs; |
| 307 | /* Start looking at an even reg */ |
| 308 | int next = reg_pool_->next_fp_reg & ~0x1; |
| 309 | |
| 310 | // First try to avoid allocating live registers |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 311 | for (int i = 0; i < num_regs; i+=2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 312 | if (next >= num_regs) |
| 313 | next = 0; |
| 314 | if ((p[next].is_temp && !p[next].in_use && !p[next].live) && |
| 315 | (p[next+1].is_temp && !p[next+1].in_use && !p[next+1].live)) { |
| 316 | Clobber(p[next].reg); |
| 317 | Clobber(p[next+1].reg); |
| 318 | p[next].in_use = true; |
| 319 | p[next+1].in_use = true; |
| 320 | DCHECK_EQ((p[next].reg+1), p[next+1].reg); |
| 321 | DCHECK_EQ((p[next].reg & 0x1), 0); |
| 322 | reg_pool_->next_fp_reg = next + 2; |
| 323 | if (reg_pool_->next_fp_reg >= num_regs) { |
| 324 | reg_pool_->next_fp_reg = 0; |
| 325 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 326 | // FIXME: should return k64BitSolo. |
| 327 | return RegStorage(RegStorage::k64BitPair, p[next].reg, p[next+1].reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 328 | } |
| 329 | next += 2; |
| 330 | } |
| 331 | next = reg_pool_->next_fp_reg & ~0x1; |
| 332 | |
| 333 | // No choice - find a pair and kill it. |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 334 | for (int i = 0; i < num_regs; i+=2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 335 | if (next >= num_regs) |
| 336 | next = 0; |
| 337 | if (p[next].is_temp && !p[next].in_use && p[next+1].is_temp && |
| 338 | !p[next+1].in_use) { |
| 339 | Clobber(p[next].reg); |
| 340 | Clobber(p[next+1].reg); |
| 341 | p[next].in_use = true; |
| 342 | p[next+1].in_use = true; |
| 343 | DCHECK_EQ((p[next].reg+1), p[next+1].reg); |
| 344 | DCHECK_EQ((p[next].reg & 0x1), 0); |
| 345 | reg_pool_->next_fp_reg = next + 2; |
| 346 | if (reg_pool_->next_fp_reg >= num_regs) { |
| 347 | reg_pool_->next_fp_reg = 0; |
| 348 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 349 | return RegStorage(RegStorage::k64BitPair, p[next].reg, p[next+1].reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 350 | } |
| 351 | next += 2; |
| 352 | } |
| 353 | LOG(FATAL) << "No free temp registers (pair)"; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 354 | return RegStorage::InvalidReg(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 355 | } |
| 356 | |
| 357 | /* Return a temp if one is available, -1 otherwise */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 358 | RegStorage Mir2Lir::AllocFreeTemp() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 359 | return AllocTempBody(reg_pool_->core_regs, |
| 360 | reg_pool_->num_core_regs, |
Vladimir Marko | 73e08b3 | 2013-11-21 10:58:36 +0000 | [diff] [blame] | 361 | ®_pool_->next_core_reg, false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 362 | } |
| 363 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 364 | RegStorage Mir2Lir::AllocTemp() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 365 | return AllocTempBody(reg_pool_->core_regs, |
| 366 | reg_pool_->num_core_regs, |
| 367 | ®_pool_->next_core_reg, true); |
| 368 | } |
| 369 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 370 | RegStorage Mir2Lir::AllocTempFloat() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 371 | return AllocTempBody(reg_pool_->FPRegs, |
| 372 | reg_pool_->num_fp_regs, |
| 373 | ®_pool_->next_fp_reg, true); |
| 374 | } |
| 375 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 376 | Mir2Lir::RegisterInfo* Mir2Lir::AllocLiveBody(RegisterInfo* p, int num_regs, int s_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 377 | if (s_reg == -1) |
| 378 | return NULL; |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 379 | for (int i = 0; i < num_regs; i++) { |
buzbee | 56c7178 | 2013-09-05 17:13:19 -0700 | [diff] [blame] | 380 | if ((p[i].s_reg == s_reg) && p[i].live) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 381 | if (p[i].is_temp) |
| 382 | p[i].in_use = true; |
| 383 | return &p[i]; |
| 384 | } |
| 385 | } |
| 386 | return NULL; |
| 387 | } |
| 388 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 389 | Mir2Lir::RegisterInfo* Mir2Lir::AllocLive(int s_reg, int reg_class) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 390 | RegisterInfo* res = NULL; |
| 391 | switch (reg_class) { |
| 392 | case kAnyReg: |
| 393 | res = AllocLiveBody(reg_pool_->FPRegs, |
| 394 | reg_pool_->num_fp_regs, s_reg); |
| 395 | if (res) |
| 396 | break; |
| 397 | /* Intentional fallthrough */ |
| 398 | case kCoreReg: |
| 399 | res = AllocLiveBody(reg_pool_->core_regs, |
| 400 | reg_pool_->num_core_regs, s_reg); |
| 401 | break; |
| 402 | case kFPReg: |
| 403 | res = AllocLiveBody(reg_pool_->FPRegs, |
| 404 | reg_pool_->num_fp_regs, s_reg); |
| 405 | break; |
| 406 | default: |
| 407 | LOG(FATAL) << "Invalid register type"; |
| 408 | } |
| 409 | return res; |
| 410 | } |
| 411 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 412 | void Mir2Lir::FreeTemp(int reg) { |
buzbee | 56c7178 | 2013-09-05 17:13:19 -0700 | [diff] [blame] | 413 | RegisterInfo* p = GetRegInfo(reg); |
| 414 | if (p->is_temp) { |
| 415 | p->in_use = false; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 416 | } |
buzbee | 56c7178 | 2013-09-05 17:13:19 -0700 | [diff] [blame] | 417 | p->pair = false; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 418 | } |
| 419 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 420 | void Mir2Lir::FreeTemp(RegStorage reg) { |
| 421 | if (reg.IsPair()) { |
| 422 | FreeTemp(reg.GetLowReg()); |
| 423 | FreeTemp(reg.GetHighReg()); |
| 424 | } else { |
| 425 | FreeTemp(reg.GetReg()); |
| 426 | } |
| 427 | } |
| 428 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 429 | Mir2Lir::RegisterInfo* Mir2Lir::IsLive(int reg) { |
buzbee | 56c7178 | 2013-09-05 17:13:19 -0700 | [diff] [blame] | 430 | RegisterInfo* p = GetRegInfo(reg); |
| 431 | return p->live ? p : NULL; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 432 | } |
| 433 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 434 | Mir2Lir::RegisterInfo* Mir2Lir::IsLive(RegStorage reg) { |
| 435 | if (reg.IsPair()) { |
| 436 | DCHECK_EQ(IsLive(reg.GetLowReg()) == nullptr, IsLive(reg.GetHighReg()) == nullptr); |
| 437 | return IsLive(reg.GetLowReg()); |
| 438 | } else { |
| 439 | return IsLive(reg.GetReg()); |
| 440 | } |
| 441 | } |
| 442 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 443 | Mir2Lir::RegisterInfo* Mir2Lir::IsTemp(int reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 444 | RegisterInfo* p = GetRegInfo(reg); |
| 445 | return (p->is_temp) ? p : NULL; |
| 446 | } |
| 447 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 448 | Mir2Lir::RegisterInfo* Mir2Lir::IsTemp(RegStorage reg) { |
| 449 | if (reg.IsPair()) { |
| 450 | DCHECK_EQ(IsTemp(reg.GetLowReg()) == nullptr, IsTemp(reg.GetHighReg()) == nullptr); |
| 451 | return IsTemp(reg.GetLowReg()); |
| 452 | } else { |
| 453 | return IsTemp(reg.GetReg()); |
| 454 | } |
| 455 | } |
| 456 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 457 | Mir2Lir::RegisterInfo* Mir2Lir::IsPromoted(int reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 458 | RegisterInfo* p = GetRegInfo(reg); |
| 459 | return (p->is_temp) ? NULL : p; |
| 460 | } |
| 461 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 462 | Mir2Lir::RegisterInfo* Mir2Lir::IsPromoted(RegStorage reg) { |
| 463 | if (reg.IsPair()) { |
| 464 | DCHECK_EQ(IsPromoted(reg.GetLowReg()) == nullptr, IsPromoted(reg.GetHighReg()) == nullptr); |
| 465 | return IsPromoted(reg.GetLowReg()); |
| 466 | } else { |
| 467 | return IsPromoted(reg.GetReg()); |
| 468 | } |
| 469 | } |
| 470 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 471 | bool Mir2Lir::IsDirty(int reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 472 | RegisterInfo* p = GetRegInfo(reg); |
| 473 | return p->dirty; |
| 474 | } |
| 475 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 476 | bool Mir2Lir::IsDirty(RegStorage reg) { |
| 477 | if (reg.IsPair()) { |
| 478 | DCHECK_EQ(IsDirty(reg.GetLowReg()), IsDirty(reg.GetHighReg())); |
| 479 | return IsDirty(reg.GetLowReg()); |
| 480 | } else { |
| 481 | return IsDirty(reg.GetReg()); |
| 482 | } |
| 483 | } |
| 484 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 485 | /* |
| 486 | * Similar to AllocTemp(), but forces the allocation of a specific |
| 487 | * register. No check is made to see if the register was previously |
| 488 | * allocated. Use with caution. |
| 489 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 490 | void Mir2Lir::LockTemp(int reg) { |
buzbee | 56c7178 | 2013-09-05 17:13:19 -0700 | [diff] [blame] | 491 | RegisterInfo* p = GetRegInfo(reg); |
| 492 | DCHECK(p->is_temp); |
| 493 | p->in_use = true; |
| 494 | p->live = false; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 495 | } |
| 496 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 497 | void Mir2Lir::LockTemp(RegStorage reg) { |
| 498 | DCHECK(!reg.IsPair()); |
| 499 | LockTemp(reg.GetReg()); |
| 500 | } |
| 501 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 502 | void Mir2Lir::ResetDef(int reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 503 | ResetDefBody(GetRegInfo(reg)); |
| 504 | } |
| 505 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 506 | void Mir2Lir::ResetDef(RegStorage reg) { |
| 507 | DCHECK(!reg.IsPair()); // Is this done? If so, do on both low and high. |
| 508 | ResetDef(reg.GetReg()); |
| 509 | } |
| 510 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 511 | void Mir2Lir::NullifyRange(LIR *start, LIR *finish, int s_reg1, int s_reg2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 512 | if (start && finish) { |
| 513 | LIR *p; |
| 514 | DCHECK_EQ(s_reg1, s_reg2); |
Brian Carlstrom | 02c8cc6 | 2013-07-18 15:54:44 -0700 | [diff] [blame] | 515 | for (p = start; ; p = p->next) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 516 | NopLIR(p); |
| 517 | if (p == finish) |
| 518 | break; |
| 519 | } |
| 520 | } |
| 521 | } |
| 522 | |
| 523 | /* |
| 524 | * Mark the beginning and end LIR of a def sequence. Note that |
| 525 | * on entry start points to the LIR prior to the beginning of the |
| 526 | * sequence. |
| 527 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 528 | void Mir2Lir::MarkDef(RegLocation rl, LIR *start, LIR *finish) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 529 | DCHECK(!rl.wide); |
| 530 | DCHECK(start && start->next); |
| 531 | DCHECK(finish); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 532 | RegisterInfo* p = GetRegInfo(rl.reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 533 | p->def_start = start->next; |
| 534 | p->def_end = finish; |
| 535 | } |
| 536 | |
| 537 | /* |
| 538 | * Mark the beginning and end LIR of a def sequence. Note that |
| 539 | * on entry start points to the LIR prior to the beginning of the |
| 540 | * sequence. |
| 541 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 542 | void Mir2Lir::MarkDefWide(RegLocation rl, LIR *start, LIR *finish) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 543 | DCHECK(rl.wide); |
| 544 | DCHECK(start && start->next); |
| 545 | DCHECK(finish); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 546 | RegisterInfo* p = GetRegInfo(rl.reg.GetLowReg()); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 547 | ResetDef(rl.reg.GetHighReg()); // Only track low of pair |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 548 | p->def_start = start->next; |
| 549 | p->def_end = finish; |
| 550 | } |
| 551 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 552 | RegLocation Mir2Lir::WideToNarrow(RegLocation rl) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 553 | DCHECK(rl.wide); |
| 554 | if (rl.location == kLocPhysReg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 555 | RegisterInfo* info_lo = GetRegInfo(rl.reg.GetLowReg()); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 556 | RegisterInfo* info_hi = GetRegInfo(rl.reg.GetHighReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 557 | if (info_lo->is_temp) { |
| 558 | info_lo->pair = false; |
| 559 | info_lo->def_start = NULL; |
| 560 | info_lo->def_end = NULL; |
| 561 | } |
| 562 | if (info_hi->is_temp) { |
| 563 | info_hi->pair = false; |
| 564 | info_hi->def_start = NULL; |
| 565 | info_hi->def_end = NULL; |
| 566 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 567 | rl.reg = RegStorage::Solo32(rl.reg.GetLowReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 568 | } |
| 569 | rl.wide = false; |
| 570 | return rl; |
| 571 | } |
| 572 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 573 | void Mir2Lir::ResetDefLoc(RegLocation rl) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 574 | DCHECK(!rl.wide); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 575 | RegisterInfo* p = IsTemp(rl.reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 576 | if (p && !(cu_->disable_opt & (1 << kSuppressLoads))) { |
| 577 | DCHECK(!p->pair); |
| 578 | NullifyRange(p->def_start, p->def_end, p->s_reg, rl.s_reg_low); |
| 579 | } |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 580 | ResetDef(rl.reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 581 | } |
| 582 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 583 | void Mir2Lir::ResetDefLocWide(RegLocation rl) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 584 | DCHECK(rl.wide); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 585 | RegisterInfo* p_low = IsTemp(rl.reg.GetLowReg()); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 586 | RegisterInfo* p_high = IsTemp(rl.reg.GetHighReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 587 | if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) { |
| 588 | DCHECK(p_low->pair); |
| 589 | NullifyRange(p_low->def_start, p_low->def_end, p_low->s_reg, rl.s_reg_low); |
| 590 | } |
| 591 | if (p_high && !(cu_->disable_opt & (1 << kSuppressLoads))) { |
| 592 | DCHECK(p_high->pair); |
| 593 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 594 | ResetDef(rl.reg.GetLowReg()); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 595 | ResetDef(rl.reg.GetHighReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 596 | } |
| 597 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 598 | void Mir2Lir::ResetDefTracking() { |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 599 | for (int i = 0; i< reg_pool_->num_core_regs; i++) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 600 | ResetDefBody(®_pool_->core_regs[i]); |
| 601 | } |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 602 | for (int i = 0; i< reg_pool_->num_fp_regs; i++) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 603 | ResetDefBody(®_pool_->FPRegs[i]); |
| 604 | } |
| 605 | } |
| 606 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 607 | void Mir2Lir::ClobberAllRegs() { |
buzbee | bd663de | 2013-09-10 15:41:31 -0700 | [diff] [blame] | 608 | GrowableArray<RegisterInfo*>::Iterator iter(&tempreg_info_); |
| 609 | for (RegisterInfo* info = iter.Next(); info != NULL; info = iter.Next()) { |
| 610 | info->live = false; |
| 611 | info->s_reg = INVALID_SREG; |
| 612 | info->def_start = NULL; |
| 613 | info->def_end = NULL; |
| 614 | info->pair = false; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 615 | } |
| 616 | } |
| 617 | |
Razvan A Lupusoru | 614c2b4 | 2014-01-28 17:05:21 -0800 | [diff] [blame] | 618 | void Mir2Lir::FlushSpecificReg(RegisterInfo* info) { |
| 619 | if (info->pair) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 620 | FlushRegWide(RegStorage(RegStorage::k64BitPair, info->reg, info->partner)); |
Razvan A Lupusoru | 614c2b4 | 2014-01-28 17:05:21 -0800 | [diff] [blame] | 621 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 622 | FlushReg(RegStorage::Solo32(info->reg)); |
Razvan A Lupusoru | 614c2b4 | 2014-01-28 17:05:21 -0800 | [diff] [blame] | 623 | } |
| 624 | } |
| 625 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 626 | // Make sure nothing is live and dirty |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 627 | void Mir2Lir::FlushAllRegsBody(RegisterInfo* info, int num_regs) { |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 628 | for (int i = 0; i < num_regs; i++) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 629 | if (info[i].live && info[i].dirty) { |
Razvan A Lupusoru | 614c2b4 | 2014-01-28 17:05:21 -0800 | [diff] [blame] | 630 | FlushSpecificReg(&info[i]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 631 | } |
| 632 | } |
| 633 | } |
| 634 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 635 | void Mir2Lir::FlushAllRegs() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 636 | FlushAllRegsBody(reg_pool_->core_regs, |
| 637 | reg_pool_->num_core_regs); |
| 638 | FlushAllRegsBody(reg_pool_->FPRegs, |
| 639 | reg_pool_->num_fp_regs); |
| 640 | ClobberAllRegs(); |
| 641 | } |
| 642 | |
| 643 | |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 644 | // TUNING: rewrite all of this reg stuff. Probably use an attribute table |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 645 | bool Mir2Lir::RegClassMatches(int reg_class, RegStorage reg) { |
| 646 | int reg_num = reg.IsPair() ? reg.GetLowReg() : reg.GetReg(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 647 | if (reg_class == kAnyReg) { |
| 648 | return true; |
| 649 | } else if (reg_class == kCoreReg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 650 | return !IsFpReg(reg_num); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 651 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 652 | return IsFpReg(reg_num); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 653 | } |
| 654 | } |
| 655 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 656 | void Mir2Lir::MarkLive(RegStorage reg, int s_reg) { |
| 657 | DCHECK(!reg.IsPair()); // Could be done - but would that be meaningful? |
| 658 | RegisterInfo* info = GetRegInfo(reg.GetReg()); |
| 659 | if ((info->s_reg == s_reg) && info->live) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 660 | return; /* already live */ |
| 661 | } else if (s_reg != INVALID_SREG) { |
| 662 | ClobberSReg(s_reg); |
| 663 | if (info->is_temp) { |
| 664 | info->live = true; |
| 665 | } |
| 666 | } else { |
| 667 | /* Can't be live if no associated s_reg */ |
| 668 | DCHECK(info->is_temp); |
| 669 | info->live = false; |
| 670 | } |
| 671 | info->s_reg = s_reg; |
| 672 | } |
| 673 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 674 | void Mir2Lir::MarkTemp(int reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 675 | RegisterInfo* info = GetRegInfo(reg); |
buzbee | bd663de | 2013-09-10 15:41:31 -0700 | [diff] [blame] | 676 | tempreg_info_.Insert(info); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 677 | info->is_temp = true; |
| 678 | } |
| 679 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 680 | void Mir2Lir::MarkTemp(RegStorage reg) { |
| 681 | DCHECK(!reg.IsPair()); |
| 682 | MarkTemp(reg.GetReg()); |
| 683 | } |
| 684 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 685 | void Mir2Lir::UnmarkTemp(int reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 686 | RegisterInfo* info = GetRegInfo(reg); |
buzbee | bd663de | 2013-09-10 15:41:31 -0700 | [diff] [blame] | 687 | tempreg_info_.Delete(info); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 688 | info->is_temp = false; |
| 689 | } |
| 690 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 691 | void Mir2Lir::UnmarkTemp(RegStorage reg) { |
| 692 | DCHECK(!reg.IsPair()); |
| 693 | UnmarkTemp(reg.GetReg()); |
| 694 | } |
| 695 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 696 | void Mir2Lir::MarkPair(int low_reg, int high_reg) { |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 697 | DCHECK_NE(low_reg, high_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 698 | RegisterInfo* info_lo = GetRegInfo(low_reg); |
| 699 | RegisterInfo* info_hi = GetRegInfo(high_reg); |
| 700 | info_lo->pair = info_hi->pair = true; |
| 701 | info_lo->partner = high_reg; |
| 702 | info_hi->partner = low_reg; |
| 703 | } |
| 704 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 705 | void Mir2Lir::MarkClean(RegLocation loc) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 706 | if (loc.wide) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 707 | RegisterInfo* info = GetRegInfo(loc.reg.GetLowReg()); |
| 708 | info->dirty = false; |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 709 | info = GetRegInfo(loc.reg.GetHighReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 710 | info->dirty = false; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 711 | } else { |
| 712 | RegisterInfo* info = GetRegInfo(loc.reg.GetReg()); |
| 713 | info->dirty = false; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 714 | } |
| 715 | } |
| 716 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 717 | void Mir2Lir::MarkDirty(RegLocation loc) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 718 | if (loc.home) { |
| 719 | // If already home, can't be dirty |
| 720 | return; |
| 721 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 722 | if (loc.wide) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 723 | RegisterInfo* info = GetRegInfo(loc.reg.GetLowReg()); |
| 724 | info->dirty = true; |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 725 | info = GetRegInfo(loc.reg.GetHighReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 726 | info->dirty = true; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 727 | } else { |
| 728 | RegisterInfo* info = GetRegInfo(loc.reg.GetReg()); |
| 729 | info->dirty = true; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 730 | } |
| 731 | } |
| 732 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 733 | void Mir2Lir::MarkInUse(int reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 734 | RegisterInfo* info = GetRegInfo(reg); |
| 735 | info->in_use = true; |
| 736 | } |
| 737 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 738 | void Mir2Lir::MarkInUse(RegStorage reg) { |
| 739 | if (reg.IsPair()) { |
| 740 | MarkInUse(reg.GetLowReg()); |
| 741 | MarkInUse(reg.GetHighReg()); |
| 742 | } else { |
| 743 | MarkInUse(reg.GetReg()); |
| 744 | } |
| 745 | } |
| 746 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 747 | void Mir2Lir::CopyRegInfo(int new_reg, int old_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 748 | RegisterInfo* new_info = GetRegInfo(new_reg); |
| 749 | RegisterInfo* old_info = GetRegInfo(old_reg); |
| 750 | // Target temp status must not change |
| 751 | bool is_temp = new_info->is_temp; |
| 752 | *new_info = *old_info; |
| 753 | // Restore target's temp status |
| 754 | new_info->is_temp = is_temp; |
| 755 | new_info->reg = new_reg; |
| 756 | } |
| 757 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 758 | void Mir2Lir::CopyRegInfo(RegStorage new_reg, RegStorage old_reg) { |
| 759 | DCHECK(!new_reg.IsPair()); |
| 760 | DCHECK(!old_reg.IsPair()); |
| 761 | CopyRegInfo(new_reg.GetReg(), old_reg.GetReg()); |
| 762 | } |
| 763 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 764 | bool Mir2Lir::CheckCorePoolSanity() { |
Brian Carlstrom | 6f485c6 | 2013-07-18 15:35:35 -0700 | [diff] [blame] | 765 | for (static int i = 0; i < reg_pool_->num_core_regs; i++) { |
| 766 | if (reg_pool_->core_regs[i].pair) { |
| 767 | static int my_reg = reg_pool_->core_regs[i].reg; |
| 768 | static int my_sreg = reg_pool_->core_regs[i].s_reg; |
| 769 | static int partner_reg = reg_pool_->core_regs[i].partner; |
| 770 | static RegisterInfo* partner = GetRegInfo(partner_reg); |
| 771 | DCHECK(partner != NULL); |
| 772 | DCHECK(partner->pair); |
| 773 | DCHECK_EQ(my_reg, partner->partner); |
| 774 | static int partner_sreg = partner->s_reg; |
| 775 | if (my_sreg == INVALID_SREG) { |
| 776 | DCHECK_EQ(partner_sreg, INVALID_SREG); |
| 777 | } else { |
| 778 | int diff = my_sreg - partner_sreg; |
| 779 | DCHECK((diff == -1) || (diff == 1)); |
| 780 | } |
| 781 | } |
| 782 | if (!reg_pool_->core_regs[i].live) { |
| 783 | DCHECK(reg_pool_->core_regs[i].def_start == NULL); |
| 784 | DCHECK(reg_pool_->core_regs[i].def_end == NULL); |
| 785 | } |
| 786 | } |
| 787 | return true; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 788 | } |
| 789 | |
| 790 | /* |
| 791 | * Return an updated location record with current in-register status. |
| 792 | * If the value lives in live temps, reflect that fact. No code |
| 793 | * is generated. If the live value is part of an older pair, |
| 794 | * clobber both low and high. |
| 795 | * TUNING: clobbering both is a bit heavy-handed, but the alternative |
| 796 | * is a bit complex when dealing with FP regs. Examine code to see |
| 797 | * if it's worthwhile trying to be more clever here. |
| 798 | */ |
| 799 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 800 | RegLocation Mir2Lir::UpdateLoc(RegLocation loc) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 801 | DCHECK(!loc.wide); |
| 802 | DCHECK(CheckCorePoolSanity()); |
| 803 | if (loc.location != kLocPhysReg) { |
| 804 | DCHECK((loc.location == kLocDalvikFrame) || |
| 805 | (loc.location == kLocCompilerTemp)); |
| 806 | RegisterInfo* info_lo = AllocLive(loc.s_reg_low, kAnyReg); |
| 807 | if (info_lo) { |
| 808 | if (info_lo->pair) { |
| 809 | Clobber(info_lo->reg); |
| 810 | Clobber(info_lo->partner); |
| 811 | FreeTemp(info_lo->reg); |
| 812 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 813 | loc.reg = RegStorage::Solo32(info_lo->reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 814 | loc.location = kLocPhysReg; |
| 815 | } |
| 816 | } |
| 817 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 818 | return loc; |
| 819 | } |
| 820 | |
| 821 | /* see comments for update_loc */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 822 | RegLocation Mir2Lir::UpdateLocWide(RegLocation loc) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 823 | DCHECK(loc.wide); |
| 824 | DCHECK(CheckCorePoolSanity()); |
| 825 | if (loc.location != kLocPhysReg) { |
| 826 | DCHECK((loc.location == kLocDalvikFrame) || |
| 827 | (loc.location == kLocCompilerTemp)); |
| 828 | // Are the dalvik regs already live in physical registers? |
| 829 | RegisterInfo* info_lo = AllocLive(loc.s_reg_low, kAnyReg); |
| 830 | RegisterInfo* info_hi = AllocLive(GetSRegHi(loc.s_reg_low), kAnyReg); |
| 831 | bool match = true; |
| 832 | match = match && (info_lo != NULL); |
| 833 | match = match && (info_hi != NULL); |
| 834 | // Are they both core or both FP? |
| 835 | match = match && (IsFpReg(info_lo->reg) == IsFpReg(info_hi->reg)); |
| 836 | // If a pair of floating point singles, are they properly aligned? |
| 837 | if (match && IsFpReg(info_lo->reg)) { |
| 838 | match &= ((info_lo->reg & 0x1) == 0); |
| 839 | match &= ((info_hi->reg - info_lo->reg) == 1); |
| 840 | } |
| 841 | // If previously used as a pair, it is the same pair? |
| 842 | if (match && (info_lo->pair || info_hi->pair)) { |
| 843 | match = (info_lo->pair == info_hi->pair); |
| 844 | match &= ((info_lo->reg == info_hi->partner) && |
| 845 | (info_hi->reg == info_lo->partner)); |
| 846 | } |
| 847 | if (match) { |
| 848 | // Can reuse - update the register usage info |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 849 | loc.location = kLocPhysReg; |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 850 | loc.reg = RegStorage(RegStorage::k64BitPair, info_lo->reg, info_hi->reg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 851 | MarkPair(loc.reg.GetLowReg(), loc.reg.GetHighReg()); |
| 852 | DCHECK(!IsFpReg(loc.reg.GetLowReg()) || ((loc.reg.GetLowReg() & 0x1) == 0)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 853 | return loc; |
| 854 | } |
| 855 | // Can't easily reuse - clobber and free any overlaps |
| 856 | if (info_lo) { |
| 857 | Clobber(info_lo->reg); |
| 858 | FreeTemp(info_lo->reg); |
| 859 | if (info_lo->pair) |
| 860 | Clobber(info_lo->partner); |
| 861 | } |
| 862 | if (info_hi) { |
| 863 | Clobber(info_hi->reg); |
| 864 | FreeTemp(info_hi->reg); |
| 865 | if (info_hi->pair) |
| 866 | Clobber(info_hi->partner); |
| 867 | } |
| 868 | } |
| 869 | return loc; |
| 870 | } |
| 871 | |
| 872 | |
| 873 | /* For use in cases we don't know (or care) width */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 874 | RegLocation Mir2Lir::UpdateRawLoc(RegLocation loc) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 875 | if (loc.wide) |
| 876 | return UpdateLocWide(loc); |
| 877 | else |
| 878 | return UpdateLoc(loc); |
| 879 | } |
| 880 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 881 | RegLocation Mir2Lir::EvalLocWide(RegLocation loc, int reg_class, bool update) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 882 | DCHECK(loc.wide); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 883 | |
| 884 | loc = UpdateLocWide(loc); |
| 885 | |
| 886 | /* If already in registers, we can assume proper form. Right reg class? */ |
| 887 | if (loc.location == kLocPhysReg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 888 | DCHECK_EQ(IsFpReg(loc.reg.GetLowReg()), IsFpReg(loc.reg.GetHighReg())); |
| 889 | DCHECK(!IsFpReg(loc.reg.GetLowReg()) || ((loc.reg.GetLowReg() & 0x1) == 0)); |
| 890 | if (!RegClassMatches(reg_class, loc.reg)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 891 | /* Wrong register class. Reallocate and copy */ |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 892 | RegStorage new_regs = AllocTypedTempWide(loc.fp, reg_class); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 893 | OpRegCopyWide(new_regs, loc.reg); |
| 894 | CopyRegInfo(new_regs.GetLowReg(), loc.reg.GetLowReg()); |
| 895 | CopyRegInfo(new_regs.GetHighReg(), loc.reg.GetHighReg()); |
| 896 | Clobber(loc.reg); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 897 | loc.reg = new_regs; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 898 | MarkPair(loc.reg.GetLowReg(), loc.reg.GetHighReg()); |
| 899 | DCHECK(!IsFpReg(loc.reg.GetLowReg()) || ((loc.reg.GetLowReg() & 0x1) == 0)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 900 | } |
| 901 | return loc; |
| 902 | } |
| 903 | |
| 904 | DCHECK_NE(loc.s_reg_low, INVALID_SREG); |
| 905 | DCHECK_NE(GetSRegHi(loc.s_reg_low), INVALID_SREG); |
| 906 | |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 907 | loc.reg = AllocTypedTempWide(loc.fp, reg_class); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 908 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 909 | MarkPair(loc.reg.GetLowReg(), loc.reg.GetHighReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 910 | if (update) { |
| 911 | loc.location = kLocPhysReg; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 912 | MarkLive(loc.reg.GetLow(), loc.s_reg_low); |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 913 | // Does this wide value live in two registers or one vector register? |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 914 | if (loc.reg.GetLowReg() != loc.reg.GetHighReg()) { |
| 915 | MarkLive(loc.reg.GetHigh(), GetSRegHi(loc.s_reg_low)); |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 916 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 917 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 918 | DCHECK(!IsFpReg(loc.reg.GetLowReg()) || ((loc.reg.GetLowReg() & 0x1) == 0)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 919 | return loc; |
| 920 | } |
| 921 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 922 | RegLocation Mir2Lir::EvalLoc(RegLocation loc, int reg_class, bool update) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 923 | if (loc.wide) |
| 924 | return EvalLocWide(loc, reg_class, update); |
| 925 | |
| 926 | loc = UpdateLoc(loc); |
| 927 | |
| 928 | if (loc.location == kLocPhysReg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 929 | if (!RegClassMatches(reg_class, loc.reg)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 930 | /* Wrong register class. Realloc, copy and transfer ownership */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 931 | RegStorage new_reg = AllocTypedTemp(loc.fp, reg_class); |
| 932 | OpRegCopy(new_reg, loc.reg); |
| 933 | CopyRegInfo(new_reg, loc.reg); |
| 934 | Clobber(loc.reg); |
| 935 | loc.reg = new_reg; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 936 | } |
| 937 | return loc; |
| 938 | } |
| 939 | |
| 940 | DCHECK_NE(loc.s_reg_low, INVALID_SREG); |
| 941 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 942 | loc.reg = AllocTypedTemp(loc.fp, reg_class); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 943 | |
| 944 | if (update) { |
| 945 | loc.location = kLocPhysReg; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 946 | MarkLive(loc.reg, loc.s_reg_low); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 947 | } |
| 948 | return loc; |
| 949 | } |
| 950 | |
| 951 | /* USE SSA names to count references of base Dalvik v_regs. */ |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 952 | void Mir2Lir::CountRefs(RefCounts* core_counts, RefCounts* fp_counts, size_t num_regs) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 953 | for (int i = 0; i < mir_graph_->GetNumSSARegs(); i++) { |
| 954 | RegLocation loc = mir_graph_->reg_location_[i]; |
| 955 | RefCounts* counts = loc.fp ? fp_counts : core_counts; |
| 956 | int p_map_idx = SRegToPMap(loc.s_reg_low); |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 957 | if (loc.fp) { |
| 958 | if (loc.wide) { |
| 959 | // Treat doubles as a unit, using upper half of fp_counts array. |
| 960 | counts[p_map_idx + num_regs].count += mir_graph_->GetUseCount(i); |
| 961 | i++; |
| 962 | } else { |
| 963 | counts[p_map_idx].count += mir_graph_->GetUseCount(i); |
| 964 | } |
| 965 | } else if (!IsInexpensiveConstant(loc)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 966 | counts[p_map_idx].count += mir_graph_->GetUseCount(i); |
| 967 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 968 | } |
| 969 | } |
| 970 | |
| 971 | /* qsort callback function, sort descending */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 972 | static int SortCounts(const void *val1, const void *val2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 973 | const Mir2Lir::RefCounts* op1 = reinterpret_cast<const Mir2Lir::RefCounts*>(val1); |
| 974 | const Mir2Lir::RefCounts* op2 = reinterpret_cast<const Mir2Lir::RefCounts*>(val2); |
Brian Carlstrom | 4b8c13e | 2013-08-23 18:10:32 -0700 | [diff] [blame] | 975 | // Note that we fall back to sorting on reg so we get stable output |
| 976 | // on differing qsort implementations (such as on host and target or |
| 977 | // between local host and build servers). |
| 978 | return (op1->count == op2->count) |
| 979 | ? (op1->s_reg - op2->s_reg) |
| 980 | : (op1->count < op2->count ? 1 : -1); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 981 | } |
| 982 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 983 | void Mir2Lir::DumpCounts(const RefCounts* arr, int size, const char* msg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 984 | LOG(INFO) << msg; |
| 985 | for (int i = 0; i < size; i++) { |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 986 | if ((arr[i].s_reg & STARTING_DOUBLE_SREG) != 0) { |
| 987 | LOG(INFO) << "s_reg[D" << (arr[i].s_reg & ~STARTING_DOUBLE_SREG) << "]: " << arr[i].count; |
| 988 | } else { |
| 989 | LOG(INFO) << "s_reg[" << arr[i].s_reg << "]: " << arr[i].count; |
| 990 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 991 | } |
| 992 | } |
| 993 | |
| 994 | /* |
| 995 | * Note: some portions of this code required even if the kPromoteRegs |
| 996 | * optimization is disabled. |
| 997 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 998 | void Mir2Lir::DoPromotion() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 999 | int dalvik_regs = cu_->num_dalvik_registers; |
Razvan A Lupusoru | da7a69b | 2014-01-08 15:09:50 -0800 | [diff] [blame] | 1000 | int num_regs = dalvik_regs + mir_graph_->GetNumUsedCompilerTemps(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1001 | const int promotion_threshold = 1; |
buzbee | d69835d | 2014-02-03 14:40:27 -0800 | [diff] [blame] | 1002 | // Allocate the promotion map - one entry for each Dalvik vReg or compiler temp |
| 1003 | promotion_map_ = static_cast<PromotionMap*> |
Vladimir Marko | 83cc7ae | 2014-02-12 18:02:05 +0000 | [diff] [blame] | 1004 | (arena_->Alloc(num_regs * sizeof(promotion_map_[0]), kArenaAllocRegAlloc)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1005 | |
| 1006 | // Allow target code to add any special registers |
| 1007 | AdjustSpillMask(); |
| 1008 | |
| 1009 | /* |
| 1010 | * Simple register promotion. Just do a static count of the uses |
| 1011 | * of Dalvik registers. Note that we examine the SSA names, but |
| 1012 | * count based on original Dalvik register name. Count refs |
| 1013 | * separately based on type in order to give allocation |
| 1014 | * preference to fp doubles - which must be allocated sequential |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 1015 | * physical single fp registers starting with an even-numbered |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1016 | * reg. |
| 1017 | * TUNING: replace with linear scan once we have the ability |
| 1018 | * to describe register live ranges for GC. |
| 1019 | */ |
| 1020 | RefCounts *core_regs = |
Mathieu Chartier | f6c4b3b | 2013-08-24 16:11:37 -0700 | [diff] [blame] | 1021 | static_cast<RefCounts*>(arena_->Alloc(sizeof(RefCounts) * num_regs, |
Vladimir Marko | 83cc7ae | 2014-02-12 18:02:05 +0000 | [diff] [blame] | 1022 | kArenaAllocRegAlloc)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1023 | RefCounts *FpRegs = |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 1024 | static_cast<RefCounts *>(arena_->Alloc(sizeof(RefCounts) * num_regs * 2, |
Vladimir Marko | 83cc7ae | 2014-02-12 18:02:05 +0000 | [diff] [blame] | 1025 | kArenaAllocRegAlloc)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1026 | // Set ssa names for original Dalvik registers |
| 1027 | for (int i = 0; i < dalvik_regs; i++) { |
| 1028 | core_regs[i].s_reg = FpRegs[i].s_reg = i; |
| 1029 | } |
Razvan A Lupusoru | da7a69b | 2014-01-08 15:09:50 -0800 | [diff] [blame] | 1030 | |
| 1031 | // Set ssa names for compiler temporaries |
| 1032 | for (unsigned int ct_idx = 0; ct_idx < mir_graph_->GetNumUsedCompilerTemps(); ct_idx++) { |
| 1033 | CompilerTemp* ct = mir_graph_->GetCompilerTemp(ct_idx); |
| 1034 | core_regs[dalvik_regs + ct_idx].s_reg = ct->s_reg_low; |
| 1035 | FpRegs[dalvik_regs + ct_idx].s_reg = ct->s_reg_low; |
| 1036 | FpRegs[num_regs + dalvik_regs + ct_idx].s_reg = ct->s_reg_low; |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 1037 | } |
| 1038 | |
| 1039 | // Duplicate in upper half to represent possible fp double starting sregs. |
| 1040 | for (int i = 0; i < num_regs; i++) { |
| 1041 | FpRegs[num_regs + i].s_reg = FpRegs[i].s_reg | STARTING_DOUBLE_SREG; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1042 | } |
| 1043 | |
| 1044 | // Sum use counts of SSA regs by original Dalvik vreg. |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 1045 | CountRefs(core_regs, FpRegs, num_regs); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1046 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1047 | |
| 1048 | // Sort the count arrays |
| 1049 | qsort(core_regs, num_regs, sizeof(RefCounts), SortCounts); |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 1050 | qsort(FpRegs, num_regs * 2, sizeof(RefCounts), SortCounts); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1051 | |
| 1052 | if (cu_->verbose) { |
| 1053 | DumpCounts(core_regs, num_regs, "Core regs after sort"); |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 1054 | DumpCounts(FpRegs, num_regs * 2, "Fp regs after sort"); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1055 | } |
| 1056 | |
| 1057 | if (!(cu_->disable_opt & (1 << kPromoteRegs))) { |
| 1058 | // Promote FpRegs |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 1059 | for (int i = 0; (i < (num_regs * 2)) && (FpRegs[i].count >= promotion_threshold); i++) { |
| 1060 | int p_map_idx = SRegToPMap(FpRegs[i].s_reg & ~STARTING_DOUBLE_SREG); |
| 1061 | if ((FpRegs[i].s_reg & STARTING_DOUBLE_SREG) != 0) { |
| 1062 | if ((promotion_map_[p_map_idx].fp_location != kLocPhysReg) && |
| 1063 | (promotion_map_[p_map_idx + 1].fp_location != kLocPhysReg)) { |
| 1064 | int low_sreg = FpRegs[i].s_reg & ~STARTING_DOUBLE_SREG; |
| 1065 | // Ignore result - if can't alloc double may still be able to alloc singles. |
| 1066 | AllocPreservedDouble(low_sreg); |
| 1067 | } |
| 1068 | } else if (promotion_map_[p_map_idx].fp_location != kLocPhysReg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 1069 | RegStorage reg = AllocPreservedSingle(FpRegs[i].s_reg); |
| 1070 | if (!reg.Valid()) { |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 1071 | break; // No more left. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1072 | } |
| 1073 | } |
| 1074 | } |
| 1075 | |
| 1076 | // Promote core regs |
| 1077 | for (int i = 0; (i < num_regs) && |
| 1078 | (core_regs[i].count >= promotion_threshold); i++) { |
| 1079 | int p_map_idx = SRegToPMap(core_regs[i].s_reg); |
| 1080 | if (promotion_map_[p_map_idx].core_location != |
| 1081 | kLocPhysReg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 1082 | RegStorage reg = AllocPreservedCoreReg(core_regs[i].s_reg); |
| 1083 | if (!reg.Valid()) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1084 | break; // No more left |
| 1085 | } |
| 1086 | } |
| 1087 | } |
| 1088 | } |
| 1089 | |
| 1090 | // Now, update SSA names to new home locations |
| 1091 | for (int i = 0; i < mir_graph_->GetNumSSARegs(); i++) { |
| 1092 | RegLocation *curr = &mir_graph_->reg_location_[i]; |
| 1093 | int p_map_idx = SRegToPMap(curr->s_reg_low); |
| 1094 | if (!curr->wide) { |
| 1095 | if (curr->fp) { |
| 1096 | if (promotion_map_[p_map_idx].fp_location == kLocPhysReg) { |
| 1097 | curr->location = kLocPhysReg; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 1098 | curr->reg = RegStorage::Solo32(promotion_map_[p_map_idx].FpReg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1099 | curr->home = true; |
| 1100 | } |
| 1101 | } else { |
| 1102 | if (promotion_map_[p_map_idx].core_location == kLocPhysReg) { |
| 1103 | curr->location = kLocPhysReg; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 1104 | curr->reg = RegStorage::Solo32(promotion_map_[p_map_idx].core_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1105 | curr->home = true; |
| 1106 | } |
| 1107 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1108 | } else { |
| 1109 | if (curr->high_word) { |
| 1110 | continue; |
| 1111 | } |
| 1112 | if (curr->fp) { |
| 1113 | if ((promotion_map_[p_map_idx].fp_location == kLocPhysReg) && |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1114 | (promotion_map_[p_map_idx+1].fp_location == kLocPhysReg)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1115 | int low_reg = promotion_map_[p_map_idx].FpReg; |
| 1116 | int high_reg = promotion_map_[p_map_idx+1].FpReg; |
| 1117 | // Doubles require pair of singles starting at even reg |
| 1118 | if (((low_reg & 0x1) == 0) && ((low_reg + 1) == high_reg)) { |
| 1119 | curr->location = kLocPhysReg; |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1120 | curr->reg = RegStorage(RegStorage::k64BitPair, low_reg, high_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1121 | curr->home = true; |
| 1122 | } |
| 1123 | } |
| 1124 | } else { |
| 1125 | if ((promotion_map_[p_map_idx].core_location == kLocPhysReg) |
| 1126 | && (promotion_map_[p_map_idx+1].core_location == |
| 1127 | kLocPhysReg)) { |
| 1128 | curr->location = kLocPhysReg; |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1129 | curr->reg = RegStorage(RegStorage::k64BitPair, promotion_map_[p_map_idx].core_reg, |
| 1130 | promotion_map_[p_map_idx+1].core_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1131 | curr->home = true; |
| 1132 | } |
| 1133 | } |
| 1134 | } |
| 1135 | } |
| 1136 | if (cu_->verbose) { |
| 1137 | DumpPromotionMap(); |
| 1138 | } |
| 1139 | } |
| 1140 | |
| 1141 | /* Returns sp-relative offset in bytes for a VReg */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1142 | int Mir2Lir::VRegOffset(int v_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1143 | return StackVisitor::GetVRegOffset(cu_->code_item, core_spill_mask_, |
| 1144 | fp_spill_mask_, frame_size_, v_reg); |
| 1145 | } |
| 1146 | |
| 1147 | /* Returns sp-relative offset in bytes for a SReg */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1148 | int Mir2Lir::SRegOffset(int s_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1149 | return VRegOffset(mir_graph_->SRegToVReg(s_reg)); |
| 1150 | } |
| 1151 | |
| 1152 | /* Mark register usage state and return long retloc */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1153 | RegLocation Mir2Lir::GetReturnWide(bool is_double) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1154 | RegLocation gpr_res = LocCReturnWide(); |
| 1155 | RegLocation fpr_res = LocCReturnDouble(); |
| 1156 | RegLocation res = is_double ? fpr_res : gpr_res; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 1157 | Clobber(res.reg.GetLowReg()); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1158 | Clobber(res.reg.GetHighReg()); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 1159 | LockTemp(res.reg.GetLowReg()); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1160 | LockTemp(res.reg.GetHighReg()); |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 1161 | // Does this wide value live in two registers or one vector register? |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 1162 | if (res.reg.GetLowReg() != res.reg.GetHighReg()) { |
| 1163 | MarkPair(res.reg.GetLowReg(), res.reg.GetHighReg()); |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 1164 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1165 | return res; |
| 1166 | } |
| 1167 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1168 | RegLocation Mir2Lir::GetReturn(bool is_float) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1169 | RegLocation gpr_res = LocCReturn(); |
| 1170 | RegLocation fpr_res = LocCReturnFloat(); |
| 1171 | RegLocation res = is_float ? fpr_res : gpr_res; |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1172 | Clobber(res.reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1173 | if (cu_->instruction_set == kMips) { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1174 | MarkInUse(res.reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1175 | } else { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1176 | LockTemp(res.reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1177 | } |
| 1178 | return res; |
| 1179 | } |
| 1180 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1181 | void Mir2Lir::SimpleRegAlloc() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1182 | DoPromotion(); |
| 1183 | |
| 1184 | if (cu_->verbose && !(cu_->disable_opt & (1 << kPromoteRegs))) { |
| 1185 | LOG(INFO) << "After Promotion"; |
| 1186 | mir_graph_->DumpRegLocTable(mir_graph_->reg_location_, mir_graph_->GetNumSSARegs()); |
| 1187 | } |
| 1188 | |
| 1189 | /* Set the frame size */ |
| 1190 | frame_size_ = ComputeFrameSize(); |
| 1191 | } |
| 1192 | |
| 1193 | /* |
| 1194 | * Get the "real" sreg number associated with an s_reg slot. In general, |
| 1195 | * s_reg values passed through codegen are the SSA names created by |
| 1196 | * dataflow analysis and refer to slot numbers in the mir_graph_->reg_location |
| 1197 | * array. However, renaming is accomplished by simply replacing RegLocation |
| 1198 | * entries in the reglocation[] array. Therefore, when location |
| 1199 | * records for operands are first created, we need to ask the locRecord |
| 1200 | * identified by the dataflow pass what it's new name is. |
| 1201 | */ |
| 1202 | int Mir2Lir::GetSRegHi(int lowSreg) { |
| 1203 | return (lowSreg == INVALID_SREG) ? INVALID_SREG : lowSreg + 1; |
| 1204 | } |
| 1205 | |
| 1206 | bool Mir2Lir::oat_live_out(int s_reg) { |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 1207 | // For now. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1208 | return true; |
| 1209 | } |
| 1210 | |
| 1211 | int Mir2Lir::oatSSASrc(MIR* mir, int num) { |
| 1212 | DCHECK_GT(mir->ssa_rep->num_uses, num); |
| 1213 | return mir->ssa_rep->uses[num]; |
| 1214 | } |
| 1215 | |
| 1216 | } // namespace art |