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David Srbeckydd973932015-04-07 20:29:48 +01001/*
2 * Copyright (C) 2015 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include <memory>
18#include <vector>
19
20#include "arch/instruction_set.h"
Vladimir Marko93205e32016-04-13 11:59:46 +010021#include "base/arena_allocator.h"
Andreas Gampe3b165bc2016-08-01 22:07:04 -070022#include "base/enums.h"
David Sehr3215fff2018-04-03 17:10:12 -070023#include "base/malloc_arena_pool.h"
David Srbeckydd973932015-04-07 20:29:48 +010024#include "cfi_test.h"
25#include "gtest/gtest.h"
26#include "jni/quick/calling_convention.h"
Andreas Gampe217488a2017-09-18 08:34:42 -070027#include "read_barrier_config.h"
David Srbeckydd973932015-04-07 20:29:48 +010028#include "utils/assembler.h"
Andreas Gampe3b165bc2016-08-01 22:07:04 -070029#include "utils/jni_macro_assembler.h"
David Srbeckydd973932015-04-07 20:29:48 +010030
31#include "jni/jni_cfi_test_expected.inc"
32
33namespace art {
34
35// Run the tests only on host.
Bilyan Borisovbb661c02016-04-04 16:27:32 +010036#ifndef ART_TARGET_ANDROID
David Srbeckydd973932015-04-07 20:29:48 +010037
38class JNICFITest : public CFITest {
39 public:
40 // Enable this flag to generate the expected outputs.
41 static constexpr bool kGenerateExpected = false;
42
Andreas Gampe3b165bc2016-08-01 22:07:04 -070043 void TestImpl(InstructionSet isa,
44 const char* isa_str,
David Srbeckydd973932015-04-07 20:29:48 +010045 const std::vector<uint8_t>& expected_asm,
46 const std::vector<uint8_t>& expected_cfi) {
Andreas Gampe3b165bc2016-08-01 22:07:04 -070047 if (Is64BitInstructionSet(isa)) {
48 TestImplSized<PointerSize::k64>(isa, isa_str, expected_asm, expected_cfi);
49 } else {
50 TestImplSized<PointerSize::k32>(isa, isa_str, expected_asm, expected_cfi);
51 }
52 }
53
54 private:
55 template <PointerSize kPointerSize>
56 void TestImplSized(InstructionSet isa,
57 const char* isa_str,
58 const std::vector<uint8_t>& expected_asm,
59 const std::vector<uint8_t>& expected_cfi) {
David Srbeckydd973932015-04-07 20:29:48 +010060 // Description of simple method.
61 const bool is_static = true;
62 const bool is_synchronized = false;
63 const char* shorty = "IIFII";
Vladimir Marko93205e32016-04-13 11:59:46 +010064
David Sehr3215fff2018-04-03 17:10:12 -070065 MallocArenaPool pool;
Vladimir Marko69d310e2017-10-09 14:12:23 +010066 ArenaAllocator allocator(&pool);
Vladimir Marko93205e32016-04-13 11:59:46 +010067
David Srbeckydd973932015-04-07 20:29:48 +010068 std::unique_ptr<JniCallingConvention> jni_conv(
Vladimir Marko69d310e2017-10-09 14:12:23 +010069 JniCallingConvention::Create(&allocator,
Igor Murashkin367f3dd2016-09-01 17:00:24 -070070 is_static,
71 is_synchronized,
72 /*is_critical_native*/false,
73 shorty,
74 isa));
David Srbeckydd973932015-04-07 20:29:48 +010075 std::unique_ptr<ManagedRuntimeCallingConvention> mr_conv(
Vladimir Marko69d310e2017-10-09 14:12:23 +010076 ManagedRuntimeCallingConvention::Create(
77 &allocator, is_static, is_synchronized, shorty, isa));
David Srbeckydd973932015-04-07 20:29:48 +010078 const int frame_size(jni_conv->FrameSize());
Vladimir Marko32248382016-05-19 10:37:24 +010079 ArrayRef<const ManagedRegister> callee_save_regs = jni_conv->CalleeSaveRegisters();
David Srbeckydd973932015-04-07 20:29:48 +010080
81 // Assemble the method.
Andreas Gampe3b165bc2016-08-01 22:07:04 -070082 std::unique_ptr<JNIMacroAssembler<kPointerSize>> jni_asm(
Vladimir Marko69d310e2017-10-09 14:12:23 +010083 JNIMacroAssembler<kPointerSize>::Create(&allocator, isa));
Vladimir Marko10ef6942015-10-22 15:25:54 +010084 jni_asm->cfi().SetEnabled(true);
David Srbeckydd973932015-04-07 20:29:48 +010085 jni_asm->BuildFrame(frame_size, mr_conv->MethodRegister(),
86 callee_save_regs, mr_conv->EntrySpills());
87 jni_asm->IncreaseFrameSize(32);
88 jni_asm->DecreaseFrameSize(32);
Andreas Gampe3db70682018-12-26 15:12:03 -080089 jni_asm->RemoveFrame(frame_size, callee_save_regs, /* may_suspend= */ true);
Vladimir Markocf93a5c2015-06-16 11:33:24 +000090 jni_asm->FinalizeCode();
David Srbeckydd973932015-04-07 20:29:48 +010091 std::vector<uint8_t> actual_asm(jni_asm->CodeSize());
92 MemoryRegion code(&actual_asm[0], actual_asm.size());
93 jni_asm->FinalizeInstructions(code);
94 ASSERT_EQ(jni_asm->cfi().GetCurrentCFAOffset(), frame_size);
95 const std::vector<uint8_t>& actual_cfi = *(jni_asm->cfi().data());
96
97 if (kGenerateExpected) {
Vladimir Markoca1e0382018-04-11 09:58:41 +000098 GenerateExpected(stdout,
99 isa,
100 isa_str,
101 ArrayRef<const uint8_t>(actual_asm),
102 ArrayRef<const uint8_t>(actual_cfi));
David Srbeckydd973932015-04-07 20:29:48 +0100103 } else {
104 EXPECT_EQ(expected_asm, actual_asm);
105 EXPECT_EQ(expected_cfi, actual_cfi);
106 }
107 }
108};
109
Vladimir Marko33bff252017-11-01 14:35:42 +0000110#define TEST_ISA(isa) \
111 TEST_F(JNICFITest, isa) { \
112 std::vector<uint8_t> expected_asm(expected_asm_##isa, \
113 expected_asm_##isa + arraysize(expected_asm_##isa)); \
114 std::vector<uint8_t> expected_cfi(expected_cfi_##isa, \
115 expected_cfi_##isa + arraysize(expected_cfi_##isa)); \
116 TestImpl(InstructionSet::isa, #isa, expected_asm, expected_cfi); \
David Srbeckydd973932015-04-07 20:29:48 +0100117 }
118
Colin Crossa75b01a2016-08-18 13:45:24 -0700119#ifdef ART_ENABLE_CODEGEN_arm
Roland Levillain6d729a72017-06-30 18:34:01 +0100120// Run the tests for ARM only with Baker read barriers, as the
121// expected generated code contains a Marking Register refresh
122// instruction.
123#if defined(USE_READ_BARRIER) && defined(USE_BAKER_READ_BARRIER)
David Srbeckydd973932015-04-07 20:29:48 +0100124TEST_ISA(kThumb2)
Colin Crossa75b01a2016-08-18 13:45:24 -0700125#endif
Roland Levillain6d729a72017-06-30 18:34:01 +0100126#endif
Roland Levillainaf24def2017-07-12 13:18:01 +0100127
Colin Crossa75b01a2016-08-18 13:45:24 -0700128#ifdef ART_ENABLE_CODEGEN_arm64
Roland Levillainaf24def2017-07-12 13:18:01 +0100129// Run the tests for ARM64 only with Baker read barriers, as the
130// expected generated code contains a Marking Register refresh
131// instruction.
132#if defined(USE_READ_BARRIER) && defined(USE_BAKER_READ_BARRIER)
David Srbeckydd973932015-04-07 20:29:48 +0100133TEST_ISA(kArm64)
Colin Crossa75b01a2016-08-18 13:45:24 -0700134#endif
Roland Levillainaf24def2017-07-12 13:18:01 +0100135#endif
136
Colin Crossa75b01a2016-08-18 13:45:24 -0700137#ifdef ART_ENABLE_CODEGEN_x86
David Srbeckydd973932015-04-07 20:29:48 +0100138TEST_ISA(kX86)
Colin Crossa75b01a2016-08-18 13:45:24 -0700139#endif
Roland Levillainaf24def2017-07-12 13:18:01 +0100140
Colin Crossa75b01a2016-08-18 13:45:24 -0700141#ifdef ART_ENABLE_CODEGEN_x86_64
David Srbeckydd973932015-04-07 20:29:48 +0100142TEST_ISA(kX86_64)
Colin Crossa75b01a2016-08-18 13:45:24 -0700143#endif
Roland Levillainaf24def2017-07-12 13:18:01 +0100144
Colin Crossa75b01a2016-08-18 13:45:24 -0700145#ifdef ART_ENABLE_CODEGEN_mips
David Srbeckydd973932015-04-07 20:29:48 +0100146TEST_ISA(kMips)
Colin Crossa75b01a2016-08-18 13:45:24 -0700147#endif
Roland Levillainaf24def2017-07-12 13:18:01 +0100148
Colin Crossa75b01a2016-08-18 13:45:24 -0700149#ifdef ART_ENABLE_CODEGEN_mips64
David Srbeckydd973932015-04-07 20:29:48 +0100150TEST_ISA(kMips64)
Colin Crossa75b01a2016-08-18 13:45:24 -0700151#endif
David Srbeckydd973932015-04-07 20:29:48 +0100152
Bilyan Borisovbb661c02016-04-04 16:27:32 +0100153#endif // ART_TARGET_ANDROID
David Srbeckydd973932015-04-07 20:29:48 +0100154
155} // namespace art