Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2014 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #ifndef ART_COMPILER_UTILS_MIPS64_ASSEMBLER_MIPS64_H_ |
| 18 | #define ART_COMPILER_UTILS_MIPS64_ASSEMBLER_MIPS64_H_ |
| 19 | |
Alexey Frunze | 19f6c69 | 2016-11-30 19:19:55 -0800 | [diff] [blame] | 20 | #include <deque> |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 21 | #include <utility> |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 22 | #include <vector> |
| 23 | |
Alexey Frunze | 19f6c69 | 2016-11-30 19:19:55 -0800 | [diff] [blame] | 24 | #include "base/arena_containers.h" |
Andreas Gampe | 3b165bc | 2016-08-01 22:07:04 -0700 | [diff] [blame] | 25 | #include "base/enums.h" |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 26 | #include "base/macros.h" |
| 27 | #include "constants_mips64.h" |
| 28 | #include "globals.h" |
| 29 | #include "managed_register_mips64.h" |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 30 | #include "offsets.h" |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 31 | #include "utils/assembler.h" |
Andreas Gampe | 3b165bc | 2016-08-01 22:07:04 -0700 | [diff] [blame] | 32 | #include "utils/jni_macro_assembler.h" |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 33 | #include "utils/label.h" |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 34 | |
| 35 | namespace art { |
| 36 | namespace mips64 { |
| 37 | |
Chris Larsen | c733dca | 2016-05-13 16:11:47 -0700 | [diff] [blame] | 38 | enum LoadConst64Path { |
| 39 | kLoadConst64PathZero = 0x0, |
| 40 | kLoadConst64PathOri = 0x1, |
| 41 | kLoadConst64PathDaddiu = 0x2, |
| 42 | kLoadConst64PathLui = 0x4, |
| 43 | kLoadConst64PathLuiOri = 0x8, |
| 44 | kLoadConst64PathOriDahi = 0x10, |
| 45 | kLoadConst64PathOriDati = 0x20, |
| 46 | kLoadConst64PathLuiDahi = 0x40, |
| 47 | kLoadConst64PathLuiDati = 0x80, |
| 48 | kLoadConst64PathDaddiuDsrlX = 0x100, |
| 49 | kLoadConst64PathOriDsllX = 0x200, |
| 50 | kLoadConst64PathDaddiuDsllX = 0x400, |
| 51 | kLoadConst64PathLuiOriDsllX = 0x800, |
| 52 | kLoadConst64PathOriDsllXOri = 0x1000, |
| 53 | kLoadConst64PathDaddiuDsllXOri = 0x2000, |
| 54 | kLoadConst64PathDaddiuDahi = 0x4000, |
| 55 | kLoadConst64PathDaddiuDati = 0x8000, |
| 56 | kLoadConst64PathDinsu1 = 0x10000, |
| 57 | kLoadConst64PathDinsu2 = 0x20000, |
| 58 | kLoadConst64PathCatchAll = 0x40000, |
| 59 | kLoadConst64PathAllPaths = 0x7ffff, |
| 60 | }; |
| 61 | |
| 62 | template <typename Asm> |
| 63 | void TemplateLoadConst32(Asm* a, GpuRegister rd, int32_t value) { |
| 64 | if (IsUint<16>(value)) { |
| 65 | // Use OR with (unsigned) immediate to encode 16b unsigned int. |
| 66 | a->Ori(rd, ZERO, value); |
| 67 | } else if (IsInt<16>(value)) { |
| 68 | // Use ADD with (signed) immediate to encode 16b signed int. |
| 69 | a->Addiu(rd, ZERO, value); |
| 70 | } else { |
| 71 | // Set 16 most significant bits of value. The "lui" instruction |
| 72 | // also clears the 16 least significant bits to zero. |
| 73 | a->Lui(rd, value >> 16); |
| 74 | if (value & 0xFFFF) { |
| 75 | // If the 16 least significant bits are non-zero, set them |
| 76 | // here. |
| 77 | a->Ori(rd, rd, value); |
| 78 | } |
| 79 | } |
| 80 | } |
| 81 | |
| 82 | static inline int InstrCountForLoadReplicatedConst32(int64_t value) { |
| 83 | int32_t x = Low32Bits(value); |
| 84 | int32_t y = High32Bits(value); |
| 85 | |
| 86 | if (x == y) { |
| 87 | return (IsUint<16>(x) || IsInt<16>(x) || ((x & 0xFFFF) == 0 && IsInt<16>(value >> 16))) ? 2 : 3; |
| 88 | } |
| 89 | |
| 90 | return INT_MAX; |
| 91 | } |
| 92 | |
| 93 | template <typename Asm, typename Rtype, typename Vtype> |
| 94 | void TemplateLoadConst64(Asm* a, Rtype rd, Vtype value) { |
| 95 | int bit31 = (value & UINT64_C(0x80000000)) != 0; |
| 96 | int rep32_count = InstrCountForLoadReplicatedConst32(value); |
| 97 | |
| 98 | // Loads with 1 instruction. |
| 99 | if (IsUint<16>(value)) { |
| 100 | // 64-bit value can be loaded as an unsigned 16-bit number. |
| 101 | a->RecordLoadConst64Path(kLoadConst64PathOri); |
| 102 | a->Ori(rd, ZERO, value); |
| 103 | } else if (IsInt<16>(value)) { |
| 104 | // 64-bit value can be loaded as an signed 16-bit number. |
| 105 | a->RecordLoadConst64Path(kLoadConst64PathDaddiu); |
| 106 | a->Daddiu(rd, ZERO, value); |
| 107 | } else if ((value & 0xFFFF) == 0 && IsInt<16>(value >> 16)) { |
| 108 | // 64-bit value can be loaded as an signed 32-bit number which has all |
| 109 | // of its 16 least significant bits set to zero. |
| 110 | a->RecordLoadConst64Path(kLoadConst64PathLui); |
| 111 | a->Lui(rd, value >> 16); |
| 112 | } else if (IsInt<32>(value)) { |
| 113 | // Loads with 2 instructions. |
| 114 | // 64-bit value can be loaded as an signed 32-bit number which has some |
| 115 | // or all of its 16 least significant bits set to one. |
| 116 | a->RecordLoadConst64Path(kLoadConst64PathLuiOri); |
| 117 | a->Lui(rd, value >> 16); |
| 118 | a->Ori(rd, rd, value); |
| 119 | } else if ((value & 0xFFFF0000) == 0 && IsInt<16>(value >> 32)) { |
| 120 | // 64-bit value which consists of an unsigned 16-bit value in its |
| 121 | // least significant 32-bits, and a signed 16-bit value in its |
| 122 | // most significant 32-bits. |
| 123 | a->RecordLoadConst64Path(kLoadConst64PathOriDahi); |
| 124 | a->Ori(rd, ZERO, value); |
| 125 | a->Dahi(rd, value >> 32); |
| 126 | } else if ((value & UINT64_C(0xFFFFFFFF0000)) == 0) { |
| 127 | // 64-bit value which consists of an unsigned 16-bit value in its |
| 128 | // least significant 48-bits, and a signed 16-bit value in its |
| 129 | // most significant 16-bits. |
| 130 | a->RecordLoadConst64Path(kLoadConst64PathOriDati); |
| 131 | a->Ori(rd, ZERO, value); |
| 132 | a->Dati(rd, value >> 48); |
| 133 | } else if ((value & 0xFFFF) == 0 && |
| 134 | (-32768 - bit31) <= (value >> 32) && (value >> 32) <= (32767 - bit31)) { |
| 135 | // 16 LSBs (Least Significant Bits) all set to zero. |
| 136 | // 48 MSBs (Most Significant Bits) hold a signed 32-bit value. |
| 137 | a->RecordLoadConst64Path(kLoadConst64PathLuiDahi); |
| 138 | a->Lui(rd, value >> 16); |
| 139 | a->Dahi(rd, (value >> 32) + bit31); |
| 140 | } else if ((value & 0xFFFF) == 0 && ((value >> 31) & 0x1FFFF) == ((0x20000 - bit31) & 0x1FFFF)) { |
| 141 | // 16 LSBs all set to zero. |
| 142 | // 48 MSBs hold a signed value which can't be represented by signed |
| 143 | // 32-bit number, and the middle 16 bits are all zero, or all one. |
| 144 | a->RecordLoadConst64Path(kLoadConst64PathLuiDati); |
| 145 | a->Lui(rd, value >> 16); |
| 146 | a->Dati(rd, (value >> 48) + bit31); |
| 147 | } else if (IsInt<16>(static_cast<int32_t>(value)) && |
| 148 | (-32768 - bit31) <= (value >> 32) && (value >> 32) <= (32767 - bit31)) { |
| 149 | // 32 LSBs contain an unsigned 16-bit number. |
| 150 | // 32 MSBs contain a signed 16-bit number. |
| 151 | a->RecordLoadConst64Path(kLoadConst64PathDaddiuDahi); |
| 152 | a->Daddiu(rd, ZERO, value); |
| 153 | a->Dahi(rd, (value >> 32) + bit31); |
| 154 | } else if (IsInt<16>(static_cast<int32_t>(value)) && |
| 155 | ((value >> 31) & 0x1FFFF) == ((0x20000 - bit31) & 0x1FFFF)) { |
| 156 | // 48 LSBs contain an unsigned 16-bit number. |
| 157 | // 16 MSBs contain a signed 16-bit number. |
| 158 | a->RecordLoadConst64Path(kLoadConst64PathDaddiuDati); |
| 159 | a->Daddiu(rd, ZERO, value); |
| 160 | a->Dati(rd, (value >> 48) + bit31); |
| 161 | } else if (IsPowerOfTwo(value + UINT64_C(1))) { |
| 162 | // 64-bit values which have their "n" MSBs set to one, and their |
| 163 | // "64-n" LSBs set to zero. "n" must meet the restrictions 0 < n < 64. |
| 164 | int shift_cnt = 64 - CTZ(value + UINT64_C(1)); |
| 165 | a->RecordLoadConst64Path(kLoadConst64PathDaddiuDsrlX); |
| 166 | a->Daddiu(rd, ZERO, -1); |
| 167 | if (shift_cnt < 32) { |
| 168 | a->Dsrl(rd, rd, shift_cnt); |
| 169 | } else { |
| 170 | a->Dsrl32(rd, rd, shift_cnt & 31); |
| 171 | } |
| 172 | } else { |
| 173 | int shift_cnt = CTZ(value); |
| 174 | int64_t tmp = value >> shift_cnt; |
| 175 | a->RecordLoadConst64Path(kLoadConst64PathOriDsllX); |
| 176 | if (IsUint<16>(tmp)) { |
| 177 | // Value can be computed by loading a 16-bit unsigned value, and |
| 178 | // then shifting left. |
| 179 | a->Ori(rd, ZERO, tmp); |
| 180 | if (shift_cnt < 32) { |
| 181 | a->Dsll(rd, rd, shift_cnt); |
| 182 | } else { |
| 183 | a->Dsll32(rd, rd, shift_cnt & 31); |
| 184 | } |
| 185 | } else if (IsInt<16>(tmp)) { |
| 186 | // Value can be computed by loading a 16-bit signed value, and |
| 187 | // then shifting left. |
| 188 | a->RecordLoadConst64Path(kLoadConst64PathDaddiuDsllX); |
| 189 | a->Daddiu(rd, ZERO, tmp); |
| 190 | if (shift_cnt < 32) { |
| 191 | a->Dsll(rd, rd, shift_cnt); |
| 192 | } else { |
| 193 | a->Dsll32(rd, rd, shift_cnt & 31); |
| 194 | } |
| 195 | } else if (rep32_count < 3) { |
| 196 | // Value being loaded has 32 LSBs equal to the 32 MSBs, and the |
| 197 | // value loaded into the 32 LSBs can be loaded with a single |
| 198 | // MIPS instruction. |
| 199 | a->LoadConst32(rd, value); |
| 200 | a->Dinsu(rd, rd, 32, 32); |
| 201 | a->RecordLoadConst64Path(kLoadConst64PathDinsu1); |
| 202 | } else if (IsInt<32>(tmp)) { |
| 203 | // Loads with 3 instructions. |
| 204 | // Value can be computed by loading a 32-bit signed value, and |
| 205 | // then shifting left. |
| 206 | a->RecordLoadConst64Path(kLoadConst64PathLuiOriDsllX); |
| 207 | a->Lui(rd, tmp >> 16); |
| 208 | a->Ori(rd, rd, tmp); |
| 209 | if (shift_cnt < 32) { |
| 210 | a->Dsll(rd, rd, shift_cnt); |
| 211 | } else { |
| 212 | a->Dsll32(rd, rd, shift_cnt & 31); |
| 213 | } |
| 214 | } else { |
| 215 | shift_cnt = 16 + CTZ(value >> 16); |
| 216 | tmp = value >> shift_cnt; |
| 217 | if (IsUint<16>(tmp)) { |
| 218 | // Value can be computed by loading a 16-bit unsigned value, |
| 219 | // shifting left, and "or"ing in another 16-bit unsigned value. |
| 220 | a->RecordLoadConst64Path(kLoadConst64PathOriDsllXOri); |
| 221 | a->Ori(rd, ZERO, tmp); |
| 222 | if (shift_cnt < 32) { |
| 223 | a->Dsll(rd, rd, shift_cnt); |
| 224 | } else { |
| 225 | a->Dsll32(rd, rd, shift_cnt & 31); |
| 226 | } |
| 227 | a->Ori(rd, rd, value); |
| 228 | } else if (IsInt<16>(tmp)) { |
| 229 | // Value can be computed by loading a 16-bit signed value, |
| 230 | // shifting left, and "or"ing in a 16-bit unsigned value. |
| 231 | a->RecordLoadConst64Path(kLoadConst64PathDaddiuDsllXOri); |
| 232 | a->Daddiu(rd, ZERO, tmp); |
| 233 | if (shift_cnt < 32) { |
| 234 | a->Dsll(rd, rd, shift_cnt); |
| 235 | } else { |
| 236 | a->Dsll32(rd, rd, shift_cnt & 31); |
| 237 | } |
| 238 | a->Ori(rd, rd, value); |
| 239 | } else if (rep32_count < 4) { |
| 240 | // Value being loaded has 32 LSBs equal to the 32 MSBs, and the |
| 241 | // value in the 32 LSBs requires 2 MIPS instructions to load. |
| 242 | a->LoadConst32(rd, value); |
| 243 | a->Dinsu(rd, rd, 32, 32); |
| 244 | a->RecordLoadConst64Path(kLoadConst64PathDinsu2); |
| 245 | } else { |
| 246 | // Loads with 3-4 instructions. |
| 247 | // Catch-all case to get any other 64-bit values which aren't |
| 248 | // handled by special cases above. |
| 249 | uint64_t tmp2 = value; |
| 250 | a->RecordLoadConst64Path(kLoadConst64PathCatchAll); |
| 251 | a->LoadConst32(rd, value); |
| 252 | if (bit31) { |
| 253 | tmp2 += UINT64_C(0x100000000); |
| 254 | } |
| 255 | if (((tmp2 >> 32) & 0xFFFF) != 0) { |
| 256 | a->Dahi(rd, tmp2 >> 32); |
| 257 | } |
| 258 | if (tmp2 & UINT64_C(0x800000000000)) { |
| 259 | tmp2 += UINT64_C(0x1000000000000); |
| 260 | } |
| 261 | if ((tmp2 >> 48) != 0) { |
| 262 | a->Dati(rd, tmp2 >> 48); |
| 263 | } |
| 264 | } |
| 265 | } |
| 266 | } |
| 267 | } |
| 268 | |
Goran Jakovljevic | 5a9e51d | 2017-03-16 16:11:43 +0000 | [diff] [blame^] | 269 | static constexpr size_t kMips64HalfwordSize = 2; |
Lazar Trsic | d967266 | 2015-09-03 17:33:01 +0200 | [diff] [blame] | 270 | static constexpr size_t kMips64WordSize = 4; |
| 271 | static constexpr size_t kMips64DoublewordSize = 8; |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 272 | |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 273 | enum LoadOperandType { |
| 274 | kLoadSignedByte, |
| 275 | kLoadUnsignedByte, |
| 276 | kLoadSignedHalfword, |
| 277 | kLoadUnsignedHalfword, |
| 278 | kLoadWord, |
Douglas Leung | d90957f | 2015-04-30 19:22:49 -0700 | [diff] [blame] | 279 | kLoadUnsignedWord, |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 280 | kLoadDoubleword |
| 281 | }; |
| 282 | |
| 283 | enum StoreOperandType { |
| 284 | kStoreByte, |
| 285 | kStoreHalfword, |
| 286 | kStoreWord, |
| 287 | kStoreDoubleword |
| 288 | }; |
| 289 | |
Chris Larsen | 1450082 | 2015-10-01 11:35:18 -0700 | [diff] [blame] | 290 | // Used to test the values returned by ClassS/ClassD. |
| 291 | enum FPClassMaskType { |
| 292 | kSignalingNaN = 0x001, |
| 293 | kQuietNaN = 0x002, |
| 294 | kNegativeInfinity = 0x004, |
| 295 | kNegativeNormal = 0x008, |
| 296 | kNegativeSubnormal = 0x010, |
| 297 | kNegativeZero = 0x020, |
| 298 | kPositiveInfinity = 0x040, |
| 299 | kPositiveNormal = 0x080, |
| 300 | kPositiveSubnormal = 0x100, |
| 301 | kPositiveZero = 0x200, |
| 302 | }; |
| 303 | |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 304 | class Mips64Label : public Label { |
| 305 | public: |
| 306 | Mips64Label() : prev_branch_id_plus_one_(0) {} |
| 307 | |
| 308 | Mips64Label(Mips64Label&& src) |
| 309 | : Label(std::move(src)), prev_branch_id_plus_one_(src.prev_branch_id_plus_one_) {} |
| 310 | |
| 311 | private: |
| 312 | uint32_t prev_branch_id_plus_one_; // To get distance from preceding branch, if any. |
| 313 | |
| 314 | friend class Mips64Assembler; |
| 315 | DISALLOW_COPY_AND_ASSIGN(Mips64Label); |
| 316 | }; |
| 317 | |
Alexey Frunze | 19f6c69 | 2016-11-30 19:19:55 -0800 | [diff] [blame] | 318 | // Assembler literal is a value embedded in code, retrieved using a PC-relative load. |
| 319 | class Literal { |
| 320 | public: |
| 321 | static constexpr size_t kMaxSize = 8; |
| 322 | |
| 323 | Literal(uint32_t size, const uint8_t* data) |
| 324 | : label_(), size_(size) { |
| 325 | DCHECK_LE(size, Literal::kMaxSize); |
| 326 | memcpy(data_, data, size); |
| 327 | } |
| 328 | |
| 329 | template <typename T> |
| 330 | T GetValue() const { |
| 331 | DCHECK_EQ(size_, sizeof(T)); |
| 332 | T value; |
| 333 | memcpy(&value, data_, sizeof(T)); |
| 334 | return value; |
| 335 | } |
| 336 | |
| 337 | uint32_t GetSize() const { |
| 338 | return size_; |
| 339 | } |
| 340 | |
| 341 | const uint8_t* GetData() const { |
| 342 | return data_; |
| 343 | } |
| 344 | |
| 345 | Mips64Label* GetLabel() { |
| 346 | return &label_; |
| 347 | } |
| 348 | |
| 349 | const Mips64Label* GetLabel() const { |
| 350 | return &label_; |
| 351 | } |
| 352 | |
| 353 | private: |
| 354 | Mips64Label label_; |
| 355 | const uint32_t size_; |
| 356 | uint8_t data_[kMaxSize]; |
| 357 | |
| 358 | DISALLOW_COPY_AND_ASSIGN(Literal); |
| 359 | }; |
| 360 | |
Alexey Frunze | 0960ac5 | 2016-12-20 17:24:59 -0800 | [diff] [blame] | 361 | // Jump table: table of labels emitted after the code and before the literals. Similar to literals. |
| 362 | class JumpTable { |
| 363 | public: |
| 364 | explicit JumpTable(std::vector<Mips64Label*>&& labels) |
| 365 | : label_(), labels_(std::move(labels)) { |
| 366 | } |
| 367 | |
| 368 | size_t GetSize() const { |
| 369 | return labels_.size() * sizeof(uint32_t); |
| 370 | } |
| 371 | |
| 372 | const std::vector<Mips64Label*>& GetData() const { |
| 373 | return labels_; |
| 374 | } |
| 375 | |
| 376 | Mips64Label* GetLabel() { |
| 377 | return &label_; |
| 378 | } |
| 379 | |
| 380 | const Mips64Label* GetLabel() const { |
| 381 | return &label_; |
| 382 | } |
| 383 | |
| 384 | private: |
| 385 | Mips64Label label_; |
| 386 | std::vector<Mips64Label*> labels_; |
| 387 | |
| 388 | DISALLOW_COPY_AND_ASSIGN(JumpTable); |
| 389 | }; |
| 390 | |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 391 | // Slowpath entered when Thread::Current()->_exception is non-null. |
| 392 | class Mips64ExceptionSlowPath { |
| 393 | public: |
| 394 | explicit Mips64ExceptionSlowPath(Mips64ManagedRegister scratch, size_t stack_adjust) |
| 395 | : scratch_(scratch), stack_adjust_(stack_adjust) {} |
| 396 | |
| 397 | Mips64ExceptionSlowPath(Mips64ExceptionSlowPath&& src) |
| 398 | : scratch_(src.scratch_), |
| 399 | stack_adjust_(src.stack_adjust_), |
| 400 | exception_entry_(std::move(src.exception_entry_)) {} |
| 401 | |
| 402 | private: |
| 403 | Mips64Label* Entry() { return &exception_entry_; } |
| 404 | const Mips64ManagedRegister scratch_; |
| 405 | const size_t stack_adjust_; |
| 406 | Mips64Label exception_entry_; |
| 407 | |
| 408 | friend class Mips64Assembler; |
| 409 | DISALLOW_COPY_AND_ASSIGN(Mips64ExceptionSlowPath); |
| 410 | }; |
| 411 | |
Andreas Gampe | 3b165bc | 2016-08-01 22:07:04 -0700 | [diff] [blame] | 412 | class Mips64Assembler FINAL : public Assembler, public JNIMacroAssembler<PointerSize::k64> { |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 413 | public: |
Igor Murashkin | ae7ff92 | 2016-10-06 14:59:19 -0700 | [diff] [blame] | 414 | using JNIBase = JNIMacroAssembler<PointerSize::k64>; |
| 415 | |
Vladimir Marko | 93205e3 | 2016-04-13 11:59:46 +0100 | [diff] [blame] | 416 | explicit Mips64Assembler(ArenaAllocator* arena) |
| 417 | : Assembler(arena), |
| 418 | overwriting_(false), |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 419 | overwrite_location_(0), |
Alexey Frunze | 19f6c69 | 2016-11-30 19:19:55 -0800 | [diff] [blame] | 420 | literals_(arena->Adapter(kArenaAllocAssembler)), |
| 421 | long_literals_(arena->Adapter(kArenaAllocAssembler)), |
Alexey Frunze | 0960ac5 | 2016-12-20 17:24:59 -0800 | [diff] [blame] | 422 | jump_tables_(arena->Adapter(kArenaAllocAssembler)), |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 423 | last_position_adjustment_(0), |
| 424 | last_old_position_(0), |
| 425 | last_branch_id_(0) { |
| 426 | cfi().DelayEmittingAdvancePCs(); |
| 427 | } |
| 428 | |
| 429 | virtual ~Mips64Assembler() { |
| 430 | for (auto& branch : branches_) { |
| 431 | CHECK(branch.IsResolved()); |
| 432 | } |
| 433 | } |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 434 | |
Andreas Gampe | 3b165bc | 2016-08-01 22:07:04 -0700 | [diff] [blame] | 435 | size_t CodeSize() const OVERRIDE { return Assembler::CodeSize(); } |
| 436 | DebugFrameOpCodeWriterForAssembler& cfi() { return Assembler::cfi(); } |
| 437 | |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 438 | // Emit Machine Instructions. |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 439 | void Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt); |
| 440 | void Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16); |
Alexey Frunze | 4dda337 | 2015-06-01 18:31:49 -0700 | [diff] [blame] | 441 | void Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64 |
| 442 | void Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16); // MIPS64 |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 443 | void Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt); |
Alexey Frunze | 4dda337 | 2015-06-01 18:31:49 -0700 | [diff] [blame] | 444 | void Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64 |
| 445 | |
Alexey Frunze | c857c74 | 2015-09-23 15:12:39 -0700 | [diff] [blame] | 446 | void MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt); |
| 447 | void MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt); |
| 448 | void DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt); |
| 449 | void ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt); |
| 450 | void DivuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt); |
| 451 | void ModuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt); |
| 452 | void Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64 |
| 453 | void Dmuh(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64 |
| 454 | void Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64 |
| 455 | void Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64 |
| 456 | void Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64 |
| 457 | void Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64 |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 458 | |
| 459 | void And(GpuRegister rd, GpuRegister rs, GpuRegister rt); |
| 460 | void Andi(GpuRegister rt, GpuRegister rs, uint16_t imm16); |
| 461 | void Or(GpuRegister rd, GpuRegister rs, GpuRegister rt); |
| 462 | void Ori(GpuRegister rt, GpuRegister rs, uint16_t imm16); |
| 463 | void Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt); |
| 464 | void Xori(GpuRegister rt, GpuRegister rs, uint16_t imm16); |
| 465 | void Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt); |
| 466 | |
Alexey Frunze | c857c74 | 2015-09-23 15:12:39 -0700 | [diff] [blame] | 467 | void Bitswap(GpuRegister rd, GpuRegister rt); |
Alexey Frunze | 19f6c69 | 2016-11-30 19:19:55 -0800 | [diff] [blame] | 468 | void Dbitswap(GpuRegister rd, GpuRegister rt); // MIPS64 |
Alexey Frunze | c857c74 | 2015-09-23 15:12:39 -0700 | [diff] [blame] | 469 | void Seb(GpuRegister rd, GpuRegister rt); |
| 470 | void Seh(GpuRegister rd, GpuRegister rt); |
Alexey Frunze | 19f6c69 | 2016-11-30 19:19:55 -0800 | [diff] [blame] | 471 | void Dsbh(GpuRegister rd, GpuRegister rt); // MIPS64 |
| 472 | void Dshd(GpuRegister rd, GpuRegister rt); // MIPS64 |
Lazar Trsic | d967266 | 2015-09-03 17:33:01 +0200 | [diff] [blame] | 473 | void Dext(GpuRegister rs, GpuRegister rt, int pos, int size); // MIPS64 |
| 474 | void Dinsu(GpuRegister rt, GpuRegister rs, int pos, int size); // MIPS64 |
Chris Larsen | e366059 | 2016-11-09 11:13:42 -0800 | [diff] [blame] | 475 | void Lsa(GpuRegister rd, GpuRegister rs, GpuRegister rt, int saPlusOne); |
| 476 | void Dlsa(GpuRegister rd, GpuRegister rs, GpuRegister rt, int saPlusOne); // MIPS64 |
Chris Larsen | 2fadd7b | 2015-08-14 14:56:10 -0700 | [diff] [blame] | 477 | void Wsbh(GpuRegister rd, GpuRegister rt); |
| 478 | void Sc(GpuRegister rt, GpuRegister base, int16_t imm9 = 0); |
Alexey Frunze | 19f6c69 | 2016-11-30 19:19:55 -0800 | [diff] [blame] | 479 | void Scd(GpuRegister rt, GpuRegister base, int16_t imm9 = 0); // MIPS64 |
Chris Larsen | 2fadd7b | 2015-08-14 14:56:10 -0700 | [diff] [blame] | 480 | void Ll(GpuRegister rt, GpuRegister base, int16_t imm9 = 0); |
Alexey Frunze | 19f6c69 | 2016-11-30 19:19:55 -0800 | [diff] [blame] | 481 | void Lld(GpuRegister rt, GpuRegister base, int16_t imm9 = 0); // MIPS64 |
Alexey Frunze | 4dda337 | 2015-06-01 18:31:49 -0700 | [diff] [blame] | 482 | |
| 483 | void Sll(GpuRegister rd, GpuRegister rt, int shamt); |
| 484 | void Srl(GpuRegister rd, GpuRegister rt, int shamt); |
Chris Larsen | 2fadd7b | 2015-08-14 14:56:10 -0700 | [diff] [blame] | 485 | void Rotr(GpuRegister rd, GpuRegister rt, int shamt); |
Alexey Frunze | 4dda337 | 2015-06-01 18:31:49 -0700 | [diff] [blame] | 486 | void Sra(GpuRegister rd, GpuRegister rt, int shamt); |
| 487 | void Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs); |
| 488 | void Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs); |
Chris Larsen | 9aebff2 | 2015-09-22 17:54:15 -0700 | [diff] [blame] | 489 | void Rotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs); |
Alexey Frunze | 4dda337 | 2015-06-01 18:31:49 -0700 | [diff] [blame] | 490 | void Srav(GpuRegister rd, GpuRegister rt, GpuRegister rs); |
| 491 | void Dsll(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64 |
| 492 | void Dsrl(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64 |
Alexey Frunze | 19f6c69 | 2016-11-30 19:19:55 -0800 | [diff] [blame] | 493 | void Drotr(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64 |
Alexey Frunze | 4dda337 | 2015-06-01 18:31:49 -0700 | [diff] [blame] | 494 | void Dsra(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64 |
| 495 | void Dsll32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64 |
| 496 | void Dsrl32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64 |
Chris Larsen | 9aebff2 | 2015-09-22 17:54:15 -0700 | [diff] [blame] | 497 | void Drotr32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64 |
Alexey Frunze | 4dda337 | 2015-06-01 18:31:49 -0700 | [diff] [blame] | 498 | void Dsra32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64 |
| 499 | void Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs); // MIPS64 |
| 500 | void Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs); // MIPS64 |
Chris Larsen | 9aebff2 | 2015-09-22 17:54:15 -0700 | [diff] [blame] | 501 | void Drotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs); // MIPS64 |
Alexey Frunze | 4dda337 | 2015-06-01 18:31:49 -0700 | [diff] [blame] | 502 | void Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs); // MIPS64 |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 503 | |
| 504 | void Lb(GpuRegister rt, GpuRegister rs, uint16_t imm16); |
| 505 | void Lh(GpuRegister rt, GpuRegister rs, uint16_t imm16); |
| 506 | void Lw(GpuRegister rt, GpuRegister rs, uint16_t imm16); |
Alexey Frunze | 4dda337 | 2015-06-01 18:31:49 -0700 | [diff] [blame] | 507 | void Ld(GpuRegister rt, GpuRegister rs, uint16_t imm16); // MIPS64 |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 508 | void Lbu(GpuRegister rt, GpuRegister rs, uint16_t imm16); |
| 509 | void Lhu(GpuRegister rt, GpuRegister rs, uint16_t imm16); |
Alexey Frunze | 4dda337 | 2015-06-01 18:31:49 -0700 | [diff] [blame] | 510 | void Lwu(GpuRegister rt, GpuRegister rs, uint16_t imm16); // MIPS64 |
Alexey Frunze | 19f6c69 | 2016-11-30 19:19:55 -0800 | [diff] [blame] | 511 | void Lwpc(GpuRegister rs, uint32_t imm19); |
| 512 | void Lwupc(GpuRegister rs, uint32_t imm19); // MIPS64 |
| 513 | void Ldpc(GpuRegister rs, uint32_t imm18); // MIPS64 |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 514 | void Lui(GpuRegister rt, uint16_t imm16); |
Alexey Frunze | 0960ac5 | 2016-12-20 17:24:59 -0800 | [diff] [blame] | 515 | void Aui(GpuRegister rt, GpuRegister rs, uint16_t imm16); |
Alexey Frunze | c061de1 | 2017-02-14 13:27:23 -0800 | [diff] [blame] | 516 | void Daui(GpuRegister rt, GpuRegister rs, uint16_t imm16); // MIPS64 |
Alexey Frunze | c857c74 | 2015-09-23 15:12:39 -0700 | [diff] [blame] | 517 | void Dahi(GpuRegister rs, uint16_t imm16); // MIPS64 |
| 518 | void Dati(GpuRegister rs, uint16_t imm16); // MIPS64 |
Alexey Frunze | 4dda337 | 2015-06-01 18:31:49 -0700 | [diff] [blame] | 519 | void Sync(uint32_t stype); |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 520 | |
| 521 | void Sb(GpuRegister rt, GpuRegister rs, uint16_t imm16); |
| 522 | void Sh(GpuRegister rt, GpuRegister rs, uint16_t imm16); |
| 523 | void Sw(GpuRegister rt, GpuRegister rs, uint16_t imm16); |
Alexey Frunze | 4dda337 | 2015-06-01 18:31:49 -0700 | [diff] [blame] | 524 | void Sd(GpuRegister rt, GpuRegister rs, uint16_t imm16); // MIPS64 |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 525 | |
| 526 | void Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt); |
| 527 | void Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt); |
| 528 | void Slti(GpuRegister rt, GpuRegister rs, uint16_t imm16); |
| 529 | void Sltiu(GpuRegister rt, GpuRegister rs, uint16_t imm16); |
Chris Larsen | 2fadd7b | 2015-08-14 14:56:10 -0700 | [diff] [blame] | 530 | void Seleqz(GpuRegister rd, GpuRegister rs, GpuRegister rt); |
| 531 | void Selnez(GpuRegister rd, GpuRegister rs, GpuRegister rt); |
| 532 | void Clz(GpuRegister rd, GpuRegister rs); |
| 533 | void Clo(GpuRegister rd, GpuRegister rs); |
Alexey Frunze | 19f6c69 | 2016-11-30 19:19:55 -0800 | [diff] [blame] | 534 | void Dclz(GpuRegister rd, GpuRegister rs); // MIPS64 |
| 535 | void Dclo(GpuRegister rd, GpuRegister rs); // MIPS64 |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 536 | |
Alexey Frunze | 4dda337 | 2015-06-01 18:31:49 -0700 | [diff] [blame] | 537 | void Jalr(GpuRegister rd, GpuRegister rs); |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 538 | void Jalr(GpuRegister rs); |
Alexey Frunze | 4dda337 | 2015-06-01 18:31:49 -0700 | [diff] [blame] | 539 | void Jr(GpuRegister rs); |
Alexey Frunze | c857c74 | 2015-09-23 15:12:39 -0700 | [diff] [blame] | 540 | void Auipc(GpuRegister rs, uint16_t imm16); |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 541 | void Addiupc(GpuRegister rs, uint32_t imm19); |
| 542 | void Bc(uint32_t imm26); |
Alexey Frunze | 19f6c69 | 2016-11-30 19:19:55 -0800 | [diff] [blame] | 543 | void Balc(uint32_t imm26); |
Alexey Frunze | c857c74 | 2015-09-23 15:12:39 -0700 | [diff] [blame] | 544 | void Jic(GpuRegister rt, uint16_t imm16); |
| 545 | void Jialc(GpuRegister rt, uint16_t imm16); |
| 546 | void Bltc(GpuRegister rs, GpuRegister rt, uint16_t imm16); |
| 547 | void Bltzc(GpuRegister rt, uint16_t imm16); |
| 548 | void Bgtzc(GpuRegister rt, uint16_t imm16); |
| 549 | void Bgec(GpuRegister rs, GpuRegister rt, uint16_t imm16); |
| 550 | void Bgezc(GpuRegister rt, uint16_t imm16); |
| 551 | void Blezc(GpuRegister rt, uint16_t imm16); |
| 552 | void Bltuc(GpuRegister rs, GpuRegister rt, uint16_t imm16); |
| 553 | void Bgeuc(GpuRegister rs, GpuRegister rt, uint16_t imm16); |
| 554 | void Beqc(GpuRegister rs, GpuRegister rt, uint16_t imm16); |
| 555 | void Bnec(GpuRegister rs, GpuRegister rt, uint16_t imm16); |
| 556 | void Beqzc(GpuRegister rs, uint32_t imm21); |
| 557 | void Bnezc(GpuRegister rs, uint32_t imm21); |
Alexey Frunze | 299a939 | 2015-12-08 16:08:02 -0800 | [diff] [blame] | 558 | void Bc1eqz(FpuRegister ft, uint16_t imm16); |
| 559 | void Bc1nez(FpuRegister ft, uint16_t imm16); |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 560 | |
| 561 | void AddS(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 562 | void SubS(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 563 | void MulS(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 564 | void DivS(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 565 | void AddD(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 566 | void SubD(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 567 | void MulD(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 568 | void DivD(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
Chris Larsen | 2fadd7b | 2015-08-14 14:56:10 -0700 | [diff] [blame] | 569 | void SqrtS(FpuRegister fd, FpuRegister fs); |
| 570 | void SqrtD(FpuRegister fd, FpuRegister fs); |
| 571 | void AbsS(FpuRegister fd, FpuRegister fs); |
| 572 | void AbsD(FpuRegister fd, FpuRegister fs); |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 573 | void MovS(FpuRegister fd, FpuRegister fs); |
| 574 | void MovD(FpuRegister fd, FpuRegister fs); |
Alexey Frunze | 4dda337 | 2015-06-01 18:31:49 -0700 | [diff] [blame] | 575 | void NegS(FpuRegister fd, FpuRegister fs); |
| 576 | void NegD(FpuRegister fd, FpuRegister fs); |
Chris Larsen | 2fadd7b | 2015-08-14 14:56:10 -0700 | [diff] [blame] | 577 | void RoundLS(FpuRegister fd, FpuRegister fs); |
| 578 | void RoundLD(FpuRegister fd, FpuRegister fs); |
| 579 | void RoundWS(FpuRegister fd, FpuRegister fs); |
| 580 | void RoundWD(FpuRegister fd, FpuRegister fs); |
Alexey Frunze | baf60b7 | 2015-12-22 15:15:03 -0800 | [diff] [blame] | 581 | void TruncLS(FpuRegister fd, FpuRegister fs); |
| 582 | void TruncLD(FpuRegister fd, FpuRegister fs); |
| 583 | void TruncWS(FpuRegister fd, FpuRegister fs); |
| 584 | void TruncWD(FpuRegister fd, FpuRegister fs); |
Chris Larsen | 2fadd7b | 2015-08-14 14:56:10 -0700 | [diff] [blame] | 585 | void CeilLS(FpuRegister fd, FpuRegister fs); |
| 586 | void CeilLD(FpuRegister fd, FpuRegister fs); |
| 587 | void CeilWS(FpuRegister fd, FpuRegister fs); |
| 588 | void CeilWD(FpuRegister fd, FpuRegister fs); |
| 589 | void FloorLS(FpuRegister fd, FpuRegister fs); |
| 590 | void FloorLD(FpuRegister fd, FpuRegister fs); |
| 591 | void FloorWS(FpuRegister fd, FpuRegister fs); |
| 592 | void FloorWD(FpuRegister fd, FpuRegister fs); |
| 593 | void SelS(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 594 | void SelD(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 595 | void RintS(FpuRegister fd, FpuRegister fs); |
| 596 | void RintD(FpuRegister fd, FpuRegister fs); |
| 597 | void ClassS(FpuRegister fd, FpuRegister fs); |
| 598 | void ClassD(FpuRegister fd, FpuRegister fs); |
| 599 | void MinS(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 600 | void MinD(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 601 | void MaxS(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 602 | void MaxD(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
Alexey Frunze | 299a939 | 2015-12-08 16:08:02 -0800 | [diff] [blame] | 603 | void CmpUnS(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 604 | void CmpEqS(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 605 | void CmpUeqS(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 606 | void CmpLtS(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 607 | void CmpUltS(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 608 | void CmpLeS(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 609 | void CmpUleS(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 610 | void CmpOrS(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 611 | void CmpUneS(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 612 | void CmpNeS(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 613 | void CmpUnD(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 614 | void CmpEqD(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 615 | void CmpUeqD(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 616 | void CmpLtD(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 617 | void CmpUltD(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 618 | void CmpLeD(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 619 | void CmpUleD(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 620 | void CmpOrD(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 621 | void CmpUneD(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
| 622 | void CmpNeD(FpuRegister fd, FpuRegister fs, FpuRegister ft); |
Alexey Frunze | 4dda337 | 2015-06-01 18:31:49 -0700 | [diff] [blame] | 623 | |
| 624 | void Cvtsw(FpuRegister fd, FpuRegister fs); |
| 625 | void Cvtdw(FpuRegister fd, FpuRegister fs); |
| 626 | void Cvtsd(FpuRegister fd, FpuRegister fs); |
| 627 | void Cvtds(FpuRegister fd, FpuRegister fs); |
Chris Larsen | 5141763 | 2015-10-02 13:24:25 -0700 | [diff] [blame] | 628 | void Cvtsl(FpuRegister fd, FpuRegister fs); |
Chris Larsen | 2fadd7b | 2015-08-14 14:56:10 -0700 | [diff] [blame] | 629 | void Cvtdl(FpuRegister fd, FpuRegister fs); |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 630 | |
| 631 | void Mfc1(GpuRegister rt, FpuRegister fs); |
Lazar Trsic | d967266 | 2015-09-03 17:33:01 +0200 | [diff] [blame] | 632 | void Mfhc1(GpuRegister rt, FpuRegister fs); |
Alexey Frunze | 4dda337 | 2015-06-01 18:31:49 -0700 | [diff] [blame] | 633 | void Mtc1(GpuRegister rt, FpuRegister fs); |
Lazar Trsic | d967266 | 2015-09-03 17:33:01 +0200 | [diff] [blame] | 634 | void Mthc1(GpuRegister rt, FpuRegister fs); |
Alexey Frunze | 4dda337 | 2015-06-01 18:31:49 -0700 | [diff] [blame] | 635 | void Dmfc1(GpuRegister rt, FpuRegister fs); // MIPS64 |
| 636 | void Dmtc1(GpuRegister rt, FpuRegister fs); // MIPS64 |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 637 | void Lwc1(FpuRegister ft, GpuRegister rs, uint16_t imm16); |
| 638 | void Ldc1(FpuRegister ft, GpuRegister rs, uint16_t imm16); |
| 639 | void Swc1(FpuRegister ft, GpuRegister rs, uint16_t imm16); |
| 640 | void Sdc1(FpuRegister ft, GpuRegister rs, uint16_t imm16); |
| 641 | |
| 642 | void Break(); |
| 643 | void Nop(); |
Alexey Frunze | 4dda337 | 2015-06-01 18:31:49 -0700 | [diff] [blame] | 644 | void Move(GpuRegister rd, GpuRegister rs); |
| 645 | void Clear(GpuRegister rd); |
| 646 | void Not(GpuRegister rd, GpuRegister rs); |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 647 | |
Goran Jakovljevic | 5a9e51d | 2017-03-16 16:11:43 +0000 | [diff] [blame^] | 648 | // MSA instructions. |
| 649 | void AndV(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 650 | void OrV(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 651 | void NorV(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 652 | void XorV(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 653 | |
| 654 | void AddvB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 655 | void AddvH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 656 | void AddvW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 657 | void AddvD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 658 | void SubvB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 659 | void SubvH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 660 | void SubvW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 661 | void SubvD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 662 | void MulvB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 663 | void MulvH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 664 | void MulvW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 665 | void MulvD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 666 | void Div_sB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 667 | void Div_sH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 668 | void Div_sW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 669 | void Div_sD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 670 | void Div_uB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 671 | void Div_uH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 672 | void Div_uW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 673 | void Div_uD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 674 | void Mod_sB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 675 | void Mod_sH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 676 | void Mod_sW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 677 | void Mod_sD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 678 | void Mod_uB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 679 | void Mod_uH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 680 | void Mod_uW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 681 | void Mod_uD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 682 | |
| 683 | void FaddW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 684 | void FaddD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 685 | void FsubW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 686 | void FsubD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 687 | void FmulW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 688 | void FmulD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 689 | void FdivW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 690 | void FdivD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 691 | |
| 692 | void Ffint_sW(VectorRegister wd, VectorRegister ws); |
| 693 | void Ffint_sD(VectorRegister wd, VectorRegister ws); |
| 694 | void Ftint_sW(VectorRegister wd, VectorRegister ws); |
| 695 | void Ftint_sD(VectorRegister wd, VectorRegister ws); |
| 696 | |
| 697 | void SllB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 698 | void SllH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 699 | void SllW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 700 | void SllD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 701 | void SraB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 702 | void SraH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 703 | void SraW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 704 | void SraD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 705 | void SrlB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 706 | void SrlH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 707 | void SrlW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 708 | void SrlD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 709 | |
| 710 | // Immediate shift instructions, where shamtN denotes shift amount (must be between 0 and 2^N-1). |
| 711 | void SlliB(VectorRegister wd, VectorRegister ws, int shamt3); |
| 712 | void SlliH(VectorRegister wd, VectorRegister ws, int shamt4); |
| 713 | void SlliW(VectorRegister wd, VectorRegister ws, int shamt5); |
| 714 | void SlliD(VectorRegister wd, VectorRegister ws, int shamt6); |
| 715 | void SraiB(VectorRegister wd, VectorRegister ws, int shamt3); |
| 716 | void SraiH(VectorRegister wd, VectorRegister ws, int shamt4); |
| 717 | void SraiW(VectorRegister wd, VectorRegister ws, int shamt5); |
| 718 | void SraiD(VectorRegister wd, VectorRegister ws, int shamt6); |
| 719 | void SrliB(VectorRegister wd, VectorRegister ws, int shamt3); |
| 720 | void SrliH(VectorRegister wd, VectorRegister ws, int shamt4); |
| 721 | void SrliW(VectorRegister wd, VectorRegister ws, int shamt5); |
| 722 | void SrliD(VectorRegister wd, VectorRegister ws, int shamt6); |
| 723 | |
| 724 | void MoveV(VectorRegister wd, VectorRegister ws); |
| 725 | void SplatiB(VectorRegister wd, VectorRegister ws, int n4); |
| 726 | void SplatiH(VectorRegister wd, VectorRegister ws, int n3); |
| 727 | void SplatiW(VectorRegister wd, VectorRegister ws, int n2); |
| 728 | void SplatiD(VectorRegister wd, VectorRegister ws, int n1); |
| 729 | void FillB(VectorRegister wd, GpuRegister rs); |
| 730 | void FillH(VectorRegister wd, GpuRegister rs); |
| 731 | void FillW(VectorRegister wd, GpuRegister rs); |
| 732 | void FillD(VectorRegister wd, GpuRegister rs); |
| 733 | |
| 734 | void LdB(VectorRegister wd, GpuRegister rs, int offset); |
| 735 | void LdH(VectorRegister wd, GpuRegister rs, int offset); |
| 736 | void LdW(VectorRegister wd, GpuRegister rs, int offset); |
| 737 | void LdD(VectorRegister wd, GpuRegister rs, int offset); |
| 738 | void StB(VectorRegister wd, GpuRegister rs, int offset); |
| 739 | void StH(VectorRegister wd, GpuRegister rs, int offset); |
| 740 | void StW(VectorRegister wd, GpuRegister rs, int offset); |
| 741 | void StD(VectorRegister wd, GpuRegister rs, int offset); |
| 742 | |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 743 | // Higher level composite instructions. |
Chris Larsen | c733dca | 2016-05-13 16:11:47 -0700 | [diff] [blame] | 744 | int InstrCountForLoadReplicatedConst32(int64_t); |
Alexey Frunze | 4dda337 | 2015-06-01 18:31:49 -0700 | [diff] [blame] | 745 | void LoadConst32(GpuRegister rd, int32_t value); |
| 746 | void LoadConst64(GpuRegister rd, int64_t value); // MIPS64 |
| 747 | |
Chris Larsen | c733dca | 2016-05-13 16:11:47 -0700 | [diff] [blame] | 748 | // This function is only used for testing purposes. |
| 749 | void RecordLoadConst64Path(int value); |
| 750 | |
Alexey Frunze | 0960ac5 | 2016-12-20 17:24:59 -0800 | [diff] [blame] | 751 | void Addiu32(GpuRegister rt, GpuRegister rs, int32_t value); |
Alexey Frunze | 4dda337 | 2015-06-01 18:31:49 -0700 | [diff] [blame] | 752 | void Daddiu64(GpuRegister rt, GpuRegister rs, int64_t value, GpuRegister rtmp = AT); // MIPS64 |
| 753 | |
Alexey Frunze | c061de1 | 2017-02-14 13:27:23 -0800 | [diff] [blame] | 754 | // |
| 755 | // Heap poisoning. |
| 756 | // |
| 757 | |
| 758 | // Poison a heap reference contained in `src` and store it in `dst`. |
| 759 | void PoisonHeapReference(GpuRegister dst, GpuRegister src) { |
| 760 | // dst = -src. |
| 761 | // Negate the 32-bit ref. |
| 762 | Dsubu(dst, ZERO, src); |
| 763 | // And constrain it to 32 bits (zero-extend into bits 32 through 63) as on Arm64 and x86/64. |
| 764 | Dext(dst, dst, 0, 32); |
| 765 | } |
| 766 | // Poison a heap reference contained in `reg`. |
| 767 | void PoisonHeapReference(GpuRegister reg) { |
| 768 | // reg = -reg. |
| 769 | PoisonHeapReference(reg, reg); |
| 770 | } |
| 771 | // Unpoison a heap reference contained in `reg`. |
| 772 | void UnpoisonHeapReference(GpuRegister reg) { |
| 773 | // reg = -reg. |
| 774 | // Negate the 32-bit ref. |
| 775 | Dsubu(reg, ZERO, reg); |
| 776 | // And constrain it to 32 bits (zero-extend into bits 32 through 63) as on Arm64 and x86/64. |
| 777 | Dext(reg, reg, 0, 32); |
| 778 | } |
| 779 | // Poison a heap reference contained in `reg` if heap poisoning is enabled. |
| 780 | void MaybePoisonHeapReference(GpuRegister reg) { |
| 781 | if (kPoisonHeapReferences) { |
| 782 | PoisonHeapReference(reg); |
| 783 | } |
| 784 | } |
| 785 | // Unpoison a heap reference contained in `reg` if heap poisoning is enabled. |
| 786 | void MaybeUnpoisonHeapReference(GpuRegister reg) { |
| 787 | if (kPoisonHeapReferences) { |
| 788 | UnpoisonHeapReference(reg); |
| 789 | } |
| 790 | } |
| 791 | |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 792 | void Bind(Label* label) OVERRIDE { |
| 793 | Bind(down_cast<Mips64Label*>(label)); |
Andreas Gampe | 85b62f2 | 2015-09-09 13:15:38 -0700 | [diff] [blame] | 794 | } |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 795 | void Jump(Label* label ATTRIBUTE_UNUSED) OVERRIDE { |
| 796 | UNIMPLEMENTED(FATAL) << "Do not use Jump for MIPS64"; |
| 797 | } |
| 798 | |
| 799 | void Bind(Mips64Label* label); |
Igor Murashkin | ae7ff92 | 2016-10-06 14:59:19 -0700 | [diff] [blame] | 800 | |
| 801 | // Don't warn about a different virtual Bind/Jump in the base class. |
| 802 | using JNIBase::Bind; |
| 803 | using JNIBase::Jump; |
| 804 | |
| 805 | // Create a new label that can be used with Jump/Bind calls. |
| 806 | std::unique_ptr<JNIMacroLabel> CreateLabel() OVERRIDE { |
| 807 | LOG(FATAL) << "Not implemented on MIPS64"; |
| 808 | UNREACHABLE(); |
| 809 | } |
| 810 | // Emit an unconditional jump to the label. |
| 811 | void Jump(JNIMacroLabel* label ATTRIBUTE_UNUSED) OVERRIDE { |
| 812 | LOG(FATAL) << "Not implemented on MIPS64"; |
| 813 | UNREACHABLE(); |
| 814 | } |
| 815 | // Emit a conditional jump to the label by applying a unary condition test to the register. |
| 816 | void Jump(JNIMacroLabel* label ATTRIBUTE_UNUSED, |
| 817 | JNIMacroUnaryCondition cond ATTRIBUTE_UNUSED, |
| 818 | ManagedRegister test ATTRIBUTE_UNUSED) OVERRIDE { |
| 819 | LOG(FATAL) << "Not implemented on MIPS64"; |
| 820 | UNREACHABLE(); |
| 821 | } |
| 822 | |
| 823 | // Code at this offset will serve as the target for the Jump call. |
| 824 | void Bind(JNIMacroLabel* label ATTRIBUTE_UNUSED) OVERRIDE { |
| 825 | LOG(FATAL) << "Not implemented on MIPS64"; |
| 826 | UNREACHABLE(); |
| 827 | } |
| 828 | |
Alexey Frunze | 19f6c69 | 2016-11-30 19:19:55 -0800 | [diff] [blame] | 829 | // Create a new literal with a given value. |
| 830 | // NOTE: Force the template parameter to be explicitly specified. |
| 831 | template <typename T> |
| 832 | Literal* NewLiteral(typename Identity<T>::type value) { |
| 833 | static_assert(std::is_integral<T>::value, "T must be an integral type."); |
| 834 | return NewLiteral(sizeof(value), reinterpret_cast<const uint8_t*>(&value)); |
| 835 | } |
| 836 | |
| 837 | // Load label address using PC-relative loads. To be used with data labels in the literal / |
| 838 | // jump table area only and not with regular code labels. |
| 839 | void LoadLabelAddress(GpuRegister dest_reg, Mips64Label* label); |
| 840 | |
| 841 | // Create a new literal with the given data. |
| 842 | Literal* NewLiteral(size_t size, const uint8_t* data); |
| 843 | |
| 844 | // Load literal using PC-relative loads. |
| 845 | void LoadLiteral(GpuRegister dest_reg, LoadOperandType load_type, Literal* literal); |
| 846 | |
Alexey Frunze | 0960ac5 | 2016-12-20 17:24:59 -0800 | [diff] [blame] | 847 | // Create a jump table for the given labels that will be emitted when finalizing. |
| 848 | // When the table is emitted, offsets will be relative to the location of the table. |
| 849 | // The table location is determined by the location of its label (the label precedes |
| 850 | // the table data) and should be loaded using LoadLabelAddress(). |
| 851 | JumpTable* CreateJumpTable(std::vector<Mips64Label*>&& labels); |
| 852 | |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 853 | void Bc(Mips64Label* label); |
Alexey Frunze | 19f6c69 | 2016-11-30 19:19:55 -0800 | [diff] [blame] | 854 | void Balc(Mips64Label* label); |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 855 | void Bltc(GpuRegister rs, GpuRegister rt, Mips64Label* label); |
| 856 | void Bltzc(GpuRegister rt, Mips64Label* label); |
| 857 | void Bgtzc(GpuRegister rt, Mips64Label* label); |
| 858 | void Bgec(GpuRegister rs, GpuRegister rt, Mips64Label* label); |
| 859 | void Bgezc(GpuRegister rt, Mips64Label* label); |
| 860 | void Blezc(GpuRegister rt, Mips64Label* label); |
| 861 | void Bltuc(GpuRegister rs, GpuRegister rt, Mips64Label* label); |
| 862 | void Bgeuc(GpuRegister rs, GpuRegister rt, Mips64Label* label); |
| 863 | void Beqc(GpuRegister rs, GpuRegister rt, Mips64Label* label); |
| 864 | void Bnec(GpuRegister rs, GpuRegister rt, Mips64Label* label); |
| 865 | void Beqzc(GpuRegister rs, Mips64Label* label); |
| 866 | void Bnezc(GpuRegister rs, Mips64Label* label); |
Alexey Frunze | 299a939 | 2015-12-08 16:08:02 -0800 | [diff] [blame] | 867 | void Bc1eqz(FpuRegister ft, Mips64Label* label); |
| 868 | void Bc1nez(FpuRegister ft, Mips64Label* label); |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 869 | |
| 870 | void EmitLoad(ManagedRegister m_dst, GpuRegister src_register, int32_t src_offset, size_t size); |
Tijana Jakovljevic | 5743386 | 2017-01-17 16:59:03 +0100 | [diff] [blame] | 871 | |
| 872 | private: |
| 873 | // This will be used as an argument for loads/stores |
| 874 | // when there is no need for implicit null checks. |
| 875 | struct NoImplicitNullChecker { |
| 876 | void operator()() const {} |
| 877 | }; |
| 878 | |
| 879 | public: |
| 880 | template <typename ImplicitNullChecker = NoImplicitNullChecker> |
Tijana Jakovljevic | ba89c34 | 2017-03-10 13:36:08 +0100 | [diff] [blame] | 881 | void StoreConstToOffset(StoreOperandType type, |
| 882 | int64_t value, |
| 883 | GpuRegister base, |
| 884 | int32_t offset, |
| 885 | GpuRegister temp, |
| 886 | ImplicitNullChecker null_checker = NoImplicitNullChecker()) { |
| 887 | // We permit `base` and `temp` to coincide (however, we check that neither is AT), |
| 888 | // in which case the `base` register may be overwritten in the process. |
| 889 | CHECK_NE(temp, AT); // Must not use AT as temp, so as not to overwrite the adjusted base. |
| 890 | if (!IsInt<16>(offset) || |
| 891 | (type == kStoreDoubleword && !IsAligned<kMips64DoublewordSize>(offset) && |
| 892 | !IsInt<16>(static_cast<int32_t>(offset + kMips64WordSize)))) { |
| 893 | LoadConst32(AT, offset & ~(kMips64DoublewordSize - 1)); |
| 894 | Daddu(AT, AT, base); |
| 895 | base = AT; |
| 896 | offset &= (kMips64DoublewordSize - 1); |
| 897 | } |
| 898 | GpuRegister reg; |
| 899 | // If the adjustment left `base` unchanged and equal to `temp`, we can't use `temp` |
| 900 | // to load and hold the value but we can use AT instead as AT hasn't been used yet. |
| 901 | // Otherwise, `temp` can be used for the value. And if `temp` is the same as the |
| 902 | // original `base` (that is, `base` prior to the adjustment), the original `base` |
| 903 | // register will be overwritten. |
| 904 | if (base == temp) { |
| 905 | temp = AT; |
| 906 | } |
| 907 | |
| 908 | if (type == kStoreDoubleword && IsAligned<kMips64DoublewordSize>(offset)) { |
| 909 | if (value == 0) { |
| 910 | reg = ZERO; |
| 911 | } else { |
| 912 | reg = temp; |
| 913 | LoadConst64(reg, value); |
| 914 | } |
| 915 | Sd(reg, base, offset); |
| 916 | null_checker(); |
| 917 | } else { |
| 918 | uint32_t low = Low32Bits(value); |
| 919 | uint32_t high = High32Bits(value); |
| 920 | if (low == 0) { |
| 921 | reg = ZERO; |
| 922 | } else { |
| 923 | reg = temp; |
| 924 | LoadConst32(reg, low); |
| 925 | } |
| 926 | switch (type) { |
| 927 | case kStoreByte: |
| 928 | Sb(reg, base, offset); |
| 929 | break; |
| 930 | case kStoreHalfword: |
| 931 | Sh(reg, base, offset); |
| 932 | break; |
| 933 | case kStoreWord: |
| 934 | Sw(reg, base, offset); |
| 935 | break; |
| 936 | case kStoreDoubleword: |
| 937 | // not aligned to kMips64DoublewordSize |
| 938 | CHECK_ALIGNED(offset, kMips64WordSize); |
| 939 | Sw(reg, base, offset); |
| 940 | null_checker(); |
| 941 | if (high == 0) { |
| 942 | reg = ZERO; |
| 943 | } else { |
| 944 | reg = temp; |
| 945 | if (high != low) { |
| 946 | LoadConst32(reg, high); |
| 947 | } |
| 948 | } |
| 949 | Sw(reg, base, offset + kMips64WordSize); |
| 950 | break; |
| 951 | default: |
| 952 | LOG(FATAL) << "UNREACHABLE"; |
| 953 | } |
| 954 | if (type != kStoreDoubleword) { |
| 955 | null_checker(); |
| 956 | } |
| 957 | } |
| 958 | } |
| 959 | |
| 960 | template <typename ImplicitNullChecker = NoImplicitNullChecker> |
Tijana Jakovljevic | 5743386 | 2017-01-17 16:59:03 +0100 | [diff] [blame] | 961 | void LoadFromOffset(LoadOperandType type, |
| 962 | GpuRegister reg, |
| 963 | GpuRegister base, |
| 964 | int32_t offset, |
| 965 | ImplicitNullChecker null_checker = NoImplicitNullChecker()) { |
| 966 | if (!IsInt<16>(offset) || |
| 967 | (type == kLoadDoubleword && !IsAligned<kMips64DoublewordSize>(offset) && |
| 968 | !IsInt<16>(static_cast<int32_t>(offset + kMips64WordSize)))) { |
| 969 | LoadConst32(AT, offset & ~(kMips64DoublewordSize - 1)); |
| 970 | Daddu(AT, AT, base); |
| 971 | base = AT; |
| 972 | offset &= (kMips64DoublewordSize - 1); |
| 973 | } |
| 974 | |
| 975 | switch (type) { |
| 976 | case kLoadSignedByte: |
| 977 | Lb(reg, base, offset); |
| 978 | break; |
| 979 | case kLoadUnsignedByte: |
| 980 | Lbu(reg, base, offset); |
| 981 | break; |
| 982 | case kLoadSignedHalfword: |
| 983 | Lh(reg, base, offset); |
| 984 | break; |
| 985 | case kLoadUnsignedHalfword: |
| 986 | Lhu(reg, base, offset); |
| 987 | break; |
| 988 | case kLoadWord: |
| 989 | CHECK_ALIGNED(offset, kMips64WordSize); |
| 990 | Lw(reg, base, offset); |
| 991 | break; |
| 992 | case kLoadUnsignedWord: |
| 993 | CHECK_ALIGNED(offset, kMips64WordSize); |
| 994 | Lwu(reg, base, offset); |
| 995 | break; |
| 996 | case kLoadDoubleword: |
| 997 | if (!IsAligned<kMips64DoublewordSize>(offset)) { |
| 998 | CHECK_ALIGNED(offset, kMips64WordSize); |
| 999 | Lwu(reg, base, offset); |
| 1000 | null_checker(); |
| 1001 | Lwu(TMP2, base, offset + kMips64WordSize); |
| 1002 | Dinsu(reg, TMP2, 32, 32); |
| 1003 | } else { |
| 1004 | Ld(reg, base, offset); |
| 1005 | null_checker(); |
| 1006 | } |
| 1007 | break; |
| 1008 | } |
| 1009 | if (type != kLoadDoubleword) { |
| 1010 | null_checker(); |
| 1011 | } |
| 1012 | } |
| 1013 | |
| 1014 | template <typename ImplicitNullChecker = NoImplicitNullChecker> |
| 1015 | void LoadFpuFromOffset(LoadOperandType type, |
| 1016 | FpuRegister reg, |
| 1017 | GpuRegister base, |
| 1018 | int32_t offset, |
| 1019 | ImplicitNullChecker null_checker = NoImplicitNullChecker()) { |
| 1020 | if (!IsInt<16>(offset) || |
| 1021 | (type == kLoadDoubleword && !IsAligned<kMips64DoublewordSize>(offset) && |
| 1022 | !IsInt<16>(static_cast<int32_t>(offset + kMips64WordSize)))) { |
| 1023 | LoadConst32(AT, offset & ~(kMips64DoublewordSize - 1)); |
| 1024 | Daddu(AT, AT, base); |
| 1025 | base = AT; |
| 1026 | offset &= (kMips64DoublewordSize - 1); |
| 1027 | } |
| 1028 | |
| 1029 | switch (type) { |
| 1030 | case kLoadWord: |
| 1031 | CHECK_ALIGNED(offset, kMips64WordSize); |
| 1032 | Lwc1(reg, base, offset); |
| 1033 | null_checker(); |
| 1034 | break; |
| 1035 | case kLoadDoubleword: |
| 1036 | if (!IsAligned<kMips64DoublewordSize>(offset)) { |
| 1037 | CHECK_ALIGNED(offset, kMips64WordSize); |
| 1038 | Lwc1(reg, base, offset); |
| 1039 | null_checker(); |
| 1040 | Lw(TMP2, base, offset + kMips64WordSize); |
| 1041 | Mthc1(TMP2, reg); |
| 1042 | } else { |
| 1043 | Ldc1(reg, base, offset); |
| 1044 | null_checker(); |
| 1045 | } |
| 1046 | break; |
| 1047 | default: |
| 1048 | LOG(FATAL) << "UNREACHABLE"; |
| 1049 | } |
| 1050 | } |
| 1051 | |
| 1052 | template <typename ImplicitNullChecker = NoImplicitNullChecker> |
| 1053 | void StoreToOffset(StoreOperandType type, |
| 1054 | GpuRegister reg, |
| 1055 | GpuRegister base, |
| 1056 | int32_t offset, |
| 1057 | ImplicitNullChecker null_checker = NoImplicitNullChecker()) { |
| 1058 | if (!IsInt<16>(offset) || |
| 1059 | (type == kStoreDoubleword && !IsAligned<kMips64DoublewordSize>(offset) && |
| 1060 | !IsInt<16>(static_cast<int32_t>(offset + kMips64WordSize)))) { |
| 1061 | LoadConst32(AT, offset & ~(kMips64DoublewordSize - 1)); |
| 1062 | Daddu(AT, AT, base); |
| 1063 | base = AT; |
| 1064 | offset &= (kMips64DoublewordSize - 1); |
| 1065 | } |
| 1066 | |
| 1067 | switch (type) { |
| 1068 | case kStoreByte: |
| 1069 | Sb(reg, base, offset); |
| 1070 | break; |
| 1071 | case kStoreHalfword: |
| 1072 | Sh(reg, base, offset); |
| 1073 | break; |
| 1074 | case kStoreWord: |
| 1075 | CHECK_ALIGNED(offset, kMips64WordSize); |
| 1076 | Sw(reg, base, offset); |
| 1077 | break; |
| 1078 | case kStoreDoubleword: |
| 1079 | if (!IsAligned<kMips64DoublewordSize>(offset)) { |
| 1080 | CHECK_ALIGNED(offset, kMips64WordSize); |
| 1081 | Sw(reg, base, offset); |
| 1082 | null_checker(); |
| 1083 | Dsrl32(TMP2, reg, 0); |
| 1084 | Sw(TMP2, base, offset + kMips64WordSize); |
| 1085 | } else { |
| 1086 | Sd(reg, base, offset); |
| 1087 | null_checker(); |
| 1088 | } |
| 1089 | break; |
| 1090 | default: |
| 1091 | LOG(FATAL) << "UNREACHABLE"; |
| 1092 | } |
| 1093 | if (type != kStoreDoubleword) { |
| 1094 | null_checker(); |
| 1095 | } |
| 1096 | } |
| 1097 | |
| 1098 | template <typename ImplicitNullChecker = NoImplicitNullChecker> |
| 1099 | void StoreFpuToOffset(StoreOperandType type, |
| 1100 | FpuRegister reg, |
| 1101 | GpuRegister base, |
| 1102 | int32_t offset, |
| 1103 | ImplicitNullChecker null_checker = NoImplicitNullChecker()) { |
| 1104 | if (!IsInt<16>(offset) || |
| 1105 | (type == kStoreDoubleword && !IsAligned<kMips64DoublewordSize>(offset) && |
| 1106 | !IsInt<16>(static_cast<int32_t>(offset + kMips64WordSize)))) { |
| 1107 | LoadConst32(AT, offset & ~(kMips64DoublewordSize - 1)); |
| 1108 | Daddu(AT, AT, base); |
| 1109 | base = AT; |
| 1110 | offset &= (kMips64DoublewordSize - 1); |
| 1111 | } |
| 1112 | |
| 1113 | switch (type) { |
| 1114 | case kStoreWord: |
| 1115 | CHECK_ALIGNED(offset, kMips64WordSize); |
| 1116 | Swc1(reg, base, offset); |
| 1117 | null_checker(); |
| 1118 | break; |
| 1119 | case kStoreDoubleword: |
| 1120 | if (!IsAligned<kMips64DoublewordSize>(offset)) { |
| 1121 | CHECK_ALIGNED(offset, kMips64WordSize); |
| 1122 | Mfhc1(TMP2, reg); |
| 1123 | Swc1(reg, base, offset); |
| 1124 | null_checker(); |
| 1125 | Sw(TMP2, base, offset + kMips64WordSize); |
| 1126 | } else { |
| 1127 | Sdc1(reg, base, offset); |
| 1128 | null_checker(); |
| 1129 | } |
| 1130 | break; |
| 1131 | default: |
| 1132 | LOG(FATAL) << "UNREACHABLE"; |
| 1133 | } |
| 1134 | } |
| 1135 | |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1136 | void LoadFromOffset(LoadOperandType type, GpuRegister reg, GpuRegister base, int32_t offset); |
| 1137 | void LoadFpuFromOffset(LoadOperandType type, FpuRegister reg, GpuRegister base, int32_t offset); |
| 1138 | void StoreToOffset(StoreOperandType type, GpuRegister reg, GpuRegister base, int32_t offset); |
| 1139 | void StoreFpuToOffset(StoreOperandType type, FpuRegister reg, GpuRegister base, int32_t offset); |
| 1140 | |
| 1141 | // Emit data (e.g. encoded instruction or immediate) to the instruction stream. |
Alexey Frunze | 4dda337 | 2015-06-01 18:31:49 -0700 | [diff] [blame] | 1142 | void Emit(uint32_t value); |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1143 | |
| 1144 | // |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1145 | // Overridden common assembler high-level functionality. |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1146 | // |
| 1147 | |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1148 | // Emit code that will create an activation on the stack. |
Vladimir Marko | 3224838 | 2016-05-19 10:37:24 +0100 | [diff] [blame] | 1149 | void BuildFrame(size_t frame_size, |
| 1150 | ManagedRegister method_reg, |
| 1151 | ArrayRef<const ManagedRegister> callee_save_regs, |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1152 | const ManagedRegisterEntrySpills& entry_spills) OVERRIDE; |
| 1153 | |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1154 | // Emit code that will remove an activation from the stack. |
Vladimir Marko | 3224838 | 2016-05-19 10:37:24 +0100 | [diff] [blame] | 1155 | void RemoveFrame(size_t frame_size, ArrayRef<const ManagedRegister> callee_save_regs) OVERRIDE; |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1156 | |
| 1157 | void IncreaseFrameSize(size_t adjust) OVERRIDE; |
| 1158 | void DecreaseFrameSize(size_t adjust) OVERRIDE; |
| 1159 | |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1160 | // Store routines. |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1161 | void Store(FrameOffset offs, ManagedRegister msrc, size_t size) OVERRIDE; |
| 1162 | void StoreRef(FrameOffset dest, ManagedRegister msrc) OVERRIDE; |
| 1163 | void StoreRawPtr(FrameOffset dest, ManagedRegister msrc) OVERRIDE; |
| 1164 | |
| 1165 | void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister mscratch) OVERRIDE; |
| 1166 | |
Andreas Gampe | 3b165bc | 2016-08-01 22:07:04 -0700 | [diff] [blame] | 1167 | void StoreStackOffsetToThread(ThreadOffset64 thr_offs, |
| 1168 | FrameOffset fr_offs, |
| 1169 | ManagedRegister mscratch) OVERRIDE; |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1170 | |
Andreas Gampe | 3b165bc | 2016-08-01 22:07:04 -0700 | [diff] [blame] | 1171 | void StoreStackPointerToThread(ThreadOffset64 thr_offs) OVERRIDE; |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1172 | |
| 1173 | void StoreSpanning(FrameOffset dest, ManagedRegister msrc, FrameOffset in_off, |
| 1174 | ManagedRegister mscratch) OVERRIDE; |
| 1175 | |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1176 | // Load routines. |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1177 | void Load(ManagedRegister mdest, FrameOffset src, size_t size) OVERRIDE; |
| 1178 | |
Andreas Gampe | 3b165bc | 2016-08-01 22:07:04 -0700 | [diff] [blame] | 1179 | void LoadFromThread(ManagedRegister mdest, ThreadOffset64 src, size_t size) OVERRIDE; |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1180 | |
Mathieu Chartier | e401d14 | 2015-04-22 13:56:20 -0700 | [diff] [blame] | 1181 | void LoadRef(ManagedRegister dest, FrameOffset src) OVERRIDE; |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1182 | |
Mathieu Chartier | e401d14 | 2015-04-22 13:56:20 -0700 | [diff] [blame] | 1183 | void LoadRef(ManagedRegister mdest, ManagedRegister base, MemberOffset offs, |
Roland Levillain | 4d02711 | 2015-07-01 15:41:14 +0100 | [diff] [blame] | 1184 | bool unpoison_reference) OVERRIDE; |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1185 | |
| 1186 | void LoadRawPtr(ManagedRegister mdest, ManagedRegister base, Offset offs) OVERRIDE; |
| 1187 | |
Andreas Gampe | 3b165bc | 2016-08-01 22:07:04 -0700 | [diff] [blame] | 1188 | void LoadRawPtrFromThread(ManagedRegister mdest, ThreadOffset64 offs) OVERRIDE; |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1189 | |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1190 | // Copying routines. |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1191 | void Move(ManagedRegister mdest, ManagedRegister msrc, size_t size) OVERRIDE; |
| 1192 | |
Andreas Gampe | 3b165bc | 2016-08-01 22:07:04 -0700 | [diff] [blame] | 1193 | void CopyRawPtrFromThread(FrameOffset fr_offs, |
| 1194 | ThreadOffset64 thr_offs, |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1195 | ManagedRegister mscratch) OVERRIDE; |
| 1196 | |
Andreas Gampe | 3b165bc | 2016-08-01 22:07:04 -0700 | [diff] [blame] | 1197 | void CopyRawPtrToThread(ThreadOffset64 thr_offs, |
| 1198 | FrameOffset fr_offs, |
| 1199 | ManagedRegister mscratch) OVERRIDE; |
| 1200 | |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1201 | void CopyRef(FrameOffset dest, FrameOffset src, ManagedRegister mscratch) OVERRIDE; |
| 1202 | |
| 1203 | void Copy(FrameOffset dest, FrameOffset src, ManagedRegister mscratch, size_t size) OVERRIDE; |
| 1204 | |
| 1205 | void Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset, ManagedRegister mscratch, |
| 1206 | size_t size) OVERRIDE; |
| 1207 | |
| 1208 | void Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src, |
| 1209 | ManagedRegister mscratch, size_t size) OVERRIDE; |
| 1210 | |
| 1211 | void Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset, ManagedRegister mscratch, |
| 1212 | size_t size) OVERRIDE; |
| 1213 | |
| 1214 | void Copy(ManagedRegister dest, Offset dest_offset, ManagedRegister src, Offset src_offset, |
| 1215 | ManagedRegister mscratch, size_t size) OVERRIDE; |
| 1216 | |
| 1217 | void Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset, |
| 1218 | ManagedRegister mscratch, size_t size) OVERRIDE; |
| 1219 | |
| 1220 | void MemoryBarrier(ManagedRegister) OVERRIDE; |
| 1221 | |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1222 | // Sign extension. |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1223 | void SignExtend(ManagedRegister mreg, size_t size) OVERRIDE; |
| 1224 | |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1225 | // Zero extension. |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1226 | void ZeroExtend(ManagedRegister mreg, size_t size) OVERRIDE; |
| 1227 | |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1228 | // Exploit fast access in managed code to Thread::Current(). |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1229 | void GetCurrentThread(ManagedRegister tr) OVERRIDE; |
| 1230 | void GetCurrentThread(FrameOffset dest_offset, ManagedRegister mscratch) OVERRIDE; |
| 1231 | |
Mathieu Chartier | 2cebb24 | 2015-04-21 16:50:40 -0700 | [diff] [blame] | 1232 | // Set up out_reg to hold a Object** into the handle scope, or to be null if the |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1233 | // value is null and null_allowed. in_reg holds a possibly stale reference |
| 1234 | // that can be used to avoid loading the handle scope entry to see if the value is |
Mathieu Chartier | 2cebb24 | 2015-04-21 16:50:40 -0700 | [diff] [blame] | 1235 | // null. |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1236 | void CreateHandleScopeEntry(ManagedRegister out_reg, FrameOffset handlescope_offset, |
| 1237 | ManagedRegister in_reg, bool null_allowed) OVERRIDE; |
| 1238 | |
Mathieu Chartier | 2cebb24 | 2015-04-21 16:50:40 -0700 | [diff] [blame] | 1239 | // Set up out_off to hold a Object** into the handle scope, or to be null if the |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1240 | // value is null and null_allowed. |
| 1241 | void CreateHandleScopeEntry(FrameOffset out_off, FrameOffset handlescope_offset, ManagedRegister |
| 1242 | mscratch, bool null_allowed) OVERRIDE; |
| 1243 | |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1244 | // src holds a handle scope entry (Object**) load this into dst. |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1245 | void LoadReferenceFromHandleScope(ManagedRegister dst, ManagedRegister src) OVERRIDE; |
| 1246 | |
| 1247 | // Heap::VerifyObject on src. In some cases (such as a reference to this) we |
| 1248 | // know that src may not be null. |
| 1249 | void VerifyObject(ManagedRegister src, bool could_be_null) OVERRIDE; |
| 1250 | void VerifyObject(FrameOffset src, bool could_be_null) OVERRIDE; |
| 1251 | |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1252 | // Call to address held at [base+offset]. |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1253 | void Call(ManagedRegister base, Offset offset, ManagedRegister mscratch) OVERRIDE; |
| 1254 | void Call(FrameOffset base, Offset offset, ManagedRegister mscratch) OVERRIDE; |
Andreas Gampe | 3b165bc | 2016-08-01 22:07:04 -0700 | [diff] [blame] | 1255 | void CallFromThread(ThreadOffset64 offset, ManagedRegister mscratch) OVERRIDE; |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1256 | |
| 1257 | // Generate code to check if Thread::Current()->exception_ is non-null |
| 1258 | // and branch to a ExceptionSlowPath if it is. |
| 1259 | void ExceptionPoll(ManagedRegister mscratch, size_t stack_adjust) OVERRIDE; |
| 1260 | |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1261 | // Emit slow paths queued during assembly and promote short branches to long if needed. |
| 1262 | void FinalizeCode() OVERRIDE; |
| 1263 | |
| 1264 | // Emit branches and finalize all instructions. |
| 1265 | void FinalizeInstructions(const MemoryRegion& region); |
| 1266 | |
| 1267 | // Returns the (always-)current location of a label (can be used in class CodeGeneratorMIPS64, |
| 1268 | // must be used instead of Mips64Label::GetPosition()). |
Alexey Frunze | 19f6c69 | 2016-11-30 19:19:55 -0800 | [diff] [blame] | 1269 | uint32_t GetLabelLocation(const Mips64Label* label) const; |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1270 | |
| 1271 | // Get the final position of a label after local fixup based on the old position |
| 1272 | // recorded before FinalizeCode(). |
| 1273 | uint32_t GetAdjustedPosition(uint32_t old_position); |
| 1274 | |
Alexey Frunze | 19f6c69 | 2016-11-30 19:19:55 -0800 | [diff] [blame] | 1275 | // Note that PC-relative literal loads are handled as pseudo branches because they need very |
| 1276 | // similar relocation and may similarly expand in size to accomodate for larger offsets relative |
| 1277 | // to PC. |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1278 | enum BranchCondition { |
| 1279 | kCondLT, |
| 1280 | kCondGE, |
| 1281 | kCondLE, |
| 1282 | kCondGT, |
| 1283 | kCondLTZ, |
| 1284 | kCondGEZ, |
| 1285 | kCondLEZ, |
| 1286 | kCondGTZ, |
| 1287 | kCondEQ, |
| 1288 | kCondNE, |
| 1289 | kCondEQZ, |
| 1290 | kCondNEZ, |
| 1291 | kCondLTU, |
| 1292 | kCondGEU, |
Alexey Frunze | 299a939 | 2015-12-08 16:08:02 -0800 | [diff] [blame] | 1293 | kCondF, // Floating-point predicate false. |
| 1294 | kCondT, // Floating-point predicate true. |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1295 | kUncond, |
| 1296 | }; |
| 1297 | friend std::ostream& operator<<(std::ostream& os, const BranchCondition& rhs); |
| 1298 | |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1299 | private: |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1300 | class Branch { |
| 1301 | public: |
| 1302 | enum Type { |
| 1303 | // Short branches. |
| 1304 | kUncondBranch, |
| 1305 | kCondBranch, |
| 1306 | kCall, |
Alexey Frunze | 19f6c69 | 2016-11-30 19:19:55 -0800 | [diff] [blame] | 1307 | // Near label. |
| 1308 | kLabel, |
| 1309 | // Near literals. |
| 1310 | kLiteral, |
| 1311 | kLiteralUnsigned, |
| 1312 | kLiteralLong, |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1313 | // Long branches. |
| 1314 | kLongUncondBranch, |
| 1315 | kLongCondBranch, |
| 1316 | kLongCall, |
Alexey Frunze | 19f6c69 | 2016-11-30 19:19:55 -0800 | [diff] [blame] | 1317 | // Far label. |
| 1318 | kFarLabel, |
| 1319 | // Far literals. |
| 1320 | kFarLiteral, |
| 1321 | kFarLiteralUnsigned, |
| 1322 | kFarLiteralLong, |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1323 | }; |
| 1324 | |
| 1325 | // Bit sizes of offsets defined as enums to minimize chance of typos. |
| 1326 | enum OffsetBits { |
| 1327 | kOffset16 = 16, |
| 1328 | kOffset18 = 18, |
| 1329 | kOffset21 = 21, |
| 1330 | kOffset23 = 23, |
| 1331 | kOffset28 = 28, |
| 1332 | kOffset32 = 32, |
| 1333 | }; |
| 1334 | |
| 1335 | static constexpr uint32_t kUnresolved = 0xffffffff; // Unresolved target_ |
| 1336 | static constexpr int32_t kMaxBranchLength = 32; |
| 1337 | static constexpr int32_t kMaxBranchSize = kMaxBranchLength * sizeof(uint32_t); |
| 1338 | |
| 1339 | struct BranchInfo { |
| 1340 | // Branch length as a number of 4-byte-long instructions. |
| 1341 | uint32_t length; |
| 1342 | // Ordinal number (0-based) of the first (or the only) instruction that contains the branch's |
| 1343 | // PC-relative offset (or its most significant 16-bit half, which goes first). |
| 1344 | uint32_t instr_offset; |
| 1345 | // Different MIPS instructions with PC-relative offsets apply said offsets to slightly |
| 1346 | // different origins, e.g. to PC or PC+4. Encode the origin distance (as a number of 4-byte |
| 1347 | // instructions) from the instruction containing the offset. |
| 1348 | uint32_t pc_org; |
| 1349 | // How large (in bits) a PC-relative offset can be for a given type of branch (kCondBranch is |
| 1350 | // an exception: use kOffset23 for beqzc/bnezc). |
| 1351 | OffsetBits offset_size; |
| 1352 | // Some MIPS instructions with PC-relative offsets shift the offset by 2. Encode the shift |
| 1353 | // count. |
| 1354 | int offset_shift; |
| 1355 | }; |
| 1356 | static const BranchInfo branch_info_[/* Type */]; |
| 1357 | |
Alexey Frunze | 19f6c69 | 2016-11-30 19:19:55 -0800 | [diff] [blame] | 1358 | // Unconditional branch or call. |
| 1359 | Branch(uint32_t location, uint32_t target, bool is_call); |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1360 | // Conditional branch. |
| 1361 | Branch(uint32_t location, |
| 1362 | uint32_t target, |
| 1363 | BranchCondition condition, |
| 1364 | GpuRegister lhs_reg, |
Alexey Frunze | 19f6c69 | 2016-11-30 19:19:55 -0800 | [diff] [blame] | 1365 | GpuRegister rhs_reg); |
| 1366 | // Label address (in literal area) or literal. |
| 1367 | Branch(uint32_t location, GpuRegister dest_reg, Type label_or_literal_type); |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1368 | |
| 1369 | // Some conditional branches with lhs = rhs are effectively NOPs, while some |
| 1370 | // others are effectively unconditional. MIPSR6 conditional branches require lhs != rhs. |
| 1371 | // So, we need a way to identify such branches in order to emit no instructions for them |
| 1372 | // or change them to unconditional. |
| 1373 | static bool IsNop(BranchCondition condition, GpuRegister lhs, GpuRegister rhs); |
| 1374 | static bool IsUncond(BranchCondition condition, GpuRegister lhs, GpuRegister rhs); |
| 1375 | |
| 1376 | static BranchCondition OppositeCondition(BranchCondition cond); |
| 1377 | |
| 1378 | Type GetType() const; |
| 1379 | BranchCondition GetCondition() const; |
| 1380 | GpuRegister GetLeftRegister() const; |
| 1381 | GpuRegister GetRightRegister() const; |
| 1382 | uint32_t GetTarget() const; |
| 1383 | uint32_t GetLocation() const; |
| 1384 | uint32_t GetOldLocation() const; |
| 1385 | uint32_t GetLength() const; |
| 1386 | uint32_t GetOldLength() const; |
| 1387 | uint32_t GetSize() const; |
| 1388 | uint32_t GetOldSize() const; |
| 1389 | uint32_t GetEndLocation() const; |
| 1390 | uint32_t GetOldEndLocation() const; |
| 1391 | bool IsLong() const; |
| 1392 | bool IsResolved() const; |
| 1393 | |
| 1394 | // Returns the bit size of the signed offset that the branch instruction can handle. |
| 1395 | OffsetBits GetOffsetSize() const; |
| 1396 | |
| 1397 | // Calculates the distance between two byte locations in the assembler buffer and |
| 1398 | // returns the number of bits needed to represent the distance as a signed integer. |
| 1399 | // |
| 1400 | // Branch instructions have signed offsets of 16, 19 (addiupc), 21 (beqzc/bnezc), |
| 1401 | // and 26 (bc) bits, which are additionally shifted left 2 positions at run time. |
| 1402 | // |
| 1403 | // Composite branches (made of several instructions) with longer reach have 32-bit |
| 1404 | // offsets encoded as 2 16-bit "halves" in two instructions (high half goes first). |
| 1405 | // The composite branches cover the range of PC + ~+/-2GB. The range is not end-to-end, |
| 1406 | // however. Consider the following implementation of a long unconditional branch, for |
| 1407 | // example: |
| 1408 | // |
| 1409 | // auipc at, offset_31_16 // at = pc + sign_extend(offset_31_16) << 16 |
| 1410 | // jic at, offset_15_0 // pc = at + sign_extend(offset_15_0) |
| 1411 | // |
| 1412 | // Both of the above instructions take 16-bit signed offsets as immediate operands. |
| 1413 | // When bit 15 of offset_15_0 is 1, it effectively causes subtraction of 0x10000 |
| 1414 | // due to sign extension. This must be compensated for by incrementing offset_31_16 |
| 1415 | // by 1. offset_31_16 can only be incremented by 1 if it's not 0x7FFF. If it is |
| 1416 | // 0x7FFF, adding 1 will overflow the positive offset into the negative range. |
| 1417 | // Therefore, the long branch range is something like from PC - 0x80000000 to |
| 1418 | // PC + 0x7FFF7FFF, IOW, shorter by 32KB on one side. |
| 1419 | // |
| 1420 | // The returned values are therefore: 18, 21, 23, 28 and 32. There's also a special |
| 1421 | // case with the addiu instruction and a 16 bit offset. |
| 1422 | static OffsetBits GetOffsetSizeNeeded(uint32_t location, uint32_t target); |
| 1423 | |
| 1424 | // Resolve a branch when the target is known. |
| 1425 | void Resolve(uint32_t target); |
| 1426 | |
| 1427 | // Relocate a branch by a given delta if needed due to expansion of this or another |
| 1428 | // branch at a given location by this delta (just changes location_ and target_). |
| 1429 | void Relocate(uint32_t expand_location, uint32_t delta); |
| 1430 | |
| 1431 | // If the branch is short, changes its type to long. |
| 1432 | void PromoteToLong(); |
| 1433 | |
| 1434 | // If necessary, updates the type by promoting a short branch to a long branch |
| 1435 | // based on the branch location and target. Returns the amount (in bytes) by |
| 1436 | // which the branch size has increased. |
| 1437 | // max_short_distance caps the maximum distance between location_ and target_ |
| 1438 | // that is allowed for short branches. This is for debugging/testing purposes. |
| 1439 | // max_short_distance = 0 forces all short branches to become long. |
| 1440 | // Use the implicit default argument when not debugging/testing. |
| 1441 | uint32_t PromoteIfNeeded(uint32_t max_short_distance = std::numeric_limits<uint32_t>::max()); |
| 1442 | |
| 1443 | // Returns the location of the instruction(s) containing the offset. |
| 1444 | uint32_t GetOffsetLocation() const; |
| 1445 | |
| 1446 | // Calculates and returns the offset ready for encoding in the branch instruction(s). |
| 1447 | uint32_t GetOffset() const; |
| 1448 | |
| 1449 | private: |
| 1450 | // Completes branch construction by determining and recording its type. |
Alexey Frunze | 19f6c69 | 2016-11-30 19:19:55 -0800 | [diff] [blame] | 1451 | void InitializeType(Type initial_type); |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1452 | // Helper for the above. |
| 1453 | void InitShortOrLong(OffsetBits ofs_size, Type short_type, Type long_type); |
| 1454 | |
| 1455 | uint32_t old_location_; // Offset into assembler buffer in bytes. |
| 1456 | uint32_t location_; // Offset into assembler buffer in bytes. |
| 1457 | uint32_t target_; // Offset into assembler buffer in bytes. |
| 1458 | |
| 1459 | GpuRegister lhs_reg_; // Left-hand side register in conditional branches or |
Alexey Frunze | 19f6c69 | 2016-11-30 19:19:55 -0800 | [diff] [blame] | 1460 | // destination register in literals. |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1461 | GpuRegister rhs_reg_; // Right-hand side register in conditional branches. |
| 1462 | BranchCondition condition_; // Condition for conditional branches. |
| 1463 | |
| 1464 | Type type_; // Current type of the branch. |
| 1465 | Type old_type_; // Initial type of the branch. |
| 1466 | }; |
| 1467 | friend std::ostream& operator<<(std::ostream& os, const Branch::Type& rhs); |
| 1468 | friend std::ostream& operator<<(std::ostream& os, const Branch::OffsetBits& rhs); |
| 1469 | |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1470 | void EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, int shamt, int funct); |
Chris Larsen | 2fadd7b | 2015-08-14 14:56:10 -0700 | [diff] [blame] | 1471 | void EmitRsd(int opcode, GpuRegister rs, GpuRegister rd, int shamt, int funct); |
| 1472 | void EmitRtd(int opcode, GpuRegister rt, GpuRegister rd, int shamt, int funct); |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1473 | void EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm); |
Alexey Frunze | 4dda337 | 2015-06-01 18:31:49 -0700 | [diff] [blame] | 1474 | void EmitI21(int opcode, GpuRegister rs, uint32_t imm21); |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1475 | void EmitI26(int opcode, uint32_t imm26); |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1476 | void EmitFR(int opcode, int fmt, FpuRegister ft, FpuRegister fs, FpuRegister fd, int funct); |
| 1477 | void EmitFI(int opcode, int fmt, FpuRegister rt, uint16_t imm); |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1478 | void EmitBcondc(BranchCondition cond, GpuRegister rs, GpuRegister rt, uint32_t imm16_21); |
Goran Jakovljevic | 5a9e51d | 2017-03-16 16:11:43 +0000 | [diff] [blame^] | 1479 | void EmitMsa3R(int operation, |
| 1480 | int df, |
| 1481 | VectorRegister wt, |
| 1482 | VectorRegister ws, |
| 1483 | VectorRegister wd, |
| 1484 | int minor_opcode); |
| 1485 | void EmitMsaBIT(int operation, int df_m, VectorRegister ws, VectorRegister wd, int minor_opcode); |
| 1486 | void EmitMsaELM(int operation, int df_n, VectorRegister ws, VectorRegister wd, int minor_opcode); |
| 1487 | void EmitMsaMI10(int s10, GpuRegister rs, VectorRegister wd, int minor_opcode, int df); |
| 1488 | void EmitMsa2R(int operation, int df, VectorRegister ws, VectorRegister wd, int minor_opcode); |
| 1489 | void EmitMsa2RF(int operation, int df, VectorRegister ws, VectorRegister wd, int minor_opcode); |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1490 | |
| 1491 | void Buncond(Mips64Label* label); |
| 1492 | void Bcond(Mips64Label* label, |
| 1493 | BranchCondition condition, |
| 1494 | GpuRegister lhs, |
| 1495 | GpuRegister rhs = ZERO); |
Alexey Frunze | 19f6c69 | 2016-11-30 19:19:55 -0800 | [diff] [blame] | 1496 | void Call(Mips64Label* label); |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1497 | void FinalizeLabeledBranch(Mips64Label* label); |
| 1498 | |
| 1499 | Branch* GetBranch(uint32_t branch_id); |
| 1500 | const Branch* GetBranch(uint32_t branch_id) const; |
| 1501 | |
Alexey Frunze | 19f6c69 | 2016-11-30 19:19:55 -0800 | [diff] [blame] | 1502 | void EmitLiterals(); |
Alexey Frunze | 0960ac5 | 2016-12-20 17:24:59 -0800 | [diff] [blame] | 1503 | void ReserveJumpTableSpace(); |
| 1504 | void EmitJumpTables(); |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1505 | void PromoteBranches(); |
| 1506 | void EmitBranch(Branch* branch); |
| 1507 | void EmitBranches(); |
| 1508 | void PatchCFI(); |
| 1509 | |
| 1510 | // Emits exception block. |
| 1511 | void EmitExceptionPoll(Mips64ExceptionSlowPath* exception); |
| 1512 | |
| 1513 | // List of exception blocks to generate at the end of the code cache. |
| 1514 | std::vector<Mips64ExceptionSlowPath> exception_blocks_; |
| 1515 | |
| 1516 | std::vector<Branch> branches_; |
| 1517 | |
| 1518 | // Whether appending instructions at the end of the buffer or overwriting the existing ones. |
| 1519 | bool overwriting_; |
| 1520 | // The current overwrite location. |
| 1521 | uint32_t overwrite_location_; |
| 1522 | |
Alexey Frunze | 19f6c69 | 2016-11-30 19:19:55 -0800 | [diff] [blame] | 1523 | // Use std::deque<> for literal labels to allow insertions at the end |
| 1524 | // without invalidating pointers and references to existing elements. |
| 1525 | ArenaDeque<Literal> literals_; |
| 1526 | ArenaDeque<Literal> long_literals_; // 64-bit literals separated for alignment reasons. |
| 1527 | |
Alexey Frunze | 0960ac5 | 2016-12-20 17:24:59 -0800 | [diff] [blame] | 1528 | // Jump table list. |
| 1529 | ArenaDeque<JumpTable> jump_tables_; |
| 1530 | |
Alexey Frunze | a0e87b0 | 2015-09-24 22:57:20 -0700 | [diff] [blame] | 1531 | // Data for AdjustedPosition(), see the description there. |
| 1532 | uint32_t last_position_adjustment_; |
| 1533 | uint32_t last_old_position_; |
| 1534 | uint32_t last_branch_id_; |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1535 | |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1536 | DISALLOW_COPY_AND_ASSIGN(Mips64Assembler); |
| 1537 | }; |
| 1538 | |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1539 | } // namespace mips64 |
| 1540 | } // namespace art |
| 1541 | |
| 1542 | #endif // ART_COMPILER_UTILS_MIPS64_ASSEMBLER_MIPS64_H_ |