Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | /* This file contains codegen for the Thumb2 ISA. */ |
| 18 | |
| 19 | #include "arm_lir.h" |
| 20 | #include "codegen_arm.h" |
| 21 | #include "dex/quick/mir_to_lir-inl.h" |
buzbee | b5860fb | 2014-06-21 15:31:01 -0700 | [diff] [blame] | 22 | #include "dex/reg_storage_eq.h" |
Ian Rogers | 166db04 | 2013-07-26 12:05:57 -0700 | [diff] [blame] | 23 | #include "entrypoints/quick/quick_entrypoints.h" |
Ian Rogers | 7e70b00 | 2014-10-08 11:47:24 -0700 | [diff] [blame] | 24 | #include "mirror/array-inl.h" |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 25 | |
| 26 | namespace art { |
| 27 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 28 | LIR* ArmMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 29 | OpRegReg(kOpCmp, src1, src2); |
| 30 | return OpCondBranch(cond, target); |
| 31 | } |
| 32 | |
| 33 | /* |
| 34 | * Generate a Thumb2 IT instruction, which can nullify up to |
| 35 | * four subsequent instructions based on a condition and its |
| 36 | * inverse. The condition applies to the first instruction, which |
| 37 | * is executed if the condition is met. The string "guide" consists |
| 38 | * of 0 to 3 chars, and applies to the 2nd through 4th instruction. |
| 39 | * A "T" means the instruction is executed if the condition is |
| 40 | * met, and an "E" means the instruction is executed if the condition |
| 41 | * is not met. |
| 42 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 43 | LIR* ArmMir2Lir::OpIT(ConditionCode ccode, const char* guide) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 44 | int mask; |
| 45 | int mask3 = 0; |
| 46 | int mask2 = 0; |
| 47 | int mask1 = 0; |
| 48 | ArmConditionCode code = ArmConditionEncoding(ccode); |
| 49 | int cond_bit = code & 1; |
| 50 | int alt_bit = cond_bit ^ 1; |
| 51 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 52 | switch (strlen(guide)) { |
| 53 | case 3: |
| 54 | mask1 = (guide[2] == 'T') ? cond_bit : alt_bit; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 55 | FALLTHROUGH_INTENDED; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 56 | case 2: |
| 57 | mask2 = (guide[1] == 'T') ? cond_bit : alt_bit; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 58 | FALLTHROUGH_INTENDED; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 59 | case 1: |
| 60 | mask3 = (guide[0] == 'T') ? cond_bit : alt_bit; |
| 61 | break; |
| 62 | case 0: |
| 63 | break; |
| 64 | default: |
| 65 | LOG(FATAL) << "OAT: bad case in OpIT"; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 66 | UNREACHABLE(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 67 | } |
| 68 | mask = (mask3 << 3) | (mask2 << 2) | (mask1 << 1) | |
| 69 | (1 << (3 - strlen(guide))); |
| 70 | return NewLIR2(kThumb2It, code, mask); |
| 71 | } |
| 72 | |
Andreas Gampe | b14329f | 2014-05-15 11:16:06 -0700 | [diff] [blame] | 73 | void ArmMir2Lir::UpdateIT(LIR* it, const char* new_guide) { |
| 74 | int mask; |
| 75 | int mask3 = 0; |
| 76 | int mask2 = 0; |
| 77 | int mask1 = 0; |
| 78 | ArmConditionCode code = static_cast<ArmConditionCode>(it->operands[0]); |
| 79 | int cond_bit = code & 1; |
| 80 | int alt_bit = cond_bit ^ 1; |
| 81 | |
Andreas Gampe | b14329f | 2014-05-15 11:16:06 -0700 | [diff] [blame] | 82 | switch (strlen(new_guide)) { |
| 83 | case 3: |
| 84 | mask1 = (new_guide[2] == 'T') ? cond_bit : alt_bit; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 85 | FALLTHROUGH_INTENDED; |
Andreas Gampe | b14329f | 2014-05-15 11:16:06 -0700 | [diff] [blame] | 86 | case 2: |
| 87 | mask2 = (new_guide[1] == 'T') ? cond_bit : alt_bit; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 88 | FALLTHROUGH_INTENDED; |
Andreas Gampe | b14329f | 2014-05-15 11:16:06 -0700 | [diff] [blame] | 89 | case 1: |
| 90 | mask3 = (new_guide[0] == 'T') ? cond_bit : alt_bit; |
| 91 | break; |
| 92 | case 0: |
| 93 | break; |
| 94 | default: |
| 95 | LOG(FATAL) << "OAT: bad case in UpdateIT"; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 96 | UNREACHABLE(); |
Andreas Gampe | b14329f | 2014-05-15 11:16:06 -0700 | [diff] [blame] | 97 | } |
| 98 | mask = (mask3 << 3) | (mask2 << 2) | (mask1 << 1) | |
| 99 | (1 << (3 - strlen(new_guide))); |
| 100 | it->operands[1] = mask; |
| 101 | } |
| 102 | |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 103 | void ArmMir2Lir::OpEndIT(LIR* it) { |
| 104 | // TODO: use the 'it' pointer to do some checks with the LIR, for example |
| 105 | // we could check that the number of instructions matches the mask |
| 106 | // in the IT instruction. |
| 107 | CHECK(it != nullptr); |
| 108 | GenBarrier(); |
| 109 | } |
| 110 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 111 | /* |
| 112 | * 64-bit 3way compare function. |
| 113 | * mov rX, #-1 |
| 114 | * cmp op1hi, op2hi |
| 115 | * blt done |
| 116 | * bgt flip |
| 117 | * sub rX, op1lo, op2lo (treat as unsigned) |
| 118 | * beq done |
| 119 | * ite hi |
| 120 | * mov(hi) rX, #-1 |
| 121 | * mov(!hi) rX, #1 |
| 122 | * flip: |
| 123 | * neg rX |
| 124 | * done: |
| 125 | */ |
buzbee | a1983d4 | 2014-04-07 12:35:39 -0700 | [diff] [blame] | 126 | void ArmMir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 127 | LIR* target1; |
| 128 | LIR* target2; |
| 129 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 130 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 131 | RegStorage t_reg = AllocTemp(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 132 | LoadConstant(t_reg, -1); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 133 | OpRegReg(kOpCmp, rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 134 | LIR* branch1 = OpCondBranch(kCondLt, NULL); |
| 135 | LIR* branch2 = OpCondBranch(kCondGt, NULL); |
buzbee | a1983d4 | 2014-04-07 12:35:39 -0700 | [diff] [blame] | 136 | OpRegRegReg(kOpSub, t_reg, rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 137 | LIR* branch3 = OpCondBranch(kCondEq, NULL); |
| 138 | |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 139 | LIR* it = OpIT(kCondHi, "E"); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 140 | NewLIR2(kThumb2MovI8M, t_reg.GetReg(), ModifiedImmediate(-1)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 141 | LoadConstant(t_reg, 1); |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 142 | OpEndIT(it); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 143 | |
| 144 | target2 = NewLIR0(kPseudoTargetLabel); |
| 145 | OpRegReg(kOpNeg, t_reg, t_reg); |
| 146 | |
| 147 | target1 = NewLIR0(kPseudoTargetLabel); |
| 148 | |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 149 | RegLocation rl_temp = LocCReturn(); // Just using as template, will change |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 150 | rl_temp.reg.SetReg(t_reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 151 | StoreValue(rl_dest, rl_temp); |
| 152 | FreeTemp(t_reg); |
| 153 | |
| 154 | branch1->target = target1; |
| 155 | branch2->target = target2; |
| 156 | branch3->target = branch1->target; |
| 157 | } |
| 158 | |
| 159 | void ArmMir2Lir::GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 160 | int64_t val, ConditionCode ccode) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 161 | int32_t val_lo = Low32Bits(val); |
| 162 | int32_t val_hi = High32Bits(val); |
Brian Carlstrom | 4274889 | 2013-07-18 18:04:08 -0700 | [diff] [blame] | 163 | DCHECK_GE(ModifiedImmediate(val_lo), 0); |
| 164 | DCHECK_GE(ModifiedImmediate(val_hi), 0); |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 165 | LIR* taken = &block_label_list_[bb->taken]; |
| 166 | LIR* not_taken = &block_label_list_[bb->fall_through]; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 167 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 168 | RegStorage low_reg = rl_src1.reg.GetLow(); |
| 169 | RegStorage high_reg = rl_src1.reg.GetHigh(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 170 | |
Vladimir Marko | 58af1f9 | 2013-12-19 13:31:15 +0000 | [diff] [blame] | 171 | if (val == 0 && (ccode == kCondEq || ccode == kCondNe)) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 172 | RegStorage t_reg = AllocTemp(); |
| 173 | NewLIR4(kThumb2OrrRRRs, t_reg.GetReg(), low_reg.GetReg(), high_reg.GetReg(), 0); |
Vladimir Marko | 58af1f9 | 2013-12-19 13:31:15 +0000 | [diff] [blame] | 174 | FreeTemp(t_reg); |
| 175 | OpCondBranch(ccode, taken); |
| 176 | return; |
| 177 | } |
| 178 | |
Brian Carlstrom | df62950 | 2013-07-17 22:39:56 -0700 | [diff] [blame] | 179 | switch (ccode) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 180 | case kCondEq: |
| 181 | case kCondNe: |
Vladimir Marko | 58af1f9 | 2013-12-19 13:31:15 +0000 | [diff] [blame] | 182 | OpCmpImmBranch(kCondNe, high_reg, val_hi, (ccode == kCondEq) ? not_taken : taken); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 183 | break; |
| 184 | case kCondLt: |
| 185 | OpCmpImmBranch(kCondLt, high_reg, val_hi, taken); |
| 186 | OpCmpImmBranch(kCondGt, high_reg, val_hi, not_taken); |
Vladimir Marko | 58af1f9 | 2013-12-19 13:31:15 +0000 | [diff] [blame] | 187 | ccode = kCondUlt; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 188 | break; |
| 189 | case kCondLe: |
| 190 | OpCmpImmBranch(kCondLt, high_reg, val_hi, taken); |
| 191 | OpCmpImmBranch(kCondGt, high_reg, val_hi, not_taken); |
| 192 | ccode = kCondLs; |
| 193 | break; |
| 194 | case kCondGt: |
| 195 | OpCmpImmBranch(kCondGt, high_reg, val_hi, taken); |
| 196 | OpCmpImmBranch(kCondLt, high_reg, val_hi, not_taken); |
| 197 | ccode = kCondHi; |
| 198 | break; |
| 199 | case kCondGe: |
| 200 | OpCmpImmBranch(kCondGt, high_reg, val_hi, taken); |
| 201 | OpCmpImmBranch(kCondLt, high_reg, val_hi, not_taken); |
Vladimir Marko | 58af1f9 | 2013-12-19 13:31:15 +0000 | [diff] [blame] | 202 | ccode = kCondUge; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 203 | break; |
| 204 | default: |
| 205 | LOG(FATAL) << "Unexpected ccode: " << ccode; |
| 206 | } |
| 207 | OpCmpImmBranch(ccode, low_reg, val_lo, taken); |
| 208 | } |
| 209 | |
Andreas Gampe | 90969af | 2014-07-15 23:02:11 -0700 | [diff] [blame] | 210 | void ArmMir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, |
| 211 | int32_t true_val, int32_t false_val, RegStorage rs_dest, |
| 212 | int dest_reg_class) { |
| 213 | // TODO: Generalize the IT below to accept more than one-instruction loads. |
| 214 | DCHECK(InexpensiveConstantInt(true_val)); |
| 215 | DCHECK(InexpensiveConstantInt(false_val)); |
| 216 | |
| 217 | if ((true_val == 0 && code == kCondEq) || |
| 218 | (false_val == 0 && code == kCondNe)) { |
| 219 | OpRegRegReg(kOpSub, rs_dest, left_op, right_op); |
| 220 | DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode)); |
| 221 | LIR* it = OpIT(kCondNe, ""); |
| 222 | LoadConstant(rs_dest, code == kCondEq ? false_val : true_val); |
| 223 | OpEndIT(it); |
| 224 | return; |
| 225 | } |
| 226 | |
| 227 | OpRegReg(kOpCmp, left_op, right_op); // Same? |
| 228 | LIR* it = OpIT(code, "E"); // if-convert the test |
| 229 | LoadConstant(rs_dest, true_val); // .eq case - load true |
| 230 | LoadConstant(rs_dest, false_val); // .eq case - load true |
| 231 | OpEndIT(it); |
| 232 | } |
| 233 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 234 | void ArmMir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 235 | RegLocation rl_result; |
| 236 | RegLocation rl_src = mir_graph_->GetSrc(mir, 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 237 | RegLocation rl_dest = mir_graph_->GetDest(mir); |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 238 | // Avoid using float regs here. |
| 239 | RegisterClass src_reg_class = rl_src.ref ? kRefReg : kCoreReg; |
| 240 | RegisterClass result_reg_class = rl_dest.ref ? kRefReg : kCoreReg; |
| 241 | rl_src = LoadValue(rl_src, src_reg_class); |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 242 | ConditionCode ccode = mir->meta.ccode; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 243 | if (mir->ssa_rep->num_uses == 1) { |
| 244 | // CONST case |
| 245 | int true_val = mir->dalvikInsn.vB; |
| 246 | int false_val = mir->dalvikInsn.vC; |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 247 | rl_result = EvalLoc(rl_dest, result_reg_class, true); |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 248 | // Change kCondNe to kCondEq for the special cases below. |
| 249 | if (ccode == kCondNe) { |
| 250 | ccode = kCondEq; |
| 251 | std::swap(true_val, false_val); |
| 252 | } |
| 253 | bool cheap_false_val = InexpensiveConstantInt(false_val); |
| 254 | if (cheap_false_val && ccode == kCondEq && (true_val == 0 || true_val == -1)) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 255 | OpRegRegImm(kOpSub, rl_result.reg, rl_src.reg, -true_val); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 256 | DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode)); |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 257 | LIR* it = OpIT(true_val == 0 ? kCondNe : kCondUge, ""); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 258 | LoadConstant(rl_result.reg, false_val); |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 259 | OpEndIT(it); // Add a scheduling barrier to keep the IT shadow intact |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 260 | } else if (cheap_false_val && ccode == kCondEq && true_val == 1) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 261 | OpRegRegImm(kOpRsub, rl_result.reg, rl_src.reg, 1); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 262 | DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode)); |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 263 | LIR* it = OpIT(kCondLs, ""); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 264 | LoadConstant(rl_result.reg, false_val); |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 265 | OpEndIT(it); // Add a scheduling barrier to keep the IT shadow intact |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 266 | } else if (cheap_false_val && InexpensiveConstantInt(true_val)) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 267 | OpRegImm(kOpCmp, rl_src.reg, 0); |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 268 | LIR* it = OpIT(ccode, "E"); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 269 | LoadConstant(rl_result.reg, true_val); |
| 270 | LoadConstant(rl_result.reg, false_val); |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 271 | OpEndIT(it); // Add a scheduling barrier to keep the IT shadow intact |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 272 | } else { |
| 273 | // Unlikely case - could be tuned. |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 274 | RegStorage t_reg1 = AllocTypedTemp(false, result_reg_class); |
| 275 | RegStorage t_reg2 = AllocTypedTemp(false, result_reg_class); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 276 | LoadConstant(t_reg1, true_val); |
| 277 | LoadConstant(t_reg2, false_val); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 278 | OpRegImm(kOpCmp, rl_src.reg, 0); |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 279 | LIR* it = OpIT(ccode, "E"); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 280 | OpRegCopy(rl_result.reg, t_reg1); |
| 281 | OpRegCopy(rl_result.reg, t_reg2); |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 282 | OpEndIT(it); // Add a scheduling barrier to keep the IT shadow intact |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 283 | } |
| 284 | } else { |
| 285 | // MOVE case |
| 286 | RegLocation rl_true = mir_graph_->reg_location_[mir->ssa_rep->uses[1]]; |
| 287 | RegLocation rl_false = mir_graph_->reg_location_[mir->ssa_rep->uses[2]]; |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 288 | rl_true = LoadValue(rl_true, result_reg_class); |
| 289 | rl_false = LoadValue(rl_false, result_reg_class); |
| 290 | rl_result = EvalLoc(rl_dest, result_reg_class, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 291 | OpRegImm(kOpCmp, rl_src.reg, 0); |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 292 | LIR* it = nullptr; |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 293 | if (rl_result.reg.GetReg() == rl_true.reg.GetReg()) { // Is the "true" case already in place? |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 294 | it = OpIT(NegateComparison(ccode), ""); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 295 | OpRegCopy(rl_result.reg, rl_false.reg); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 296 | } else if (rl_result.reg.GetReg() == rl_false.reg.GetReg()) { // False case in place? |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 297 | it = OpIT(ccode, ""); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 298 | OpRegCopy(rl_result.reg, rl_true.reg); |
buzbee | 252254b | 2013-09-08 16:20:53 -0700 | [diff] [blame] | 299 | } else { // Normal - select between the two. |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 300 | it = OpIT(ccode, "E"); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 301 | OpRegCopy(rl_result.reg, rl_true.reg); |
| 302 | OpRegCopy(rl_result.reg, rl_false.reg); |
buzbee | 252254b | 2013-09-08 16:20:53 -0700 | [diff] [blame] | 303 | } |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 304 | OpEndIT(it); // Add a scheduling barrier to keep the IT shadow intact |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 305 | } |
| 306 | StoreValue(rl_dest, rl_result); |
| 307 | } |
| 308 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 309 | void ArmMir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 310 | RegLocation rl_src1 = mir_graph_->GetSrcWide(mir, 0); |
| 311 | RegLocation rl_src2 = mir_graph_->GetSrcWide(mir, 2); |
| 312 | // Normalize such that if either operand is constant, src2 will be constant. |
Vladimir Marko | a894607 | 2014-01-22 10:30:44 +0000 | [diff] [blame] | 313 | ConditionCode ccode = mir->meta.ccode; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 314 | if (rl_src1.is_const) { |
Vladimir Marko | 58af1f9 | 2013-12-19 13:31:15 +0000 | [diff] [blame] | 315 | std::swap(rl_src1, rl_src2); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 316 | ccode = FlipComparisonOrder(ccode); |
| 317 | } |
| 318 | if (rl_src2.is_const) { |
buzbee | 082833c | 2014-05-17 23:16:26 -0700 | [diff] [blame] | 319 | rl_src2 = UpdateLocWide(rl_src2); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 320 | // Do special compare/branch against simple const operand if not already in registers. |
| 321 | int64_t val = mir_graph_->ConstantValueWide(rl_src2); |
buzbee | 082833c | 2014-05-17 23:16:26 -0700 | [diff] [blame] | 322 | if ((rl_src2.location != kLocPhysReg) && |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 323 | ((ModifiedImmediate(Low32Bits(val)) >= 0) && (ModifiedImmediate(High32Bits(val)) >= 0))) { |
| 324 | GenFusedLongCmpImmBranch(bb, rl_src1, val, ccode); |
| 325 | return; |
| 326 | } |
| 327 | } |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 328 | LIR* taken = &block_label_list_[bb->taken]; |
| 329 | LIR* not_taken = &block_label_list_[bb->fall_through]; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 330 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 331 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 332 | OpRegReg(kOpCmp, rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); |
Brian Carlstrom | df62950 | 2013-07-17 22:39:56 -0700 | [diff] [blame] | 333 | switch (ccode) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 334 | case kCondEq: |
| 335 | OpCondBranch(kCondNe, not_taken); |
| 336 | break; |
| 337 | case kCondNe: |
| 338 | OpCondBranch(kCondNe, taken); |
| 339 | break; |
| 340 | case kCondLt: |
| 341 | OpCondBranch(kCondLt, taken); |
| 342 | OpCondBranch(kCondGt, not_taken); |
Vladimir Marko | 58af1f9 | 2013-12-19 13:31:15 +0000 | [diff] [blame] | 343 | ccode = kCondUlt; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 344 | break; |
| 345 | case kCondLe: |
| 346 | OpCondBranch(kCondLt, taken); |
| 347 | OpCondBranch(kCondGt, not_taken); |
| 348 | ccode = kCondLs; |
| 349 | break; |
| 350 | case kCondGt: |
| 351 | OpCondBranch(kCondGt, taken); |
| 352 | OpCondBranch(kCondLt, not_taken); |
| 353 | ccode = kCondHi; |
| 354 | break; |
| 355 | case kCondGe: |
| 356 | OpCondBranch(kCondGt, taken); |
| 357 | OpCondBranch(kCondLt, not_taken); |
Vladimir Marko | 58af1f9 | 2013-12-19 13:31:15 +0000 | [diff] [blame] | 358 | ccode = kCondUge; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 359 | break; |
| 360 | default: |
| 361 | LOG(FATAL) << "Unexpected ccode: " << ccode; |
| 362 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 363 | OpRegReg(kOpCmp, rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 364 | OpCondBranch(ccode, taken); |
| 365 | } |
| 366 | |
| 367 | /* |
| 368 | * Generate a register comparison to an immediate and branch. Caller |
| 369 | * is responsible for setting branch target field. |
| 370 | */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 371 | LIR* ArmMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) { |
Andreas Gampe | 9522af9 | 2014-07-14 20:16:59 -0700 | [diff] [blame] | 372 | LIR* branch = nullptr; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 373 | ArmConditionCode arm_cond = ArmConditionEncoding(cond); |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 374 | /* |
| 375 | * A common use of OpCmpImmBranch is for null checks, and using the Thumb 16-bit |
| 376 | * compare-and-branch if zero is ideal if it will reach. However, because null checks |
Mingyao Yang | 3a74d15 | 2014-04-21 15:39:44 -0700 | [diff] [blame] | 377 | * branch forward to a slow path, they will frequently not reach - and thus have to |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 378 | * be converted to a long form during assembly (which will trigger another assembly |
| 379 | * pass). Here we estimate the branch distance for checks, and if large directly |
| 380 | * generate the long form in an attempt to avoid an extra assembly pass. |
Mingyao Yang | 3a74d15 | 2014-04-21 15:39:44 -0700 | [diff] [blame] | 381 | * TODO: consider interspersing slowpaths in code following unconditional branches. |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 382 | */ |
| 383 | bool skip = ((target != NULL) && (target->opcode == kPseudoThrowTarget)); |
Razvan A Lupusoru | 7503597 | 2014-09-11 15:24:59 -0700 | [diff] [blame] | 384 | skip &= ((mir_graph_->GetNumDalvikInsns() - current_dalvik_offset_) > 64); |
Andreas Gampe | 9522af9 | 2014-07-14 20:16:59 -0700 | [diff] [blame] | 385 | if (!skip && reg.Low8() && (check_value == 0)) { |
| 386 | if (arm_cond == kArmCondEq || arm_cond == kArmCondNe) { |
| 387 | branch = NewLIR2((arm_cond == kArmCondEq) ? kThumb2Cbz : kThumb2Cbnz, |
| 388 | reg.GetReg(), 0); |
| 389 | } else if (arm_cond == kArmCondLs) { |
| 390 | // kArmCondLs is an unsigned less or equal. A comparison r <= 0 is then the same as cbz. |
| 391 | // This case happens for a bounds check of array[0]. |
| 392 | branch = NewLIR2(kThumb2Cbz, reg.GetReg(), 0); |
| 393 | } |
| 394 | } |
| 395 | |
| 396 | if (branch == nullptr) { |
Vladimir Marko | 2247984 | 2013-11-19 17:04:50 +0000 | [diff] [blame] | 397 | OpRegImm(kOpCmp, reg, check_value); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 398 | branch = NewLIR2(kThumbBCond, 0, arm_cond); |
| 399 | } |
Andreas Gampe | 9522af9 | 2014-07-14 20:16:59 -0700 | [diff] [blame] | 400 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 401 | branch->target = target; |
| 402 | return branch; |
| 403 | } |
| 404 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 405 | LIR* ArmMir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 406 | LIR* res; |
| 407 | int opcode; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 408 | // If src or dest is a pair, we'll be using low reg. |
| 409 | if (r_dest.IsPair()) { |
| 410 | r_dest = r_dest.GetLow(); |
| 411 | } |
| 412 | if (r_src.IsPair()) { |
| 413 | r_src = r_src.GetLow(); |
| 414 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 415 | if (r_dest.IsFloat() || r_src.IsFloat()) |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 416 | return OpFpRegCopy(r_dest, r_src); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 417 | if (r_dest.Low8() && r_src.Low8()) |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 418 | opcode = kThumbMovRR; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 419 | else if (!r_dest.Low8() && !r_src.Low8()) |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 420 | opcode = kThumbMovRR_H2H; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 421 | else if (r_dest.Low8()) |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 422 | opcode = kThumbMovRR_H2L; |
| 423 | else |
| 424 | opcode = kThumbMovRR_L2H; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 425 | res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 426 | if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { |
| 427 | res->flags.is_nop = true; |
| 428 | } |
| 429 | return res; |
| 430 | } |
| 431 | |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 432 | void ArmMir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) { |
| 433 | if (r_dest != r_src) { |
| 434 | LIR* res = OpRegCopyNoInsert(r_dest, r_src); |
| 435 | AppendLIR(res); |
| 436 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 437 | } |
| 438 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 439 | void ArmMir2Lir::OpRegCopyWide(RegStorage r_dest, RegStorage r_src) { |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 440 | if (r_dest != r_src) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 441 | bool dest_fp = r_dest.IsFloat(); |
| 442 | bool src_fp = r_src.IsFloat(); |
| 443 | DCHECK(r_dest.Is64Bit()); |
| 444 | DCHECK(r_src.Is64Bit()); |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 445 | if (dest_fp) { |
| 446 | if (src_fp) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 447 | OpRegCopy(r_dest, r_src); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 448 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 449 | NewLIR3(kThumb2Fmdrr, r_dest.GetReg(), r_src.GetLowReg(), r_src.GetHighReg()); |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 450 | } |
| 451 | } else { |
| 452 | if (src_fp) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 453 | NewLIR3(kThumb2Fmrrd, r_dest.GetLowReg(), r_dest.GetHighReg(), r_src.GetReg()); |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 454 | } else { |
| 455 | // Handle overlap |
| 456 | if (r_src.GetHighReg() == r_dest.GetLowReg()) { |
| 457 | DCHECK_NE(r_src.GetLowReg(), r_dest.GetHighReg()); |
| 458 | OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); |
| 459 | OpRegCopy(r_dest.GetLow(), r_src.GetLow()); |
| 460 | } else { |
| 461 | OpRegCopy(r_dest.GetLow(), r_src.GetLow()); |
| 462 | OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); |
| 463 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 464 | } |
| 465 | } |
| 466 | } |
| 467 | } |
| 468 | |
| 469 | // Table of magic divisors |
| 470 | struct MagicTable { |
| 471 | uint32_t magic; |
| 472 | uint32_t shift; |
| 473 | DividePattern pattern; |
| 474 | }; |
| 475 | |
| 476 | static const MagicTable magic_table[] = { |
| 477 | {0, 0, DivideNone}, // 0 |
| 478 | {0, 0, DivideNone}, // 1 |
| 479 | {0, 0, DivideNone}, // 2 |
| 480 | {0x55555556, 0, Divide3}, // 3 |
| 481 | {0, 0, DivideNone}, // 4 |
| 482 | {0x66666667, 1, Divide5}, // 5 |
| 483 | {0x2AAAAAAB, 0, Divide3}, // 6 |
| 484 | {0x92492493, 2, Divide7}, // 7 |
| 485 | {0, 0, DivideNone}, // 8 |
| 486 | {0x38E38E39, 1, Divide5}, // 9 |
| 487 | {0x66666667, 2, Divide5}, // 10 |
| 488 | {0x2E8BA2E9, 1, Divide5}, // 11 |
| 489 | {0x2AAAAAAB, 1, Divide5}, // 12 |
| 490 | {0x4EC4EC4F, 2, Divide5}, // 13 |
| 491 | {0x92492493, 3, Divide7}, // 14 |
| 492 | {0x88888889, 3, Divide7}, // 15 |
| 493 | }; |
| 494 | |
| 495 | // Integer division by constant via reciprocal multiply (Hacker's Delight, 10-4) |
buzbee | 11b63d1 | 2013-08-27 07:34:17 -0700 | [diff] [blame] | 496 | bool ArmMir2Lir::SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 497 | RegLocation rl_src, RegLocation rl_dest, int lit) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 498 | if ((lit < 0) || (lit >= static_cast<int>(sizeof(magic_table)/sizeof(magic_table[0])))) { |
| 499 | return false; |
| 500 | } |
| 501 | DividePattern pattern = magic_table[lit].pattern; |
| 502 | if (pattern == DivideNone) { |
| 503 | return false; |
| 504 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 505 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 506 | RegStorage r_magic = AllocTemp(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 507 | LoadConstant(r_magic, magic_table[lit].magic); |
| 508 | rl_src = LoadValue(rl_src, kCoreReg); |
| 509 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 510 | RegStorage r_hi = AllocTemp(); |
| 511 | RegStorage r_lo = AllocTemp(); |
Zheng Xu | f9719f9 | 2014-04-02 13:31:31 +0100 | [diff] [blame] | 512 | |
| 513 | // rl_dest and rl_src might overlap. |
| 514 | // Reuse r_hi to save the div result for reminder case. |
| 515 | RegStorage r_div_result = is_div ? rl_result.reg : r_hi; |
| 516 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 517 | NewLIR4(kThumb2Smull, r_lo.GetReg(), r_hi.GetReg(), r_magic.GetReg(), rl_src.reg.GetReg()); |
Brian Carlstrom | df62950 | 2013-07-17 22:39:56 -0700 | [diff] [blame] | 518 | switch (pattern) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 519 | case Divide3: |
Zheng Xu | f9719f9 | 2014-04-02 13:31:31 +0100 | [diff] [blame] | 520 | OpRegRegRegShift(kOpSub, r_div_result, r_hi, rl_src.reg, EncodeShift(kArmAsr, 31)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 521 | break; |
| 522 | case Divide5: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 523 | OpRegRegImm(kOpAsr, r_lo, rl_src.reg, 31); |
Zheng Xu | f9719f9 | 2014-04-02 13:31:31 +0100 | [diff] [blame] | 524 | OpRegRegRegShift(kOpRsub, r_div_result, r_lo, r_hi, |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 525 | EncodeShift(kArmAsr, magic_table[lit].shift)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 526 | break; |
| 527 | case Divide7: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 528 | OpRegReg(kOpAdd, r_hi, rl_src.reg); |
| 529 | OpRegRegImm(kOpAsr, r_lo, rl_src.reg, 31); |
Zheng Xu | f9719f9 | 2014-04-02 13:31:31 +0100 | [diff] [blame] | 530 | OpRegRegRegShift(kOpRsub, r_div_result, r_lo, r_hi, |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 531 | EncodeShift(kArmAsr, magic_table[lit].shift)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 532 | break; |
| 533 | default: |
| 534 | LOG(FATAL) << "Unexpected pattern: " << pattern; |
| 535 | } |
Zheng Xu | f9719f9 | 2014-04-02 13:31:31 +0100 | [diff] [blame] | 536 | |
| 537 | if (!is_div) { |
| 538 | // div_result = src / lit |
| 539 | // tmp1 = div_result * lit |
| 540 | // dest = src - tmp1 |
| 541 | RegStorage tmp1 = r_lo; |
| 542 | EasyMultiplyOp ops[2]; |
| 543 | |
| 544 | bool canEasyMultiply = GetEasyMultiplyTwoOps(lit, ops); |
| 545 | DCHECK_NE(canEasyMultiply, false); |
| 546 | |
| 547 | GenEasyMultiplyTwoOps(tmp1, r_div_result, ops); |
| 548 | OpRegRegReg(kOpSub, rl_result.reg, rl_src.reg, tmp1); |
| 549 | } |
| 550 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 551 | StoreValue(rl_dest, rl_result); |
| 552 | return true; |
| 553 | } |
| 554 | |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 555 | // Try to convert *lit to 1 RegRegRegShift/RegRegShift form. |
| 556 | bool ArmMir2Lir::GetEasyMultiplyOp(int lit, ArmMir2Lir::EasyMultiplyOp* op) { |
| 557 | if (IsPowerOfTwo(lit)) { |
| 558 | op->op = kOpLsl; |
| 559 | op->shift = LowestSetBit(lit); |
| 560 | return true; |
| 561 | } |
| 562 | |
| 563 | if (IsPowerOfTwo(lit - 1)) { |
| 564 | op->op = kOpAdd; |
| 565 | op->shift = LowestSetBit(lit - 1); |
| 566 | return true; |
| 567 | } |
| 568 | |
| 569 | if (IsPowerOfTwo(lit + 1)) { |
| 570 | op->op = kOpRsub; |
| 571 | op->shift = LowestSetBit(lit + 1); |
| 572 | return true; |
| 573 | } |
| 574 | |
| 575 | op->op = kOpInvalid; |
Zheng Xu | f9719f9 | 2014-04-02 13:31:31 +0100 | [diff] [blame] | 576 | op->shift = 0; |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 577 | return false; |
| 578 | } |
| 579 | |
| 580 | // Try to convert *lit to 1~2 RegRegRegShift/RegRegShift forms. |
| 581 | bool ArmMir2Lir::GetEasyMultiplyTwoOps(int lit, EasyMultiplyOp* ops) { |
| 582 | GetEasyMultiplyOp(lit, &ops[0]); |
| 583 | if (GetEasyMultiplyOp(lit, &ops[0])) { |
| 584 | ops[1].op = kOpInvalid; |
Zheng Xu | f9719f9 | 2014-04-02 13:31:31 +0100 | [diff] [blame] | 585 | ops[1].shift = 0; |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 586 | return true; |
| 587 | } |
| 588 | |
| 589 | int lit1 = lit; |
| 590 | uint32_t shift = LowestSetBit(lit1); |
| 591 | if (GetEasyMultiplyOp(lit1 >> shift, &ops[0])) { |
| 592 | ops[1].op = kOpLsl; |
| 593 | ops[1].shift = shift; |
| 594 | return true; |
| 595 | } |
| 596 | |
| 597 | lit1 = lit - 1; |
| 598 | shift = LowestSetBit(lit1); |
| 599 | if (GetEasyMultiplyOp(lit1 >> shift, &ops[0])) { |
| 600 | ops[1].op = kOpAdd; |
| 601 | ops[1].shift = shift; |
| 602 | return true; |
| 603 | } |
| 604 | |
| 605 | lit1 = lit + 1; |
| 606 | shift = LowestSetBit(lit1); |
| 607 | if (GetEasyMultiplyOp(lit1 >> shift, &ops[0])) { |
| 608 | ops[1].op = kOpRsub; |
| 609 | ops[1].shift = shift; |
| 610 | return true; |
| 611 | } |
| 612 | |
| 613 | return false; |
| 614 | } |
| 615 | |
Zheng Xu | f9719f9 | 2014-04-02 13:31:31 +0100 | [diff] [blame] | 616 | // Generate instructions to do multiply. |
| 617 | // Additional temporary register is required, |
| 618 | // if it need to generate 2 instructions and src/dest overlap. |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 619 | void ArmMir2Lir::GenEasyMultiplyTwoOps(RegStorage r_dest, RegStorage r_src, EasyMultiplyOp* ops) { |
Zheng Xu | f9719f9 | 2014-04-02 13:31:31 +0100 | [diff] [blame] | 620 | // tmp1 = ( src << shift1) + [ src | -src | 0 ] |
| 621 | // dest = (tmp1 << shift2) + [ src | -src | 0 ] |
| 622 | |
| 623 | RegStorage r_tmp1; |
| 624 | if (ops[1].op == kOpInvalid) { |
| 625 | r_tmp1 = r_dest; |
| 626 | } else if (r_dest.GetReg() != r_src.GetReg()) { |
| 627 | r_tmp1 = r_dest; |
| 628 | } else { |
| 629 | r_tmp1 = AllocTemp(); |
| 630 | } |
| 631 | |
| 632 | switch (ops[0].op) { |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 633 | case kOpLsl: |
Zheng Xu | f9719f9 | 2014-04-02 13:31:31 +0100 | [diff] [blame] | 634 | OpRegRegImm(kOpLsl, r_tmp1, r_src, ops[0].shift); |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 635 | break; |
| 636 | case kOpAdd: |
Zheng Xu | f9719f9 | 2014-04-02 13:31:31 +0100 | [diff] [blame] | 637 | OpRegRegRegShift(kOpAdd, r_tmp1, r_src, r_src, EncodeShift(kArmLsl, ops[0].shift)); |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 638 | break; |
| 639 | case kOpRsub: |
Zheng Xu | f9719f9 | 2014-04-02 13:31:31 +0100 | [diff] [blame] | 640 | OpRegRegRegShift(kOpRsub, r_tmp1, r_src, r_src, EncodeShift(kArmLsl, ops[0].shift)); |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 641 | break; |
| 642 | default: |
Zheng Xu | f9719f9 | 2014-04-02 13:31:31 +0100 | [diff] [blame] | 643 | DCHECK_EQ(ops[0].op, kOpInvalid); |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 644 | break; |
Zheng Xu | f9719f9 | 2014-04-02 13:31:31 +0100 | [diff] [blame] | 645 | } |
| 646 | |
| 647 | switch (ops[1].op) { |
| 648 | case kOpInvalid: |
| 649 | return; |
| 650 | case kOpLsl: |
| 651 | OpRegRegImm(kOpLsl, r_dest, r_tmp1, ops[1].shift); |
| 652 | break; |
| 653 | case kOpAdd: |
| 654 | OpRegRegRegShift(kOpAdd, r_dest, r_src, r_tmp1, EncodeShift(kArmLsl, ops[1].shift)); |
| 655 | break; |
| 656 | case kOpRsub: |
| 657 | OpRegRegRegShift(kOpRsub, r_dest, r_src, r_tmp1, EncodeShift(kArmLsl, ops[1].shift)); |
| 658 | break; |
| 659 | default: |
| 660 | LOG(FATAL) << "Unexpected opcode passed to GenEasyMultiplyTwoOps"; |
| 661 | break; |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 662 | } |
| 663 | } |
| 664 | |
| 665 | bool ArmMir2Lir::EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) { |
| 666 | EasyMultiplyOp ops[2]; |
| 667 | |
| 668 | if (!GetEasyMultiplyTwoOps(lit, ops)) { |
| 669 | return false; |
| 670 | } |
| 671 | |
| 672 | rl_src = LoadValue(rl_src, kCoreReg); |
| 673 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 674 | |
| 675 | GenEasyMultiplyTwoOps(rl_result.reg, rl_src.reg, ops); |
| 676 | StoreValue(rl_dest, rl_result); |
| 677 | return true; |
| 678 | } |
| 679 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 680 | RegLocation ArmMir2Lir::GenDivRem(RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 681 | RegLocation rl_src2, bool is_div, int flags) { |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 682 | LOG(FATAL) << "Unexpected use of GenDivRem for Arm"; |
| 683 | return rl_dest; |
| 684 | } |
| 685 | |
| 686 | RegLocation ArmMir2Lir::GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div) { |
| 687 | LOG(FATAL) << "Unexpected use of GenDivRemLit for Arm"; |
| 688 | return rl_dest; |
| 689 | } |
| 690 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 691 | RegLocation ArmMir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg1, int lit, bool is_div) { |
Dave Allison | 7020278 | 2013-10-22 17:52:19 -0700 | [diff] [blame] | 692 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 693 | |
| 694 | // Put the literal in a temp. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 695 | RegStorage lit_temp = AllocTemp(); |
Dave Allison | 7020278 | 2013-10-22 17:52:19 -0700 | [diff] [blame] | 696 | LoadConstant(lit_temp, lit); |
| 697 | // Use the generic case for div/rem with arg2 in a register. |
| 698 | // TODO: The literal temp can be freed earlier during a modulus to reduce reg pressure. |
| 699 | rl_result = GenDivRem(rl_result, reg1, lit_temp, is_div); |
| 700 | FreeTemp(lit_temp); |
| 701 | |
| 702 | return rl_result; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 703 | } |
| 704 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 705 | RegLocation ArmMir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg1, RegStorage reg2, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 706 | bool is_div) { |
Dave Allison | 7020278 | 2013-10-22 17:52:19 -0700 | [diff] [blame] | 707 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 708 | if (is_div) { |
| 709 | // Simple case, use sdiv instruction. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 710 | OpRegRegReg(kOpDiv, rl_result.reg, reg1, reg2); |
Dave Allison | 7020278 | 2013-10-22 17:52:19 -0700 | [diff] [blame] | 711 | } else { |
| 712 | // Remainder case, use the following code: |
| 713 | // temp = reg1 / reg2 - integer division |
| 714 | // temp = temp * reg2 |
| 715 | // dest = reg1 - temp |
| 716 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 717 | RegStorage temp = AllocTemp(); |
Dave Allison | 7020278 | 2013-10-22 17:52:19 -0700 | [diff] [blame] | 718 | OpRegRegReg(kOpDiv, temp, reg1, reg2); |
| 719 | OpRegReg(kOpMul, temp, reg2); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 720 | OpRegRegReg(kOpSub, rl_result.reg, reg1, temp); |
Dave Allison | 7020278 | 2013-10-22 17:52:19 -0700 | [diff] [blame] | 721 | FreeTemp(temp); |
| 722 | } |
| 723 | |
| 724 | return rl_result; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 725 | } |
| 726 | |
Serban Constantinescu | 23abec9 | 2014-07-02 16:13:38 +0100 | [diff] [blame] | 727 | bool ArmMir2Lir::GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 728 | DCHECK_EQ(cu_->instruction_set, kThumb2); |
Serban Constantinescu | 23abec9 | 2014-07-02 16:13:38 +0100 | [diff] [blame] | 729 | if (is_long) { |
| 730 | return false; |
| 731 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 732 | RegLocation rl_src1 = info->args[0]; |
| 733 | RegLocation rl_src2 = info->args[1]; |
| 734 | rl_src1 = LoadValue(rl_src1, kCoreReg); |
| 735 | rl_src2 = LoadValue(rl_src2, kCoreReg); |
| 736 | RegLocation rl_dest = InlineTarget(info); |
| 737 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 738 | OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg); |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 739 | LIR* it = OpIT((is_min) ? kCondGt : kCondLt, "E"); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 740 | OpRegReg(kOpMov, rl_result.reg, rl_src2.reg); |
| 741 | OpRegReg(kOpMov, rl_result.reg, rl_src1.reg); |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 742 | OpEndIT(it); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 743 | StoreValue(rl_dest, rl_result); |
| 744 | return true; |
| 745 | } |
| 746 | |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 747 | bool ArmMir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) { |
| 748 | RegLocation rl_src_address = info->args[0]; // long address |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 749 | rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[1] |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 750 | RegLocation rl_dest = InlineTarget(info); |
| 751 | RegLocation rl_address = LoadValue(rl_src_address, kCoreReg); |
| 752 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 753 | if (size == k64) { |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 754 | // Fake unaligned LDRD by two unaligned LDR instructions on ARMv7 with SCTLR.A set to 0. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 755 | if (rl_address.reg.GetReg() != rl_result.reg.GetLowReg()) { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 756 | Load32Disp(rl_address.reg, 0, rl_result.reg.GetLow()); |
| 757 | Load32Disp(rl_address.reg, 4, rl_result.reg.GetHigh()); |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 758 | } else { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 759 | Load32Disp(rl_address.reg, 4, rl_result.reg.GetHigh()); |
| 760 | Load32Disp(rl_address.reg, 0, rl_result.reg.GetLow()); |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 761 | } |
| 762 | StoreValueWide(rl_dest, rl_result); |
| 763 | } else { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 764 | DCHECK(size == kSignedByte || size == kSignedHalf || size == k32); |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 765 | // Unaligned load with LDR and LDRSH is allowed on ARMv7 with SCTLR.A set to 0. |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 766 | LoadBaseDisp(rl_address.reg, 0, rl_result.reg, size, kNotVolatile); |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 767 | StoreValue(rl_dest, rl_result); |
| 768 | } |
| 769 | return true; |
| 770 | } |
| 771 | |
| 772 | bool ArmMir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) { |
| 773 | RegLocation rl_src_address = info->args[0]; // long address |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 774 | rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[1] |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 775 | RegLocation rl_src_value = info->args[2]; // [size] value |
| 776 | RegLocation rl_address = LoadValue(rl_src_address, kCoreReg); |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 777 | if (size == k64) { |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 778 | // Fake unaligned STRD by two unaligned STR instructions on ARMv7 with SCTLR.A set to 0. |
| 779 | RegLocation rl_value = LoadValueWide(rl_src_value, kCoreReg); |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 780 | StoreBaseDisp(rl_address.reg, 0, rl_value.reg.GetLow(), k32, kNotVolatile); |
| 781 | StoreBaseDisp(rl_address.reg, 4, rl_value.reg.GetHigh(), k32, kNotVolatile); |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 782 | } else { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 783 | DCHECK(size == kSignedByte || size == kSignedHalf || size == k32); |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 784 | // Unaligned store with STR and STRSH is allowed on ARMv7 with SCTLR.A set to 0. |
| 785 | RegLocation rl_value = LoadValue(rl_src_value, kCoreReg); |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 786 | StoreBaseDisp(rl_address.reg, 0, rl_value.reg, size, kNotVolatile); |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 787 | } |
| 788 | return true; |
| 789 | } |
| 790 | |
Hans Boehm | 48f5c47 | 2014-06-27 14:50:10 -0700 | [diff] [blame] | 791 | // Generate a CAS with memory_order_seq_cst semantics. |
Vladimir Marko | 1c282e2 | 2013-11-21 14:49:47 +0000 | [diff] [blame] | 792 | bool ArmMir2Lir::GenInlinedCas(CallInfo* info, bool is_long, bool is_object) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 793 | DCHECK_EQ(cu_->instruction_set, kThumb2); |
| 794 | // Unused - RegLocation rl_src_unsafe = info->args[0]; |
Vladimir Marko | 1c282e2 | 2013-11-21 14:49:47 +0000 | [diff] [blame] | 795 | RegLocation rl_src_obj = info->args[1]; // Object - known non-null |
| 796 | RegLocation rl_src_offset = info->args[2]; // long low |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 797 | rl_src_offset = NarrowRegLoc(rl_src_offset); // ignore high half in info->args[3] |
Vladimir Marko | 1c282e2 | 2013-11-21 14:49:47 +0000 | [diff] [blame] | 798 | RegLocation rl_src_expected = info->args[4]; // int, long or Object |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 799 | // If is_long, high half is in info->args[5] |
| 800 | RegLocation rl_src_new_value = info->args[is_long ? 6 : 5]; // int, long or Object |
| 801 | // If is_long, high half is in info->args[7] |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 802 | RegLocation rl_dest = InlineTarget(info); // boolean place for result |
| 803 | |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 804 | // We have only 5 temporary registers available and actually only 4 if the InlineTarget |
| 805 | // above locked one of the temps. For a straightforward CAS64 we need 7 registers: |
| 806 | // r_ptr (1), new_value (2), expected(2) and ldrexd result (2). If neither expected nor |
| 807 | // new_value is in a non-temp core register we shall reload them in the ldrex/strex loop |
| 808 | // into the same temps, reducing the number of required temps down to 5. We shall work |
| 809 | // around the potentially locked temp by using LR for r_ptr, unconditionally. |
| 810 | // TODO: Pass information about the need for more temps to the stack frame generation |
| 811 | // code so that we can rely on being able to allocate enough temps. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 812 | DCHECK(!GetRegInfo(rs_rARM_LR)->IsTemp()); |
| 813 | MarkTemp(rs_rARM_LR); |
| 814 | FreeTemp(rs_rARM_LR); |
| 815 | LockTemp(rs_rARM_LR); |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 816 | bool load_early = true; |
| 817 | if (is_long) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 818 | RegStorage expected_reg = rl_src_expected.reg.IsPair() ? rl_src_expected.reg.GetLow() : |
| 819 | rl_src_expected.reg; |
| 820 | RegStorage new_val_reg = rl_src_new_value.reg.IsPair() ? rl_src_new_value.reg.GetLow() : |
| 821 | rl_src_new_value.reg; |
| 822 | bool expected_is_core_reg = rl_src_expected.location == kLocPhysReg && !expected_reg.IsFloat(); |
| 823 | bool new_value_is_core_reg = rl_src_new_value.location == kLocPhysReg && !new_val_reg.IsFloat(); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 824 | bool expected_is_good_reg = expected_is_core_reg && !IsTemp(expected_reg); |
| 825 | bool new_value_is_good_reg = new_value_is_core_reg && !IsTemp(new_val_reg); |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 826 | |
| 827 | if (!expected_is_good_reg && !new_value_is_good_reg) { |
| 828 | // None of expected/new_value is non-temp reg, need to load both late |
| 829 | load_early = false; |
| 830 | // Make sure they are not in the temp regs and the load will not be skipped. |
| 831 | if (expected_is_core_reg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 832 | FlushRegWide(rl_src_expected.reg); |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 833 | ClobberSReg(rl_src_expected.s_reg_low); |
| 834 | ClobberSReg(GetSRegHi(rl_src_expected.s_reg_low)); |
| 835 | rl_src_expected.location = kLocDalvikFrame; |
| 836 | } |
| 837 | if (new_value_is_core_reg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 838 | FlushRegWide(rl_src_new_value.reg); |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 839 | ClobberSReg(rl_src_new_value.s_reg_low); |
| 840 | ClobberSReg(GetSRegHi(rl_src_new_value.s_reg_low)); |
| 841 | rl_src_new_value.location = kLocDalvikFrame; |
| 842 | } |
| 843 | } |
| 844 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 845 | |
Hans Boehm | 48f5c47 | 2014-06-27 14:50:10 -0700 | [diff] [blame] | 846 | // Prevent reordering with prior memory operations. |
| 847 | GenMemBarrier(kAnyStore); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 848 | |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 849 | RegLocation rl_object = LoadValue(rl_src_obj, kRefReg); |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 850 | RegLocation rl_new_value; |
| 851 | if (!is_long) { |
buzbee | 7c02e91 | 2014-10-03 13:14:17 -0700 | [diff] [blame] | 852 | rl_new_value = LoadValue(rl_src_new_value, LocToRegClass(rl_src_new_value)); |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 853 | } else if (load_early) { |
| 854 | rl_new_value = LoadValueWide(rl_src_new_value, kCoreReg); |
| 855 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 856 | |
Vladimir Marko | 1c282e2 | 2013-11-21 14:49:47 +0000 | [diff] [blame] | 857 | if (is_object && !mir_graph_->IsConstantNullRef(rl_new_value)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 858 | // Mark card for object assuming new value is stored. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 859 | MarkGCCard(rl_new_value.reg, rl_object.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 860 | } |
| 861 | |
| 862 | RegLocation rl_offset = LoadValue(rl_src_offset, kCoreReg); |
| 863 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 864 | RegStorage r_ptr = rs_rARM_LR; |
| 865 | OpRegRegReg(kOpAdd, r_ptr, rl_object.reg, rl_offset.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 866 | |
| 867 | // Free now unneeded rl_object and rl_offset to give more temps. |
| 868 | ClobberSReg(rl_object.s_reg_low); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 869 | FreeTemp(rl_object.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 870 | ClobberSReg(rl_offset.s_reg_low); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 871 | FreeTemp(rl_offset.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 872 | |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 873 | RegLocation rl_expected; |
| 874 | if (!is_long) { |
buzbee | 7c02e91 | 2014-10-03 13:14:17 -0700 | [diff] [blame] | 875 | rl_expected = LoadValue(rl_src_expected, LocToRegClass(rl_src_new_value)); |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 876 | } else if (load_early) { |
| 877 | rl_expected = LoadValueWide(rl_src_expected, kCoreReg); |
| 878 | } else { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 879 | // NOTE: partially defined rl_expected & rl_new_value - but we just want the regs. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 880 | RegStorage low_reg = AllocTemp(); |
| 881 | RegStorage high_reg = AllocTemp(); |
| 882 | rl_new_value.reg = RegStorage::MakeRegPair(low_reg, high_reg); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 883 | rl_expected = rl_new_value; |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 884 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 885 | |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 886 | // do { |
| 887 | // tmp = [r_ptr] - expected; |
| 888 | // } while (tmp == 0 && failure([r_ptr] <- r_new_value)); |
| 889 | // result = tmp != 0; |
| 890 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 891 | RegStorage r_tmp = AllocTemp(); |
Jeff Hao | 2de2aa1 | 2013-09-12 17:20:31 -0700 | [diff] [blame] | 892 | LIR* target = NewLIR0(kPseudoTargetLabel); |
Jeff Hao | 2de2aa1 | 2013-09-12 17:20:31 -0700 | [diff] [blame] | 893 | |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 894 | LIR* it = nullptr; |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 895 | if (is_long) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 896 | RegStorage r_tmp_high = AllocTemp(); |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 897 | if (!load_early) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 898 | LoadValueDirectWide(rl_src_expected, rl_expected.reg); |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 899 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 900 | NewLIR3(kThumb2Ldrexd, r_tmp.GetReg(), r_tmp_high.GetReg(), r_ptr.GetReg()); |
| 901 | OpRegReg(kOpSub, r_tmp, rl_expected.reg.GetLow()); |
| 902 | OpRegReg(kOpSub, r_tmp_high, rl_expected.reg.GetHigh()); |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 903 | if (!load_early) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 904 | LoadValueDirectWide(rl_src_new_value, rl_new_value.reg); |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 905 | } |
| 906 | // Make sure we use ORR that sets the ccode |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 907 | if (r_tmp.Low8() && r_tmp_high.Low8()) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 908 | NewLIR2(kThumbOrr, r_tmp.GetReg(), r_tmp_high.GetReg()); |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 909 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 910 | NewLIR4(kThumb2OrrRRRs, r_tmp.GetReg(), r_tmp.GetReg(), r_tmp_high.GetReg(), 0); |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 911 | } |
| 912 | FreeTemp(r_tmp_high); // Now unneeded |
| 913 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 914 | DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode)); |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 915 | it = OpIT(kCondEq, "T"); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 916 | NewLIR4(kThumb2Strexd /* eq */, r_tmp.GetReg(), rl_new_value.reg.GetLowReg(), rl_new_value.reg.GetHighReg(), r_ptr.GetReg()); |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 917 | |
| 918 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 919 | NewLIR3(kThumb2Ldrex, r_tmp.GetReg(), r_ptr.GetReg(), 0); |
| 920 | OpRegReg(kOpSub, r_tmp, rl_expected.reg); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 921 | DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode)); |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 922 | it = OpIT(kCondEq, "T"); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 923 | NewLIR4(kThumb2Strex /* eq */, r_tmp.GetReg(), rl_new_value.reg.GetReg(), r_ptr.GetReg(), 0); |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 924 | } |
| 925 | |
| 926 | // Still one conditional left from OpIT(kCondEq, "T") from either branch |
| 927 | OpRegImm(kOpCmp /* eq */, r_tmp, 1); |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 928 | OpEndIT(it); |
Dave Allison | 43a065c | 2014-04-01 15:14:46 -0700 | [diff] [blame] | 929 | |
Jeff Hao | 2de2aa1 | 2013-09-12 17:20:31 -0700 | [diff] [blame] | 930 | OpCondBranch(kCondEq, target); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 931 | |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 932 | if (!load_early) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 933 | FreeTemp(rl_expected.reg); // Now unneeded. |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 934 | } |
| 935 | |
Hans Boehm | 48f5c47 | 2014-06-27 14:50:10 -0700 | [diff] [blame] | 936 | // Prevent reordering with subsequent memory operations. |
| 937 | GenMemBarrier(kLoadAny); |
| 938 | |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 939 | // result := (tmp1 != 0) ? 0 : 1; |
| 940 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 941 | OpRegRegImm(kOpRsub, rl_result.reg, r_tmp, 1); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 942 | DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode)); |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 943 | it = OpIT(kCondUlt, ""); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 944 | LoadConstant(rl_result.reg, 0); /* cc */ |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 945 | FreeTemp(r_tmp); // Now unneeded. |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 946 | OpEndIT(it); // Barrier to terminate OpIT. |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 947 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 948 | StoreValue(rl_dest, rl_result); |
| 949 | |
Vladimir Marko | 3e5af82 | 2013-11-21 15:01:20 +0000 | [diff] [blame] | 950 | // Now, restore lr to its non-temp status. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 951 | Clobber(rs_rARM_LR); |
| 952 | UnmarkTemp(rs_rARM_LR); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 953 | return true; |
| 954 | } |
| 955 | |
Zheng Xu | 947717a | 2014-08-07 14:05:23 +0800 | [diff] [blame] | 956 | bool ArmMir2Lir::GenInlinedArrayCopyCharArray(CallInfo* info) { |
| 957 | constexpr int kLargeArrayThreshold = 256; |
| 958 | |
| 959 | RegLocation rl_src = info->args[0]; |
| 960 | RegLocation rl_src_pos = info->args[1]; |
| 961 | RegLocation rl_dst = info->args[2]; |
| 962 | RegLocation rl_dst_pos = info->args[3]; |
| 963 | RegLocation rl_length = info->args[4]; |
| 964 | // Compile time check, handle exception by non-inline method to reduce related meta-data. |
| 965 | if ((rl_src_pos.is_const && (mir_graph_->ConstantValue(rl_src_pos) < 0)) || |
| 966 | (rl_dst_pos.is_const && (mir_graph_->ConstantValue(rl_dst_pos) < 0)) || |
| 967 | (rl_length.is_const && (mir_graph_->ConstantValue(rl_length) < 0))) { |
| 968 | return false; |
| 969 | } |
| 970 | |
| 971 | ClobberCallerSave(); |
| 972 | LockCallTemps(); // Prepare for explicit register usage. |
| 973 | LockTemp(rs_r12); |
| 974 | RegStorage rs_src = rs_r0; |
| 975 | RegStorage rs_dst = rs_r1; |
| 976 | LoadValueDirectFixed(rl_src, rs_src); |
| 977 | LoadValueDirectFixed(rl_dst, rs_dst); |
| 978 | |
| 979 | // Handle null pointer exception in slow-path. |
| 980 | LIR* src_check_branch = OpCmpImmBranch(kCondEq, rs_src, 0, nullptr); |
| 981 | LIR* dst_check_branch = OpCmpImmBranch(kCondEq, rs_dst, 0, nullptr); |
| 982 | // Handle potential overlapping in slow-path. |
| 983 | LIR* src_dst_same = OpCmpBranch(kCondEq, rs_src, rs_dst, nullptr); |
| 984 | // Handle exception or big length in slow-path. |
| 985 | RegStorage rs_length = rs_r2; |
| 986 | LoadValueDirectFixed(rl_length, rs_length); |
| 987 | LIR* len_neg_or_too_big = OpCmpImmBranch(kCondHi, rs_length, kLargeArrayThreshold, nullptr); |
| 988 | // Src bounds check. |
| 989 | RegStorage rs_pos = rs_r3; |
| 990 | RegStorage rs_arr_length = rs_r12; |
| 991 | LoadValueDirectFixed(rl_src_pos, rs_pos); |
| 992 | LIR* src_pos_negative = OpCmpImmBranch(kCondLt, rs_pos, 0, nullptr); |
| 993 | Load32Disp(rs_src, mirror::Array::LengthOffset().Int32Value(), rs_arr_length); |
| 994 | OpRegReg(kOpSub, rs_arr_length, rs_pos); |
| 995 | LIR* src_bad_len = OpCmpBranch(kCondLt, rs_arr_length, rs_length, nullptr); |
| 996 | // Dst bounds check. |
| 997 | LoadValueDirectFixed(rl_dst_pos, rs_pos); |
| 998 | LIR* dst_pos_negative = OpCmpImmBranch(kCondLt, rs_pos, 0, nullptr); |
| 999 | Load32Disp(rs_dst, mirror::Array::LengthOffset().Int32Value(), rs_arr_length); |
| 1000 | OpRegReg(kOpSub, rs_arr_length, rs_pos); |
| 1001 | LIR* dst_bad_len = OpCmpBranch(kCondLt, rs_arr_length, rs_length, nullptr); |
| 1002 | |
| 1003 | // Everything is checked now. |
| 1004 | OpRegImm(kOpAdd, rs_dst, mirror::Array::DataOffset(2).Int32Value()); |
| 1005 | OpRegReg(kOpAdd, rs_dst, rs_pos); |
| 1006 | OpRegReg(kOpAdd, rs_dst, rs_pos); |
| 1007 | OpRegImm(kOpAdd, rs_src, mirror::Array::DataOffset(2).Int32Value()); |
| 1008 | LoadValueDirectFixed(rl_src_pos, rs_pos); |
| 1009 | OpRegReg(kOpAdd, rs_src, rs_pos); |
| 1010 | OpRegReg(kOpAdd, rs_src, rs_pos); |
| 1011 | |
| 1012 | RegStorage rs_tmp = rs_pos; |
| 1013 | OpRegRegImm(kOpLsl, rs_length, rs_length, 1); |
| 1014 | |
| 1015 | // Copy one element. |
| 1016 | OpRegRegImm(kOpAnd, rs_tmp, rs_length, 2); |
| 1017 | LIR* jmp_to_begin_loop = OpCmpImmBranch(kCondEq, rs_tmp, 0, nullptr); |
| 1018 | OpRegImm(kOpSub, rs_length, 2); |
| 1019 | LoadBaseIndexed(rs_src, rs_length, rs_tmp, 0, kSignedHalf); |
| 1020 | StoreBaseIndexed(rs_dst, rs_length, rs_tmp, 0, kSignedHalf); |
| 1021 | |
| 1022 | // Copy two elements. |
| 1023 | LIR *begin_loop = NewLIR0(kPseudoTargetLabel); |
| 1024 | LIR* jmp_to_ret = OpCmpImmBranch(kCondEq, rs_length, 0, nullptr); |
| 1025 | OpRegImm(kOpSub, rs_length, 4); |
| 1026 | LoadBaseIndexed(rs_src, rs_length, rs_tmp, 0, k32); |
| 1027 | StoreBaseIndexed(rs_dst, rs_length, rs_tmp, 0, k32); |
| 1028 | OpUnconditionalBranch(begin_loop); |
| 1029 | |
| 1030 | LIR *check_failed = NewLIR0(kPseudoTargetLabel); |
| 1031 | LIR* launchpad_branch = OpUnconditionalBranch(nullptr); |
| 1032 | LIR* return_point = NewLIR0(kPseudoTargetLabel); |
| 1033 | |
| 1034 | src_check_branch->target = check_failed; |
| 1035 | dst_check_branch->target = check_failed; |
| 1036 | src_dst_same->target = check_failed; |
| 1037 | len_neg_or_too_big->target = check_failed; |
| 1038 | src_pos_negative->target = check_failed; |
| 1039 | src_bad_len->target = check_failed; |
| 1040 | dst_pos_negative->target = check_failed; |
| 1041 | dst_bad_len->target = check_failed; |
| 1042 | jmp_to_begin_loop->target = begin_loop; |
| 1043 | jmp_to_ret->target = return_point; |
| 1044 | |
| 1045 | AddIntrinsicSlowPath(info, launchpad_branch, return_point); |
Serguei Katkov | 9863daf | 2014-09-04 15:21:32 +0700 | [diff] [blame] | 1046 | ClobberCallerSave(); // We must clobber everything because slow path will return here |
Zheng Xu | 947717a | 2014-08-07 14:05:23 +0800 | [diff] [blame] | 1047 | |
| 1048 | return true; |
| 1049 | } |
| 1050 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1051 | LIR* ArmMir2Lir::OpPcRelLoad(RegStorage reg, LIR* target) { |
| 1052 | return RawLIR(current_dalvik_offset_, kThumb2LdrPcRel12, reg.GetReg(), 0, 0, 0, 0, target); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1053 | } |
| 1054 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1055 | LIR* ArmMir2Lir::OpVldm(RegStorage r_base, int count) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1056 | return NewLIR3(kThumb2Vldms, r_base.GetReg(), rs_fr0.GetReg(), count); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1057 | } |
| 1058 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1059 | LIR* ArmMir2Lir::OpVstm(RegStorage r_base, int count) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1060 | return NewLIR3(kThumb2Vstms, r_base.GetReg(), rs_fr0.GetReg(), count); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1061 | } |
| 1062 | |
| 1063 | void ArmMir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src, |
| 1064 | RegLocation rl_result, int lit, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1065 | int first_bit, int second_bit) { |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 1066 | OpRegRegRegShift(kOpAdd, rl_result.reg, rl_src.reg, rl_src.reg, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1067 | EncodeShift(kArmLsl, second_bit - first_bit)); |
| 1068 | if (first_bit != 0) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1069 | OpRegRegImm(kOpLsl, rl_result.reg, rl_result.reg, first_bit); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1070 | } |
| 1071 | } |
| 1072 | |
Mingyao Yang | e643a17 | 2014-04-08 11:02:52 -0700 | [diff] [blame] | 1073 | void ArmMir2Lir::GenDivZeroCheckWide(RegStorage reg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1074 | DCHECK(reg.IsPair()); // TODO: support k64BitSolo. |
| 1075 | RegStorage t_reg = AllocTemp(); |
| 1076 | NewLIR4(kThumb2OrrRRRs, t_reg.GetReg(), reg.GetLowReg(), reg.GetHighReg(), 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1077 | FreeTemp(t_reg); |
Mingyao Yang | e643a17 | 2014-04-08 11:02:52 -0700 | [diff] [blame] | 1078 | GenDivZeroCheck(kCondEq); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1079 | } |
| 1080 | |
| 1081 | // Test suspend flag, return target of taken suspend branch |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1082 | LIR* ArmMir2Lir::OpTestSuspend(LIR* target) { |
Wei Jin | 04f4d8a | 2014-05-29 18:04:29 -0700 | [diff] [blame] | 1083 | #ifdef ARM_R4_SUSPEND_FLAG |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1084 | NewLIR2(kThumbSubRI8, rs_rARM_SUSPEND.GetReg(), 1); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1085 | return OpCondBranch((target == NULL) ? kCondEq : kCondNe, target); |
Wei Jin | 04f4d8a | 2014-05-29 18:04:29 -0700 | [diff] [blame] | 1086 | #else |
| 1087 | RegStorage t_reg = AllocTemp(); |
| 1088 | LoadBaseDisp(rs_rARM_SELF, Thread::ThreadFlagsOffset<4>().Int32Value(), |
| 1089 | t_reg, kUnsignedHalf); |
| 1090 | LIR* cmp_branch = OpCmpImmBranch((target == NULL) ? kCondNe : kCondEq, t_reg, |
| 1091 | 0, target); |
| 1092 | FreeTemp(t_reg); |
| 1093 | return cmp_branch; |
| 1094 | #endif |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1095 | } |
| 1096 | |
| 1097 | // Decrement register and branch on condition |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1098 | LIR* ArmMir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1099 | // Combine sub & test using sub setflags encoding here |
Vladimir Marko | dbb8c49 | 2014-02-28 17:36:39 +0000 | [diff] [blame] | 1100 | OpRegRegImm(kOpSub, reg, reg, 1); // For value == 1, this should set flags. |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1101 | DCHECK(last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1102 | return OpCondBranch(c_code, target); |
| 1103 | } |
| 1104 | |
Andreas Gampe | b14329f | 2014-05-15 11:16:06 -0700 | [diff] [blame] | 1105 | bool ArmMir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1106 | #if ANDROID_SMP != 0 |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 1107 | // Start off with using the last LIR as the barrier. If it is not enough, then we will generate one. |
| 1108 | LIR* barrier = last_lir_insn_; |
| 1109 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1110 | int dmb_flavor; |
| 1111 | // TODO: revisit Arm barrier kinds |
| 1112 | switch (barrier_kind) { |
Hans Boehm | 48f5c47 | 2014-06-27 14:50:10 -0700 | [diff] [blame] | 1113 | case kAnyStore: dmb_flavor = kISH; break; |
| 1114 | case kLoadAny: dmb_flavor = kISH; break; |
Ian Rogers | b122a4b | 2013-11-19 18:00:50 -0800 | [diff] [blame] | 1115 | case kStoreStore: dmb_flavor = kISHST; break; |
Hans Boehm | 48f5c47 | 2014-06-27 14:50:10 -0700 | [diff] [blame] | 1116 | case kAnyAny: dmb_flavor = kISH; break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1117 | default: |
| 1118 | LOG(FATAL) << "Unexpected MemBarrierKind: " << barrier_kind; |
| 1119 | dmb_flavor = kSY; // quiet gcc. |
| 1120 | break; |
| 1121 | } |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 1122 | |
Andreas Gampe | b14329f | 2014-05-15 11:16:06 -0700 | [diff] [blame] | 1123 | bool ret = false; |
| 1124 | |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 1125 | // If the same barrier already exists, don't generate another. |
| 1126 | if (barrier == nullptr |
| 1127 | || (barrier != nullptr && (barrier->opcode != kThumb2Dmb || barrier->operands[0] != dmb_flavor))) { |
| 1128 | barrier = NewLIR1(kThumb2Dmb, dmb_flavor); |
Andreas Gampe | b14329f | 2014-05-15 11:16:06 -0700 | [diff] [blame] | 1129 | ret = true; |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 1130 | } |
| 1131 | |
| 1132 | // At this point we must have a memory barrier. Mark it as a scheduling barrier as well. |
| 1133 | DCHECK(!barrier->flags.use_def_invalid); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1134 | barrier->u.m.def_mask = &kEncodeAll; |
Andreas Gampe | b14329f | 2014-05-15 11:16:06 -0700 | [diff] [blame] | 1135 | return ret; |
| 1136 | #else |
| 1137 | return false; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1138 | #endif |
| 1139 | } |
| 1140 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1141 | void ArmMir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1142 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 1143 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1144 | RegStorage z_reg = AllocTemp(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1145 | LoadConstantNoClobber(z_reg, 0); |
| 1146 | // Check for destructive overlap |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1147 | if (rl_result.reg.GetLowReg() == rl_src.reg.GetHighReg()) { |
| 1148 | RegStorage t_reg = AllocTemp(); |
| 1149 | OpRegRegReg(kOpSub, rl_result.reg.GetLow(), z_reg, rl_src.reg.GetLow()); |
| 1150 | OpRegRegReg(kOpSbc, rl_result.reg.GetHigh(), z_reg, t_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1151 | FreeTemp(t_reg); |
| 1152 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1153 | OpRegRegReg(kOpSub, rl_result.reg.GetLow(), z_reg, rl_src.reg.GetLow()); |
| 1154 | OpRegRegReg(kOpSbc, rl_result.reg.GetHigh(), z_reg, rl_src.reg.GetHigh()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1155 | } |
| 1156 | FreeTemp(z_reg); |
| 1157 | StoreValueWide(rl_dest, rl_result); |
| 1158 | } |
| 1159 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1160 | void ArmMir2Lir::GenMulLong(Instruction::Code opcode, RegLocation rl_dest, |
| 1161 | RegLocation rl_src1, RegLocation rl_src2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1162 | /* |
Zheng Xu | d7f8e02 | 2014-03-13 13:40:30 +0000 | [diff] [blame] | 1163 | * tmp1 = src1.hi * src2.lo; // src1.hi is no longer needed |
| 1164 | * dest = src1.lo * src2.lo; |
| 1165 | * tmp1 += src1.lo * src2.hi; |
| 1166 | * dest.hi += tmp1; |
| 1167 | * |
| 1168 | * To pull off inline multiply, we have a worst-case requirement of 7 temporary |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1169 | * registers. Normally for Arm, we get 5. We can get to 6 by including |
| 1170 | * lr in the temp set. The only problematic case is all operands and result are |
| 1171 | * distinct, and none have been promoted. In that case, we can succeed by aggressively |
| 1172 | * freeing operand temp registers after they are no longer needed. All other cases |
| 1173 | * can proceed normally. We'll just punt on the case of the result having a misaligned |
| 1174 | * overlap with either operand and send that case to a runtime handler. |
| 1175 | */ |
| 1176 | RegLocation rl_result; |
Alexei Zavjalov | d8c3e36 | 2014-10-08 15:51:59 +0700 | [diff] [blame] | 1177 | if (PartiallyIntersects(rl_src1, rl_dest) || (PartiallyIntersects(rl_src2, rl_dest))) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1178 | FlushAllRegs(); |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 1179 | CallRuntimeHelperRegLocationRegLocation(kQuickLmul, rl_src1, rl_src2, false); |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 1180 | rl_result = GetReturnWide(kCoreReg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1181 | StoreValueWide(rl_dest, rl_result); |
| 1182 | return; |
| 1183 | } |
Zheng Xu | d7f8e02 | 2014-03-13 13:40:30 +0000 | [diff] [blame] | 1184 | |
| 1185 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 1186 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 1187 | |
| 1188 | int reg_status = 0; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1189 | RegStorage res_lo; |
| 1190 | RegStorage res_hi; |
| 1191 | bool dest_promoted = rl_dest.location == kLocPhysReg && rl_dest.reg.Valid() && |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1192 | !IsTemp(rl_dest.reg.GetLow()) && !IsTemp(rl_dest.reg.GetHigh()); |
| 1193 | bool src1_promoted = !IsTemp(rl_src1.reg.GetLow()) && !IsTemp(rl_src1.reg.GetHigh()); |
| 1194 | bool src2_promoted = !IsTemp(rl_src2.reg.GetLow()) && !IsTemp(rl_src2.reg.GetHigh()); |
Zheng Xu | d7f8e02 | 2014-03-13 13:40:30 +0000 | [diff] [blame] | 1195 | // Check if rl_dest is *not* either operand and we have enough temp registers. |
| 1196 | if ((rl_dest.s_reg_low != rl_src1.s_reg_low && rl_dest.s_reg_low != rl_src2.s_reg_low) && |
| 1197 | (dest_promoted || src1_promoted || src2_promoted)) { |
| 1198 | // In this case, we do not need to manually allocate temp registers for result. |
| 1199 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1200 | res_lo = rl_result.reg.GetLow(); |
| 1201 | res_hi = rl_result.reg.GetHigh(); |
Zheng Xu | d7f8e02 | 2014-03-13 13:40:30 +0000 | [diff] [blame] | 1202 | } else { |
| 1203 | res_lo = AllocTemp(); |
| 1204 | if ((rl_src1.s_reg_low == rl_src2.s_reg_low) || src1_promoted || src2_promoted) { |
| 1205 | // In this case, we have enough temp registers to be allocated for result. |
| 1206 | res_hi = AllocTemp(); |
| 1207 | reg_status = 1; |
| 1208 | } else { |
| 1209 | // In this case, all temps are now allocated. |
| 1210 | // res_hi will be allocated after we can free src1_hi. |
| 1211 | reg_status = 2; |
| 1212 | } |
| 1213 | } |
| 1214 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1215 | // Temporarily add LR to the temp pool, and assign it to tmp1 |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1216 | MarkTemp(rs_rARM_LR); |
| 1217 | FreeTemp(rs_rARM_LR); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1218 | RegStorage tmp1 = rs_rARM_LR; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1219 | LockTemp(rs_rARM_LR); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1220 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1221 | if (rl_src1.reg == rl_src2.reg) { |
| 1222 | DCHECK(res_hi.Valid()); |
| 1223 | DCHECK(res_lo.Valid()); |
| 1224 | NewLIR3(kThumb2MulRRR, tmp1.GetReg(), rl_src1.reg.GetLowReg(), rl_src1.reg.GetHighReg()); |
| 1225 | NewLIR4(kThumb2Umull, res_lo.GetReg(), res_hi.GetReg(), rl_src1.reg.GetLowReg(), |
| 1226 | rl_src1.reg.GetLowReg()); |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 1227 | OpRegRegRegShift(kOpAdd, res_hi, res_hi, tmp1, EncodeShift(kArmLsl, 1)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1228 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1229 | NewLIR3(kThumb2MulRRR, tmp1.GetReg(), rl_src2.reg.GetLowReg(), rl_src1.reg.GetHighReg()); |
Zheng Xu | d7f8e02 | 2014-03-13 13:40:30 +0000 | [diff] [blame] | 1230 | if (reg_status == 2) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1231 | DCHECK(!res_hi.Valid()); |
| 1232 | DCHECK_NE(rl_src1.reg.GetLowReg(), rl_src2.reg.GetLowReg()); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1233 | DCHECK_NE(rl_src1.reg.GetHighReg(), rl_src2.reg.GetHighReg()); |
buzbee | 082833c | 2014-05-17 23:16:26 -0700 | [diff] [blame] | 1234 | // Will force free src1_hi, so must clobber. |
| 1235 | Clobber(rl_src1.reg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1236 | FreeTemp(rl_src1.reg.GetHigh()); |
Zheng Xu | d7f8e02 | 2014-03-13 13:40:30 +0000 | [diff] [blame] | 1237 | res_hi = AllocTemp(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1238 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1239 | DCHECK(res_hi.Valid()); |
| 1240 | DCHECK(res_lo.Valid()); |
| 1241 | NewLIR4(kThumb2Umull, res_lo.GetReg(), res_hi.GetReg(), rl_src2.reg.GetLowReg(), |
| 1242 | rl_src1.reg.GetLowReg()); |
| 1243 | NewLIR4(kThumb2Mla, tmp1.GetReg(), rl_src1.reg.GetLowReg(), rl_src2.reg.GetHighReg(), |
| 1244 | tmp1.GetReg()); |
| 1245 | NewLIR4(kThumb2AddRRR, res_hi.GetReg(), tmp1.GetReg(), res_hi.GetReg(), 0); |
Zheng Xu | d7f8e02 | 2014-03-13 13:40:30 +0000 | [diff] [blame] | 1246 | if (reg_status == 2) { |
buzbee | 082833c | 2014-05-17 23:16:26 -0700 | [diff] [blame] | 1247 | FreeTemp(rl_src1.reg.GetLow()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1248 | } |
| 1249 | } |
Zheng Xu | d7f8e02 | 2014-03-13 13:40:30 +0000 | [diff] [blame] | 1250 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1251 | // Now, restore lr to its non-temp status. |
Zheng Xu | d7f8e02 | 2014-03-13 13:40:30 +0000 | [diff] [blame] | 1252 | FreeTemp(tmp1); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1253 | Clobber(rs_rARM_LR); |
| 1254 | UnmarkTemp(rs_rARM_LR); |
Zheng Xu | d7f8e02 | 2014-03-13 13:40:30 +0000 | [diff] [blame] | 1255 | |
| 1256 | if (reg_status != 0) { |
| 1257 | // We had manually allocated registers for rl_result. |
| 1258 | // Now construct a RegLocation. |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 1259 | rl_result = GetReturnWide(kCoreReg); // Just using as a template. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1260 | rl_result.reg = RegStorage::MakeRegPair(res_lo, res_hi); |
Zheng Xu | d7f8e02 | 2014-03-13 13:40:30 +0000 | [diff] [blame] | 1261 | } |
| 1262 | |
| 1263 | StoreValueWide(rl_dest, rl_result); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1264 | } |
| 1265 | |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1266 | void ArmMir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 1267 | RegLocation rl_src2, int flags) { |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1268 | switch (opcode) { |
| 1269 | case Instruction::MUL_LONG: |
| 1270 | case Instruction::MUL_LONG_2ADDR: |
| 1271 | GenMulLong(opcode, rl_dest, rl_src1, rl_src2); |
| 1272 | return; |
| 1273 | case Instruction::NEG_LONG: |
| 1274 | GenNegLong(rl_dest, rl_src2); |
| 1275 | return; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1276 | |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1277 | default: |
| 1278 | break; |
| 1279 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1280 | |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1281 | // Fallback for all other ops. |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 1282 | Mir2Lir::GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2, flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1283 | } |
| 1284 | |
| 1285 | /* |
| 1286 | * Generate array load |
| 1287 | */ |
| 1288 | void ArmMir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 1289 | RegLocation rl_index, RegLocation rl_dest, int scale) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1290 | RegisterClass reg_class = RegClassBySize(size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1291 | int len_offset = mirror::Array::LengthOffset().Int32Value(); |
| 1292 | int data_offset; |
| 1293 | RegLocation rl_result; |
| 1294 | bool constant_index = rl_index.is_const; |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 1295 | rl_array = LoadValue(rl_array, kRefReg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1296 | if (!constant_index) { |
| 1297 | rl_index = LoadValue(rl_index, kCoreReg); |
| 1298 | } |
| 1299 | |
| 1300 | if (rl_dest.wide) { |
| 1301 | data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); |
| 1302 | } else { |
| 1303 | data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); |
| 1304 | } |
| 1305 | |
| 1306 | // If index is constant, just fold it into the data offset |
| 1307 | if (constant_index) { |
| 1308 | data_offset += mir_graph_->ConstantValue(rl_index) << scale; |
| 1309 | } |
| 1310 | |
| 1311 | /* null object? */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1312 | GenNullCheck(rl_array.reg, opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1313 | |
| 1314 | bool needs_range_check = (!(opt_flags & MIR_IGNORE_RANGE_CHECK)); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1315 | RegStorage reg_len; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1316 | if (needs_range_check) { |
| 1317 | reg_len = AllocTemp(); |
| 1318 | /* Get len */ |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 1319 | Load32Disp(rl_array.reg, len_offset, reg_len); |
Dave Allison | b373e09 | 2014-02-20 16:06:36 -0800 | [diff] [blame] | 1320 | MarkPossibleNullPointerException(opt_flags); |
| 1321 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1322 | ForceImplicitNullCheck(rl_array.reg, opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1323 | } |
| 1324 | if (rl_dest.wide || rl_dest.fp || constant_index) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1325 | RegStorage reg_ptr; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1326 | if (constant_index) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1327 | reg_ptr = rl_array.reg; // NOTE: must not alter reg_ptr in constant case. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1328 | } else { |
| 1329 | // No special indexed operation, lea + load w/ displacement |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 1330 | reg_ptr = AllocTempRef(); |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 1331 | OpRegRegRegShift(kOpAdd, reg_ptr, rl_array.reg, rl_index.reg, EncodeShift(kArmLsl, scale)); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1332 | FreeTemp(rl_index.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1333 | } |
| 1334 | rl_result = EvalLoc(rl_dest, reg_class, true); |
| 1335 | |
| 1336 | if (needs_range_check) { |
| 1337 | if (constant_index) { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1338 | GenArrayBoundsCheck(mir_graph_->ConstantValue(rl_index), reg_len); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1339 | } else { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1340 | GenArrayBoundsCheck(rl_index.reg, reg_len); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1341 | } |
| 1342 | FreeTemp(reg_len); |
| 1343 | } |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 1344 | LoadBaseDisp(reg_ptr, data_offset, rl_result.reg, size, kNotVolatile); |
Vladimir Marko | 455759b | 2014-05-06 20:49:36 +0100 | [diff] [blame] | 1345 | MarkPossibleNullPointerException(opt_flags); |
| 1346 | if (!constant_index) { |
| 1347 | FreeTemp(reg_ptr); |
| 1348 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1349 | if (rl_dest.wide) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1350 | StoreValueWide(rl_dest, rl_result); |
| 1351 | } else { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1352 | StoreValue(rl_dest, rl_result); |
| 1353 | } |
| 1354 | } else { |
| 1355 | // Offset base, then use indexed load |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 1356 | RegStorage reg_ptr = AllocTempRef(); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1357 | OpRegRegImm(kOpAdd, reg_ptr, rl_array.reg, data_offset); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1358 | FreeTemp(rl_array.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1359 | rl_result = EvalLoc(rl_dest, reg_class, true); |
| 1360 | |
| 1361 | if (needs_range_check) { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1362 | GenArrayBoundsCheck(rl_index.reg, reg_len); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1363 | FreeTemp(reg_len); |
| 1364 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1365 | LoadBaseIndexed(reg_ptr, rl_index.reg, rl_result.reg, scale, size); |
Dave Allison | b373e09 | 2014-02-20 16:06:36 -0800 | [diff] [blame] | 1366 | MarkPossibleNullPointerException(opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1367 | FreeTemp(reg_ptr); |
| 1368 | StoreValue(rl_dest, rl_result); |
| 1369 | } |
| 1370 | } |
| 1371 | |
| 1372 | /* |
| 1373 | * Generate array store |
| 1374 | * |
| 1375 | */ |
| 1376 | void ArmMir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 1377 | RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1378 | RegisterClass reg_class = RegClassBySize(size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1379 | int len_offset = mirror::Array::LengthOffset().Int32Value(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1380 | bool constant_index = rl_index.is_const; |
| 1381 | |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 1382 | int data_offset; |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 1383 | if (size == k64 || size == kDouble) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1384 | data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); |
| 1385 | } else { |
| 1386 | data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); |
| 1387 | } |
| 1388 | |
| 1389 | // If index is constant, just fold it into the data offset. |
| 1390 | if (constant_index) { |
| 1391 | data_offset += mir_graph_->ConstantValue(rl_index) << scale; |
| 1392 | } |
| 1393 | |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 1394 | rl_array = LoadValue(rl_array, kRefReg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1395 | if (!constant_index) { |
| 1396 | rl_index = LoadValue(rl_index, kCoreReg); |
| 1397 | } |
| 1398 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1399 | RegStorage reg_ptr; |
Ian Rogers | 773aab1 | 2013-10-14 13:50:10 -0700 | [diff] [blame] | 1400 | bool allocated_reg_ptr_temp = false; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1401 | if (constant_index) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1402 | reg_ptr = rl_array.reg; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1403 | } else if (IsTemp(rl_array.reg) && !card_mark) { |
| 1404 | Clobber(rl_array.reg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1405 | reg_ptr = rl_array.reg; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1406 | } else { |
Ian Rogers | 773aab1 | 2013-10-14 13:50:10 -0700 | [diff] [blame] | 1407 | allocated_reg_ptr_temp = true; |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 1408 | reg_ptr = AllocTempRef(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1409 | } |
| 1410 | |
| 1411 | /* null object? */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1412 | GenNullCheck(rl_array.reg, opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1413 | |
| 1414 | bool needs_range_check = (!(opt_flags & MIR_IGNORE_RANGE_CHECK)); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1415 | RegStorage reg_len; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1416 | if (needs_range_check) { |
| 1417 | reg_len = AllocTemp(); |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 1418 | // NOTE: max live temps(4) here. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1419 | /* Get len */ |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 1420 | Load32Disp(rl_array.reg, len_offset, reg_len); |
Dave Allison | b373e09 | 2014-02-20 16:06:36 -0800 | [diff] [blame] | 1421 | MarkPossibleNullPointerException(opt_flags); |
| 1422 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1423 | ForceImplicitNullCheck(rl_array.reg, opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1424 | } |
| 1425 | /* at this point, reg_ptr points to array, 2 live temps */ |
| 1426 | if (rl_src.wide || rl_src.fp || constant_index) { |
| 1427 | if (rl_src.wide) { |
| 1428 | rl_src = LoadValueWide(rl_src, reg_class); |
| 1429 | } else { |
| 1430 | rl_src = LoadValue(rl_src, reg_class); |
| 1431 | } |
| 1432 | if (!constant_index) { |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 1433 | OpRegRegRegShift(kOpAdd, reg_ptr, rl_array.reg, rl_index.reg, EncodeShift(kArmLsl, scale)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1434 | } |
| 1435 | if (needs_range_check) { |
| 1436 | if (constant_index) { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1437 | GenArrayBoundsCheck(mir_graph_->ConstantValue(rl_index), reg_len); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1438 | } else { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1439 | GenArrayBoundsCheck(rl_index.reg, reg_len); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1440 | } |
| 1441 | FreeTemp(reg_len); |
| 1442 | } |
| 1443 | |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 1444 | StoreBaseDisp(reg_ptr, data_offset, rl_src.reg, size, kNotVolatile); |
Dave Allison | b373e09 | 2014-02-20 16:06:36 -0800 | [diff] [blame] | 1445 | MarkPossibleNullPointerException(opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1446 | } else { |
| 1447 | /* reg_ptr -> array data */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1448 | OpRegRegImm(kOpAdd, reg_ptr, rl_array.reg, data_offset); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1449 | rl_src = LoadValue(rl_src, reg_class); |
| 1450 | if (needs_range_check) { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1451 | GenArrayBoundsCheck(rl_index.reg, reg_len); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1452 | FreeTemp(reg_len); |
| 1453 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1454 | StoreBaseIndexed(reg_ptr, rl_index.reg, rl_src.reg, scale, size); |
Dave Allison | b373e09 | 2014-02-20 16:06:36 -0800 | [diff] [blame] | 1455 | MarkPossibleNullPointerException(opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1456 | } |
Ian Rogers | 773aab1 | 2013-10-14 13:50:10 -0700 | [diff] [blame] | 1457 | if (allocated_reg_ptr_temp) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1458 | FreeTemp(reg_ptr); |
| 1459 | } |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 1460 | if (card_mark) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1461 | MarkGCCard(rl_src.reg, rl_array.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1462 | } |
| 1463 | } |
| 1464 | |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 1465 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1466 | void ArmMir2Lir::GenShiftImmOpLong(Instruction::Code opcode, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 1467 | RegLocation rl_dest, RegLocation rl_src, RegLocation rl_shift, |
| 1468 | int flags) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1469 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 1470 | // Per spec, we only care about low 6 bits of shift amount. |
| 1471 | int shift_amount = mir_graph_->ConstantValue(rl_shift) & 0x3f; |
| 1472 | if (shift_amount == 0) { |
| 1473 | StoreValueWide(rl_dest, rl_src); |
| 1474 | return; |
| 1475 | } |
Alexei Zavjalov | d8c3e36 | 2014-10-08 15:51:59 +0700 | [diff] [blame] | 1476 | if (PartiallyIntersects(rl_src, rl_dest)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1477 | GenShiftOpLong(opcode, rl_dest, rl_src, rl_shift); |
| 1478 | return; |
| 1479 | } |
| 1480 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Brian Carlstrom | df62950 | 2013-07-17 22:39:56 -0700 | [diff] [blame] | 1481 | switch (opcode) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1482 | case Instruction::SHL_LONG: |
| 1483 | case Instruction::SHL_LONG_2ADDR: |
| 1484 | if (shift_amount == 1) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1485 | OpRegRegReg(kOpAdd, rl_result.reg.GetLow(), rl_src.reg.GetLow(), rl_src.reg.GetLow()); |
| 1486 | OpRegRegReg(kOpAdc, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), rl_src.reg.GetHigh()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1487 | } else if (shift_amount == 32) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1488 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg); |
| 1489 | LoadConstant(rl_result.reg.GetLow(), 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1490 | } else if (shift_amount > 31) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1491 | OpRegRegImm(kOpLsl, rl_result.reg.GetHigh(), rl_src.reg.GetLow(), shift_amount - 32); |
| 1492 | LoadConstant(rl_result.reg.GetLow(), 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1493 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1494 | OpRegRegImm(kOpLsl, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), shift_amount); |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 1495 | OpRegRegRegShift(kOpOr, rl_result.reg.GetHigh(), rl_result.reg.GetHigh(), rl_src.reg.GetLow(), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1496 | EncodeShift(kArmLsr, 32 - shift_amount)); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1497 | OpRegRegImm(kOpLsl, rl_result.reg.GetLow(), rl_src.reg.GetLow(), shift_amount); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1498 | } |
| 1499 | break; |
| 1500 | case Instruction::SHR_LONG: |
| 1501 | case Instruction::SHR_LONG_2ADDR: |
| 1502 | if (shift_amount == 32) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1503 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); |
| 1504 | OpRegRegImm(kOpAsr, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), 31); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1505 | } else if (shift_amount > 31) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1506 | OpRegRegImm(kOpAsr, rl_result.reg.GetLow(), rl_src.reg.GetHigh(), shift_amount - 32); |
| 1507 | OpRegRegImm(kOpAsr, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), 31); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1508 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1509 | RegStorage t_reg = AllocTemp(); |
| 1510 | OpRegRegImm(kOpLsr, t_reg, rl_src.reg.GetLow(), shift_amount); |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 1511 | OpRegRegRegShift(kOpOr, rl_result.reg.GetLow(), t_reg, rl_src.reg.GetHigh(), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1512 | EncodeShift(kArmLsl, 32 - shift_amount)); |
| 1513 | FreeTemp(t_reg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1514 | OpRegRegImm(kOpAsr, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), shift_amount); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1515 | } |
| 1516 | break; |
| 1517 | case Instruction::USHR_LONG: |
| 1518 | case Instruction::USHR_LONG_2ADDR: |
| 1519 | if (shift_amount == 32) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1520 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); |
| 1521 | LoadConstant(rl_result.reg.GetHigh(), 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1522 | } else if (shift_amount > 31) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1523 | OpRegRegImm(kOpLsr, rl_result.reg.GetLow(), rl_src.reg.GetHigh(), shift_amount - 32); |
| 1524 | LoadConstant(rl_result.reg.GetHigh(), 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1525 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1526 | RegStorage t_reg = AllocTemp(); |
| 1527 | OpRegRegImm(kOpLsr, t_reg, rl_src.reg.GetLow(), shift_amount); |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 1528 | OpRegRegRegShift(kOpOr, rl_result.reg.GetLow(), t_reg, rl_src.reg.GetHigh(), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1529 | EncodeShift(kArmLsl, 32 - shift_amount)); |
| 1530 | FreeTemp(t_reg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1531 | OpRegRegImm(kOpLsr, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), shift_amount); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1532 | } |
| 1533 | break; |
| 1534 | default: |
| 1535 | LOG(FATAL) << "Unexpected case"; |
| 1536 | } |
| 1537 | StoreValueWide(rl_dest, rl_result); |
| 1538 | } |
| 1539 | |
| 1540 | void ArmMir2Lir::GenArithImmOpLong(Instruction::Code opcode, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 1541 | RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, |
| 1542 | int flags) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1543 | if ((opcode == Instruction::SUB_LONG_2ADDR) || (opcode == Instruction::SUB_LONG)) { |
| 1544 | if (!rl_src2.is_const) { |
| 1545 | // Don't bother with special handling for subtract from immediate. |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 1546 | GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2, flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1547 | return; |
| 1548 | } |
| 1549 | } else { |
| 1550 | // Normalize |
| 1551 | if (!rl_src2.is_const) { |
| 1552 | DCHECK(rl_src1.is_const); |
Vladimir Marko | 58af1f9 | 2013-12-19 13:31:15 +0000 | [diff] [blame] | 1553 | std::swap(rl_src1, rl_src2); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1554 | } |
| 1555 | } |
Alexei Zavjalov | d8c3e36 | 2014-10-08 15:51:59 +0700 | [diff] [blame] | 1556 | if (PartiallyIntersects(rl_src1, rl_dest)) { |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 1557 | GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2, flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1558 | return; |
| 1559 | } |
| 1560 | DCHECK(rl_src2.is_const); |
| 1561 | int64_t val = mir_graph_->ConstantValueWide(rl_src2); |
| 1562 | uint32_t val_lo = Low32Bits(val); |
| 1563 | uint32_t val_hi = High32Bits(val); |
| 1564 | int32_t mod_imm_lo = ModifiedImmediate(val_lo); |
| 1565 | int32_t mod_imm_hi = ModifiedImmediate(val_hi); |
| 1566 | |
| 1567 | // Only a subset of add/sub immediate instructions set carry - so bail if we don't fit |
Brian Carlstrom | df62950 | 2013-07-17 22:39:56 -0700 | [diff] [blame] | 1568 | switch (opcode) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1569 | case Instruction::ADD_LONG: |
| 1570 | case Instruction::ADD_LONG_2ADDR: |
| 1571 | case Instruction::SUB_LONG: |
| 1572 | case Instruction::SUB_LONG_2ADDR: |
| 1573 | if ((mod_imm_lo < 0) || (mod_imm_hi < 0)) { |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 1574 | GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2, flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1575 | return; |
| 1576 | } |
| 1577 | break; |
| 1578 | default: |
| 1579 | break; |
| 1580 | } |
| 1581 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 1582 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 1583 | // NOTE: once we've done the EvalLoc on dest, we can no longer bail. |
| 1584 | switch (opcode) { |
| 1585 | case Instruction::ADD_LONG: |
| 1586 | case Instruction::ADD_LONG_2ADDR: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1587 | NewLIR3(kThumb2AddRRI8M, rl_result.reg.GetLowReg(), rl_src1.reg.GetLowReg(), mod_imm_lo); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1588 | NewLIR3(kThumb2AdcRRI8M, rl_result.reg.GetHighReg(), rl_src1.reg.GetHighReg(), mod_imm_hi); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1589 | break; |
| 1590 | case Instruction::OR_LONG: |
| 1591 | case Instruction::OR_LONG_2ADDR: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1592 | if ((val_lo != 0) || (rl_result.reg.GetLowReg() != rl_src1.reg.GetLowReg())) { |
| 1593 | OpRegRegImm(kOpOr, rl_result.reg.GetLow(), rl_src1.reg.GetLow(), val_lo); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1594 | } |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1595 | if ((val_hi != 0) || (rl_result.reg.GetHighReg() != rl_src1.reg.GetHighReg())) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1596 | OpRegRegImm(kOpOr, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), val_hi); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1597 | } |
| 1598 | break; |
| 1599 | case Instruction::XOR_LONG: |
| 1600 | case Instruction::XOR_LONG_2ADDR: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1601 | OpRegRegImm(kOpXor, rl_result.reg.GetLow(), rl_src1.reg.GetLow(), val_lo); |
| 1602 | OpRegRegImm(kOpXor, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), val_hi); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1603 | break; |
| 1604 | case Instruction::AND_LONG: |
| 1605 | case Instruction::AND_LONG_2ADDR: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1606 | if ((val_lo != 0xffffffff) || (rl_result.reg.GetLowReg() != rl_src1.reg.GetLowReg())) { |
| 1607 | OpRegRegImm(kOpAnd, rl_result.reg.GetLow(), rl_src1.reg.GetLow(), val_lo); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1608 | } |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1609 | if ((val_hi != 0xffffffff) || (rl_result.reg.GetHighReg() != rl_src1.reg.GetHighReg())) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1610 | OpRegRegImm(kOpAnd, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), val_hi); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1611 | } |
| 1612 | break; |
| 1613 | case Instruction::SUB_LONG_2ADDR: |
| 1614 | case Instruction::SUB_LONG: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1615 | NewLIR3(kThumb2SubRRI8M, rl_result.reg.GetLowReg(), rl_src1.reg.GetLowReg(), mod_imm_lo); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1616 | NewLIR3(kThumb2SbcRRI8M, rl_result.reg.GetHighReg(), rl_src1.reg.GetHighReg(), mod_imm_hi); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1617 | break; |
| 1618 | default: |
| 1619 | LOG(FATAL) << "Unexpected opcode " << opcode; |
| 1620 | } |
| 1621 | StoreValueWide(rl_dest, rl_result); |
| 1622 | } |
| 1623 | |
| 1624 | } // namespace art |