Blame - compiler/dex/quick/x86/assemble_x86.cc - platform/art

2014-04-30 10:10:47 -0400

[diff] [blame]

178

{ kX86Lea32RM, kRegMem, IS_TERTIARY_OP | IS_LOAD | REG_DEF0_USE1, { 0, 0, 0x8D, 0, 0, 0, 0, 0 }, "Lea32RM", "!0r,[!1r+!2d]" },

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

179

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

180

{ kX86Lea32RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8D, 0, 0, 0, 0, 0 }, "Lea32RA", "!0r,[!1r+!2r<<!3d+!4d]" },

181

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

182

{ kX86Cmov32RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, {0, 0, 0x0F, 0x40, 0, 0, 0, 0}, "Cmovcc32RR", "!2c !0r,!1r" },

183

Mark Mendell

2014-04-30 10:10:47 -0400

[diff] [blame]

184

{ kX86Cmov32RMC, kRegMemCond, IS_QUAD_OP | IS_LOAD | REG_DEF0_USE01 | USES_CCODES, {0, 0, 0x0F, 0x40, 0, 0, 0, 0}, "Cmovcc32RM", "!3c !0r,[!1r+!2d]" },

185

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

186

#define SHIFT_ENCODING_MAP(opname, modrm_opcode) \

187

{ kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8RI", "!0r,!1d" }, \

188

{ kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8MI", "[!0r+!1d],!2d" }, \

189

{ kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

190

{ kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8RC", "!0r,cl" }, \

191

{ kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8MC", "[!0r+!1d],cl" }, \

192

{ kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \

193

\

194

{ kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16RI", "!0r,!1d" }, \

195

{ kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16MI", "[!0r+!1d],!2d" }, \

196

{ kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

197

{ kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16RC", "!0r,cl" }, \

198

{ kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16MC", "[!0r+!1d],cl" }, \

199

{ kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \

200

\

201

{ kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32RI", "!0r,!1d" }, \

202

{ kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32MI", "[!0r+!1d],!2d" }, \

203

{ kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \

204

{ kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32RC", "!0r,cl" }, \

205

{ kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32MC", "[!0r+!1d],cl" }, \

206

{ kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" }

207

208

SHIFT_ENCODING_MAP(Rol, 0x0),

209

SHIFT_ENCODING_MAP(Ror, 0x1),

210

SHIFT_ENCODING_MAP(Rcl, 0x2),

211

SHIFT_ENCODING_MAP(Rcr, 0x3),

212

SHIFT_ENCODING_MAP(Sal, 0x4),

213

SHIFT_ENCODING_MAP(Shr, 0x5),

214

SHIFT_ENCODING_MAP(Sar, 0x7),

215

#undef SHIFT_ENCODING_MAP

216

217

{ kX86Cmc, kNullary, NO_OPERAND, { 0, 0, 0xF5, 0, 0, 0, 0, 0}, "Cmc", "" },

Mark Mendell

2014-04-30 10:10:47 -0400

[diff] [blame]

218

{ kX86Shld32RRI, kRegRegImmRev, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xA4, 0, 0, 0, 1}, "Shld32RRI", "!0r,!1r,!2d" },

219

{ kX86Shld32MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { 0, 0, 0x0F, 0xA4, 0, 0, 0, 1}, "Shld32MRI", "[!0r+!1d],!2r,!3d" },

220

{ kX86Shrd32RRI, kRegRegImmRev, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xAC, 0, 0, 0, 1}, "Shrd32RRI", "!0r,!1r,!2d" },

221

{ kX86Shrd32MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { 0, 0, 0x0F, 0xAC, 0, 0, 0, 1}, "Shrd32MRI", "[!0r+!1d],!2r,!3d" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

222

223

{ kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8RI", "!0r,!1d" },

224

{ kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8MI", "[!0r+!1d],!2d" },

225

{ kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" },

226

{ kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16RI", "!0r,!1d" },

227

{ kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16MI", "[!0r+!1d],!2d" },

228

{ kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" },

229

{ kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32RI", "!0r,!1d" },

230

{ kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32MI", "[!0r+!1d],!2d" },

231

{ kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" },

232

{ kX86Test32RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0}, "Test32RR", "!0r,!1r" },

233

234

#define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \

235

reg, reg_kind, reg_flags, \

236

mem, mem_kind, mem_flags, \

237

arr, arr_kind, arr_flags, imm, \

238

b_flags, hw_flags, w_flags, \

239

b_format, hw_format, w_format) \

Mark Mendell

2014-04-30 10:10:47 -0400

[diff] [blame]

240

{ kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #reg, b_format "!0r" }, \

241

{ kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #mem, b_format "[!0r+!1d]" }, \

242

{ kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #arr, b_format "[!0r+!1r<<!2d+!3d]" }, \

243

{ kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #reg, hw_format "!0r" }, \

244

{ kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #mem, hw_format "[!0r+!1d]" }, \

245

{ kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #arr, hw_format "[!0r+!1r<<!2d+!3d]" }, \

246

{ kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #reg, w_format "!0r" }, \

247

{ kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #mem, w_format "[!0r+!1d]" }, \

248

{ kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #arr, w_format "[!0r+!1r<<!2d+!3d]" }

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

249

250

UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

251

UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),

252

Mark Mendell

2bf31e6

2014-01-23 12:13:40 -0800

[diff] [blame]

253

UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

254

UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),

255

UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

256

UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

257

#undef UNARY_ENCODING_MAP

258

Mark Mendell

2bf31e6

2014-01-23 12:13:40 -0800

[diff] [blame]

259

{ kx86Cdq32Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { 0, 0, 0x99, 0, 0, 0, 0, 0 }, "Cdq", "" },

Vladimir Marko

a6fd8ba

2013-12-13 10:53:49 +0000

[diff] [blame]

260

{ kX86Bswap32R, kRegOpcode, IS_UNARY_OP | REG_DEF0_USE0, { 0, 0, 0x0F, 0xC8, 0, 0, 0, 0 }, "Bswap32R", "!0r" },

261

{ kX86Push32R, kRegOpcode, IS_UNARY_OP | REG_USE0 | REG_USE_SP | REG_DEF_SP | IS_STORE, { 0, 0, 0x50, 0, 0, 0, 0, 0 }, "Push32R", "!0r" },

262

{ kX86Pop32R, kRegOpcode, IS_UNARY_OP | REG_DEF0 | REG_USE_SP | REG_DEF_SP | IS_LOAD, { 0, 0, 0x58, 0, 0, 0, 0, 0 }, "Pop32R", "!0r" },

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

263

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

264

#define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \

Mark Mendell

2014-04-30 10:10:47 -0400

[diff] [blame]

265

{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \

266

{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \

267

{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

268

269

EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0),

270

{ kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdMR", "[!0r+!1d],!2r" },

271

{ kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" },

272

273

EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0),

274

{ kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssMR", "[!0r+!1d],!2r" },

275

{ kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" },

276

277

EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0),

278

EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0),

279

EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0),

280

EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0),

281

EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0),

282

EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0),

Mark Mendell

2014-04-30 10:10:47 -0400

[diff] [blame]

283

EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES|REG_USE0),

284

EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES|REG_USE0),

285

EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES|REG_USE0),

286

EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES|REG_USE0),

287

EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0_USE0),

288

EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0_USE0),

289

EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0_USE0),

290

EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0_USE0),

291

EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0_USE0),

292

EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0_USE0),

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

293

EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0),

294

EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0),

Mark Mendell

2014-04-30 10:10:47 -0400

[diff] [blame]

295

EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0_USE0),

296

EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0_USE0),

297

EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0_USE0),

298

EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0_USE0),

299

EXT_0F_ENCODING_MAP(Punpckldq, 0x66, 0x62, REG_DEF0_USE0),

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

300

301

{ kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1 }, "PsrlqRI", "!0r,!1d" },

302

{ kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1 }, "PsllqRI", "!0r,!1d" },

Mark Mendell

bff1ef0

2013-12-13 13:47:34 -0800

[diff] [blame]

303

{ kX86SqrtsdRR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0xF2, 0, 0x0F, 0x51, 0, 0, 0, 0 }, "SqrtsdRR", "!0r,!1r" },

Razvan A Lupusoru

614c2b4

2014-01-28 17:05:21 -0800

[diff] [blame]

304

Serguei Katkov

e90501d

2014-03-12 15:56:54 +0700

[diff] [blame]

305

{ kX86Fild32M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDB, 0x00, 0, 0, 0, 0 }, "Fild32M", "[!0r,!1d]" },

306

{ kX86Fild64M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDF, 0x00, 0, 5, 0, 0 }, "Fild64M", "[!0r,!1d]" },

307

{ kX86Fstp32M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xD9, 0x00, 0, 3, 0, 0 }, "FstpsM", "[!0r,!1d]" },

308

{ kX86Fstp64M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDD, 0x00, 0, 3, 0, 0 }, "FstpdM", "[!0r,!1d]" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

309

Razvan A Lupusoru

2c498d1

2014-01-29 16:02:57 -0800

[diff] [blame]

310

EXT_0F_ENCODING_MAP(Movups, 0x0, 0x10, REG_DEF0),

311

{ kX86MovupsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovupsMR", "[!0r+!1d],!2r" },

312

{ kX86MovupsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovupsAR", "[!0r+!1r<<!2d+!3d],!4r" },

313

314

EXT_0F_ENCODING_MAP(Movaps, 0x0, 0x28, REG_DEF0),

315

{ kX86MovapsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0 }, "MovapsMR", "[!0r+!1d],!2r" },

316

{ kX86MovapsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0 }, "MovapsAR", "[!0r+!1r<<!2d+!3d],!4r" },

317

318

{ kX86MovlpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0 }, "MovlpsRM", "!0r,[!1r+!2d]" },

319

{ kX86MovlpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0 }, "MovlpsRA", "!0r,[!1r+!2r<<!3d+!4d]" },

320

{ kX86MovlpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0 }, "MovlpsMR", "[!0r+!1d],!2r" },

321

{ kX86MovlpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0 }, "MovlpsAR", "[!0r+!1r<<!2d+!3d],!4r" },

322

323

{ kX86MovhpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0 }, "MovhpsRM", "!0r,[!1r+!2d]" },

324

{ kX86MovhpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0 }, "MovhpsRA", "!0r,[!1r+!2r<<!3d+!4d]" },

325

{ kX86MovhpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0 }, "MovhpsMR", "[!0r+!1d],!2r" },

326

{ kX86MovhpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0 }, "MovhpsAR", "[!0r+!1r<<!2d+!3d],!4r" },

327

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

328

EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0),

Mark Mendell

2014-04-30 10:10:47 -0400

[diff] [blame]

329

{ kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxRR", "!0r,!1r" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

330

{ kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxMR", "[!0r+!1d],!2r" },

331

{ kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" },

332

333

{ kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8R", "!1c !0r" },

334

{ kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8M", "!2c [!0r+!1d]" },

335

{ kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" },

336

337

// TODO: load/store?

338

// Encode the modrm opcode as an extra opcode byte to avoid computation during assembly.

339

{ kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0 }, "Mfence", "" },

340

Mark Mendell

2014-04-30 10:10:47 -0400

[diff] [blame]

341

EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES),

342

EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES),

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

343

344

{ kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "!0r,!1r" },

345

{ kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1d],!2r" },

346

{ kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

347

{ kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1d],!2r" },

348

{ kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },

Vladimir Marko

70b797d

2013-12-03 15:25:24 +0000

[diff] [blame]

349

{ kX86LockCmpxchg8bM, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1d]" },

350

{ kX86LockCmpxchg8bA, kArray, IS_STORE | IS_QUAD_OP | REG_USE01 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1r<<!2d+!3d]" },

Razvan A Lupusoru

99ad723

2014-02-25 17:41:08 -0800

[diff] [blame]

351

{ kX86XchgMR, kMemReg, IS_STORE | IS_LOAD | IS_TERTIARY_OP | REG_DEF2 | REG_USE02, { 0, 0, 0x87, 0, 0, 0, 0, 0 }, "Xchg", "[!0r+!1d],!2r" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

352

353

EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0),

354

EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0),

355

EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0),

356

EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0),

357

#undef EXT_0F_ENCODING_MAP

358

359

{ kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc8", "!1c !0t" },

360

{ kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0 }, "Jcc32", "!1c !0t" },

361

{ kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0 }, "Jmp8", "!0t" },

362

{ kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp32", "!0t" },

363

{ kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpR", "!0r" },

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

364

{ kX86Jecxz8, kJmp, NO_OPERAND | IS_BRANCH | NEEDS_FIXUP | REG_USEC, { 0, 0, 0xE3, 0, 0, 0, 0, 0 }, "Jecxz", "!0t" },

Brian Carlstrom

60d7a65

2014-03-13 18:10:08 -0700

[diff] [blame]

365

{ kX86JmpT, kJmp, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpT", "fs:[!0d]" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

366

{ kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "!0r" },

367

{ kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "[!0r+!1d]" },

368

{ kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "[!0r+!1r<<!2d+!3d]" },

369

{ kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallT", "fs:[!0d]" },

Mark Mendell

2014-02-06 11:02:52 -0800

[diff] [blame]

370

{ kX86CallI, kCall, IS_UNARY_OP | IS_BRANCH, { 0, 0, 0xE8, 0, 0, 0, 0, 4 }, "CallI", "!0d" },

Brian Carlstrom

b1eba21

2013-07-17 18:07:19 -0700

[diff] [blame]

371

{ kX86Ret, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0 }, "Ret", "" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

372

373

{ kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0 }, "StartOfMethod", "!0r" },

374

{ kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" },

375

{ kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "PcRelAdr", "!0r,!1d" },

Mark Mendell

2014-04-30 10:10:47 -0400

[diff] [blame]

376

{ kX86RepneScasw, kPrefix2Nullary, NO_OPERAND | REG_USEA | REG_USEC | SETS_CCODES, { 0x66, 0xF2, 0xAF, 0, 0, 0, 0, 0 }, "RepNE ScasW", "" },

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

377

};

378

379

static size_t ComputeSize(const X86EncodingMap* entry, int base, int displacement, bool has_sib) {

380

size_t size = 0;

381

if (entry->skeleton.prefix1 > 0) {

382

++size;

383

if (entry->skeleton.prefix2 > 0) {

++size;

}

}

++size; // opcode

if (entry->skeleton.opcode == 0x0F) {

389

++size;

390

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

++size;

}

}

++size; // modrm

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

395

if (has_sib || RegStorage::RegNum(base) == rs_rX86_SP.GetRegNum()) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

396

// SP requires a SIB byte.

397

++size;

398

}

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

399

if (displacement != 0 || RegStorage::RegNum(base) == rs_rBP.GetRegNum()) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

400

// BP requires an explicit displacement, even when it's 0.

401

if (entry->opcode != kX86Lea32RA) {

402

DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0ULL) << entry->name;

403

}

404

size += IS_SIMM8(displacement) ? 1 : 4;

405

}

406

size += entry->skeleton.immediate_bytes;

return size;

}

int X86Mir2Lir::GetInsnSize(LIR* lir) {

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

411

DCHECK(!IsPseudoLirOp(lir->opcode));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

412

const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode];

413

switch (entry->kind) {

414

case kData:

415

return 4; // 4 bytes of data

416

case kNop:

417

return lir->operands[0]; // length of nop is sole operand

418

case kNullary:

419

return 1; // 1 byte of opcode

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

420

case kPrefix2Nullary:

421

return 3; // 1 byte of opcode + 2 prefixes

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

422

case kRegOpcode: // lir operands - 0: reg

423

return ComputeSize(entry, 0, 0, false) - 1; // substract 1 for modrm

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

424

case kReg: // lir operands - 0: reg

425

return ComputeSize(entry, 0, 0, false);

426

case kMem: // lir operands - 0: base, 1: disp

427

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

428

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

429

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

430

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

431

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

Mark Mendell

2014-04-30 10:10:47 -0400

[diff] [blame]

432

case kMemRegImm: // lir operands - 0: base, 1: disp, 2: reg 3: immediate

433

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

434

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

435

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

436

case kThreadReg: // lir operands - 0: disp, 1: reg

437

return ComputeSize(entry, 0, lir->operands[0], false);

438

case kRegReg:

439

return ComputeSize(entry, 0, 0, false);

440

case kRegRegStore:

441

return ComputeSize(entry, 0, 0, false);

442

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

443

return ComputeSize(entry, lir->operands[1], lir->operands[2], false);

444

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

445

return ComputeSize(entry, lir->operands[1], lir->operands[4], true);

446

case kRegThread: // lir operands - 0: reg, 1: disp

447

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

448

case kRegImm: { // lir operands - 0: reg, 1: immediate

449

size_t size = ComputeSize(entry, 0, 0, false);

450

if (entry->skeleton.ax_opcode == 0) {

451

return size;

452

} else {

453

// AX opcodes don't require the modrm byte.

454

int reg = lir->operands[0];

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

455

return size - (RegStorage::RegNum(reg) == rs_rAX.GetRegNum() ? 1 : 0);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

456

}

457

}

458

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

459

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

460

case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

461

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

462

case kThreadImm: // lir operands - 0: disp, 1: imm

463

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

464

case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

465

case kRegRegImmRev:

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

466

return ComputeSize(entry, 0, 0, false);

467

case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm

468

return ComputeSize(entry, lir->operands[1], lir->operands[2], false);

469

case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm

470

return ComputeSize(entry, lir->operands[1], lir->operands[4], true);

471

case kMovRegImm: // lir operands - 0: reg, 1: immediate

472

return 1 + entry->skeleton.immediate_bytes;

473

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

474

// Shift by immediate one has a shorter opcode.

475

return ComputeSize(entry, 0, 0, false) - (lir->operands[1] == 1 ? 1 : 0);

476

case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate

477

// Shift by immediate one has a shorter opcode.

478

return ComputeSize(entry, lir->operands[0], lir->operands[1], false) -

479

(lir->operands[2] == 1 ? 1 : 0);

480

case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate

481

// Shift by immediate one has a shorter opcode.

482

return ComputeSize(entry, lir->operands[0], lir->operands[3], true) -

483

(lir->operands[4] == 1 ? 1 : 0);

484

case kShiftRegCl:

485

return ComputeSize(entry, 0, 0, false);

486

case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl

487

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

488

case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

489

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

490

case kRegCond: // lir operands - 0: reg, 1: cond

491

return ComputeSize(entry, 0, 0, false);

492

case kMemCond: // lir operands - 0: base, 1: disp, 2: cond

493

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

494

case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond

495

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

496

case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: cond

497

return ComputeSize(entry, 0, 0, false);

Mark Mendell

2014-04-30 10:10:47 -0400

[diff] [blame]

498

case kRegMemCond: // lir operands - 0: reg, 1: reg, 2: disp, 3:cond

499

return ComputeSize(entry, lir->operands[1], lir->operands[2], false);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

500

case kJcc:

501

if (lir->opcode == kX86Jcc8) {

502

return 2; // opcode + rel8

503

} else {

504

DCHECK(lir->opcode == kX86Jcc32);

505

return 6; // 2 byte opcode + rel32

506

}

507

case kJmp:

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

508

if (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jecxz8) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

509

return 2; // opcode + rel8

510

} else if (lir->opcode == kX86Jmp32) {

511

return 5; // opcode + rel32

Brian Carlstrom

60d7a65

2014-03-13 18:10:08 -0700

[diff] [blame]

512

} else if (lir->opcode == kX86JmpT) {

513

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

514

} else {

515

DCHECK(lir->opcode == kX86JmpR);

516

return 2; // opcode + modrm

517

}

518

case kCall:

519

switch (lir->opcode) {

Mark Mendell

2014-02-06 11:02:52 -0800

[diff] [blame]

520

case kX86CallI: return 5; // opcode 0:disp

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

521

case kX86CallR: return 2; // opcode modrm

522

case kX86CallM: // lir operands - 0: base, 1: disp

523

return ComputeSize(entry, lir->operands[0], lir->operands[1], false);

524

case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp

525

return ComputeSize(entry, lir->operands[0], lir->operands[3], true);

526

case kX86CallT: // lir operands - 0: disp

527

return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit

default:

break;

}

break;

case kPcRel:

if (entry->opcode == kX86PcRelLoadRA) {

534

// lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

535

return ComputeSize(entry, lir->operands[1], 0x12345678, true);

536

} else {

537

DCHECK(entry->opcode == kX86PcRelAdr);

Brian Carlstrom

7934ac2

2013-07-26 10:54:15 -0700

[diff] [blame]

538

return 5; // opcode with reg + 4 byte immediate

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

539

}

540

case kMacro:

541

DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod));

542

return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ +

543

ComputeSize(&X86Mir2Lir::EncodingMap[kX86Sub32RI], 0, 0, false) -

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

544

(RegStorage::RegNum(lir->operands[0]) == rs_rAX.GetRegNum() ? 1 : 0); // shorter ax encoding

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

default:

break;

}

UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name;

return 0;

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

552

void X86Mir2Lir::EmitPrefix(const X86EncodingMap* entry) {

553

if (entry->skeleton.prefix1 != 0) {

554

code_buffer_.push_back(entry->skeleton.prefix1);

555

if (entry->skeleton.prefix2 != 0) {

556

code_buffer_.push_back(entry->skeleton.prefix2);

557

}

558

} else {

559

DCHECK_EQ(0, entry->skeleton.prefix2);

}

}

void X86Mir2Lir::EmitOpcode(const X86EncodingMap* entry) {

564

code_buffer_.push_back(entry->skeleton.opcode);

565

if (entry->skeleton.opcode == 0x0F) {

566

code_buffer_.push_back(entry->skeleton.extra_opcode1);

567

if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {

568

code_buffer_.push_back(entry->skeleton.extra_opcode2);

569

} else {

570

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

571

}

572

} else {

573

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

574

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

}

}

void X86Mir2Lir::EmitPrefixAndOpcode(const X86EncodingMap* entry) {

EmitPrefix(entry);

EmitOpcode(entry);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

583

static uint8_t ModrmForDisp(int base, int disp) {

584

// BP requires an explicit disp, so do not omit it in the 0 case

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

585

if (disp == 0 && RegStorage::RegNum(base) != rs_rBP.GetRegNum()) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

586

return 0;

587

} else if (IS_SIMM8(disp)) {

return 1;

} else {

return 2;

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

594

void X86Mir2Lir::EmitDisp(uint8_t base, int disp) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

595

// BP requires an explicit disp, so do not omit it in the 0 case

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

596

if (disp == 0 && RegStorage::RegNum(base) != rs_rBP.GetRegNum()) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

597

return;

598

} else if (IS_SIMM8(disp)) {

599

code_buffer_.push_back(disp & 0xFF);

600

} else {

601

code_buffer_.push_back(disp & 0xFF);

602

code_buffer_.push_back((disp >> 8) & 0xFF);

603

code_buffer_.push_back((disp >> 16) & 0xFF);

604

code_buffer_.push_back((disp >> 24) & 0xFF);

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

608

void X86Mir2Lir::EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int disp) {

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

609

DCHECK_LT(RegStorage::RegNum(reg_or_opcode), 8);

610

DCHECK_LT(RegStorage::RegNum(base), 8);

611

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (RegStorage::RegNum(reg_or_opcode) << 3) |

612

RegStorage::RegNum(base);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

613

code_buffer_.push_back(modrm);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

614

if (RegStorage::RegNum(base) == rs_rX86_SP.GetRegNum()) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

615

// Special SIB for SP base

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

616

code_buffer_.push_back(0 << 6 | rs_rX86_SP.GetRegNum() << 3 | rs_rX86_SP.GetRegNum());

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

617

}

618

EmitDisp(base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

619

}

620

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

621

void X86Mir2Lir::EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index,

622

int scale, int disp) {

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

623

DCHECK_LT(RegStorage::RegNum(reg_or_opcode), 8);

624

uint8_t modrm = (ModrmForDisp(base, disp) << 6) | RegStorage::RegNum(reg_or_opcode) << 3 |

625

rs_rX86_SP.GetRegNum();

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

626

code_buffer_.push_back(modrm);

627

DCHECK_LT(scale, 4);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

628

DCHECK_LT(RegStorage::RegNum(index), 8);

629

DCHECK_LT(RegStorage::RegNum(base), 8);

630

uint8_t sib = (scale << 6) | (RegStorage::RegNum(index) << 3) | RegStorage::RegNum(base);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

631

code_buffer_.push_back(sib);

632

EmitDisp(base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

633

}

634

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

635

void X86Mir2Lir::EmitImm(const X86EncodingMap* entry, int imm) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

636

switch (entry->skeleton.immediate_bytes) {

637

case 1:

638

DCHECK(IS_SIMM8(imm));

639

code_buffer_.push_back(imm & 0xFF);

640

break;

641

case 2:

642

DCHECK(IS_SIMM16(imm));

643

code_buffer_.push_back(imm & 0xFF);

644

code_buffer_.push_back((imm >> 8) & 0xFF);

645

break;

646

case 4:

647

code_buffer_.push_back(imm & 0xFF);

648

code_buffer_.push_back((imm >> 8) & 0xFF);

649

code_buffer_.push_back((imm >> 16) & 0xFF);

650

code_buffer_.push_back((imm >> 24) & 0xFF);

651

break;

652

default:

653

LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes

654

<< ") for instruction: " << entry->name;

break;

}

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

659

void X86Mir2Lir::EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg) {

660

EmitPrefixAndOpcode(entry);

661

// There's no 3-byte instruction with +rd

662

DCHECK(entry->skeleton.opcode != 0x0F ||

663

(entry->skeleton.extra_opcode1 != 0x38 && entry->skeleton.extra_opcode1 != 0x3A));

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

664

DCHECK(!RegStorage::IsFloat(reg));

665

DCHECK_LT(RegStorage::RegNum(reg), 8);

666

code_buffer_.back() += RegStorage::RegNum(reg);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

667

DCHECK_EQ(0, entry->skeleton.ax_opcode);

668

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

669

}

670

671

void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, uint8_t reg) {

672

EmitPrefixAndOpcode(entry);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

673

if (RegStorage::RegNum(reg) >= 4) {

674

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " "

675

<< static_cast<int>(RegStorage::RegNum(reg))

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

676

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

677

}

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

678

DCHECK_LT(RegStorage::RegNum(reg), 8);

679

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | RegStorage::RegNum(reg);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

680

code_buffer_.push_back(modrm);

681

DCHECK_EQ(0, entry->skeleton.ax_opcode);

682

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

683

}

684

685

void X86Mir2Lir::EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp) {

686

EmitPrefix(entry);

687

code_buffer_.push_back(entry->skeleton.opcode);

688

DCHECK_NE(0x0F, entry->skeleton.opcode);

689

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

690

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

691

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

692

DCHECK_EQ(0, entry->skeleton.ax_opcode);

693

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

694

}

695

696

void X86Mir2Lir::EmitOpArray(const X86EncodingMap* entry, uint8_t base, uint8_t index,

697

int scale, int disp) {

698

EmitPrefixAndOpcode(entry);

699

EmitModrmSibDisp(entry->skeleton.modrm_opcode, base, index, scale, disp);

700

DCHECK_EQ(0, entry->skeleton.ax_opcode);

701

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

702

}

703

704

void X86Mir2Lir::EmitMemReg(const X86EncodingMap* entry,

705

uint8_t base, int disp, uint8_t reg) {

706

EmitPrefixAndOpcode(entry);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

707

if (RegStorage::RegNum(reg) >= 4) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

708

DCHECK(strchr(entry->name, '8') == NULL ||

709

entry->opcode == kX86Movzx8RM || entry->opcode == kX86Movsx8RM)

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

710

<< entry->name << " " << static_cast<int>(RegStorage::RegNum(reg))

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

711

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

712

}

713

EmitModrmDisp(reg, base, disp);

714

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

715

DCHECK_EQ(0, entry->skeleton.ax_opcode);

716

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

717

}

718

719

void X86Mir2Lir::EmitRegMem(const X86EncodingMap* entry,

720

uint8_t reg, uint8_t base, int disp) {

721

// Opcode will flip operands.

722

EmitMemReg(entry, base, disp, reg);

723

}

724

725

void X86Mir2Lir::EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index,

726

int scale, int disp) {

727

EmitPrefixAndOpcode(entry);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

728

EmitModrmSibDisp(reg, base, index, scale, disp);

729

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

730

DCHECK_EQ(0, entry->skeleton.ax_opcode);

731

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

732

}

733

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

734

void X86Mir2Lir::EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale,

735

int disp, uint8_t reg) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

736

// Opcode will flip operands.

737

EmitRegArray(entry, reg, base, index, scale, disp);

738

}

739

Mark Mendell

2014-04-30 10:10:47 -0400

[diff] [blame]

740

void X86Mir2Lir::EmitArrayImm(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale,

741

int disp, int32_t imm) {

742

EmitPrefixAndOpcode(entry);

743

EmitModrmSibDisp(entry->skeleton.modrm_opcode, base, index, scale, disp);

744

DCHECK_EQ(0, entry->skeleton.ax_opcode);

Mark Mendell

9ed4277

2014-05-07 17:26:12 -0400

[diff] [blame]

745

EmitImm(entry, imm);

Mark Mendell

2014-04-30 10:10:47 -0400

[diff] [blame]

746

}

747

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

748

void X86Mir2Lir::EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp) {

749

DCHECK_NE(entry->skeleton.prefix1, 0);

750

EmitPrefixAndOpcode(entry);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

751

if (RegStorage::RegNum(reg) >= 4) {

752

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " "

753

<< static_cast<int>(RegStorage::RegNum(reg))

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

754

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

755

}

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

756

DCHECK_LT(RegStorage::RegNum(reg), 8);

757

uint8_t modrm = (0 << 6) | (RegStorage::RegNum(reg) << 3) | rs_rBP.GetRegNum();

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

758

code_buffer_.push_back(modrm);

759

code_buffer_.push_back(disp & 0xFF);

760

code_buffer_.push_back((disp >> 8) & 0xFF);

761

code_buffer_.push_back((disp >> 16) & 0xFF);

762

code_buffer_.push_back((disp >> 24) & 0xFF);

763

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

764

DCHECK_EQ(0, entry->skeleton.ax_opcode);

765

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

766

}

767

768

void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2) {

769

EmitPrefixAndOpcode(entry);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

770

DCHECK_LT(RegStorage::RegNum(reg1), 8);

771

DCHECK_LT(RegStorage::RegNum(reg2), 8);

772

uint8_t modrm = (3 << 6) | (RegStorage::RegNum(reg1) << 3) | RegStorage::RegNum(reg2);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

773

code_buffer_.push_back(modrm);

774

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

775

DCHECK_EQ(0, entry->skeleton.ax_opcode);

776

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

777

}

778

779

void X86Mir2Lir::EmitRegRegImm(const X86EncodingMap* entry,

780

uint8_t reg1, uint8_t reg2, int32_t imm) {

781

EmitPrefixAndOpcode(entry);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

782

DCHECK_LT(RegStorage::RegNum(reg1), 8);

783

DCHECK_LT(RegStorage::RegNum(reg2), 8);

784

uint8_t modrm = (3 << 6) | (RegStorage::RegNum(reg1) << 3) | RegStorage::RegNum(reg2);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

785

code_buffer_.push_back(modrm);

786

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

787

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

791

void X86Mir2Lir::EmitRegRegImmRev(const X86EncodingMap* entry,

792

uint8_t reg1, uint8_t reg2, int32_t imm) {

793

EmitRegRegImm(entry, reg2, reg1, imm);

794

}

795

796

void X86Mir2Lir::EmitRegMemImm(const X86EncodingMap* entry,

797

uint8_t reg, uint8_t base, int disp, int32_t imm) {

798

EmitPrefixAndOpcode(entry);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

799

DCHECK(!RegStorage::IsFloat(reg));

800

DCHECK_LT(RegStorage::RegNum(reg), 8);

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

801

EmitModrmDisp(reg, base, disp);

802

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

803

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Mark Mendell

2014-04-30 10:10:47 -0400

[diff] [blame]

807

void X86Mir2Lir::EmitMemRegImm(const X86EncodingMap* entry,

808

uint8_t base, int disp, uint8_t reg, int32_t imm) {

809

EmitRegMemImm(entry, reg, base, disp, imm);

810

}

811

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

812

void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

813

if (entry->skeleton.prefix1 != 0) {

814

code_buffer_.push_back(entry->skeleton.prefix1);

815

if (entry->skeleton.prefix2 != 0) {

816

code_buffer_.push_back(entry->skeleton.prefix2);

817

}

818

} else {

819

DCHECK_EQ(0, entry->skeleton.prefix2);

820

}

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

821

if (RegStorage::RegNum(reg) == rs_rAX.GetRegNum() && entry->skeleton.ax_opcode != 0) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

822

code_buffer_.push_back(entry->skeleton.ax_opcode);

823

} else {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

824

EmitOpcode(entry);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

825

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | RegStorage::RegNum(reg);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

826

code_buffer_.push_back(modrm);

827

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

828

EmitImm(entry, imm);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

829

}

830

Mark Mendell

343adb5

2013-12-18 06:02:17 -0800

[diff] [blame]

831

void X86Mir2Lir::EmitMemImm(const X86EncodingMap* entry, uint8_t base, int disp, int32_t imm) {

832

EmitPrefixAndOpcode(entry);

833

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

834

DCHECK_EQ(0, entry->skeleton.ax_opcode);

EmitImm(entry, imm);

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

838

void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int disp, int imm) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

839

EmitPrefixAndOpcode(entry);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

840

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rs_rBP.GetRegNum();

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

841

code_buffer_.push_back(modrm);

842

code_buffer_.push_back(disp & 0xFF);

843

code_buffer_.push_back((disp >> 8) & 0xFF);

844

code_buffer_.push_back((disp >> 16) & 0xFF);

845

code_buffer_.push_back((disp >> 24) & 0xFF);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

846

EmitImm(entry, imm);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

847

DCHECK_EQ(entry->skeleton.ax_opcode, 0);

848

}

849

850

void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

851

DCHECK_LT(RegStorage::RegNum(reg), 8);

852

code_buffer_.push_back(0xB8 + RegStorage::RegNum(reg));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

853

code_buffer_.push_back(imm & 0xFF);

854

code_buffer_.push_back((imm >> 8) & 0xFF);

855

code_buffer_.push_back((imm >> 16) & 0xFF);

856

code_buffer_.push_back((imm >> 24) & 0xFF);

857

}

858

859

void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

860

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

861

if (imm != 1) {

862

code_buffer_.push_back(entry->skeleton.opcode);

863

} else {

864

// Shorter encoding for 1 bit shift

865

code_buffer_.push_back(entry->skeleton.ax_opcode);

866

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

867

DCHECK_NE(0x0F, entry->skeleton.opcode);

868

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

869

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

870

if (RegStorage::RegNum(reg) >= 4) {

871

DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " "

872

<< static_cast<int>(RegStorage::RegNum(reg))

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

873

<< " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file);

874

}

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

875

DCHECK_LT(RegStorage::RegNum(reg), 8);

876

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | RegStorage::RegNum(reg);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

877

code_buffer_.push_back(modrm);

878

if (imm != 1) {

879

DCHECK_EQ(entry->skeleton.immediate_bytes, 1);

880

DCHECK(IS_SIMM8(imm));

881

code_buffer_.push_back(imm & 0xFF);

}

}

void X86Mir2Lir::EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl) {

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

886

DCHECK_EQ(cl, static_cast<uint8_t>(rs_rCX.GetReg()));

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

887

EmitPrefix(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

888

code_buffer_.push_back(entry->skeleton.opcode);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

889

DCHECK_NE(0x0F, entry->skeleton.opcode);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

890

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

891

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

892

DCHECK_LT(RegStorage::RegNum(reg), 8);

893

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | RegStorage::RegNum(reg);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

894

code_buffer_.push_back(modrm);

895

DCHECK_EQ(0, entry->skeleton.ax_opcode);

896

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

897

}

898

Mark Mendell

2014-01-28 12:59:49 -0800

[diff] [blame]

899

void X86Mir2Lir::EmitShiftMemCl(const X86EncodingMap* entry, uint8_t base,

900

int displacement, uint8_t cl) {

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

901

DCHECK_EQ(cl, static_cast<uint8_t>(rs_rCX.GetReg()));

Mark Mendell

2014-01-28 12:59:49 -0800

[diff] [blame]

902

EmitPrefix(entry);

903

code_buffer_.push_back(entry->skeleton.opcode);

904

DCHECK_NE(0x0F, entry->skeleton.opcode);

905

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

906

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

907

DCHECK_LT(RegStorage::RegNum(base), 8);

Mark Mendell

2014-01-28 12:59:49 -0800

[diff] [blame]

908

EmitModrmDisp(entry->skeleton.modrm_opcode, base, displacement);

909

DCHECK_EQ(0, entry->skeleton.ax_opcode);

910

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

911

}

912

Mark Mendell

2014-04-30 10:10:47 -0400

[diff] [blame]

913

void X86Mir2Lir::EmitShiftMemImm(const X86EncodingMap* entry, uint8_t base,

914

int displacement, int imm) {

915

EmitPrefix(entry);

916

if (imm != 1) {

917

code_buffer_.push_back(entry->skeleton.opcode);

918

} else {

919

// Shorter encoding for 1 bit shift

920

code_buffer_.push_back(entry->skeleton.ax_opcode);

921

}

922

DCHECK_NE(0x0F, entry->skeleton.opcode);

923

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

924

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

925

EmitModrmDisp(entry->skeleton.modrm_opcode, base, displacement);

926

if (imm != 1) {

927

DCHECK_EQ(entry->skeleton.immediate_bytes, 1);

928

DCHECK(IS_SIMM8(imm));

929

code_buffer_.push_back(imm & 0xFF);

}

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

933

void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition) {

934

if (entry->skeleton.prefix1 != 0) {

935

code_buffer_.push_back(entry->skeleton.prefix1);

936

if (entry->skeleton.prefix2 != 0) {

937

code_buffer_.push_back(entry->skeleton.prefix2);

938

}

939

} else {

940

DCHECK_EQ(0, entry->skeleton.prefix2);

941

}

942

DCHECK_EQ(0, entry->skeleton.ax_opcode);

943

DCHECK_EQ(0x0F, entry->skeleton.opcode);

944

code_buffer_.push_back(0x0F);

945

DCHECK_EQ(0x90, entry->skeleton.extra_opcode1);

946

code_buffer_.push_back(0x90 | condition);

947

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

948

DCHECK_LT(RegStorage::RegNum(reg), 8);

949

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | RegStorage::RegNum(reg);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

950

code_buffer_.push_back(modrm);

951

DCHECK_EQ(entry->skeleton.immediate_bytes, 0);

952

}

953

Mark Mendell

2014-04-30 10:10:47 -0400

[diff] [blame]

954

void X86Mir2Lir::EmitMemCond(const X86EncodingMap* entry, uint8_t base, int displacement, uint8_t condition) {

955

if (entry->skeleton.prefix1 != 0) {

956

code_buffer_.push_back(entry->skeleton.prefix1);

957

if (entry->skeleton.prefix2 != 0) {

958

code_buffer_.push_back(entry->skeleton.prefix2);

959

}

960

} else {

961

DCHECK_EQ(0, entry->skeleton.prefix2);

962

}

963

DCHECK_EQ(0, entry->skeleton.ax_opcode);

964

DCHECK_EQ(0x0F, entry->skeleton.opcode);

965

code_buffer_.push_back(0x0F);

966

DCHECK_EQ(0x90, entry->skeleton.extra_opcode1);

967

code_buffer_.push_back(0x90 | condition);

968

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

969

EmitModrmDisp(entry->skeleton.modrm_opcode, base, displacement);

970

DCHECK_EQ(entry->skeleton.immediate_bytes, 0);

971

}

972

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

973

void X86Mir2Lir::EmitRegRegCond(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2,

974

uint8_t condition) {

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

975

// Generate prefix and opcode without the condition

976

EmitPrefixAndOpcode(entry);

977

978

// Now add the condition. The last byte of opcode is the one that receives it.

979

DCHECK_LE(condition, 0xF);

980

code_buffer_.back() += condition;

981

982

// Not expecting to have to encode immediate or do anything special for ModR/M since there are two registers.

983

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

984

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

985

986

// Check that registers requested for encoding are sane.

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

987

DCHECK_LT(RegStorage::RegNum(reg1), 8);

988

DCHECK_LT(RegStorage::RegNum(reg2), 8);

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

989

990

// For register to register encoding, the mod is 3.

991

const uint8_t mod = (3 << 6);

992

993

// Encode the ModR/M byte now.

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

994

const uint8_t modrm = mod | (RegStorage::RegNum(reg1) << 3) | RegStorage::RegNum(reg2);

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

995

code_buffer_.push_back(modrm);

996

}

997

Mark Mendell

2014-04-30 10:10:47 -0400

[diff] [blame]

998

void X86Mir2Lir::EmitRegMemCond(const X86EncodingMap* entry, uint8_t reg1, uint8_t base, int displacement, uint8_t condition) {

999

// Generate prefix and opcode without the condition

1000

EmitPrefixAndOpcode(entry);

1001

1002

// Now add the condition. The last byte of opcode is the one that receives it.

1003

DCHECK_LE(condition, 0xF);

1004

code_buffer_.back() += condition;

1005

1006

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1007

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1008

1009

// Check that registers requested for encoding are sane.

DCHECK_LT(reg1, 8);

DCHECK_LT(base, 8);

EmitModrmDisp(reg1, base, displacement);

1014

}

1015

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1016

void X86Mir2Lir::EmitJmp(const X86EncodingMap* entry, int rel) {

1017

if (entry->opcode == kX86Jmp8) {

1018

DCHECK(IS_SIMM8(rel));

1019

code_buffer_.push_back(0xEB);

1020

code_buffer_.push_back(rel & 0xFF);

1021

} else if (entry->opcode == kX86Jmp32) {

1022

code_buffer_.push_back(0xE9);

1023

code_buffer_.push_back(rel & 0xFF);

1024

code_buffer_.push_back((rel >> 8) & 0xFF);

1025

code_buffer_.push_back((rel >> 16) & 0xFF);

1026

code_buffer_.push_back((rel >> 24) & 0xFF);

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

1027

} else if (entry->opcode == kX86Jecxz8) {

1028

DCHECK(IS_SIMM8(rel));

1029

code_buffer_.push_back(0xE3);

1030

code_buffer_.push_back(rel & 0xFF);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1031

} else {

1032

DCHECK(entry->opcode == kX86JmpR);

1033

code_buffer_.push_back(entry->skeleton.opcode);

1034

uint8_t reg = static_cast<uint8_t>(rel);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

1035

DCHECK_LT(RegStorage::RegNum(reg), 8);

1036

uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | RegStorage::RegNum(reg);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1037

code_buffer_.push_back(modrm);

}

}

void X86Mir2Lir::EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc) {

1042

DCHECK_LT(cc, 16);

1043

if (entry->opcode == kX86Jcc8) {

1044

DCHECK(IS_SIMM8(rel));

1045

code_buffer_.push_back(0x70 | cc);

1046

code_buffer_.push_back(rel & 0xFF);

1047

} else {

1048

DCHECK(entry->opcode == kX86Jcc32);

1049

code_buffer_.push_back(0x0F);

1050

code_buffer_.push_back(0x80 | cc);

1051

code_buffer_.push_back(rel & 0xFF);

1052

code_buffer_.push_back((rel >> 8) & 0xFF);

1053

code_buffer_.push_back((rel >> 16) & 0xFF);

1054

code_buffer_.push_back((rel >> 24) & 0xFF);

}

}

void X86Mir2Lir::EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp) {

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1059

EmitPrefixAndOpcode(entry);

1060

EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1061

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1062

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1063

}

1064

Mark Mendell

2014-02-06 11:02:52 -0800

[diff] [blame]

1065

void X86Mir2Lir::EmitCallImmediate(const X86EncodingMap* entry, int disp) {

1066

EmitPrefixAndOpcode(entry);

1067

DCHECK_EQ(4, entry->skeleton.immediate_bytes);

1068

code_buffer_.push_back(disp & 0xFF);

1069

code_buffer_.push_back((disp >> 8) & 0xFF);

1070

code_buffer_.push_back((disp >> 16) & 0xFF);

1071

code_buffer_.push_back((disp >> 24) & 0xFF);

1072

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1073

}

1074

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1075

void X86Mir2Lir::EmitCallThread(const X86EncodingMap* entry, int disp) {

1076

DCHECK_NE(entry->skeleton.prefix1, 0);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1077

EmitPrefixAndOpcode(entry);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

1078

uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rs_rBP.GetRegNum();

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1079

code_buffer_.push_back(modrm);

1080

code_buffer_.push_back(disp & 0xFF);

1081

code_buffer_.push_back((disp >> 8) & 0xFF);

1082

code_buffer_.push_back((disp >> 16) & 0xFF);

1083

code_buffer_.push_back((disp >> 24) & 0xFF);

1084

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1085

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1086

}

1087

1088

void X86Mir2Lir::EmitPcRel(const X86EncodingMap* entry, uint8_t reg,

1089

int base_or_table, uint8_t index, int scale, int table_or_disp) {

1090

int disp;

1091

if (entry->opcode == kX86PcRelLoadRA) {

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1092

Mir2Lir::EmbeddedData *tab_rec =

1093

reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(table_or_disp));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1094

disp = tab_rec->offset;

1095

} else {

1096

DCHECK(entry->opcode == kX86PcRelAdr);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1097

Mir2Lir::EmbeddedData *tab_rec =

1098

reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(base_or_table));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1099

disp = tab_rec->offset;

1100

}

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1101

EmitPrefix(entry);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

1102

DCHECK_LT(RegStorage::RegNum(reg), 8);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1103

if (entry->opcode == kX86PcRelLoadRA) {

1104

code_buffer_.push_back(entry->skeleton.opcode);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1105

DCHECK_NE(0x0F, entry->skeleton.opcode);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1106

DCHECK_EQ(0, entry->skeleton.extra_opcode1);

1107

DCHECK_EQ(0, entry->skeleton.extra_opcode2);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

1108

uint8_t modrm = (2 << 6) | (RegStorage::RegNum(reg) << 3) | rs_rX86_SP.GetRegNum();

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1109

code_buffer_.push_back(modrm);

1110

DCHECK_LT(scale, 4);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

1111

DCHECK_LT(RegStorage::RegNum(index), 8);

1112

DCHECK_LT(RegStorage::RegNum(base_or_table), 8);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1113

uint8_t base = static_cast<uint8_t>(base_or_table);

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

1114

uint8_t sib = (scale << 6) | (RegStorage::RegNum(index) << 3) | RegStorage::RegNum(base);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1115

code_buffer_.push_back(sib);

1116

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1117

} else {

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

1118

code_buffer_.push_back(entry->skeleton.opcode + RegStorage::RegNum(reg));

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1119

}

1120

code_buffer_.push_back(disp & 0xFF);

1121

code_buffer_.push_back((disp >> 8) & 0xFF);

1122

code_buffer_.push_back((disp >> 16) & 0xFF);

1123

code_buffer_.push_back((disp >> 24) & 0xFF);

1124

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1125

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1126

}

1127

1128

void X86Mir2Lir::EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset) {

1129

DCHECK(entry->opcode == kX86StartOfMethod) << entry->name;

1130

code_buffer_.push_back(0xE8); // call +0

1131

code_buffer_.push_back(0);

1132

code_buffer_.push_back(0);

1133

code_buffer_.push_back(0);

1134

code_buffer_.push_back(0);

1135

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

1136

DCHECK_LT(RegStorage::RegNum(reg), 8);

1137

code_buffer_.push_back(0x58 + RegStorage::RegNum(reg)); // pop reg

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1138

buzbee

2014-03-31 10:14:40 -0700

[diff] [blame]

1139

EmitRegImm(&X86Mir2Lir::EncodingMap[kX86Sub32RI], RegStorage::RegNum(reg),

1140

offset + 5 /* size of call +0 */);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1141

}

1142

1143

void X86Mir2Lir::EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) {

1144

UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " "

1145

<< BuildInsnString(entry->fmt, lir, 0);

1146

for (int i = 0; i < GetInsnSize(lir); ++i) {

1147

code_buffer_.push_back(0xCC); // push breakpoint instruction - int 3

}

}

/*

* Assemble the LIR into binary instruction format. Note that we may

1153

* discover that pc-relative displacements may not fit the selected

1154

* instruction. In those cases we will try to substitute a new code

1155

* sequence or request that the trace be shortened and retried.

1156

*/

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1157

AssemblerStatus X86Mir2Lir::AssembleInstructions(CodeOffset start_addr) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1158

LIR *lir;

1159

AssemblerStatus res = kSuccess; // Assume success

1160

1161

const bool kVerbosePcFixup = false;

1162

for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

1163

if (IsPseudoLirOp(lir->opcode)) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

continue;

}

if (lir->flags.is_nop) {

continue;

}

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1171

if (lir->flags.fixup != kFixupNone) {

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1172

switch (lir->opcode) {

1173

case kX86Jcc8: {

1174

LIR *target_lir = lir->target;

1175

DCHECK(target_lir != NULL);

1176

int delta = 0;

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1177

CodeOffset pc;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1178

if (IS_SIMM8(lir->operands[0])) {

1179

pc = lir->offset + 2 /* opcode + rel8 */;

1180

} else {

1181

pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1182

}

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1183

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1184

delta = target - pc;

1185

if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

1186

if (kVerbosePcFixup) {

1187

LOG(INFO) << "Retry for JCC growth at " << lir->offset

1188

<< " delta: " << delta << " old delta: " << lir->operands[0];

1189

}

1190

lir->opcode = kX86Jcc32;

1191

SetupResourceMasks(lir);

1192

res = kRetryAll;

1193

}

1194

if (kVerbosePcFixup) {

1195

LOG(INFO) << "Source:";

1196

DumpLIRInsn(lir, 0);

1197

LOG(INFO) << "Target:";

1198

DumpLIRInsn(target_lir, 0);

1199

LOG(INFO) << "Delta " << delta;

1200

}

1201

lir->operands[0] = delta;

break;

}

case kX86Jcc32: {

LIR *target_lir = lir->target;

1206

DCHECK(target_lir != NULL);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1207

CodeOffset pc = lir->offset + 6 /* 2 byte opcode + rel32 */;

1208

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1209

int delta = target - pc;

1210

if (kVerbosePcFixup) {

1211

LOG(INFO) << "Source:";

1212

DumpLIRInsn(lir, 0);

1213

LOG(INFO) << "Target:";

1214

DumpLIRInsn(target_lir, 0);

1215

LOG(INFO) << "Delta " << delta;

1216

}

1217

lir->operands[0] = delta;

1218

break;

1219

}

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

1220

case kX86Jecxz8: {

1221

LIR *target_lir = lir->target;

1222

DCHECK(target_lir != NULL);

1223

CodeOffset pc;

1224

pc = lir->offset + 2; // opcode + rel8

1225

CodeOffset target = target_lir->offset;

1226

int delta = target - pc;

1227

lir->operands[0] = delta;

1228

DCHECK(IS_SIMM8(delta));

1229

break;

1230

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1231

case kX86Jmp8: {

1232

LIR *target_lir = lir->target;

1233

DCHECK(target_lir != NULL);

1234

int delta = 0;

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1235

CodeOffset pc;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1236

if (IS_SIMM8(lir->operands[0])) {

1237

pc = lir->offset + 2 /* opcode + rel8 */;

1238

} else {

1239

pc = lir->offset + 5 /* opcode + rel32 */;

1240

}

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1241

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1242

delta = target - pc;

1243

if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && delta == 0) {

1244

// Useless branch

buzbee

252254b

2013-09-08 16:20:53 -0700

[diff] [blame]

1245

NopLIR(lir);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1246

if (kVerbosePcFixup) {

1247

LOG(INFO) << "Retry for useless branch at " << lir->offset;

1248

}

1249

res = kRetryAll;

1250

} else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {

1251

if (kVerbosePcFixup) {

1252

LOG(INFO) << "Retry for JMP growth at " << lir->offset;

1253

}

1254

lir->opcode = kX86Jmp32;

1255

SetupResourceMasks(lir);

1256

res = kRetryAll;

1257

}

1258

lir->operands[0] = delta;

break;

}

case kX86Jmp32: {

LIR *target_lir = lir->target;

1263

DCHECK(target_lir != NULL);

buzbee

2013-10-11 15:24:55 -0700

[diff] [blame]

1264

CodeOffset pc = lir->offset + 5 /* opcode + rel32 */;

1265

CodeOffset target = target_lir->offset;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1266

int delta = target - pc;

1267

lir->operands[0] = delta;

1268

break;

1269

}

1270

default:

Mark Mendell

67c39c4

2014-01-31 17:28:00 -0800

[diff] [blame]

1271

if (lir->flags.fixup == kFixupLoad) {

1272

LIR *target_lir = lir->target;

1273

DCHECK(target_lir != NULL);

1274

CodeOffset target = target_lir->offset;

1275

lir->operands[2] = target;

1276

int newSize = GetInsnSize(lir);

1277

if (newSize != lir->flags.size) {

1278

lir->flags.size = newSize;

1279

res = kRetryAll;

1280

}

1281

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

break;

}

}

/*

* If one of the pc-relative instructions expanded we'll have

1288

* to make another pass. Don't bother to fully assemble the

1289

* instruction.

1290

*/

1291

if (res != kSuccess) {

1292

continue;

1293

}

1294

CHECK_EQ(static_cast<size_t>(lir->offset), code_buffer_.size());

1295

const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode];

1296

size_t starting_cbuf_size = code_buffer_.size();

1297

switch (entry->kind) {

1298

case kData: // 4 bytes of data

1299

code_buffer_.push_back(lir->operands[0]);

1300

break;

1301

case kNullary: // 1 byte of opcode

1302

DCHECK_EQ(0, entry->skeleton.prefix1);

1303

DCHECK_EQ(0, entry->skeleton.prefix2);

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1304

EmitOpcode(entry);

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1305

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1306

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1307

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1308

break;

Mark Mendell

2014-02-19 20:06:20 -0800

[diff] [blame]

1309

case kPrefix2Nullary: // 1 byte of opcode + 2 prefixes.

1310

DCHECK_NE(0, entry->skeleton.prefix1);

1311

DCHECK_NE(0, entry->skeleton.prefix2);

1312

EmitPrefixAndOpcode(entry);

1313

DCHECK_EQ(0, entry->skeleton.modrm_opcode);

1314

DCHECK_EQ(0, entry->skeleton.ax_opcode);

1315

DCHECK_EQ(0, entry->skeleton.immediate_bytes);

1316

break;

Vladimir Marko

a8b4caf

2013-10-24 15:08:57 +0100

[diff] [blame]

1317

case kRegOpcode: // lir operands - 0: reg

1318

EmitOpRegOpcode(entry, lir->operands[0]);

1319

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1320

case kReg: // lir operands - 0: reg

1321

EmitOpReg(entry, lir->operands[0]);

1322

break;

1323

case kMem: // lir operands - 0: base, 1: disp

1324

EmitOpMem(entry, lir->operands[0], lir->operands[1]);

1325

break;

Vladimir Marko

2013-12-03 15:20:45 +0000

[diff] [blame]

1326

case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp

1327

EmitOpArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3]);

1328

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1329

case kMemReg: // lir operands - 0: base, 1: disp, 2: reg

1330

EmitMemReg(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1331

break;

Mark Mendell

343adb5

2013-12-18 06:02:17 -0800

[diff] [blame]

1332

case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate

1333

EmitMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1334

break;

Mark Mendell

2014-04-30 10:10:47 -0400

[diff] [blame]

1335

case kArrayImm: // lir operands - 0: base, 1: index, 2: disp, 3:scale, 4:immediate

1336

EmitArrayImm(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1337

lir->operands[3], lir->operands[4]);

1338

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1339

case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg

1340

EmitArrayReg(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1341

lir->operands[3], lir->operands[4]);

1342

break;

1343

case kRegMem: // lir operands - 0: reg, 1: base, 2: disp

1344

EmitRegMem(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1345

break;

1346

case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp

1347

EmitRegArray(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1348

lir->operands[3], lir->operands[4]);

1349

break;

1350

case kRegThread: // lir operands - 0: reg, 1: disp

1351

EmitRegThread(entry, lir->operands[0], lir->operands[1]);

1352

break;

1353

case kRegReg: // lir operands - 0: reg1, 1: reg2

1354

EmitRegReg(entry, lir->operands[0], lir->operands[1]);

1355

break;

1356

case kRegRegStore: // lir operands - 0: reg2, 1: reg1

1357

EmitRegReg(entry, lir->operands[1], lir->operands[0]);

1358

break;

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

1359

case kRegRegImmRev:

1360

EmitRegRegImmRev(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1361

break;

Mark Mendell

2014-04-30 10:10:47 -0400

[diff] [blame]

1362

case kMemRegImm:

1363

EmitMemRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1364

lir->operands[3]);

1365

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1366

case kRegRegImm:

1367

EmitRegRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1368

break;

Mark Mendell

2014-01-22 09:05:18 -0800

[diff] [blame]

1369

case kRegMemImm:

1370

EmitRegMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1371

lir->operands[3]);

1372

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1373

case kRegImm: // lir operands - 0: reg, 1: immediate

1374

EmitRegImm(entry, lir->operands[0], lir->operands[1]);

1375

break;

1376

case kThreadImm: // lir operands - 0: disp, 1: immediate

1377

EmitThreadImm(entry, lir->operands[0], lir->operands[1]);

1378

break;

1379

case kMovRegImm: // lir operands - 0: reg, 1: immediate

1380

EmitMovRegImm(entry, lir->operands[0], lir->operands[1]);

1381

break;

1382

case kShiftRegImm: // lir operands - 0: reg, 1: immediate

1383

EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]);

1384

break;

Mark Mendell

2014-04-30 10:10:47 -0400

[diff] [blame]

1385

case kShiftMemImm: // lir operands - 0: base, 1: disp, 2:immediate

1386

EmitShiftMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1387

break;

Brian Carlstrom

7934ac2

2013-07-26 10:54:15 -0700

[diff] [blame]

1388

case kShiftRegCl: // lir operands - 0: reg, 1: cl

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1389

EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]);

1390

break;

Mark Mendell

2014-01-28 12:59:49 -0800

[diff] [blame]

1391

case kShiftMemCl: // lir operands - 0: base, 1:displacement, 2: cl

1392

EmitShiftMemCl(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1393

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1394

case kRegCond: // lir operands - 0: reg, 1: condition

1395

EmitRegCond(entry, lir->operands[0], lir->operands[1]);

1396

break;

Mark Mendell

2014-04-30 10:10:47 -0400

[diff] [blame]

1397

case kMemCond: // lir operands - 0: base, 1: displacement, 2: condition

1398

EmitMemCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1399

break;

Razvan A Lupusoru

2013-12-20 17:27:23 -0800

[diff] [blame]

1400

case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: condition

1401

EmitRegRegCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]);

1402

break;

Mark Mendell

2014-04-30 10:10:47 -0400

[diff] [blame]

1403

case kRegMemCond: // lir operands - 0: reg, 1: reg, displacement, 3: condition

1404

EmitRegMemCond(entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3]);

1405

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1406

case kJmp: // lir operands - 0: rel

Brian Carlstrom

60d7a65

2014-03-13 18:10:08 -0700

[diff] [blame]

1407

if (entry->opcode == kX86JmpT) {

1408

// This works since the instruction format for jmp and call is basically the same and

1409

// EmitCallThread loads opcode info.

1410

EmitCallThread(entry, lir->operands[0]);

1411

} else {

1412

EmitJmp(entry, lir->operands[0]);

1413

}

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1414

break;

1415

case kJcc: // lir operands - 0: rel, 1: CC, target assigned

1416

EmitJcc(entry, lir->operands[0], lir->operands[1]);

1417

break;

1418

case kCall:

1419

switch (entry->opcode) {

Mark Mendell

2014-02-06 11:02:52 -0800

[diff] [blame]

1420

case kX86CallI: // lir operands - 0: disp

1421

EmitCallImmediate(entry, lir->operands[0]);

1422

break;

Brian Carlstrom

2013-07-12 13:46:57 -0700

[diff] [blame]

1423

case kX86CallM: // lir operands - 0: base, 1: disp

1424

EmitCallMem(entry, lir->operands[0], lir->operands[1]);

1425

break;

1426

case kX86CallT: // lir operands - 0: disp

1427

EmitCallThread(entry, lir->operands[0]);

1428

break;

1429

default:

1430

EmitUnimplemented(entry, lir);

break;

}

break;

case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table

1435

EmitPcRel(entry, lir->operands[0], lir->operands[1], lir->operands[2],

1436

lir->operands[3], lir->operands[4]);

1437

break;

1438

case kMacro:

1439

EmitMacro(entry, lir->operands[0], lir->offset);

1440

break;

1441

default:

1442

EmitUnimplemented(entry, lir);

1443

break;

1444

}

1445

CHECK_EQ(static_cast<size_t>(GetInsnSize(lir)),

1446

code_buffer_.size() - starting_cbuf_size)

1447

<< "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name;

}

return res;

}

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1452

// LIR offset assignment.

1453

// TODO: consolidate w/ Arm assembly mechanism.

1454

int X86Mir2Lir::AssignInsnOffsets() {

LIR* lir;

int offset = 0;

for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) {

1459

lir->offset = offset;

buzbee

409fe94

2013-10-11 10:49:56 -0700

[diff] [blame]

1460

if (LIKELY(!IsPseudoLirOp(lir->opcode))) {

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1461

if (!lir->flags.is_nop) {

1462

offset += lir->flags.size;

1463

}

1464

} else if (UNLIKELY(lir->opcode == kPseudoPseudoAlign4)) {

1465

if (offset & 0x2) {

1466

offset += 2;

1467

lir->operands[0] = 1;

1468

} else {

1469

lir->operands[0] = 0;

1470

}

1471

}

1472

/* Pseudo opcodes don't consume space */

}

return offset;

}

/*

* Walk the compilation unit and assign offsets to instructions

1479

* and literals and compute the total size of the compiled unit.

1480

* TODO: consolidate w/ Arm assembly mechanism.

1481

*/

1482

void X86Mir2Lir::AssignOffsets() {

1483

int offset = AssignInsnOffsets();

1484

1485

/* Const values have to be word aligned */

Andreas Gampe

6601882

2014-05-05 20:47:19 -0700

[diff] [blame]

1486

offset = RoundUp(offset, 4);

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1487

1488

/* Set up offsets for literals */

1489

data_offset_ = offset;

1490

1491

offset = AssignLiteralOffset(offset);

1492

1493

offset = AssignSwitchTablesOffset(offset);

1494

1495

offset = AssignFillArrayDataOffset(offset);

1496

1497

total_size_ = offset;

}

/*

* Go over each instruction in the list and calculate the offset from the top

1502

* before sending them off to the assembler. If out-of-range branch distance is

1503

* seen rearrange the instructions a bit to correct it.

1504

* TODO: consolidate w/ Arm assembly mechanism.

1505

*/

1506

void X86Mir2Lir::AssembleLIR() {

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1507

cu_->NewTimingSplit("Assemble");

Mark Mendell

2014-02-06 11:02:52 -0800

[diff] [blame]

1508

1509

// We will remove the method address if we never ended up using it

1510

if (store_method_addr_ && !store_method_addr_used_) {

1511

setup_method_address_[0]->flags.is_nop = true;

1512

setup_method_address_[1]->flags.is_nop = true;

1513

}

1514

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1515

AssignOffsets();

1516

int assembler_retries = 0;

1517

/*

1518

* Assemble here. Note that we generate code with optimistic assumptions

1519

* and if found now to work, we'll have to redo the sequence and retry.

*/

while (true) {

AssemblerStatus res = AssembleInstructions(0);

1524

if (res == kSuccess) {

break;

} else {

assembler_retries++;

if (assembler_retries > MAX_ASSEMBLER_RETRIES) {

1529

CodegenDump();

1530

LOG(FATAL) << "Assembler error - too many retries";

1531

}

1532

// Redo offsets and try again

1533

AssignOffsets();

1534

code_buffer_.clear();

}

}

// Install literals

InstallLiteralPools();

1540

1541

// Install switch tables

1542

InstallSwitchTables();

1543

1544

// Install fill array data

1545

InstallFillArrayData();

1546

1547

// Create the mapping table and native offset to reference map.

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1548

cu_->NewTimingSplit("PcMappingTable");

buzbee

2013-09-14 16:15:25 -0700

[diff] [blame]

1549

CreateMappingTables();

1550

buzbee

a61f495

2013-08-23 14:27:06 -0700

[diff] [blame]

1551

cu_->NewTimingSplit("GcMap");

buzbee