Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "arm64_lir.h" |
| 18 | #include "codegen_arm64.h" |
| 19 | #include "dex/quick/mir_to_lir-inl.h" |
| 20 | |
| 21 | namespace art { |
| 22 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 23 | /* This file contains codegen for the A64 ISA. */ |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 24 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 25 | static int32_t EncodeImmSingle(uint32_t bits) { |
| 26 | /* |
| 27 | * Valid values will have the form: |
| 28 | * |
| 29 | * aBbb.bbbc.defg.h000.0000.0000.0000.0000 |
| 30 | * |
| 31 | * where B = not(b). In other words, if b == 1, then B == 0 and viceversa. |
| 32 | */ |
| 33 | |
| 34 | // bits[19..0] are cleared. |
| 35 | if ((bits & 0x0007ffff) != 0) |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 36 | return -1; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 37 | |
| 38 | // bits[29..25] are all set or all cleared. |
| 39 | uint32_t b_pattern = (bits >> 16) & 0x3e00; |
| 40 | if (b_pattern != 0 && b_pattern != 0x3e00) |
| 41 | return -1; |
| 42 | |
| 43 | // bit[30] and bit[29] are opposite. |
| 44 | if (((bits ^ (bits << 1)) & 0x40000000) == 0) |
| 45 | return -1; |
| 46 | |
| 47 | // bits: aBbb.bbbc.defg.h000.0000.0000.0000.0000 |
| 48 | // bit7: a000.0000 |
| 49 | uint32_t bit7 = ((bits >> 31) & 0x1) << 7; |
| 50 | // bit6: 0b00.0000 |
| 51 | uint32_t bit6 = ((bits >> 29) & 0x1) << 6; |
| 52 | // bit5_to_0: 00cd.efgh |
| 53 | uint32_t bit5_to_0 = (bits >> 19) & 0x3f; |
| 54 | return (bit7 | bit6 | bit5_to_0); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 55 | } |
| 56 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 57 | static int32_t EncodeImmDouble(uint64_t bits) { |
| 58 | /* |
| 59 | * Valid values will have the form: |
| 60 | * |
| 61 | * aBbb.bbbb.bbcd.efgh.0000.0000.0000.0000 |
| 62 | * 0000.0000.0000.0000.0000.0000.0000.0000 |
| 63 | * |
| 64 | * where B = not(b). |
| 65 | */ |
| 66 | |
| 67 | // bits[47..0] are cleared. |
| 68 | if ((bits & UINT64_C(0xffffffffffff)) != 0) |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 69 | return -1; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 70 | |
| 71 | // bits[61..54] are all set or all cleared. |
| 72 | uint32_t b_pattern = (bits >> 48) & 0x3fc0; |
| 73 | if (b_pattern != 0 && b_pattern != 0x3fc0) |
| 74 | return -1; |
| 75 | |
| 76 | // bit[62] and bit[61] are opposite. |
| 77 | if (((bits ^ (bits << 1)) & UINT64_C(0x4000000000000000)) == 0) |
| 78 | return -1; |
| 79 | |
| 80 | // bit7: a000.0000 |
| 81 | uint32_t bit7 = ((bits >> 63) & 0x1) << 7; |
| 82 | // bit6: 0b00.0000 |
| 83 | uint32_t bit6 = ((bits >> 61) & 0x1) << 6; |
| 84 | // bit5_to_0: 00cd.efgh |
| 85 | uint32_t bit5_to_0 = (bits >> 48) & 0x3f; |
| 86 | return (bit7 | bit6 | bit5_to_0); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 87 | } |
| 88 | |
Matteo Franchin | c41e6dc | 2014-06-13 19:16:28 +0100 | [diff] [blame] | 89 | LIR* Arm64Mir2Lir::LoadFPConstantValue(RegStorage r_dest, int32_t value) { |
| 90 | DCHECK(r_dest.IsSingle()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 91 | if (value == 0) { |
Matteo Franchin | c41e6dc | 2014-06-13 19:16:28 +0100 | [diff] [blame] | 92 | return NewLIR2(kA64Fmov2sw, r_dest.GetReg(), rwzr); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 93 | } else { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 94 | int32_t encoded_imm = EncodeImmSingle((uint32_t)value); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 95 | if (encoded_imm >= 0) { |
Matteo Franchin | c41e6dc | 2014-06-13 19:16:28 +0100 | [diff] [blame] | 96 | return NewLIR2(kA64Fmov2fI, r_dest.GetReg(), encoded_imm); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 97 | } |
| 98 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 99 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 100 | LIR* data_target = ScanLiteralPool(literal_list_, value, 0); |
| 101 | if (data_target == NULL) { |
| 102 | data_target = AddWordData(&literal_list_, value); |
| 103 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 104 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 105 | ScopedMemRefType mem_ref_type(this, ResourceMask::kLiteral); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 106 | LIR* load_pc_rel = RawLIR(current_dalvik_offset_, kA64Ldr2fp, |
Matteo Franchin | c41e6dc | 2014-06-13 19:16:28 +0100 | [diff] [blame] | 107 | r_dest.GetReg(), 0, 0, 0, 0, data_target); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 108 | AppendLIR(load_pc_rel); |
| 109 | return load_pc_rel; |
| 110 | } |
| 111 | |
Matteo Franchin | c41e6dc | 2014-06-13 19:16:28 +0100 | [diff] [blame] | 112 | LIR* Arm64Mir2Lir::LoadFPConstantValueWide(RegStorage r_dest, int64_t value) { |
| 113 | DCHECK(r_dest.IsDouble()); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 114 | if (value == 0) { |
Matteo Franchin | c41e6dc | 2014-06-13 19:16:28 +0100 | [diff] [blame] | 115 | return NewLIR2(kA64Fmov2Sx, r_dest.GetReg(), rxzr); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 116 | } else { |
| 117 | int32_t encoded_imm = EncodeImmDouble(value); |
| 118 | if (encoded_imm >= 0) { |
Matteo Franchin | c41e6dc | 2014-06-13 19:16:28 +0100 | [diff] [blame] | 119 | return NewLIR2(FWIDE(kA64Fmov2fI), r_dest.GetReg(), encoded_imm); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 120 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 121 | } |
| 122 | |
| 123 | // No short form - load from the literal pool. |
| 124 | int32_t val_lo = Low32Bits(value); |
| 125 | int32_t val_hi = High32Bits(value); |
| 126 | LIR* data_target = ScanLiteralPoolWide(literal_list_, val_lo, val_hi); |
| 127 | if (data_target == NULL) { |
| 128 | data_target = AddWideData(&literal_list_, val_lo, val_hi); |
| 129 | } |
| 130 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 131 | ScopedMemRefType mem_ref_type(this, ResourceMask::kLiteral); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 132 | LIR* load_pc_rel = RawLIR(current_dalvik_offset_, FWIDE(kA64Ldr2fp), |
Matteo Franchin | c41e6dc | 2014-06-13 19:16:28 +0100 | [diff] [blame] | 133 | r_dest.GetReg(), 0, 0, 0, 0, data_target); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 134 | AppendLIR(load_pc_rel); |
| 135 | return load_pc_rel; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 136 | } |
| 137 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 138 | static int CountLeadingZeros(bool is_wide, uint64_t value) { |
Matteo Franchin | c41e6dc | 2014-06-13 19:16:28 +0100 | [diff] [blame] | 139 | return (is_wide) ? __builtin_clzll(value) : __builtin_clz((uint32_t)value); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 140 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 141 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 142 | static int CountTrailingZeros(bool is_wide, uint64_t value) { |
Matteo Franchin | c41e6dc | 2014-06-13 19:16:28 +0100 | [diff] [blame] | 143 | return (is_wide) ? __builtin_ctzll(value) : __builtin_ctz((uint32_t)value); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 144 | } |
| 145 | |
| 146 | static int CountSetBits(bool is_wide, uint64_t value) { |
| 147 | return ((is_wide) ? |
Zheng Xu | e2eb29e | 2014-06-12 10:22:33 +0800 | [diff] [blame] | 148 | __builtin_popcountll(value) : __builtin_popcount((uint32_t)value)); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 149 | } |
| 150 | |
| 151 | /** |
| 152 | * @brief Try encoding an immediate in the form required by logical instructions. |
| 153 | * |
| 154 | * @param is_wide Whether @p value is a 64-bit (as opposed to 32-bit) value. |
| 155 | * @param value An integer to be encoded. This is interpreted as 64-bit if @p is_wide is true and as |
| 156 | * 32-bit if @p is_wide is false. |
| 157 | * @return A non-negative integer containing the encoded immediate or -1 if the encoding failed. |
| 158 | * @note This is the inverse of Arm64Mir2Lir::DecodeLogicalImmediate(). |
| 159 | */ |
| 160 | int Arm64Mir2Lir::EncodeLogicalImmediate(bool is_wide, uint64_t value) { |
| 161 | unsigned n, imm_s, imm_r; |
| 162 | |
| 163 | // Logical immediates are encoded using parameters n, imm_s and imm_r using |
| 164 | // the following table: |
| 165 | // |
| 166 | // N imms immr size S R |
| 167 | // 1 ssssss rrrrrr 64 UInt(ssssss) UInt(rrrrrr) |
| 168 | // 0 0sssss xrrrrr 32 UInt(sssss) UInt(rrrrr) |
| 169 | // 0 10ssss xxrrrr 16 UInt(ssss) UInt(rrrr) |
| 170 | // 0 110sss xxxrrr 8 UInt(sss) UInt(rrr) |
| 171 | // 0 1110ss xxxxrr 4 UInt(ss) UInt(rr) |
| 172 | // 0 11110s xxxxxr 2 UInt(s) UInt(r) |
| 173 | // (s bits must not be all set) |
| 174 | // |
| 175 | // A pattern is constructed of size bits, where the least significant S+1 |
| 176 | // bits are set. The pattern is rotated right by R, and repeated across a |
| 177 | // 32 or 64-bit value, depending on destination register width. |
| 178 | // |
| 179 | // To test if an arbitary immediate can be encoded using this scheme, an |
| 180 | // iterative algorithm is used. |
| 181 | // |
| 182 | |
| 183 | // 1. If the value has all set or all clear bits, it can't be encoded. |
| 184 | if (value == 0 || value == ~UINT64_C(0) || |
| 185 | (!is_wide && (uint32_t)value == ~UINT32_C(0))) { |
| 186 | return -1; |
| 187 | } |
| 188 | |
| 189 | unsigned lead_zero = CountLeadingZeros(is_wide, value); |
| 190 | unsigned lead_one = CountLeadingZeros(is_wide, ~value); |
| 191 | unsigned trail_zero = CountTrailingZeros(is_wide, value); |
| 192 | unsigned trail_one = CountTrailingZeros(is_wide, ~value); |
| 193 | unsigned set_bits = CountSetBits(is_wide, value); |
| 194 | |
| 195 | // The fixed bits in the immediate s field. |
| 196 | // If width == 64 (X reg), start at 0xFFFFFF80. |
| 197 | // If width == 32 (W reg), start at 0xFFFFFFC0, as the iteration for 64-bit |
| 198 | // widths won't be executed. |
| 199 | unsigned width = (is_wide) ? 64 : 32; |
| 200 | int imm_s_fixed = (is_wide) ? -128 : -64; |
| 201 | int imm_s_mask = 0x3f; |
| 202 | |
| 203 | for (;;) { |
| 204 | // 2. If the value is two bits wide, it can be encoded. |
| 205 | if (width == 2) { |
| 206 | n = 0; |
| 207 | imm_s = 0x3C; |
| 208 | imm_r = (value & 3) - 1; |
| 209 | break; |
| 210 | } |
| 211 | |
| 212 | n = (width == 64) ? 1 : 0; |
| 213 | imm_s = ((imm_s_fixed | (set_bits - 1)) & imm_s_mask); |
| 214 | if ((lead_zero + set_bits) == width) { |
| 215 | imm_r = 0; |
| 216 | } else { |
| 217 | imm_r = (lead_zero > 0) ? (width - trail_zero) : lead_one; |
| 218 | } |
| 219 | |
| 220 | // 3. If the sum of leading zeros, trailing zeros and set bits is |
| 221 | // equal to the bit width of the value, it can be encoded. |
| 222 | if (lead_zero + trail_zero + set_bits == width) { |
| 223 | break; |
| 224 | } |
| 225 | |
| 226 | // 4. If the sum of leading ones, trailing ones and unset bits in the |
| 227 | // value is equal to the bit width of the value, it can be encoded. |
| 228 | if (lead_one + trail_one + (width - set_bits) == width) { |
| 229 | break; |
| 230 | } |
| 231 | |
| 232 | // 5. If the most-significant half of the bitwise value is equal to |
| 233 | // the least-significant half, return to step 2 using the |
| 234 | // least-significant half of the value. |
| 235 | uint64_t mask = (UINT64_C(1) << (width >> 1)) - 1; |
| 236 | if ((value & mask) == ((value >> (width >> 1)) & mask)) { |
| 237 | width >>= 1; |
| 238 | set_bits >>= 1; |
| 239 | imm_s_fixed >>= 1; |
| 240 | continue; |
| 241 | } |
| 242 | |
| 243 | // 6. Otherwise, the value can't be encoded. |
| 244 | return -1; |
| 245 | } |
| 246 | |
| 247 | return (n << 12 | imm_r << 6 | imm_s); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 248 | } |
| 249 | |
| 250 | bool Arm64Mir2Lir::InexpensiveConstantInt(int32_t value) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 251 | return false; // (ModifiedImmediate(value) >= 0) || (ModifiedImmediate(~value) >= 0); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 252 | } |
| 253 | |
| 254 | bool Arm64Mir2Lir::InexpensiveConstantFloat(int32_t value) { |
| 255 | return EncodeImmSingle(value) >= 0; |
| 256 | } |
| 257 | |
| 258 | bool Arm64Mir2Lir::InexpensiveConstantLong(int64_t value) { |
| 259 | return InexpensiveConstantInt(High32Bits(value)) && InexpensiveConstantInt(Low32Bits(value)); |
| 260 | } |
| 261 | |
| 262 | bool Arm64Mir2Lir::InexpensiveConstantDouble(int64_t value) { |
| 263 | return EncodeImmDouble(value) >= 0; |
| 264 | } |
| 265 | |
| 266 | /* |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 267 | * Load a immediate using one single instruction when possible; otherwise |
| 268 | * use a pair of movz and movk instructions. |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 269 | * |
| 270 | * No additional register clobbering operation performed. Use this version when |
| 271 | * 1) r_dest is freshly returned from AllocTemp or |
| 272 | * 2) The codegen is under fixed register usage |
| 273 | */ |
| 274 | LIR* Arm64Mir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) { |
| 275 | LIR* res; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 276 | |
| 277 | if (r_dest.IsFloat()) { |
Matteo Franchin | c41e6dc | 2014-06-13 19:16:28 +0100 | [diff] [blame] | 278 | return LoadFPConstantValue(r_dest, value); |
| 279 | } |
| 280 | |
| 281 | if (r_dest.Is64Bit()) { |
| 282 | return LoadConstantWide(r_dest, value); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 283 | } |
| 284 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 285 | // Loading SP/ZR with an immediate is not supported. |
Matteo Franchin | c41e6dc | 2014-06-13 19:16:28 +0100 | [diff] [blame] | 286 | DCHECK(!A64_REG_IS_SP(r_dest.GetReg())); |
| 287 | DCHECK(!A64_REG_IS_ZR(r_dest.GetReg())); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 288 | |
| 289 | // Compute how many movk, movz instructions are needed to load the value. |
| 290 | uint16_t high_bits = High16Bits(value); |
| 291 | uint16_t low_bits = Low16Bits(value); |
| 292 | |
| 293 | bool low_fast = ((uint16_t)(low_bits + 1) <= 1); |
| 294 | bool high_fast = ((uint16_t)(high_bits + 1) <= 1); |
| 295 | |
| 296 | if (LIKELY(low_fast || high_fast)) { |
| 297 | // 1 instruction is enough to load the immediate. |
| 298 | if (LIKELY(low_bits == high_bits)) { |
| 299 | // Value is either 0 or -1: we can just use wzr. |
| 300 | ArmOpcode opcode = LIKELY(low_bits == 0) ? kA64Mov2rr : kA64Mvn2rr; |
| 301 | res = NewLIR2(opcode, r_dest.GetReg(), rwzr); |
| 302 | } else { |
| 303 | uint16_t uniform_bits, useful_bits; |
| 304 | int shift; |
| 305 | |
| 306 | if (LIKELY(high_fast)) { |
| 307 | shift = 0; |
| 308 | uniform_bits = high_bits; |
| 309 | useful_bits = low_bits; |
| 310 | } else { |
| 311 | shift = 1; |
| 312 | uniform_bits = low_bits; |
| 313 | useful_bits = high_bits; |
| 314 | } |
| 315 | |
| 316 | if (UNLIKELY(uniform_bits != 0)) { |
| 317 | res = NewLIR3(kA64Movn3rdM, r_dest.GetReg(), ~useful_bits, shift); |
| 318 | } else { |
| 319 | res = NewLIR3(kA64Movz3rdM, r_dest.GetReg(), useful_bits, shift); |
| 320 | } |
| 321 | } |
| 322 | } else { |
| 323 | // movk, movz require 2 instructions. Try detecting logical immediates. |
| 324 | int log_imm = EncodeLogicalImmediate(/*is_wide=*/false, value); |
| 325 | if (log_imm >= 0) { |
| 326 | res = NewLIR3(kA64Orr3Rrl, r_dest.GetReg(), rwzr, log_imm); |
| 327 | } else { |
| 328 | // Use 2 instructions. |
| 329 | res = NewLIR3(kA64Movz3rdM, r_dest.GetReg(), low_bits, 0); |
| 330 | NewLIR3(kA64Movk3rdM, r_dest.GetReg(), high_bits, 1); |
| 331 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 332 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 333 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 334 | return res; |
| 335 | } |
| 336 | |
Matteo Franchin | c41e6dc | 2014-06-13 19:16:28 +0100 | [diff] [blame] | 337 | // TODO: clean up the names. LoadConstantWide() should really be LoadConstantNoClobberWide(). |
| 338 | LIR* Arm64Mir2Lir::LoadConstantWide(RegStorage r_dest, int64_t value) { |
| 339 | // Maximum number of instructions to use for encoding the immediate. |
| 340 | const int max_num_ops = 2; |
| 341 | |
| 342 | if (r_dest.IsFloat()) { |
| 343 | return LoadFPConstantValueWide(r_dest, value); |
| 344 | } |
| 345 | |
| 346 | DCHECK(r_dest.Is64Bit()); |
| 347 | |
| 348 | // Loading SP/ZR with an immediate is not supported. |
| 349 | DCHECK(!A64_REG_IS_SP(r_dest.GetReg())); |
| 350 | DCHECK(!A64_REG_IS_ZR(r_dest.GetReg())); |
| 351 | |
| 352 | if (LIKELY(value == INT64_C(0) || value == INT64_C(-1))) { |
| 353 | // value is either 0 or -1: we can just use xzr. |
| 354 | ArmOpcode opcode = LIKELY(value == 0) ? WIDE(kA64Mov2rr) : WIDE(kA64Mvn2rr); |
| 355 | return NewLIR2(opcode, r_dest.GetReg(), rxzr); |
| 356 | } |
| 357 | |
| 358 | // At least one in value's halfwords is not 0x0, nor 0xffff: find out how many. |
| 359 | int num_0000_halfwords = 0; |
| 360 | int num_ffff_halfwords = 0; |
| 361 | uint64_t uvalue = static_cast<uint64_t>(value); |
| 362 | for (int shift = 0; shift < 64; shift += 16) { |
| 363 | uint16_t halfword = static_cast<uint16_t>(uvalue >> shift); |
| 364 | if (halfword == 0) |
| 365 | num_0000_halfwords++; |
| 366 | else if (halfword == UINT16_C(0xffff)) |
| 367 | num_ffff_halfwords++; |
| 368 | } |
| 369 | int num_fast_halfwords = std::max(num_0000_halfwords, num_ffff_halfwords); |
| 370 | |
| 371 | if (num_fast_halfwords < 3) { |
| 372 | // A single movz/movn is not enough. Try the logical immediate route. |
| 373 | int log_imm = EncodeLogicalImmediate(/*is_wide=*/true, value); |
| 374 | if (log_imm >= 0) { |
| 375 | return NewLIR3(WIDE(kA64Orr3Rrl), r_dest.GetReg(), rxzr, log_imm); |
| 376 | } |
| 377 | } |
| 378 | |
| 379 | if (num_fast_halfwords >= 4 - max_num_ops) { |
| 380 | // We can encode the number using a movz/movn followed by one or more movk. |
| 381 | ArmOpcode op; |
| 382 | uint16_t background; |
| 383 | LIR* res = nullptr; |
| 384 | |
| 385 | // Decide whether to use a movz or a movn. |
| 386 | if (num_0000_halfwords >= num_ffff_halfwords) { |
| 387 | op = WIDE(kA64Movz3rdM); |
| 388 | background = 0; |
| 389 | } else { |
| 390 | op = WIDE(kA64Movn3rdM); |
| 391 | background = 0xffff; |
| 392 | } |
| 393 | |
| 394 | // Emit the first instruction (movz, movn). |
| 395 | int shift; |
| 396 | for (shift = 0; shift < 4; shift++) { |
| 397 | uint16_t halfword = static_cast<uint16_t>(uvalue >> (shift << 4)); |
| 398 | if (halfword != background) { |
| 399 | res = NewLIR3(op, r_dest.GetReg(), halfword ^ background, shift); |
| 400 | break; |
| 401 | } |
| 402 | } |
| 403 | |
| 404 | // Emit the movk instructions. |
| 405 | for (shift++; shift < 4; shift++) { |
| 406 | uint16_t halfword = static_cast<uint16_t>(uvalue >> (shift << 4)); |
| 407 | if (halfword != background) { |
| 408 | NewLIR3(WIDE(kA64Movk3rdM), r_dest.GetReg(), halfword, shift); |
| 409 | } |
| 410 | } |
| 411 | return res; |
| 412 | } |
| 413 | |
| 414 | // Use the literal pool. |
| 415 | int32_t val_lo = Low32Bits(value); |
| 416 | int32_t val_hi = High32Bits(value); |
| 417 | LIR* data_target = ScanLiteralPoolWide(literal_list_, val_lo, val_hi); |
| 418 | if (data_target == NULL) { |
| 419 | data_target = AddWideData(&literal_list_, val_lo, val_hi); |
| 420 | } |
| 421 | |
| 422 | ScopedMemRefType mem_ref_type(this, ResourceMask::kLiteral); |
| 423 | LIR *res = RawLIR(current_dalvik_offset_, WIDE(kA64Ldr2rp), |
| 424 | r_dest.GetReg(), 0, 0, 0, 0, data_target); |
| 425 | AppendLIR(res); |
| 426 | return res; |
| 427 | } |
| 428 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 429 | LIR* Arm64Mir2Lir::OpUnconditionalBranch(LIR* target) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 430 | LIR* res = NewLIR1(kA64B1t, 0 /* offset to be patched during assembly */); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 431 | res->target = target; |
| 432 | return res; |
| 433 | } |
| 434 | |
| 435 | LIR* Arm64Mir2Lir::OpCondBranch(ConditionCode cc, LIR* target) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 436 | LIR* branch = NewLIR2(kA64B2ct, ArmConditionEncoding(cc), |
| 437 | 0 /* offset to be patched */); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 438 | branch->target = target; |
| 439 | return branch; |
| 440 | } |
| 441 | |
| 442 | LIR* Arm64Mir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 443 | ArmOpcode opcode = kA64Brk1d; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 444 | switch (op) { |
| 445 | case kOpBlx: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 446 | opcode = kA64Blr1x; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 447 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 448 | // TODO(Arm64): port kThumbBx. |
| 449 | // case kOpBx: |
| 450 | // opcode = kThumbBx; |
| 451 | // break; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 452 | default: |
| 453 | LOG(FATAL) << "Bad opcode " << op; |
| 454 | } |
| 455 | return NewLIR1(opcode, r_dest_src.GetReg()); |
| 456 | } |
| 457 | |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 458 | LIR* Arm64Mir2Lir::OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift) { |
| 459 | ArmOpcode wide = (r_dest_src1.Is64Bit()) ? WIDE(0) : UNWIDE(0); |
| 460 | CHECK_EQ(r_dest_src1.Is64Bit(), r_src2.Is64Bit()); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 461 | ArmOpcode opcode = kA64Brk1d; |
| 462 | |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 463 | switch (op) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 464 | case kOpCmn: |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 465 | opcode = kA64Cmn3rro; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 466 | break; |
| 467 | case kOpCmp: |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 468 | opcode = kA64Cmp3rro; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 469 | break; |
| 470 | case kOpMov: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 471 | opcode = kA64Mov2rr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 472 | break; |
| 473 | case kOpMvn: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 474 | opcode = kA64Mvn2rr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 475 | break; |
| 476 | case kOpNeg: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 477 | opcode = kA64Neg3rro; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 478 | break; |
| 479 | case kOpTst: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 480 | opcode = kA64Tst3rro; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 481 | break; |
| 482 | case kOpRev: |
| 483 | DCHECK_EQ(shift, 0); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 484 | // Binary, but rm is encoded twice. |
Serban Constantinescu | 169489b | 2014-06-11 16:43:35 +0100 | [diff] [blame] | 485 | return NewLIR2(kA64Rev2rr | wide, r_dest_src1.GetReg(), r_src2.GetReg()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 486 | break; |
| 487 | case kOpRevsh: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 488 | // Binary, but rm is encoded twice. |
Serban Constantinescu | 169489b | 2014-06-11 16:43:35 +0100 | [diff] [blame] | 489 | return NewLIR2(kA64Rev162rr | wide, r_dest_src1.GetReg(), r_src2.GetReg()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 490 | break; |
| 491 | case kOp2Byte: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 492 | DCHECK_EQ(shift, ENCODE_NO_SHIFT); |
| 493 | // "sbfx r1, r2, #imm1, #imm2" is "sbfm r1, r2, #imm1, #(imm1 + imm2 - 1)". |
| 494 | // For now we use sbfm directly. |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 495 | return NewLIR4(kA64Sbfm4rrdd | wide, r_dest_src1.GetReg(), r_src2.GetReg(), 0, 7); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 496 | case kOp2Short: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 497 | DCHECK_EQ(shift, ENCODE_NO_SHIFT); |
| 498 | // For now we use sbfm rather than its alias, sbfx. |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 499 | return NewLIR4(kA64Sbfm4rrdd | wide, r_dest_src1.GetReg(), r_src2.GetReg(), 0, 15); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 500 | case kOp2Char: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 501 | // "ubfx r1, r2, #imm1, #imm2" is "ubfm r1, r2, #imm1, #(imm1 + imm2 - 1)". |
| 502 | // For now we use ubfm directly. |
| 503 | DCHECK_EQ(shift, ENCODE_NO_SHIFT); |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 504 | return NewLIR4(kA64Ubfm4rrdd | wide, r_dest_src1.GetReg(), r_src2.GetReg(), 0, 15); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 505 | default: |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 506 | return OpRegRegRegShift(op, r_dest_src1, r_dest_src1, r_src2, shift); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 507 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 508 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 509 | DCHECK(!IsPseudoLirOp(opcode)); |
| 510 | if (EncodingMap[opcode].flags & IS_BINARY_OP) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 511 | DCHECK_EQ(shift, ENCODE_NO_SHIFT); |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 512 | return NewLIR2(opcode | wide, r_dest_src1.GetReg(), r_src2.GetReg()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 513 | } else if (EncodingMap[opcode].flags & IS_TERTIARY_OP) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 514 | ArmEncodingKind kind = EncodingMap[opcode].field_loc[2].kind; |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 515 | if (kind == kFmtShift) { |
| 516 | return NewLIR3(opcode | wide, r_dest_src1.GetReg(), r_src2.GetReg(), shift); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 517 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 518 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 519 | |
| 520 | LOG(FATAL) << "Unexpected encoding operand count"; |
| 521 | return NULL; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 522 | } |
| 523 | |
Stuart Monteith | f8ec48e | 2014-06-06 17:05:08 +0100 | [diff] [blame] | 524 | LIR* Arm64Mir2Lir::OpRegRegExtend(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int extend) { |
| 525 | ArmOpcode wide = (r_dest_src1.Is64Bit()) ? WIDE(0) : UNWIDE(0); |
| 526 | ArmOpcode opcode = kA64Brk1d; |
| 527 | |
| 528 | switch (op) { |
| 529 | case kOpCmn: |
| 530 | opcode = kA64Cmn3Rre; |
| 531 | break; |
| 532 | case kOpCmp: |
| 533 | opcode = kA64Cmp3Rre; |
| 534 | break; |
| 535 | default: |
| 536 | LOG(FATAL) << "Bad Opcode: " << opcode; |
| 537 | break; |
| 538 | } |
| 539 | |
| 540 | DCHECK(!IsPseudoLirOp(opcode)); |
| 541 | if (EncodingMap[opcode].flags & IS_TERTIARY_OP) { |
| 542 | ArmEncodingKind kind = EncodingMap[opcode].field_loc[2].kind; |
| 543 | if (kind == kFmtExtend) { |
| 544 | return NewLIR3(opcode | wide, r_dest_src1.GetReg(), r_src2.GetReg(), extend); |
| 545 | } |
| 546 | } |
| 547 | |
| 548 | LOG(FATAL) << "Unexpected encoding operand count"; |
| 549 | return NULL; |
| 550 | } |
| 551 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 552 | LIR* Arm64Mir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) { |
Stuart Monteith | f8ec48e | 2014-06-06 17:05:08 +0100 | [diff] [blame] | 553 | /* RegReg operations with SP in first parameter need extended register instruction form. |
| 554 | * Only CMN and CMP instructions are implemented. |
| 555 | */ |
| 556 | if (r_dest_src1 == rs_rA64_SP) { |
| 557 | return OpRegRegExtend(op, r_dest_src1, r_src2, ENCODE_NO_EXTEND); |
| 558 | } else { |
| 559 | return OpRegRegShift(op, r_dest_src1, r_src2, ENCODE_NO_SHIFT); |
| 560 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 561 | } |
| 562 | |
| 563 | LIR* Arm64Mir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) { |
| 564 | UNIMPLEMENTED(FATAL); |
| 565 | return nullptr; |
| 566 | } |
| 567 | |
| 568 | LIR* Arm64Mir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) { |
| 569 | UNIMPLEMENTED(FATAL); |
| 570 | return nullptr; |
| 571 | } |
| 572 | |
| 573 | LIR* Arm64Mir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 574 | LOG(FATAL) << "Unexpected use of OpCondRegReg for Arm64"; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 575 | return NULL; |
| 576 | } |
| 577 | |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 578 | LIR* Arm64Mir2Lir::OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, |
| 579 | RegStorage r_src2, int shift) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 580 | ArmOpcode opcode = kA64Brk1d; |
| 581 | |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 582 | switch (op) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 583 | case kOpAdd: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 584 | opcode = kA64Add4rrro; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 585 | break; |
| 586 | case kOpSub: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 587 | opcode = kA64Sub4rrro; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 588 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 589 | // case kOpRsub: |
| 590 | // opcode = kA64RsubWWW; |
| 591 | // break; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 592 | case kOpAdc: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 593 | opcode = kA64Adc3rrr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 594 | break; |
| 595 | case kOpAnd: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 596 | opcode = kA64And4rrro; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 597 | break; |
| 598 | case kOpXor: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 599 | opcode = kA64Eor4rrro; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 600 | break; |
| 601 | case kOpMul: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 602 | opcode = kA64Mul3rrr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 603 | break; |
| 604 | case kOpDiv: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 605 | opcode = kA64Sdiv3rrr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 606 | break; |
| 607 | case kOpOr: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 608 | opcode = kA64Orr4rrro; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 609 | break; |
| 610 | case kOpSbc: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 611 | opcode = kA64Sbc3rrr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 612 | break; |
| 613 | case kOpLsl: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 614 | opcode = kA64Lsl3rrr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 615 | break; |
| 616 | case kOpLsr: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 617 | opcode = kA64Lsr3rrr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 618 | break; |
| 619 | case kOpAsr: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 620 | opcode = kA64Asr3rrr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 621 | break; |
| 622 | case kOpRor: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 623 | opcode = kA64Ror3rrr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 624 | break; |
| 625 | default: |
| 626 | LOG(FATAL) << "Bad opcode: " << op; |
| 627 | break; |
| 628 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 629 | |
| 630 | // The instructions above belong to two kinds: |
| 631 | // - 4-operands instructions, where the last operand is a shift/extend immediate, |
| 632 | // - 3-operands instructions with no shift/extend. |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 633 | ArmOpcode widened_opcode = r_dest.Is64Bit() ? WIDE(opcode) : opcode; |
| 634 | CHECK_EQ(r_dest.Is64Bit(), r_src1.Is64Bit()); |
| 635 | CHECK_EQ(r_dest.Is64Bit(), r_src2.Is64Bit()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 636 | if (EncodingMap[opcode].flags & IS_QUAD_OP) { |
Matteo Franchin | 0955f7e | 2014-05-23 17:32:52 +0100 | [diff] [blame] | 637 | DCHECK(!IsExtendEncoding(shift)); |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 638 | return NewLIR4(widened_opcode, r_dest.GetReg(), r_src1.GetReg(), r_src2.GetReg(), shift); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 639 | } else { |
| 640 | DCHECK(EncodingMap[opcode].flags & IS_TERTIARY_OP); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 641 | DCHECK_EQ(shift, ENCODE_NO_SHIFT); |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 642 | return NewLIR3(widened_opcode, r_dest.GetReg(), r_src1.GetReg(), r_src2.GetReg()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 643 | } |
| 644 | } |
| 645 | |
| 646 | LIR* Arm64Mir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) { |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 647 | return OpRegRegRegShift(op, r_dest, r_src1, r_src2, ENCODE_NO_SHIFT); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 648 | } |
| 649 | |
| 650 | LIR* Arm64Mir2Lir::OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) { |
Zheng Xu | e2eb29e | 2014-06-12 10:22:33 +0800 | [diff] [blame] | 651 | return OpRegRegImm64(op, r_dest, r_src1, static_cast<int64_t>(value)); |
| 652 | } |
| 653 | |
| 654 | LIR* Arm64Mir2Lir::OpRegRegImm64(OpKind op, RegStorage r_dest, RegStorage r_src1, int64_t value) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 655 | LIR* res; |
| 656 | bool neg = (value < 0); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 657 | int64_t abs_value = (neg) ? -value : value; |
| 658 | ArmOpcode opcode = kA64Brk1d; |
| 659 | ArmOpcode alt_opcode = kA64Brk1d; |
| 660 | int32_t log_imm = -1; |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 661 | bool is_wide = r_dest.Is64Bit(); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 662 | ArmOpcode wide = (is_wide) ? WIDE(0) : UNWIDE(0); |
Andreas Gampe | 9f975bf | 2014-06-18 17:45:32 -0700 | [diff] [blame^] | 663 | int info = 0; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 664 | |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 665 | switch (op) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 666 | case kOpLsl: { |
| 667 | // "lsl w1, w2, #imm" is an alias of "ubfm w1, w2, #(-imm MOD 32), #(31-imm)" |
Zheng Xu | 2d41a65 | 2014-06-09 11:05:31 +0800 | [diff] [blame] | 668 | // and "lsl x1, x2, #imm" of "ubfm x1, x2, #(-imm MOD 64), #(63-imm)". |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 669 | // For now, we just use ubfm directly. |
Zheng Xu | 2d41a65 | 2014-06-09 11:05:31 +0800 | [diff] [blame] | 670 | int max_value = (is_wide) ? 63 : 31; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 671 | return NewLIR4(kA64Ubfm4rrdd | wide, r_dest.GetReg(), r_src1.GetReg(), |
Zheng Xu | 2d41a65 | 2014-06-09 11:05:31 +0800 | [diff] [blame] | 672 | (-value) & max_value, max_value - value); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 673 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 674 | case kOpLsr: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 675 | return NewLIR3(kA64Lsr3rrd | wide, r_dest.GetReg(), r_src1.GetReg(), value); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 676 | case kOpAsr: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 677 | return NewLIR3(kA64Asr3rrd | wide, r_dest.GetReg(), r_src1.GetReg(), value); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 678 | case kOpRor: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 679 | // "ror r1, r2, #imm" is an alias of "extr r1, r2, r2, #imm". |
| 680 | // For now, we just use extr directly. |
| 681 | return NewLIR4(kA64Extr4rrrd | wide, r_dest.GetReg(), r_src1.GetReg(), r_src1.GetReg(), |
| 682 | value); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 683 | case kOpAdd: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 684 | neg = !neg; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 685 | // Note: intentional fallthrough |
| 686 | case kOpSub: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 687 | // Add and sub below read/write sp rather than xzr. |
| 688 | if (abs_value < 0x1000) { |
| 689 | opcode = (neg) ? kA64Add4RRdT : kA64Sub4RRdT; |
| 690 | return NewLIR4(opcode | wide, r_dest.GetReg(), r_src1.GetReg(), abs_value, 0); |
| 691 | } else if ((abs_value & UINT64_C(0xfff)) == 0 && ((abs_value >> 12) < 0x1000)) { |
| 692 | opcode = (neg) ? kA64Add4RRdT : kA64Sub4RRdT; |
| 693 | return NewLIR4(opcode | wide, r_dest.GetReg(), r_src1.GetReg(), abs_value >> 12, 1); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 694 | } else { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 695 | log_imm = -1; |
Andreas Gampe | 9f975bf | 2014-06-18 17:45:32 -0700 | [diff] [blame^] | 696 | alt_opcode = (neg) ? kA64Add4rrre : kA64Sub4rrre; |
| 697 | // To make it correct, we need: |
| 698 | // 23..21 = 001 = extend |
| 699 | // 15..13 = 01x = LSL/UXTW/X / x defines wide or not |
| 700 | // 12..10 = 000 = no shift (in case of SP) |
| 701 | // => info = 00101x000 |
| 702 | // => =0x 0 5 (0/8) |
| 703 | info = (is_wide ? 8 : 0) | 0x50; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 704 | } |
| 705 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 706 | // case kOpRsub: |
| 707 | // opcode = kThumb2RsubRRI8M; |
| 708 | // alt_opcode = kThumb2RsubRRR; |
| 709 | // break; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 710 | case kOpAdc: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 711 | log_imm = -1; |
| 712 | alt_opcode = kA64Adc3rrr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 713 | break; |
| 714 | case kOpSbc: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 715 | log_imm = -1; |
| 716 | alt_opcode = kA64Sbc3rrr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 717 | break; |
| 718 | case kOpOr: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 719 | log_imm = EncodeLogicalImmediate(is_wide, value); |
| 720 | opcode = kA64Orr3Rrl; |
| 721 | alt_opcode = kA64Orr4rrro; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 722 | break; |
| 723 | case kOpAnd: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 724 | log_imm = EncodeLogicalImmediate(is_wide, value); |
| 725 | opcode = kA64And3Rrl; |
| 726 | alt_opcode = kA64And4rrro; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 727 | break; |
| 728 | case kOpXor: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 729 | log_imm = EncodeLogicalImmediate(is_wide, value); |
| 730 | opcode = kA64Eor3Rrl; |
| 731 | alt_opcode = kA64Eor4rrro; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 732 | break; |
| 733 | case kOpMul: |
| 734 | // TUNING: power of 2, shift & add |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 735 | log_imm = -1; |
| 736 | alt_opcode = kA64Mul3rrr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 737 | break; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 738 | default: |
| 739 | LOG(FATAL) << "Bad opcode: " << op; |
| 740 | } |
| 741 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 742 | if (log_imm >= 0) { |
| 743 | return NewLIR3(opcode | wide, r_dest.GetReg(), r_src1.GetReg(), log_imm); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 744 | } else { |
Andreas Gampe | 9f975bf | 2014-06-18 17:45:32 -0700 | [diff] [blame^] | 745 | RegStorage r_scratch; |
Zheng Xu | e2eb29e | 2014-06-12 10:22:33 +0800 | [diff] [blame] | 746 | if (IS_WIDE(wide)) { |
| 747 | r_scratch = AllocTempWide(); |
| 748 | LoadConstantWide(r_scratch, value); |
| 749 | } else { |
| 750 | r_scratch = AllocTemp(); |
| 751 | LoadConstant(r_scratch, value); |
| 752 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 753 | if (EncodingMap[alt_opcode].flags & IS_QUAD_OP) |
Andreas Gampe | 9f975bf | 2014-06-18 17:45:32 -0700 | [diff] [blame^] | 754 | res = NewLIR4(alt_opcode | wide, r_dest.GetReg(), r_src1.GetReg(), r_scratch.GetReg(), info); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 755 | else |
Zheng Xu | e2eb29e | 2014-06-12 10:22:33 +0800 | [diff] [blame] | 756 | res = NewLIR3(alt_opcode | wide, r_dest.GetReg(), r_src1.GetReg(), r_scratch.GetReg()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 757 | FreeTemp(r_scratch); |
| 758 | return res; |
| 759 | } |
| 760 | } |
| 761 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 762 | LIR* Arm64Mir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) { |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 763 | return OpRegImm64(op, r_dest_src1, static_cast<int64_t>(value)); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 764 | } |
| 765 | |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 766 | LIR* Arm64Mir2Lir::OpRegImm64(OpKind op, RegStorage r_dest_src1, int64_t value) { |
| 767 | ArmOpcode wide = (r_dest_src1.Is64Bit()) ? WIDE(0) : UNWIDE(0); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 768 | ArmOpcode opcode = kA64Brk1d; |
| 769 | ArmOpcode neg_opcode = kA64Brk1d; |
| 770 | bool shift; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 771 | bool neg = (value < 0); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 772 | uint64_t abs_value = (neg) ? -value : value; |
| 773 | |
| 774 | if (LIKELY(abs_value < 0x1000)) { |
| 775 | // abs_value is a 12-bit immediate. |
| 776 | shift = false; |
| 777 | } else if ((abs_value & UINT64_C(0xfff)) == 0 && ((abs_value >> 12) < 0x1000)) { |
| 778 | // abs_value is a shifted 12-bit immediate. |
| 779 | shift = true; |
| 780 | abs_value >>= 12; |
Zheng Xu | e2eb29e | 2014-06-12 10:22:33 +0800 | [diff] [blame] | 781 | } else if (LIKELY(abs_value < 0x1000000 && (op == kOpAdd || op == kOpSub))) { |
| 782 | // Note: It is better to use two ADD/SUB instead of loading a number to a temp register. |
| 783 | // This works for both normal registers and SP. |
| 784 | // For a frame size == 0x2468, it will be encoded as: |
| 785 | // sub sp, #0x2000 |
| 786 | // sub sp, #0x468 |
| 787 | if (neg) { |
| 788 | op = (op == kOpAdd) ? kOpSub : kOpAdd; |
| 789 | } |
| 790 | OpRegImm64(op, r_dest_src1, abs_value & (~INT64_C(0xfff))); |
| 791 | return OpRegImm64(op, r_dest_src1, abs_value & 0xfff); |
| 792 | } else if (LIKELY(A64_REG_IS_SP(r_dest_src1.GetReg()) && (op == kOpAdd || op == kOpSub))) { |
| 793 | // Note: "sub sp, sp, Xm" is not correct on arm64. |
| 794 | // We need special instructions for SP. |
| 795 | // Also operation on 32-bit SP should be avoided. |
| 796 | DCHECK(IS_WIDE(wide)); |
| 797 | RegStorage r_tmp = AllocTempWide(); |
| 798 | OpRegRegImm(kOpAdd, r_tmp, r_dest_src1, 0); |
| 799 | OpRegImm64(op, r_tmp, value); |
| 800 | return OpRegRegImm(kOpAdd, r_dest_src1, r_tmp, 0); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 801 | } else { |
Zheng Xu | e2eb29e | 2014-06-12 10:22:33 +0800 | [diff] [blame] | 802 | RegStorage r_tmp; |
| 803 | LIR* res; |
| 804 | if (IS_WIDE(wide)) { |
| 805 | r_tmp = AllocTempWide(); |
| 806 | res = LoadConstantWide(r_tmp, value); |
| 807 | } else { |
| 808 | r_tmp = AllocTemp(); |
| 809 | res = LoadConstant(r_tmp, value); |
| 810 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 811 | OpRegReg(op, r_dest_src1, r_tmp); |
| 812 | FreeTemp(r_tmp); |
| 813 | return res; |
| 814 | } |
| 815 | |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 816 | switch (op) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 817 | case kOpAdd: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 818 | neg_opcode = kA64Sub4RRdT; |
| 819 | opcode = kA64Add4RRdT; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 820 | break; |
| 821 | case kOpSub: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 822 | neg_opcode = kA64Add4RRdT; |
| 823 | opcode = kA64Sub4RRdT; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 824 | break; |
| 825 | case kOpCmp: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 826 | neg_opcode = kA64Cmn3RdT; |
| 827 | opcode = kA64Cmp3RdT; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 828 | break; |
| 829 | default: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 830 | LOG(FATAL) << "Bad op-kind in OpRegImm: " << op; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 831 | break; |
| 832 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 833 | |
| 834 | if (UNLIKELY(neg)) |
| 835 | opcode = neg_opcode; |
| 836 | |
| 837 | if (EncodingMap[opcode].flags & IS_QUAD_OP) |
| 838 | return NewLIR4(opcode | wide, r_dest_src1.GetReg(), r_dest_src1.GetReg(), abs_value, |
| 839 | (shift) ? 1 : 0); |
| 840 | else |
| 841 | return NewLIR3(opcode | wide, r_dest_src1.GetReg(), abs_value, (shift) ? 1 : 0); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 842 | } |
| 843 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 844 | int Arm64Mir2Lir::EncodeShift(int shift_type, int amount) { |
| 845 | return ((shift_type & 0x3) << 7) | (amount & 0x1f); |
| 846 | } |
| 847 | |
| 848 | int Arm64Mir2Lir::EncodeExtend(int extend_type, int amount) { |
| 849 | return (1 << 6) | ((extend_type & 0x7) << 3) | (amount & 0x7); |
| 850 | } |
| 851 | |
| 852 | bool Arm64Mir2Lir::IsExtendEncoding(int encoded_value) { |
| 853 | return ((1 << 6) & encoded_value) != 0; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 854 | } |
| 855 | |
| 856 | LIR* Arm64Mir2Lir::LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 857 | int scale, OpSize size) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 858 | LIR* load; |
Matteo Franchin | 0955f7e | 2014-05-23 17:32:52 +0100 | [diff] [blame] | 859 | int expected_scale = 0; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 860 | ArmOpcode opcode = kA64Brk1d; |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 861 | DCHECK(r_base.Is64Bit()); |
| 862 | // TODO: need a cleaner handling of index registers here and throughout. |
| 863 | if (r_index.Is32Bit()) { |
| 864 | r_index = As64BitReg(r_index); |
| 865 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 866 | |
| 867 | if (r_dest.IsFloat()) { |
Matteo Franchin | 0955f7e | 2014-05-23 17:32:52 +0100 | [diff] [blame] | 868 | if (r_dest.IsDouble()) { |
| 869 | DCHECK(size == k64 || size == kDouble); |
| 870 | expected_scale = 3; |
| 871 | opcode = FWIDE(kA64Ldr4fXxG); |
| 872 | } else { |
| 873 | DCHECK(r_dest.IsSingle()); |
| 874 | DCHECK(size == k32 || size == kSingle); |
| 875 | expected_scale = 2; |
| 876 | opcode = kA64Ldr4fXxG; |
| 877 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 878 | |
Matteo Franchin | 0955f7e | 2014-05-23 17:32:52 +0100 | [diff] [blame] | 879 | DCHECK(scale == 0 || scale == expected_scale); |
| 880 | return NewLIR4(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(), |
| 881 | (scale != 0) ? 1 : 0); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 882 | } |
| 883 | |
| 884 | switch (size) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 885 | case kDouble: |
| 886 | case kWord: |
| 887 | case k64: |
Matteo Franchin | 0955f7e | 2014-05-23 17:32:52 +0100 | [diff] [blame] | 888 | opcode = WIDE(kA64Ldr4rXxG); |
| 889 | expected_scale = 3; |
| 890 | break; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 891 | case kSingle: |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 892 | case k32: |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 893 | case kReference: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 894 | opcode = kA64Ldr4rXxG; |
Matteo Franchin | 0955f7e | 2014-05-23 17:32:52 +0100 | [diff] [blame] | 895 | expected_scale = 2; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 896 | break; |
| 897 | case kUnsignedHalf: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 898 | opcode = kA64Ldrh4wXxd; |
Matteo Franchin | 0955f7e | 2014-05-23 17:32:52 +0100 | [diff] [blame] | 899 | expected_scale = 1; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 900 | break; |
| 901 | case kSignedHalf: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 902 | opcode = kA64Ldrsh4rXxd; |
Matteo Franchin | 0955f7e | 2014-05-23 17:32:52 +0100 | [diff] [blame] | 903 | expected_scale = 1; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 904 | break; |
| 905 | case kUnsignedByte: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 906 | opcode = kA64Ldrb3wXx; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 907 | break; |
| 908 | case kSignedByte: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 909 | opcode = kA64Ldrsb3rXx; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 910 | break; |
| 911 | default: |
| 912 | LOG(FATAL) << "Bad size: " << size; |
| 913 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 914 | |
Matteo Franchin | 0955f7e | 2014-05-23 17:32:52 +0100 | [diff] [blame] | 915 | if (UNLIKELY(expected_scale == 0)) { |
| 916 | // This is a tertiary op (e.g. ldrb, ldrsb), it does not not support scale. |
| 917 | DCHECK_NE(EncodingMap[UNWIDE(opcode)].flags & IS_TERTIARY_OP, 0U); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 918 | DCHECK_EQ(scale, 0); |
Matteo Franchin | 0955f7e | 2014-05-23 17:32:52 +0100 | [diff] [blame] | 919 | load = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg()); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 920 | } else { |
Matteo Franchin | 0955f7e | 2014-05-23 17:32:52 +0100 | [diff] [blame] | 921 | DCHECK(scale == 0 || scale == expected_scale); |
| 922 | load = NewLIR4(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(), |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 923 | (scale != 0) ? 1 : 0); |
| 924 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 925 | |
| 926 | return load; |
| 927 | } |
| 928 | |
| 929 | LIR* Arm64Mir2Lir::StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 930 | int scale, OpSize size) { |
| 931 | LIR* store; |
Matteo Franchin | 0955f7e | 2014-05-23 17:32:52 +0100 | [diff] [blame] | 932 | int expected_scale = 0; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 933 | ArmOpcode opcode = kA64Brk1d; |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 934 | DCHECK(r_base.Is64Bit()); |
| 935 | // TODO: need a cleaner handling of index registers here and throughout. |
| 936 | if (r_index.Is32Bit()) { |
| 937 | r_index = As64BitReg(r_index); |
| 938 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 939 | |
| 940 | if (r_src.IsFloat()) { |
Matteo Franchin | 0955f7e | 2014-05-23 17:32:52 +0100 | [diff] [blame] | 941 | if (r_src.IsDouble()) { |
| 942 | DCHECK(size == k64 || size == kDouble); |
| 943 | expected_scale = 3; |
| 944 | opcode = FWIDE(kA64Str4fXxG); |
| 945 | } else { |
| 946 | DCHECK(r_src.IsSingle()); |
| 947 | DCHECK(size == k32 || size == kSingle); |
| 948 | expected_scale = 2; |
| 949 | opcode = kA64Str4fXxG; |
| 950 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 951 | |
Matteo Franchin | 0955f7e | 2014-05-23 17:32:52 +0100 | [diff] [blame] | 952 | DCHECK(scale == 0 || scale == expected_scale); |
| 953 | return NewLIR4(opcode, r_src.GetReg(), r_base.GetReg(), r_index.GetReg(), |
| 954 | (scale != 0) ? 1 : 0); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 955 | } |
| 956 | |
| 957 | switch (size) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 958 | case kDouble: // Intentional fall-trough. |
| 959 | case kWord: // Intentional fall-trough. |
| 960 | case k64: |
Matteo Franchin | 0955f7e | 2014-05-23 17:32:52 +0100 | [diff] [blame] | 961 | opcode = WIDE(kA64Str4rXxG); |
| 962 | expected_scale = 3; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 963 | break; |
| 964 | case kSingle: // Intentional fall-trough. |
| 965 | case k32: // Intentional fall-trough. |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 966 | case kReference: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 967 | opcode = kA64Str4rXxG; |
Matteo Franchin | 0955f7e | 2014-05-23 17:32:52 +0100 | [diff] [blame] | 968 | expected_scale = 2; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 969 | break; |
| 970 | case kUnsignedHalf: |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 971 | case kSignedHalf: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 972 | opcode = kA64Strh4wXxd; |
Matteo Franchin | 0955f7e | 2014-05-23 17:32:52 +0100 | [diff] [blame] | 973 | expected_scale = 1; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 974 | break; |
| 975 | case kUnsignedByte: |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 976 | case kSignedByte: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 977 | opcode = kA64Strb3wXx; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 978 | break; |
| 979 | default: |
| 980 | LOG(FATAL) << "Bad size: " << size; |
| 981 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 982 | |
Matteo Franchin | 0955f7e | 2014-05-23 17:32:52 +0100 | [diff] [blame] | 983 | if (UNLIKELY(expected_scale == 0)) { |
| 984 | // This is a tertiary op (e.g. strb), it does not not support scale. |
| 985 | DCHECK_NE(EncodingMap[UNWIDE(opcode)].flags & IS_TERTIARY_OP, 0U); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 986 | DCHECK_EQ(scale, 0); |
Matteo Franchin | 0955f7e | 2014-05-23 17:32:52 +0100 | [diff] [blame] | 987 | store = NewLIR3(opcode, r_src.GetReg(), r_base.GetReg(), r_index.GetReg()); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 988 | } else { |
Matteo Franchin | 0955f7e | 2014-05-23 17:32:52 +0100 | [diff] [blame] | 989 | store = NewLIR4(opcode, r_src.GetReg(), r_base.GetReg(), r_index.GetReg(), |
| 990 | (scale != 0) ? 1 : 0); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 991 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 992 | |
| 993 | return store; |
| 994 | } |
| 995 | |
| 996 | /* |
| 997 | * Load value from base + displacement. Optionally perform null check |
| 998 | * on base (which must have an associated s_reg and MIR). If not |
| 999 | * performing null check, incoming MIR can be null. |
| 1000 | */ |
| 1001 | LIR* Arm64Mir2Lir::LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 1002 | OpSize size) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1003 | LIR* load = NULL; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1004 | ArmOpcode opcode = kA64Brk1d; |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 1005 | ArmOpcode alt_opcode = kA64Brk1d; |
| 1006 | int scale = 0; |
| 1007 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1008 | switch (size) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1009 | case kDouble: // Intentional fall-through. |
| 1010 | case kWord: // Intentional fall-through. |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1011 | case k64: |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 1012 | scale = 3; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1013 | if (r_dest.IsFloat()) { |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 1014 | DCHECK(r_dest.IsDouble()); |
| 1015 | opcode = FWIDE(kA64Ldr3fXD); |
| 1016 | alt_opcode = FWIDE(kA64Ldur3fXd); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1017 | } else { |
Matteo Franchin | 0955f7e | 2014-05-23 17:32:52 +0100 | [diff] [blame] | 1018 | opcode = WIDE(kA64Ldr3rXD); |
| 1019 | alt_opcode = WIDE(kA64Ldur3rXd); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1020 | } |
| 1021 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1022 | case kSingle: // Intentional fall-through. |
| 1023 | case k32: // Intentional fall-trough. |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1024 | case kReference: |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 1025 | scale = 2; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1026 | if (r_dest.IsFloat()) { |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 1027 | DCHECK(r_dest.IsSingle()); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1028 | opcode = kA64Ldr3fXD; |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 1029 | } else { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1030 | opcode = kA64Ldr3rXD; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1031 | } |
| 1032 | break; |
| 1033 | case kUnsignedHalf: |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 1034 | scale = 1; |
| 1035 | opcode = kA64Ldrh3wXF; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1036 | break; |
| 1037 | case kSignedHalf: |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 1038 | scale = 1; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1039 | opcode = kA64Ldrsh3rXF; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1040 | break; |
| 1041 | case kUnsignedByte: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1042 | opcode = kA64Ldrb3wXd; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1043 | break; |
| 1044 | case kSignedByte: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1045 | opcode = kA64Ldrsb3rXd; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1046 | break; |
| 1047 | default: |
| 1048 | LOG(FATAL) << "Bad size: " << size; |
| 1049 | } |
| 1050 | |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 1051 | bool displacement_is_aligned = (displacement & ((1 << scale) - 1)) == 0; |
| 1052 | int scaled_disp = displacement >> scale; |
| 1053 | if (displacement_is_aligned && scaled_disp >= 0 && scaled_disp < 4096) { |
| 1054 | // Can use scaled load. |
| 1055 | load = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), scaled_disp); |
| 1056 | } else if (alt_opcode != kA64Brk1d && IS_SIGNED_IMM9(displacement)) { |
| 1057 | // Can use unscaled load. |
| 1058 | load = NewLIR3(alt_opcode, r_dest.GetReg(), r_base.GetReg(), displacement); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1059 | } else { |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 1060 | // Use long sequence. |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 1061 | // TODO: cleaner support for index/displacement registers? Not a reference, but must match width. |
| 1062 | RegStorage r_scratch = AllocTempWide(); |
| 1063 | LoadConstantWide(r_scratch, displacement); |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 1064 | load = LoadBaseIndexed(r_base, r_scratch, r_dest, 0, size); |
| 1065 | FreeTemp(r_scratch); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1066 | } |
| 1067 | |
| 1068 | // TODO: in future may need to differentiate Dalvik accesses w/ spills |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1069 | if (mem_ref_type_ == ResourceMask::kDalvikReg) { |
| 1070 | DCHECK(r_base == rs_rA64_SP); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1071 | AnnotateDalvikRegAccess(load, displacement >> 2, true /* is_load */, r_dest.Is64Bit()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1072 | } |
| 1073 | return load; |
| 1074 | } |
| 1075 | |
Vladimir Marko | 674744e | 2014-04-24 15:18:26 +0100 | [diff] [blame] | 1076 | LIR* Arm64Mir2Lir::LoadBaseDispVolatile(RegStorage r_base, int displacement, RegStorage r_dest, |
| 1077 | OpSize size) { |
| 1078 | // LoadBaseDisp() will emit correct insn for atomic load on arm64 |
| 1079 | // assuming r_dest is correctly prepared using RegClassForFieldLoadStore(). |
| 1080 | return LoadBaseDisp(r_base, displacement, r_dest, size); |
| 1081 | } |
| 1082 | |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 1083 | LIR* Arm64Mir2Lir::LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, |
| 1084 | OpSize size) { |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 1085 | return LoadBaseDispBody(r_base, displacement, r_dest, size); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1086 | } |
| 1087 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1088 | |
| 1089 | LIR* Arm64Mir2Lir::StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1090 | OpSize size) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1091 | LIR* store = NULL; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1092 | ArmOpcode opcode = kA64Brk1d; |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 1093 | ArmOpcode alt_opcode = kA64Brk1d; |
| 1094 | int scale = 0; |
| 1095 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1096 | switch (size) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1097 | case kDouble: // Intentional fall-through. |
| 1098 | case kWord: // Intentional fall-through. |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1099 | case k64: |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 1100 | scale = 3; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1101 | if (r_src.IsFloat()) { |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 1102 | DCHECK(r_src.IsDouble()); |
| 1103 | opcode = FWIDE(kA64Str3fXD); |
| 1104 | alt_opcode = FWIDE(kA64Stur3fXd); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1105 | } else { |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 1106 | opcode = FWIDE(kA64Str3rXD); |
| 1107 | alt_opcode = FWIDE(kA64Stur3rXd); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1108 | } |
| 1109 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1110 | case kSingle: // Intentional fall-through. |
| 1111 | case k32: // Intentional fall-trough. |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1112 | case kReference: |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 1113 | scale = 2; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1114 | if (r_src.IsFloat()) { |
| 1115 | DCHECK(r_src.IsSingle()); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1116 | opcode = kA64Str3fXD; |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 1117 | } else { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1118 | opcode = kA64Str3rXD; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1119 | } |
| 1120 | break; |
| 1121 | case kUnsignedHalf: |
| 1122 | case kSignedHalf: |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 1123 | scale = 1; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1124 | opcode = kA64Strh3wXF; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1125 | break; |
| 1126 | case kUnsignedByte: |
| 1127 | case kSignedByte: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1128 | opcode = kA64Strb3wXd; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1129 | break; |
| 1130 | default: |
| 1131 | LOG(FATAL) << "Bad size: " << size; |
| 1132 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1133 | |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 1134 | bool displacement_is_aligned = (displacement & ((1 << scale) - 1)) == 0; |
| 1135 | int scaled_disp = displacement >> scale; |
| 1136 | if (displacement_is_aligned && scaled_disp >= 0 && scaled_disp < 4096) { |
| 1137 | // Can use scaled store. |
| 1138 | store = NewLIR3(opcode, r_src.GetReg(), r_base.GetReg(), scaled_disp); |
| 1139 | } else if (alt_opcode != kA64Brk1d && IS_SIGNED_IMM9(displacement)) { |
| 1140 | // Can use unscaled store. |
| 1141 | store = NewLIR3(alt_opcode, r_src.GetReg(), r_base.GetReg(), displacement); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1142 | } else { |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 1143 | // Use long sequence. |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 1144 | RegStorage r_scratch = AllocTempWide(); |
| 1145 | LoadConstantWide(r_scratch, displacement); |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 1146 | store = StoreBaseIndexed(r_base, r_scratch, r_src, 0, size); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1147 | FreeTemp(r_scratch); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1148 | } |
| 1149 | |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 1150 | // TODO: In future, may need to differentiate Dalvik & spill accesses. |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1151 | if (mem_ref_type_ == ResourceMask::kDalvikReg) { |
| 1152 | DCHECK(r_base == rs_rA64_SP); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1153 | AnnotateDalvikRegAccess(store, displacement >> 2, false /* is_load */, r_src.Is64Bit()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1154 | } |
| 1155 | return store; |
| 1156 | } |
| 1157 | |
Vladimir Marko | 674744e | 2014-04-24 15:18:26 +0100 | [diff] [blame] | 1158 | LIR* Arm64Mir2Lir::StoreBaseDispVolatile(RegStorage r_base, int displacement, RegStorage r_src, |
| 1159 | OpSize size) { |
| 1160 | // StoreBaseDisp() will emit correct insn for atomic store on arm64 |
| 1161 | // assuming r_dest is correctly prepared using RegClassForFieldLoadStore(). |
| 1162 | return StoreBaseDisp(r_base, displacement, r_src, size); |
| 1163 | } |
| 1164 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1165 | LIR* Arm64Mir2Lir::StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, |
Vladimir Marko | 674744e | 2014-04-24 15:18:26 +0100 | [diff] [blame] | 1166 | OpSize size) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1167 | return StoreBaseDispBody(r_base, displacement, r_src, size); |
| 1168 | } |
| 1169 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1170 | LIR* Arm64Mir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1171 | LOG(FATAL) << "Unexpected use of OpFpRegCopy for Arm64"; |
| 1172 | return NULL; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1173 | } |
| 1174 | |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 1175 | LIR* Arm64Mir2Lir::OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) { |
| 1176 | UNIMPLEMENTED(FATAL) << "Should not be used."; |
| 1177 | return nullptr; |
| 1178 | } |
| 1179 | |
| 1180 | LIR* Arm64Mir2Lir::OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1181 | LOG(FATAL) << "Unexpected use of OpThreadMem for Arm64"; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1182 | return NULL; |
| 1183 | } |
| 1184 | |
| 1185 | LIR* Arm64Mir2Lir::OpMem(OpKind op, RegStorage r_base, int disp) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1186 | LOG(FATAL) << "Unexpected use of OpMem for Arm64"; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1187 | return NULL; |
| 1188 | } |
| 1189 | |
| 1190 | LIR* Arm64Mir2Lir::StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1191 | int displacement, RegStorage r_src, OpSize size) { |
| 1192 | LOG(FATAL) << "Unexpected use of StoreBaseIndexedDisp for Arm64"; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1193 | return NULL; |
| 1194 | } |
| 1195 | |
| 1196 | LIR* Arm64Mir2Lir::OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1197 | LOG(FATAL) << "Unexpected use of OpRegMem for Arm64"; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1198 | return NULL; |
| 1199 | } |
| 1200 | |
| 1201 | LIR* Arm64Mir2Lir::LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 1202 | int displacement, RegStorage r_dest, OpSize size) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1203 | LOG(FATAL) << "Unexpected use of LoadBaseIndexedDisp for Arm64"; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1204 | return NULL; |
| 1205 | } |
| 1206 | |
| 1207 | } // namespace art |