Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
Brian Carlstrom | fc0e321 | 2013-07-17 14:40:12 -0700 | [diff] [blame] | 17 | #ifndef ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ |
| 18 | #define ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 19 | |
| 20 | #include "dex/compiler_internals.h" |
| 21 | #include "x86_lir.h" |
| 22 | |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 23 | #include <map> |
| 24 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 25 | namespace art { |
| 26 | |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 27 | class X86Mir2Lir : public Mir2Lir { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 28 | protected: |
| 29 | class InToRegStorageMapper { |
| 30 | public: |
| 31 | virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide) = 0; |
| 32 | virtual ~InToRegStorageMapper() {} |
| 33 | }; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 34 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 35 | class InToRegStorageX86_64Mapper : public InToRegStorageMapper { |
| 36 | public: |
| 37 | InToRegStorageX86_64Mapper() : cur_core_reg_(0), cur_fp_reg_(0) {} |
| 38 | virtual ~InToRegStorageX86_64Mapper() {} |
| 39 | virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide); |
| 40 | private: |
| 41 | int cur_core_reg_; |
| 42 | int cur_fp_reg_; |
| 43 | }; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 44 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 45 | class InToRegStorageMapping { |
| 46 | public: |
| 47 | InToRegStorageMapping() : max_mapped_in_(0), is_there_stack_mapped_(false), |
| 48 | initialized_(false) {} |
| 49 | void Initialize(RegLocation* arg_locs, int count, InToRegStorageMapper* mapper); |
| 50 | int GetMaxMappedIn() { return max_mapped_in_; } |
| 51 | bool IsThereStackMapped() { return is_there_stack_mapped_; } |
| 52 | RegStorage Get(int in_position); |
| 53 | bool IsInitialized() { return initialized_; } |
| 54 | private: |
| 55 | std::map<int, RegStorage> mapping_; |
| 56 | int max_mapped_in_; |
| 57 | bool is_there_stack_mapped_; |
| 58 | bool initialized_; |
| 59 | }; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 60 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 61 | public: |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 62 | X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 63 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 64 | // Required for target - codegen helpers. |
| 65 | bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, |
| 66 | RegLocation rl_dest, int lit); |
| 67 | bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; |
| 68 | LIR* CheckSuspendUsingLoad() OVERRIDE; |
| 69 | RegStorage LoadHelper(ThreadOffset<4> offset) OVERRIDE; |
| 70 | RegStorage LoadHelper(ThreadOffset<8> offset) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 71 | LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 72 | OpSize size, VolatileKind is_volatile) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 73 | LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 74 | OpSize size) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 75 | LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, |
| 76 | RegStorage r_dest, OpSize size) OVERRIDE; |
| 77 | LIR* LoadConstantNoClobber(RegStorage r_dest, int value); |
| 78 | LIR* LoadConstantWide(RegStorage r_dest, int64_t value); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 79 | LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 80 | OpSize size, VolatileKind is_volatile) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 81 | LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, |
| 82 | OpSize size) OVERRIDE; |
| 83 | LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, |
| 84 | RegStorage r_src, OpSize size) OVERRIDE; |
| 85 | void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 86 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 87 | // Required for target - register utilities. |
| 88 | RegStorage TargetReg(SpecialTargetRegister reg); |
| 89 | RegStorage GetArgMappingToPhysicalReg(int arg_num); |
| 90 | RegStorage GetCoreArgMappingToPhysicalReg(int core_arg_num); |
| 91 | RegLocation GetReturnAlt(); |
| 92 | RegLocation GetReturnWideAlt(); |
| 93 | RegLocation LocCReturn(); |
| 94 | RegLocation LocCReturnRef(); |
| 95 | RegLocation LocCReturnDouble(); |
| 96 | RegLocation LocCReturnFloat(); |
| 97 | RegLocation LocCReturnWide(); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 98 | ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 99 | void AdjustSpillMask(); |
| 100 | void ClobberCallerSave(); |
| 101 | void FreeCallTemps(); |
| 102 | void LockCallTemps(); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 103 | void CompilerInitializeRegAlloc(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 104 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 105 | // Required for target - miscellaneous. |
| 106 | void AssembleLIR(); |
| 107 | int AssignInsnOffsets(); |
| 108 | void AssignOffsets(); |
| 109 | AssemblerStatus AssembleInstructions(CodeOffset start_addr); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 110 | void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE; |
| 111 | void SetupTargetResourceMasks(LIR* lir, uint64_t flags, |
| 112 | ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 113 | const char* GetTargetInstFmt(int opcode); |
| 114 | const char* GetTargetInstName(int opcode); |
| 115 | std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 116 | ResourceMask GetPCUseDefEncoding() const OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 117 | uint64_t GetTargetInstFlags(int opcode); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 118 | size_t GetInsnSize(LIR* lir) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 119 | bool IsUnconditionalBranch(LIR* lir); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 120 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 121 | // Check support for volatile load/store of a given size. |
| 122 | bool SupportsVolatileLoadStore(OpSize size) OVERRIDE; |
| 123 | // Get the register class for load/store of a field. |
| 124 | RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE; |
Vladimir Marko | 674744e | 2014-04-24 15:18:26 +0100 | [diff] [blame] | 125 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 126 | // Required for target - Dalvik-level generators. |
| 127 | void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 128 | RegLocation rl_src2); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 129 | void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, |
| 130 | RegLocation rl_dest, int scale); |
| 131 | void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, |
| 132 | RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark); |
| 133 | void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
| 134 | RegLocation rl_src1, RegLocation rl_shift); |
| 135 | void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 136 | RegLocation rl_src2); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 137 | void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 138 | RegLocation rl_src2); |
| 139 | void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 140 | RegLocation rl_src2); |
| 141 | void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 142 | RegLocation rl_src2); |
| 143 | void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 144 | RegLocation rl_src2); |
Alexei Zavjalov | bd3682e | 2014-06-12 03:08:01 +0700 | [diff] [blame] | 145 | void GenRemFP(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, bool is_double); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 146 | void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 147 | RegLocation rl_src2); |
| 148 | void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src); |
| 149 | bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object); |
| 150 | bool GenInlinedMinMaxInt(CallInfo* info, bool is_min); |
| 151 | bool GenInlinedSqrt(CallInfo* info); |
Yixin Shou | 7071c8d | 2014-03-05 06:07:48 -0500 | [diff] [blame] | 152 | bool GenInlinedAbsFloat(CallInfo* info) OVERRIDE; |
| 153 | bool GenInlinedAbsDouble(CallInfo* info) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 154 | bool GenInlinedPeek(CallInfo* info, OpSize size); |
| 155 | bool GenInlinedPoke(CallInfo* info, OpSize size); |
| 156 | void GenNotLong(RegLocation rl_dest, RegLocation rl_src); |
| 157 | void GenNegLong(RegLocation rl_dest, RegLocation rl_src); |
| 158 | void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 159 | RegLocation rl_src2); |
| 160 | void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 161 | RegLocation rl_src2); |
| 162 | void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 163 | RegLocation rl_src2); |
| 164 | void GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, |
| 165 | RegLocation rl_src2, bool is_div); |
| 166 | // TODO: collapse reg_lo, reg_hi |
| 167 | RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div); |
| 168 | RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div); |
| 169 | void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); |
| 170 | void GenDivZeroCheckWide(RegStorage reg); |
| 171 | void GenArrayBoundsCheck(RegStorage index, RegStorage array_base, int32_t len_offset); |
| 172 | void GenArrayBoundsCheck(int32_t index, RegStorage array_base, int32_t len_offset); |
| 173 | void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method); |
| 174 | void GenExitSequence(); |
| 175 | void GenSpecialExitSequence(); |
| 176 | void GenFillArrayData(DexOffset table_offset, RegLocation rl_src); |
| 177 | void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); |
| 178 | void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir); |
| 179 | void GenSelect(BasicBlock* bb, MIR* mir); |
| 180 | bool GenMemBarrier(MemBarrierKind barrier_kind); |
| 181 | void GenMoveException(RegLocation rl_dest); |
| 182 | void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, |
| 183 | int first_bit, int second_bit); |
| 184 | void GenNegDouble(RegLocation rl_dest, RegLocation rl_src); |
| 185 | void GenNegFloat(RegLocation rl_dest, RegLocation rl_src); |
| 186 | void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); |
| 187 | void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); |
| 188 | void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); |
Razvan A Lupusoru | 3bc0174 | 2014-02-06 13:18:43 -0800 | [diff] [blame] | 189 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 190 | /* |
| 191 | * @brief Generate a two address long operation with a constant value |
| 192 | * @param rl_dest location of result |
| 193 | * @param rl_src constant source operand |
| 194 | * @param op Opcode to be generated |
| 195 | * @return success or not |
| 196 | */ |
| 197 | bool GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); |
| 198 | /* |
| 199 | * @brief Generate a three address long operation with a constant value |
| 200 | * @param rl_dest location of result |
| 201 | * @param rl_src1 source operand |
| 202 | * @param rl_src2 constant source operand |
| 203 | * @param op Opcode to be generated |
| 204 | * @return success or not |
| 205 | */ |
| 206 | bool GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, |
| 207 | Instruction::Code op); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 208 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 209 | /** |
| 210 | * @brief Generate a long arithmetic operation. |
| 211 | * @param rl_dest The destination. |
| 212 | * @param rl_src1 First operand. |
| 213 | * @param rl_src2 Second operand. |
| 214 | * @param op The DEX opcode for the operation. |
| 215 | * @param is_commutative The sources can be swapped if needed. |
| 216 | */ |
| 217 | virtual void GenLongArith(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, |
| 218 | Instruction::Code op, bool is_commutative); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 219 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 220 | /** |
| 221 | * @brief Generate a two operand long arithmetic operation. |
| 222 | * @param rl_dest The destination. |
| 223 | * @param rl_src Second operand. |
| 224 | * @param op The DEX opcode for the operation. |
| 225 | */ |
| 226 | void GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 227 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 228 | /** |
| 229 | * @brief Generate a long operation. |
| 230 | * @param rl_dest The destination. Must be in a register |
| 231 | * @param rl_src The other operand. May be in a register or in memory. |
| 232 | * @param op The DEX opcode for the operation. |
| 233 | */ |
| 234 | virtual void GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 235 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 236 | /** |
| 237 | * @brief Implement instanceof a final class with x86 specific code. |
| 238 | * @param use_declaring_class 'true' if we can use the class itself. |
| 239 | * @param type_idx Type index to use if use_declaring_class is 'false'. |
| 240 | * @param rl_dest Result to be set to 0 or 1. |
| 241 | * @param rl_src Object to be tested. |
| 242 | */ |
| 243 | void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, |
| 244 | RegLocation rl_src); |
| 245 | /* |
| 246 | * |
| 247 | * @brief Implement Set up instanceof a class with x86 specific code. |
| 248 | * @param needs_access_check 'true' if we must check the access. |
| 249 | * @param type_known_final 'true' if the type is known to be a final class. |
| 250 | * @param type_known_abstract 'true' if the type is known to be an abstract class. |
| 251 | * @param use_declaring_class 'true' if the type can be loaded off the current Method*. |
| 252 | * @param can_assume_type_is_in_dex_cache 'true' if the type is known to be in the cache. |
| 253 | * @param type_idx Type index to use if use_declaring_class is 'false'. |
| 254 | * @param rl_dest Result to be set to 0 or 1. |
| 255 | * @param rl_src Object to be tested. |
| 256 | */ |
| 257 | void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, |
| 258 | bool type_known_abstract, bool use_declaring_class, |
| 259 | bool can_assume_type_is_in_dex_cache, |
| 260 | uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src); |
Mark Mendell | 6607d97 | 2014-02-10 06:54:18 -0800 | [diff] [blame] | 261 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 262 | void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, |
| 263 | RegLocation rl_src1, RegLocation rl_shift); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 264 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 265 | // Single operation generators. |
| 266 | LIR* OpUnconditionalBranch(LIR* target); |
| 267 | LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target); |
| 268 | LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target); |
| 269 | LIR* OpCondBranch(ConditionCode cc, LIR* target); |
| 270 | LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target); |
| 271 | LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src); |
| 272 | LIR* OpIT(ConditionCode cond, const char* guide); |
| 273 | void OpEndIT(LIR* it); |
| 274 | LIR* OpMem(OpKind op, RegStorage r_base, int disp); |
| 275 | LIR* OpPcRelLoad(RegStorage reg, LIR* target); |
| 276 | LIR* OpReg(OpKind op, RegStorage r_dest_src); |
| 277 | void OpRegCopy(RegStorage r_dest, RegStorage r_src); |
| 278 | LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src); |
| 279 | LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value); |
| 280 | LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset); |
| 281 | LIR* OpRegMem(OpKind op, RegStorage r_dest, RegLocation value); |
| 282 | LIR* OpMemReg(OpKind op, RegLocation rl_dest, int value); |
| 283 | LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2); |
| 284 | LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type); |
| 285 | LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); |
| 286 | LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src); |
| 287 | LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value); |
| 288 | LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2); |
| 289 | LIR* OpTestSuspend(LIR* target); |
| 290 | LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) OVERRIDE; |
| 291 | LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) OVERRIDE; |
| 292 | LIR* OpVldm(RegStorage r_base, int count); |
| 293 | LIR* OpVstm(RegStorage r_base, int count); |
| 294 | void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset); |
| 295 | void OpRegCopyWide(RegStorage dest, RegStorage src); |
| 296 | void OpTlsCmp(ThreadOffset<4> offset, int val) OVERRIDE; |
| 297 | void OpTlsCmp(ThreadOffset<8> offset, int val) OVERRIDE; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 298 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 299 | void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset); |
| 300 | void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<8> thread_offset); |
| 301 | void SpillCoreRegs(); |
| 302 | void UnSpillCoreRegs(); |
| 303 | static const X86EncodingMap EncodingMap[kX86Last]; |
| 304 | bool InexpensiveConstantInt(int32_t value); |
| 305 | bool InexpensiveConstantFloat(int32_t value); |
| 306 | bool InexpensiveConstantLong(int64_t value); |
| 307 | bool InexpensiveConstantDouble(int64_t value); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 308 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 309 | /* |
| 310 | * @brief Should try to optimize for two address instructions? |
| 311 | * @return true if we try to avoid generating three operand instructions. |
| 312 | */ |
| 313 | virtual bool GenerateTwoOperandInstructions() const { return true; } |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 314 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 315 | /* |
| 316 | * @brief x86 specific codegen for int operations. |
| 317 | * @param opcode Operation to perform. |
| 318 | * @param rl_dest Destination for the result. |
| 319 | * @param rl_lhs Left hand operand. |
| 320 | * @param rl_rhs Right hand operand. |
| 321 | */ |
| 322 | void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_lhs, |
| 323 | RegLocation rl_rhs); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 324 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 325 | /* |
| 326 | * @brief Dump a RegLocation using printf |
| 327 | * @param loc Register location to dump |
| 328 | */ |
| 329 | static void DumpRegLocation(RegLocation loc); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 330 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 331 | /* |
| 332 | * @brief Load the Method* of a dex method into the register. |
| 333 | * @param target_method The MethodReference of the method to be invoked. |
| 334 | * @param type How the method will be invoked. |
| 335 | * @param register that will contain the code address. |
| 336 | * @note register will be passed to TargetReg to get physical register. |
| 337 | */ |
| 338 | void LoadMethodAddress(const MethodReference& target_method, InvokeType type, |
| 339 | SpecialTargetRegister symbolic_reg); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 340 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 341 | /* |
| 342 | * @brief Load the Class* of a Dex Class type into the register. |
| 343 | * @param type How the method will be invoked. |
| 344 | * @param register that will contain the code address. |
| 345 | * @note register will be passed to TargetReg to get physical register. |
| 346 | */ |
| 347 | void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 348 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 349 | void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 350 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 351 | int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 352 | NextCallInsn next_call_insn, |
| 353 | const MethodReference& target_method, |
| 354 | uint32_t vtable_idx, |
| 355 | uintptr_t direct_code, uintptr_t direct_method, InvokeType type, |
| 356 | bool skip_this); |
| 357 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 358 | int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, |
| 359 | NextCallInsn next_call_insn, |
| 360 | const MethodReference& target_method, |
| 361 | uint32_t vtable_idx, |
| 362 | uintptr_t direct_code, uintptr_t direct_method, InvokeType type, |
| 363 | bool skip_this); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 364 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 365 | /* |
| 366 | * @brief Generate a relative call to the method that will be patched at link time. |
| 367 | * @param target_method The MethodReference of the method to be invoked. |
| 368 | * @param type How the method will be invoked. |
| 369 | * @returns Call instruction |
| 370 | */ |
| 371 | virtual LIR * CallWithLinkerFixup(const MethodReference& target_method, InvokeType type); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 372 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 373 | /* |
| 374 | * @brief Handle x86 specific literals |
| 375 | */ |
| 376 | void InstallLiteralPools(); |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 377 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 378 | /* |
| 379 | * @brief Generate the debug_frame CFI information. |
| 380 | * @returns pointer to vector containing CFE information |
| 381 | */ |
| 382 | static std::vector<uint8_t>* ReturnCommonCallFrameInformation(); |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 383 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 384 | /* |
| 385 | * @brief Generate the debug_frame FDE information. |
| 386 | * @returns pointer to vector containing CFE information |
| 387 | */ |
| 388 | std::vector<uint8_t>* ReturnCallFrameInformation(); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 389 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 390 | protected: |
| 391 | size_t ComputeSize(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_index, |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 392 | int32_t raw_base, int32_t displacement); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 393 | void CheckValidByteRegister(const X86EncodingMap* entry, int32_t raw_reg); |
| 394 | void EmitPrefix(const X86EncodingMap* entry, |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 395 | int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 396 | void EmitOpcode(const X86EncodingMap* entry); |
| 397 | void EmitPrefixAndOpcode(const X86EncodingMap* entry, |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 398 | int32_t reg_r, int32_t reg_x, int32_t reg_b); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 399 | void EmitDisp(uint8_t base, int32_t disp); |
| 400 | void EmitModrmThread(uint8_t reg_or_opcode); |
| 401 | void EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int32_t disp); |
| 402 | void EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, int scale, |
| 403 | int32_t disp); |
| 404 | void EmitImm(const X86EncodingMap* entry, int64_t imm); |
| 405 | void EmitNullary(const X86EncodingMap* entry); |
| 406 | void EmitOpRegOpcode(const X86EncodingMap* entry, int32_t raw_reg); |
| 407 | void EmitOpReg(const X86EncodingMap* entry, int32_t raw_reg); |
| 408 | void EmitOpMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp); |
| 409 | void EmitOpArray(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, |
| 410 | int32_t disp); |
| 411 | void EmitMemReg(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_reg); |
| 412 | void EmitRegMem(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, int32_t disp); |
| 413 | void EmitRegArray(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, |
| 414 | int32_t raw_index, int scale, int32_t disp); |
| 415 | void EmitArrayReg(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, |
| 416 | int32_t disp, int32_t raw_reg); |
| 417 | void EmitMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm); |
| 418 | void EmitArrayImm(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, |
| 419 | int32_t raw_disp, int32_t imm); |
| 420 | void EmitRegThread(const X86EncodingMap* entry, int32_t raw_reg, int32_t disp); |
| 421 | void EmitRegReg(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2); |
| 422 | void EmitRegRegImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t imm); |
| 423 | void EmitRegMemImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, |
| 424 | int32_t imm); |
| 425 | void EmitMemRegImm(const X86EncodingMap* entry, int32_t base, int32_t disp, int32_t raw_reg1, |
| 426 | int32_t imm); |
| 427 | void EmitRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); |
| 428 | void EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm); |
| 429 | void EmitMovRegImm(const X86EncodingMap* entry, int32_t raw_reg, int64_t imm); |
| 430 | void EmitShiftRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); |
| 431 | void EmitShiftRegCl(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_cl); |
| 432 | void EmitShiftMemCl(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_cl); |
| 433 | void EmitShiftMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm); |
| 434 | void EmitRegCond(const X86EncodingMap* entry, int32_t raw_reg, int32_t cc); |
| 435 | void EmitMemCond(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t cc); |
| 436 | void EmitRegRegCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t cc); |
| 437 | void EmitRegMemCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, |
| 438 | int32_t cc); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 439 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 440 | void EmitJmp(const X86EncodingMap* entry, int32_t rel); |
| 441 | void EmitJcc(const X86EncodingMap* entry, int32_t rel, int32_t cc); |
| 442 | void EmitCallMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp); |
| 443 | void EmitCallImmediate(const X86EncodingMap* entry, int32_t disp); |
| 444 | void EmitCallThread(const X86EncodingMap* entry, int32_t disp); |
| 445 | void EmitPcRel(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base_or_table, |
| 446 | int32_t raw_index, int scale, int32_t table_or_disp); |
| 447 | void EmitMacro(const X86EncodingMap* entry, int32_t raw_reg, int32_t offset); |
| 448 | void EmitUnimplemented(const X86EncodingMap* entry, LIR* lir); |
| 449 | void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, |
| 450 | int64_t val, ConditionCode ccode); |
| 451 | void GenConstWide(RegLocation rl_dest, int64_t value); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 452 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 453 | static bool ProvidesFullMemoryBarrier(X86OpCode opcode); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 454 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 455 | /* |
| 456 | * @brief Ensure that a temporary register is byte addressable. |
| 457 | * @returns a temporary guarenteed to be byte addressable. |
| 458 | */ |
| 459 | virtual RegStorage AllocateByteRegister(); |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 460 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 461 | /* |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 462 | * @brief Check if a register is byte addressable. |
| 463 | * @returns true if a register is byte addressable. |
| 464 | */ |
| 465 | bool IsByteRegister(RegStorage reg); |
| 466 | |
| 467 | /* |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 468 | * @brief generate inline code for fast case of Strng.indexOf. |
| 469 | * @param info Call parameters |
| 470 | * @param zero_based 'true' if the index into the string is 0. |
| 471 | * @returns 'true' if the call was inlined, 'false' if a regular call needs to be |
| 472 | * generated. |
| 473 | */ |
| 474 | bool GenInlinedIndexOf(CallInfo* info, bool zero_based); |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 475 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 476 | /* |
| 477 | * @brief Load 128 bit constant into vector register. |
| 478 | * @param bb The basic block in which the MIR is from. |
| 479 | * @param mir The MIR whose opcode is kMirConstVector |
| 480 | * @note vA is the TypeSize for the register. |
| 481 | * @note vB is the destination XMM register. arg[0..3] are 32 bit constant values. |
| 482 | */ |
| 483 | void GenConst128(BasicBlock* bb, MIR* mir); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 484 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 485 | /* |
| 486 | * @brief MIR to move a vectorized register to another. |
| 487 | * @param bb The basic block in which the MIR is from. |
| 488 | * @param mir The MIR whose opcode is kMirConstVector. |
| 489 | * @note vA: TypeSize |
| 490 | * @note vB: destination |
| 491 | * @note vC: source |
| 492 | */ |
| 493 | void GenMoveVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 494 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 495 | /* |
| 496 | * @brief Packed multiply of units in two vector registers: vB = vB .* @note vC using vA to know the type of the vector. |
| 497 | * @param bb The basic block in which the MIR is from. |
| 498 | * @param mir The MIR whose opcode is kMirConstVector. |
| 499 | * @note vA: TypeSize |
| 500 | * @note vB: destination and source |
| 501 | * @note vC: source |
| 502 | */ |
| 503 | void GenMultiplyVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 504 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 505 | /* |
| 506 | * @brief Packed addition of units in two vector registers: vB = vB .+ vC using vA to know the type of the vector. |
| 507 | * @param bb The basic block in which the MIR is from. |
| 508 | * @param mir The MIR whose opcode is kMirConstVector. |
| 509 | * @note vA: TypeSize |
| 510 | * @note vB: destination and source |
| 511 | * @note vC: source |
| 512 | */ |
| 513 | void GenAddVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 514 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 515 | /* |
| 516 | * @brief Packed subtraction of units in two vector registers: vB = vB .- vC using vA to know the type of the vector. |
| 517 | * @param bb The basic block in which the MIR is from. |
| 518 | * @param mir The MIR whose opcode is kMirConstVector. |
| 519 | * @note vA: TypeSize |
| 520 | * @note vB: destination and source |
| 521 | * @note vC: source |
| 522 | */ |
| 523 | void GenSubtractVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 524 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 525 | /* |
| 526 | * @brief Packed shift left of units in two vector registers: vB = vB .<< vC using vA to know the type of the vector. |
| 527 | * @param bb The basic block in which the MIR is from. |
| 528 | * @param mir The MIR whose opcode is kMirConstVector. |
| 529 | * @note vA: TypeSize |
| 530 | * @note vB: destination and source |
| 531 | * @note vC: immediate |
| 532 | */ |
| 533 | void GenShiftLeftVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 534 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 535 | /* |
| 536 | * @brief Packed signed shift right of units in two vector registers: vB = vB .>> vC using vA to know the type of the vector. |
| 537 | * @param bb The basic block in which the MIR is from. |
| 538 | * @param mir The MIR whose opcode is kMirConstVector. |
| 539 | * @note vA: TypeSize |
| 540 | * @note vB: destination and source |
| 541 | * @note vC: immediate |
| 542 | */ |
| 543 | void GenSignedShiftRightVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 544 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 545 | /* |
| 546 | * @brief Packed unsigned shift right of units in two vector registers: vB = vB .>>> vC using vA to know the type of the vector. |
| 547 | * @param bb The basic block in which the MIR is from.. |
| 548 | * @param mir The MIR whose opcode is kMirConstVector. |
| 549 | * @note vA: TypeSize |
| 550 | * @note vB: destination and source |
| 551 | * @note vC: immediate |
| 552 | */ |
| 553 | void GenUnsignedShiftRightVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 554 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 555 | /* |
| 556 | * @brief Packed bitwise and of units in two vector registers: vB = vB .& vC using vA to know the type of the vector. |
| 557 | * @note vA: TypeSize |
| 558 | * @note vB: destination and source |
| 559 | * @note vC: source |
| 560 | */ |
| 561 | void GenAndVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 562 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 563 | /* |
| 564 | * @brief Packed bitwise or of units in two vector registers: vB = vB .| vC using vA to know the type of the vector. |
| 565 | * @param bb The basic block in which the MIR is from. |
| 566 | * @param mir The MIR whose opcode is kMirConstVector. |
| 567 | * @note vA: TypeSize |
| 568 | * @note vB: destination and source |
| 569 | * @note vC: source |
| 570 | */ |
| 571 | void GenOrVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 572 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 573 | /* |
| 574 | * @brief Packed bitwise xor of units in two vector registers: vB = vB .^ vC using vA to know the type of the vector. |
| 575 | * @param bb The basic block in which the MIR is from. |
| 576 | * @param mir The MIR whose opcode is kMirConstVector. |
| 577 | * @note vA: TypeSize |
| 578 | * @note vB: destination and source |
| 579 | * @note vC: source |
| 580 | */ |
| 581 | void GenXorVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 582 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 583 | /* |
| 584 | * @brief Reduce a 128-bit packed element into a single VR by taking lower bits |
| 585 | * @param bb The basic block in which the MIR is from. |
| 586 | * @param mir The MIR whose opcode is kMirConstVector. |
| 587 | * @details Instruction does a horizontal addition of the packed elements and then adds it to VR. |
| 588 | * @note vA: TypeSize |
| 589 | * @note vB: destination and source VR (not vector register) |
| 590 | * @note vC: source (vector register) |
| 591 | */ |
| 592 | void GenAddReduceVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 593 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 594 | /* |
| 595 | * @brief Extract a packed element into a single VR. |
| 596 | * @param bb The basic block in which the MIR is from. |
| 597 | * @param mir The MIR whose opcode is kMirConstVector. |
| 598 | * @note vA: TypeSize |
| 599 | * @note vB: destination VR (not vector register) |
| 600 | * @note vC: source (vector register) |
| 601 | * @note arg[0]: The index to use for extraction from vector register (which packed element). |
| 602 | */ |
| 603 | void GenReduceVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 604 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 605 | /* |
| 606 | * @brief Create a vector value, with all TypeSize values equal to vC |
| 607 | * @param bb The basic block in which the MIR is from. |
| 608 | * @param mir The MIR whose opcode is kMirConstVector. |
| 609 | * @note vA: TypeSize. |
| 610 | * @note vB: destination vector register. |
| 611 | * @note vC: source VR (not vector register). |
| 612 | */ |
| 613 | void GenSetVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 614 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 615 | /* |
| 616 | * @brief Generate code for a vector opcode. |
| 617 | * @param bb The basic block in which the MIR is from. |
| 618 | * @param mir The MIR whose opcode is a non-standard opcode. |
| 619 | */ |
| 620 | void GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 621 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 622 | /* |
| 623 | * @brief Return the correct x86 opcode for the Dex operation |
| 624 | * @param op Dex opcode for the operation |
| 625 | * @param loc Register location of the operand |
| 626 | * @param is_high_op 'true' if this is an operation on the high word |
| 627 | * @param value Immediate value for the operation. Used for byte variants |
| 628 | * @returns the correct x86 opcode to perform the operation |
| 629 | */ |
| 630 | X86OpCode GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, int32_t value); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 631 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 632 | /* |
| 633 | * @brief Return the correct x86 opcode for the Dex operation |
| 634 | * @param op Dex opcode for the operation |
| 635 | * @param dest location of the destination. May be register or memory. |
| 636 | * @param rhs Location for the rhs of the operation. May be in register or memory. |
| 637 | * @param is_high_op 'true' if this is an operation on the high word |
| 638 | * @returns the correct x86 opcode to perform the operation |
| 639 | * @note at most one location may refer to memory |
| 640 | */ |
| 641 | X86OpCode GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, |
| 642 | bool is_high_op); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 643 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 644 | /* |
| 645 | * @brief Is this operation a no-op for this opcode and value |
| 646 | * @param op Dex opcode for the operation |
| 647 | * @param value Immediate value for the operation. |
| 648 | * @returns 'true' if the operation will have no effect |
| 649 | */ |
| 650 | bool IsNoOp(Instruction::Code op, int32_t value); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 651 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 652 | /** |
| 653 | * @brief Calculate magic number and shift for a given divisor |
| 654 | * @param divisor divisor number for calculation |
| 655 | * @param magic hold calculated magic number |
| 656 | * @param shift hold calculated shift |
| 657 | */ |
| 658 | void CalculateMagicAndShift(int divisor, int& magic, int& shift); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 659 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 660 | /* |
| 661 | * @brief Generate an integer div or rem operation. |
| 662 | * @param rl_dest Destination Location. |
| 663 | * @param rl_src1 Numerator Location. |
| 664 | * @param rl_src2 Divisor Location. |
| 665 | * @param is_div 'true' if this is a division, 'false' for a remainder. |
| 666 | * @param check_zero 'true' if an exception should be generated if the divisor is 0. |
| 667 | */ |
| 668 | RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, |
| 669 | bool is_div, bool check_zero); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 670 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 671 | /* |
| 672 | * @brief Generate an integer div or rem operation by a literal. |
| 673 | * @param rl_dest Destination Location. |
| 674 | * @param rl_src Numerator Location. |
| 675 | * @param lit Divisor. |
| 676 | * @param is_div 'true' if this is a division, 'false' for a remainder. |
| 677 | */ |
| 678 | RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, int lit, bool is_div); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 679 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 680 | /* |
| 681 | * Generate code to implement long shift operations. |
| 682 | * @param opcode The DEX opcode to specify the shift type. |
| 683 | * @param rl_dest The destination. |
| 684 | * @param rl_src The value to be shifted. |
| 685 | * @param shift_amount How much to shift. |
| 686 | * @returns the RegLocation of the result. |
| 687 | */ |
| 688 | RegLocation GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
| 689 | RegLocation rl_src, int shift_amount); |
| 690 | /* |
| 691 | * Generate an imul of a register by a constant or a better sequence. |
| 692 | * @param dest Destination Register. |
| 693 | * @param src Source Register. |
| 694 | * @param val Constant multiplier. |
| 695 | */ |
| 696 | void GenImulRegImm(RegStorage dest, RegStorage src, int val); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 697 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 698 | /* |
| 699 | * Generate an imul of a memory location by a constant or a better sequence. |
| 700 | * @param dest Destination Register. |
| 701 | * @param sreg Symbolic register. |
| 702 | * @param displacement Displacement on stack of Symbolic Register. |
| 703 | * @param val Constant multiplier. |
| 704 | */ |
| 705 | void GenImulMemImm(RegStorage dest, int sreg, int displacement, int val); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 706 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 707 | /* |
| 708 | * @brief Compare memory to immediate, and branch if condition true. |
| 709 | * @param cond The condition code that when true will branch to the target. |
| 710 | * @param temp_reg A temporary register that can be used if compare memory is not |
| 711 | * supported by the architecture. |
| 712 | * @param base_reg The register holding the base address. |
| 713 | * @param offset The offset from the base. |
| 714 | * @param check_value The immediate to compare to. |
| 715 | */ |
| 716 | LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, |
| 717 | int offset, int check_value, LIR* target); |
Mark Mendell | 766e929 | 2014-01-27 07:55:47 -0800 | [diff] [blame] | 718 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 719 | /* |
| 720 | * Can this operation be using core registers without temporaries? |
| 721 | * @param rl_lhs Left hand operand. |
| 722 | * @param rl_rhs Right hand operand. |
| 723 | * @returns 'true' if the operation can proceed without needing temporary regs. |
| 724 | */ |
| 725 | bool IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs); |
Razvan A Lupusoru | 614c2b4 | 2014-01-28 17:05:21 -0800 | [diff] [blame] | 726 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 727 | /** |
| 728 | * @brief Generates inline code for conversion of long to FP by using x87/ |
| 729 | * @param rl_dest The destination of the FP. |
| 730 | * @param rl_src The source of the long. |
| 731 | * @param is_double 'true' if dealing with double, 'false' for float. |
| 732 | */ |
| 733 | virtual void GenLongToFP(RegLocation rl_dest, RegLocation rl_src, bool is_double); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 734 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 735 | /* |
| 736 | * @brief Perform MIR analysis before compiling method. |
| 737 | * @note Invokes Mir2LiR::Materialize after analysis. |
| 738 | */ |
| 739 | void Materialize(); |
Razvan A Lupusoru | 614c2b4 | 2014-01-28 17:05:21 -0800 | [diff] [blame] | 740 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 741 | /* |
| 742 | * Mir2Lir's UpdateLoc() looks to see if the Dalvik value is currently live in any temp register |
| 743 | * without regard to data type. In practice, this can result in UpdateLoc returning a |
| 744 | * location record for a Dalvik float value in a core register, and vis-versa. For targets |
| 745 | * which can inexpensively move data between core and float registers, this can often be a win. |
| 746 | * However, for x86 this is generally not a win. These variants of UpdateLoc() |
| 747 | * take a register class argument - and will return an in-register location record only if |
| 748 | * the value is live in a temp register of the correct class. Additionally, if the value is in |
| 749 | * a temp register of the wrong register class, it will be clobbered. |
| 750 | */ |
| 751 | RegLocation UpdateLocTyped(RegLocation loc, int reg_class); |
| 752 | RegLocation UpdateLocWideTyped(RegLocation loc, int reg_class); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 753 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 754 | /* |
| 755 | * @brief Analyze MIR before generating code, to prepare for the code generation. |
| 756 | */ |
| 757 | void AnalyzeMIR(); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 758 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 759 | /* |
| 760 | * @brief Analyze one basic block. |
| 761 | * @param bb Basic block to analyze. |
| 762 | */ |
| 763 | void AnalyzeBB(BasicBlock * bb); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 764 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 765 | /* |
| 766 | * @brief Analyze one extended MIR instruction |
| 767 | * @param opcode MIR instruction opcode. |
| 768 | * @param bb Basic block containing instruction. |
| 769 | * @param mir Extended instruction to analyze. |
| 770 | */ |
| 771 | void AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 772 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 773 | /* |
| 774 | * @brief Analyze one MIR instruction |
| 775 | * @param opcode MIR instruction opcode. |
| 776 | * @param bb Basic block containing instruction. |
| 777 | * @param mir Instruction to analyze. |
| 778 | */ |
| 779 | virtual void AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 780 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 781 | /* |
| 782 | * @brief Analyze one MIR float/double instruction |
| 783 | * @param opcode MIR instruction opcode. |
| 784 | * @param bb Basic block containing instruction. |
| 785 | * @param mir Instruction to analyze. |
| 786 | */ |
| 787 | void AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 788 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 789 | /* |
| 790 | * @brief Analyze one use of a double operand. |
| 791 | * @param rl_use Double RegLocation for the operand. |
| 792 | */ |
| 793 | void AnalyzeDoubleUse(RegLocation rl_use); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 794 | |
Yixin Shou | 7071c8d | 2014-03-05 06:07:48 -0500 | [diff] [blame] | 795 | /* |
| 796 | * @brief Analyze one invoke-static MIR instruction |
| 797 | * @param opcode MIR instruction opcode. |
| 798 | * @param bb Basic block containing instruction. |
| 799 | * @param mir Instruction to analyze. |
| 800 | */ |
| 801 | void AnalyzeInvokeStatic(int opcode, BasicBlock * bb, MIR *mir); |
| 802 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 803 | // Information derived from analysis of MIR |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 804 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 805 | // The compiler temporary for the code address of the method. |
| 806 | CompilerTemp *base_of_code_; |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 807 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 808 | // Have we decided to compute a ptr to code and store in temporary VR? |
| 809 | bool store_method_addr_; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 810 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 811 | // Have we used the stored method address? |
| 812 | bool store_method_addr_used_; |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 813 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 814 | // Instructions to remove if we didn't use the stored method address. |
| 815 | LIR* setup_method_address_[2]; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 816 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 817 | // Instructions needing patching with Method* values. |
| 818 | GrowableArray<LIR*> method_address_insns_; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 819 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 820 | // Instructions needing patching with Class Type* values. |
| 821 | GrowableArray<LIR*> class_type_address_insns_; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 822 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 823 | // Instructions needing patching with PC relative code addresses. |
| 824 | GrowableArray<LIR*> call_method_insns_; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 825 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 826 | // Prologue decrement of stack pointer. |
| 827 | LIR* stack_decrement_; |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 828 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 829 | // Epilogue increment of stack pointer. |
| 830 | LIR* stack_increment_; |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 831 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 832 | // The list of const vector literals. |
| 833 | LIR *const_vectors_; |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 834 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 835 | /* |
| 836 | * @brief Search for a matching vector literal |
| 837 | * @param mir A kMirOpConst128b MIR instruction to match. |
| 838 | * @returns pointer to matching LIR constant, or nullptr if not found. |
| 839 | */ |
| 840 | LIR *ScanVectorLiteral(MIR *mir); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 841 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 842 | /* |
| 843 | * @brief Add a constant vector literal |
| 844 | * @param mir A kMirOpConst128b MIR instruction to match. |
| 845 | */ |
| 846 | LIR *AddVectorLiteral(MIR *mir); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 847 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 848 | InToRegStorageMapping in_to_reg_storage_mapping_; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 849 | }; |
| 850 | |
| 851 | } // namespace art |
| 852 | |
Brian Carlstrom | fc0e321 | 2013-07-17 14:40:12 -0700 | [diff] [blame] | 853 | #endif // ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ |