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gerrit-public.fairphone.software / platform / art / c830430ed65497c2268649d8e78121364e31b184 / . / compiler / dex / quick / arm64 / assemble_arm64.cc
blob: 93caf89d1c707af3aa1570312f20c1b9917c40c2 [file] [log] [blame]
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "arm64_lir.h"
18#include "codegen_arm64.h"
19#include "dex/quick/mir_to_lir-inl.h"
20
21namespace art {
22
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]23// The macros below are exclusively used in the encoding map.
24
25// Most generic way of providing two variants for one instructions.
26#define CUSTOM_VARIANTS(variant1, variant2) variant1, variant2
27
28// Used for instructions which do not have a wide variant.
29#define NO_VARIANTS(variant) \
30 CUSTOM_VARIANTS(variant, 0)
31
32// Used for instructions which have a wide variant with the sf bit set to 1.
33#define SF_VARIANTS(sf0_skeleton) \
34 CUSTOM_VARIANTS(sf0_skeleton, (sf0_skeleton | 0x80000000))
35
36// Used for instructions which have a wide variant with the size bits set to either x0 or x1.
37#define SIZE_VARIANTS(sizex0_skeleton) \
38 CUSTOM_VARIANTS(sizex0_skeleton, (sizex0_skeleton | 0x40000000))
39
40// Used for instructions which have a wide variant with the sf and n bits set to 1.
41#define SF_N_VARIANTS(sf0_n0_skeleton) \
42 CUSTOM_VARIANTS(sf0_n0_skeleton, (sf0_n0_skeleton | 0x80400000))
43
44// Used for FP instructions which have a single and double precision variants, with he type bits set
45// to either 00 or 01.
46#define FLOAT_VARIANTS(type00_skeleton) \
47 CUSTOM_VARIANTS(type00_skeleton, (type00_skeleton | 0x00400000))
48
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]49/*
50 * opcode: ArmOpcode enum
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]51 * variants: instruction skeletons supplied via CUSTOM_VARIANTS or derived macros.
52 * a{n}k: key to applying argument {n} \
53 * a{n}s: argument {n} start bit position | n = 0, 1, 2, 3
54 * a{n}e: argument {n} end bit position /
55 * flags: instruction attributes (used in optimization)
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]56 * name: mnemonic name
57 * fmt: for pretty-printing
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]58 * fixup: used for second-pass fixes (e.g. adresses fixups in branch instructions).
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]59 */
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]60#define ENCODING_MAP(opcode, variants, a0k, a0s, a0e, a1k, a1s, a1e, a2k, a2s, a2e, \
61 a3k, a3s, a3e, flags, name, fmt, fixup) \
62 {variants, {{a0k, a0s, a0e}, {a1k, a1s, a1e}, {a2k, a2s, a2e}, \
63 {a3k, a3s, a3e}}, opcode, flags, name, fmt, 4, fixup}
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]64
65/* Instruction dump string format keys: !pf, where "!" is the start
66 * of the key, "p" is which numeric operand to use and "f" is the
67 * print format.
68 *
69 * [p]ositions:
70 * 0 -> operands[0] (dest)
71 * 1 -> operands[1] (src1)
72 * 2 -> operands[2] (src2)
73 * 3 -> operands[3] (extra)
74 *
75 * [f]ormats:
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]76 * d -> decimal
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]77 * D -> decimal*4 or decimal*8 depending on the instruction width
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]78 * E -> decimal*4
79 * F -> decimal*2
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]80 * G -> ", lsl #2" or ", lsl #3" depending on the instruction width
81 * c -> branch condition (eq, ne, etc.)
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]82 * t -> pc-relative target
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]83 * p -> pc-relative address
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]84 * s -> single precision floating point register
85 * S -> double precision floating point register
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]86 * f -> single or double precision register (depending on instruction width)
87 * I -> 8-bit immediate floating point number
88 * l -> logical immediate
89 * M -> 16-bit shift expression ("" or ", lsl #16" or ", lsl #32"...)
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]90 * B -> dmb option string (sy, st, ish, ishst, nsh, hshst)
91 * H -> operand shift
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]92 * T -> register shift (either ", lsl #0" or ", lsl #12")
93 * e -> register extend (e.g. uxtb #1)
94 * o -> register shift (e.g. lsl #1) for Word registers
95 * w -> word (32-bit) register wn, or wzr
96 * W -> word (32-bit) register wn, or wsp
97 * x -> extended (64-bit) register xn, or xzr
98 * X -> extended (64-bit) register xn, or sp
99 * r -> register with same width as instruction, r31 -> wzr, xzr
100 * R -> register with same width as instruction, r31 -> wsp, sp
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]101 *
102 * [!] escape. To insert "!", use "!!"
103 */
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]104/* NOTE: must be kept in sync with enum ArmOpcode from arm64_lir.h */
105const ArmEncodingMap Arm64Mir2Lir::EncodingMap[kA64Last] = {
106 ENCODING_MAP(WIDE(kA64Adc3rrr), SF_VARIANTS(0x1a000000),
107 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16,
108 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
109 "adc", "!0r, !1r, !2r", kFixupNone),
110 ENCODING_MAP(WIDE(kA64Add4RRdT), SF_VARIANTS(0x11000000),
111 kFmtRegROrSp, 4, 0, kFmtRegROrSp, 9, 5, kFmtBitBlt, 21, 10,
112 kFmtBitBlt, 23, 22, IS_QUAD_OP | REG_DEF0_USE1,
113 "add", "!0R, !1R, #!2d!3T", kFixupNone),
114 ENCODING_MAP(WIDE(kA64Add4rrro), SF_VARIANTS(0x0b000000),
115 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16,
116 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE1,
117 "add", "!0r, !1r, !2r!3o", kFixupNone),
118 // Note: adr is binary, but declared as tertiary. The third argument is used while doing the
119 // fixups and contains information to identify the adr label.
120 ENCODING_MAP(kA64Adr2xd, NO_VARIANTS(0x10000000),
121 kFmtRegX, 4, 0, kFmtImm21, -1, -1, kFmtUnused, -1, -1,
122 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0 | NEEDS_FIXUP,
123 "adr", "!0x, #!1d", kFixupAdr),
124 ENCODING_MAP(WIDE(kA64And3Rrl), SF_VARIANTS(0x12000000),
125 kFmtRegROrSp, 4, 0, kFmtRegR, 9, 5, kFmtBitBlt, 22, 10,
126 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
127 "and", "!0R, !1r, #!2l", kFixupNone),
128 ENCODING_MAP(WIDE(kA64And4rrro), SF_VARIANTS(0x0a000000),
129 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16,
130 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
131 "and", "!0r, !1r, !2r!3o", kFixupNone),
132 ENCODING_MAP(WIDE(kA64Asr3rrd), CUSTOM_VARIANTS(0x13007c00, 0x9340fc00),
133 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtBitBlt, 21, 16,
134 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
135 "asr", "!0r, !1r, #!2d", kFixupNone),
136 ENCODING_MAP(WIDE(kA64Asr3rrr), SF_VARIANTS(0x1ac02800),
137 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16,
138 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
139 "asr", "!0r, !1r, !2r", kFixupNone),
140 ENCODING_MAP(kA64B2ct, NO_VARIANTS(0x54000000),
141 kFmtBitBlt, 3, 0, kFmtBitBlt, 23, 5, kFmtUnused, -1, -1,
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]142 kFmtUnused, -1, -1, IS_BINARY_OP | IS_BRANCH | USES_CCODES |
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]143 NEEDS_FIXUP, "b.!0c", "!1t", kFixupCondBranch),
144 ENCODING_MAP(kA64Blr1x, NO_VARIANTS(0xd63f0000),
145 kFmtRegX, 9, 5, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]146 kFmtUnused, -1, -1,
147 IS_UNARY_OP | REG_USE0 | IS_BRANCH | REG_DEF_LR,
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]148 "blr", "!0x", kFixupNone),
149 ENCODING_MAP(kA64Br1x, NO_VARIANTS(0xd61f0000),
150 kFmtRegX, 9, 5, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
151 kFmtUnused, -1, -1, IS_UNARY_OP | REG_USE0 | IS_BRANCH,
152 "br", "!0x", kFixupNone),
153 ENCODING_MAP(kA64Brk1d, NO_VARIANTS(0xd4200000),
154 kFmtBitBlt, 20, 5, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]155 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH,
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]156 "brk", "!0d", kFixupNone),
157 ENCODING_MAP(kA64B1t, NO_VARIANTS(0x14000000),
158 kFmtBitBlt, 25, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
159 kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP,
160 "b", "!0t", kFixupT1Branch),
161 ENCODING_MAP(WIDE(kA64Cbnz2rt), SF_VARIANTS(0x35000000),
162 kFmtRegR, 4, 0, kFmtBitBlt, 23, 5, kFmtUnused, -1, -1,
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]163 kFmtUnused, -1, -1,
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]164 IS_BINARY_OP | REG_USE0 | IS_BRANCH | NEEDS_FIXUP,
165 "cbnz", "!0r, !1t", kFixupCBxZ),
166 ENCODING_MAP(WIDE(kA64Cbz2rt), SF_VARIANTS(0x34000000),
167 kFmtRegR, 4, 0, kFmtBitBlt, 23, 5, kFmtUnused, -1, -1,
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]168 kFmtUnused, -1, -1,
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]169 IS_BINARY_OP | REG_USE0 | IS_BRANCH | NEEDS_FIXUP,
170 "cbz", "!0r, !1t", kFixupCBxZ),
171 ENCODING_MAP(WIDE(kA64Cmn3Rro), SF_VARIANTS(0x6b20001f),
172 kFmtRegROrSp, 9, 5, kFmtRegR, 20, 16, kFmtShift, -1, -1,
173 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | SETS_CCODES,
174 "cmn", "!0R, !1r!2o", kFixupNone),
175 ENCODING_MAP(WIDE(kA64Cmn3RdT), SF_VARIANTS(0x3100001f),
176 kFmtRegROrSp, 9, 5, kFmtBitBlt, 21, 10, kFmtBitBlt, 23, 22,
177 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE0 | SETS_CCODES,
178 "cmn", "!0R, #!1d!2T", kFixupNone),
Zheng Xuc8304302014-05-15 17:21:01 +0100[diff] [blame^]179 ENCODING_MAP(WIDE(kA64Cmp3Rro), SF_VARIANTS(0x6b00001f),
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]180 kFmtRegROrSp, 9, 5, kFmtRegR, 20, 16, kFmtShift, -1, -1,
181 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | SETS_CCODES,
182 "cmp", "!0R, !1r!2o", kFixupNone),
183 ENCODING_MAP(WIDE(kA64Cmp3RdT), SF_VARIANTS(0x7100001f),
184 kFmtRegROrSp, 9, 5, kFmtBitBlt, 21, 10, kFmtBitBlt, 23, 22,
185 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE0 | SETS_CCODES,
186 "cmp", "!0R, #!1d!2T", kFixupNone),
187 ENCODING_MAP(WIDE(kA64Csel4rrrc), SF_VARIANTS(0x1a800000),
188 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16,
189 kFmtBitBlt, 15, 12, IS_QUAD_OP | REG_DEF0_USE12 | USES_CCODES,
190 "csel", "!0r, !1r, !2r, !3c", kFixupNone),
191 ENCODING_MAP(WIDE(kA64Csinc4rrrc), SF_VARIANTS(0x1a800400),
192 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16,
193 kFmtBitBlt, 15, 12, IS_QUAD_OP | REG_DEF0_USE12 | USES_CCODES,
194 "csinc", "!0r, !1r, !2r, !3c", kFixupNone),
195 ENCODING_MAP(WIDE(kA64Csneg4rrrc), SF_VARIANTS(0x5a800400),
196 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16,
197 kFmtBitBlt, 15, 12, IS_QUAD_OP | REG_DEF0_USE12 | USES_CCODES,
198 "csneg", "!0r, !1r, !2r, !3c", kFixupNone),
199 ENCODING_MAP(kA64Dmb1B, NO_VARIANTS(0xd50330bf),
200 kFmtBitBlt, 11, 8, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]201 kFmtUnused, -1, -1, IS_UNARY_OP,
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]202 "dmb", "#!0B", kFixupNone),
203 ENCODING_MAP(WIDE(kA64Eor3Rrl), SF_VARIANTS(0x52000000),
204 kFmtRegROrSp, 4, 0, kFmtRegR, 9, 5, kFmtBitBlt, 22, 10,
205 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
206 "eor", "!0R, !1r, #!2l", kFixupNone),
207 ENCODING_MAP(WIDE(kA64Eor4rrro), SF_VARIANTS(0x4a000000),
208 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16,
209 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
210 "eor", "!0r, !1r, !2r!3o", kFixupNone),
211 ENCODING_MAP(WIDE(kA64Extr4rrrd), SF_N_VARIANTS(0x13800000),
212 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16,
213 kFmtBitBlt, 15, 10, IS_QUAD_OP | REG_DEF0_USE12,
214 "extr", "!0r, !1r, !2r, #!3d", kFixupNone),
215 ENCODING_MAP(FWIDE(kA64Fabs2ff), FLOAT_VARIANTS(0x1e20c000),
216 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtUnused, -1, -1,
217 kFmtUnused, -1, -1, IS_BINARY_OP| REG_DEF0_USE1,
218 "fabs", "!0f, !1f", kFixupNone),
219 ENCODING_MAP(FWIDE(kA64Fadd3fff), FLOAT_VARIANTS(0x1e202800),
220 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtRegF, 20, 16,
221 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
222 "fadd", "!0f, !1f, !2f", kFixupNone),
223 ENCODING_MAP(FWIDE(kA64Fcmp1f), FLOAT_VARIANTS(0x1e202008),
224 kFmtRegF, 9, 5, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
225 kFmtUnused, -1, -1, IS_UNARY_OP | REG_USE0 | SETS_CCODES,
226 "fcmp", "!0f, #0", kFixupNone),
227 ENCODING_MAP(FWIDE(kA64Fcmp2ff), FLOAT_VARIANTS(0x1e202000),
228 kFmtRegF, 9, 5, kFmtRegF, 20, 16, kFmtUnused, -1, -1,
229 kFmtUnused, -1, -1, IS_BINARY_OP | REG_USE01 | SETS_CCODES,
230 "fcmp", "!0f, !1f", kFixupNone),
231 ENCODING_MAP(FWIDE(kA64Fcvtzs2wf), FLOAT_VARIANTS(0x1e380000),
232 kFmtRegW, 4, 0, kFmtRegF, 9, 5, kFmtUnused, -1, -1,
233 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
234 "fcvtzs", "!0w, !1f", kFixupNone),
235 ENCODING_MAP(FWIDE(kA64Fcvtzs2xf), FLOAT_VARIANTS(0x9e380000),
236 kFmtRegX, 4, 0, kFmtRegF, 9, 5, kFmtUnused, -1, -1,
237 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
238 "fcvtzs", "!0x, !1f", kFixupNone),
239 ENCODING_MAP(kA64Fcvt2Ss, NO_VARIANTS(0x1e22C000),
240 kFmtRegD, 4, 0, kFmtRegS, 9, 5, kFmtUnused, -1, -1,
241 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
242 "fcvt", "!0S, !1s", kFixupNone),
243 ENCODING_MAP(kA64Fcvt2sS, NO_VARIANTS(0x1e624000),
244 kFmtRegS, 4, 0, kFmtRegD, 9, 5, kFmtUnused, -1, -1,
245 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
246 "fcvt", "!0s, !1S", kFixupNone),
247 ENCODING_MAP(FWIDE(kA64Fdiv3fff), FLOAT_VARIANTS(0x1e201800),
248 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtRegF, 20, 16,
249 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
250 "fdiv", "!0f, !1f, !2f", kFixupNone),
251 ENCODING_MAP(FWIDE(kA64Fmov2ff), FLOAT_VARIANTS(0x1e204000),
252 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtUnused, -1, -1,
253 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
254 "fmov", "!0f, !1f", kFixupNone),
255 ENCODING_MAP(FWIDE(kA64Fmov2fI), FLOAT_VARIANTS(0x1e201000),
256 kFmtRegF, 4, 0, kFmtBitBlt, 20, 13, kFmtUnused, -1, -1,
257 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
258 "fmov", "!0f, #!1I", kFixupNone),
259 ENCODING_MAP(kA64Fmov2sw, NO_VARIANTS(0x1e270000),
260 kFmtRegS, 4, 0, kFmtRegW, 9, 5, kFmtUnused, -1, -1,
261 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
262 "fmov", "!0s, !1w", kFixupNone),
263 ENCODING_MAP(kA64Fmov2Sx, NO_VARIANTS(0x9e6f0000),
264 kFmtRegD, 4, 0, kFmtRegX, 9, 5, kFmtUnused, -1, -1,
265 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
266 "fmov", "!0S, !1x", kFixupNone),
267 ENCODING_MAP(kA64Fmov2ws, NO_VARIANTS(0x1e260000),
268 kFmtRegW, 4, 0, kFmtRegS, 9, 5, kFmtUnused, -1, -1,
269 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
270 "fmov", "!0w, !1s", kFixupNone),
271 ENCODING_MAP(kA64Fmov2xS, NO_VARIANTS(0x9e6e0000),
272 kFmtRegX, 4, 0, kFmtRegD, 9, 5, kFmtUnused, -1, -1,
273 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
274 "fmov", "!0x, !1S", kFixupNone),
275 ENCODING_MAP(FWIDE(kA64Fmul3fff), FLOAT_VARIANTS(0x1e200800),
276 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtRegF, 20, 16,
277 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
278 "fmul", "!0f, !1f, !2f", kFixupNone),
279 ENCODING_MAP(FWIDE(kA64Fneg2ff), FLOAT_VARIANTS(0x1e214000),
280 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtUnused, -1, -1,
281 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
282 "fneg", "!0f, !1f", kFixupNone),
283 ENCODING_MAP(FWIDE(kA64Frintz2ff), FLOAT_VARIANTS(0x1e25c000),
284 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtUnused, -1, -1,
285 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
286 "frintz", "!0f, !1f", kFixupNone),
287 ENCODING_MAP(FWIDE(kA64Fsqrt2ff), FLOAT_VARIANTS(0x1e61c000),
288 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtUnused, -1, -1,
289 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
290 "fsqrt", "!0f, !1f", kFixupNone),
291 ENCODING_MAP(FWIDE(kA64Fsub3fff), FLOAT_VARIANTS(0x1e203800),
292 kFmtRegF, 4, 0, kFmtRegF, 9, 5, kFmtRegF, 20, 16,
293 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
294 "fsub", "!0f, !1f, !2f", kFixupNone),
295 ENCODING_MAP(kA64Ldrb3wXd, NO_VARIANTS(0x39400000),
296 kFmtRegW, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10,
297 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
298 "ldrb", "!0w, [!1X, #!2d]", kFixupNone),
299 ENCODING_MAP(kA64Ldrb3wXx, NO_VARIANTS(0x38606800),
300 kFmtRegW, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16,
301 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
302 "ldrb", "!0w, [!1X, !2x]", kFixupNone),
303 ENCODING_MAP(WIDE(kA64Ldrsb3rXd), CUSTOM_VARIANTS(0x39c00000, 0x39800000),
304 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10,
305 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
306 "ldrsb", "!0r, [!1X, #!2d]", kFixupNone),
307 ENCODING_MAP(WIDE(kA64Ldrsb3rXx), CUSTOM_VARIANTS(0x38e06800, 0x38a06800),
308 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16,
309 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_LOAD,
310 "ldrsb", "!0r, [!1X, !2x]", kFixupNone),
311 ENCODING_MAP(kA64Ldrh3wXF, NO_VARIANTS(0x79400000),
312 kFmtRegW, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10,
313 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
314 "ldrh", "!0w, [!1X, #!2F]", kFixupNone),
315 ENCODING_MAP(kA64Ldrh4wXxd, NO_VARIANTS(0x78606800),
316 kFmtRegW, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16,
317 kFmtBitBlt, 12, 12, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD,
318 "ldrh", "!0w, [!1X, !2x, lsl #!3d]", kFixupNone),
319 ENCODING_MAP(WIDE(kA64Ldrsh3rXF), CUSTOM_VARIANTS(0x79c00000, 0x79800000),
320 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10,
321 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
322 "ldrsh", "!0r, [!1X, #!2F]", kFixupNone),
323 ENCODING_MAP(WIDE(kA64Ldrsh4rXxd), CUSTOM_VARIANTS(0x78e06800, 0x78906800),
324 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16,
325 kFmtBitBlt, 12, 12, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD,
326 "ldrsh", "!0r, [!1X, !2x, lsl #!3d]", kFixupNone),
327 ENCODING_MAP(FWIDE(kA64Ldr2fp), SIZE_VARIANTS(0x1c000000),
328 kFmtRegF, 4, 0, kFmtBitBlt, 23, 5, kFmtUnused, -1, -1,
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]329 kFmtUnused, -1, -1,
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]330 IS_BINARY_OP | REG_DEF0 | REG_USE_PC | IS_LOAD | NEEDS_FIXUP,
331 "ldr", "!0f, !1p", kFixupLoad),
332 ENCODING_MAP(WIDE(kA64Ldr2rp), SIZE_VARIANTS(0x18000000),
333 kFmtRegR, 4, 0, kFmtBitBlt, 23, 5, kFmtUnused, -1, -1,
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]334 kFmtUnused, -1, -1,
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]335 IS_BINARY_OP | REG_DEF0 | REG_USE_PC | IS_LOAD | NEEDS_FIXUP,
336 "ldr", "!0r, !1p", kFixupLoad),
337 ENCODING_MAP(FWIDE(kA64Ldr3fXD), SIZE_VARIANTS(0xbd400000),
338 kFmtRegF, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10,
339 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
340 "ldr", "!0f, [!1X, #!2D]", kFixupNone),
341 ENCODING_MAP(WIDE(kA64Ldr3rXD), SIZE_VARIANTS(0xb9400000),
342 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10,
343 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
344 "ldr", "!0r, [!1X, #!2D]", kFixupNone),
345 ENCODING_MAP(FWIDE(kA64Ldr4fXxG), SIZE_VARIANTS(0xbc606800),
346 kFmtRegF, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16,
347 kFmtBitBlt, 12, 12, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD,
348 "ldr", "!0f, [!1X, !2x!3G]", kFixupNone),
349 ENCODING_MAP(WIDE(kA64Ldr4rXxG), SIZE_VARIANTS(0xb8606800),
350 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16,
351 kFmtBitBlt, 12, 12, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD,
352 "ldr", "!0r, [!1X, !2x!3G]", kFixupNone),
353 ENCODING_MAP(WIDE(kA64LdrPost3rXd), SIZE_VARIANTS(0xb8400400),
354 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 20, 12,
355 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF01 | REG_USE1 | IS_LOAD,
356 "ldr", "!0r, [!1X], #!2d", kFixupNone),
357 ENCODING_MAP(WIDE(kA64Ldp4rrXD), SF_VARIANTS(0x29400000),
358 kFmtRegR, 4, 0, kFmtRegR, 14, 10, kFmtRegXOrSp, 9, 5,
359 kFmtBitBlt, 21, 15, IS_QUAD_OP | REG_USE2 | REG_DEF012 | IS_LOAD,
360 "ldp", "!0r, !1r, [!2X, #!3D]", kFixupNone),
361 ENCODING_MAP(WIDE(kA64LdpPost4rrXD), CUSTOM_VARIANTS(0x28c00000, 0xa8c00000),
362 kFmtRegR, 4, 0, kFmtRegR, 14, 10, kFmtRegXOrSp, 9, 5,
363 kFmtBitBlt, 21, 15, IS_QUAD_OP | REG_USE2 | REG_DEF012 | IS_LOAD,
364 "ldp", "!0r, !1r, [!2X], #!3D", kFixupNone),
365 ENCODING_MAP(FWIDE(kA64Ldur3fXd), CUSTOM_VARIANTS(0xbc400000, 0xfc400000),
366 kFmtRegF, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 20, 12,
367 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
368 "ldur", "!0f, [!1X, #!2d]", kFixupNone),
369 ENCODING_MAP(WIDE(kA64Ldur3rXd), SIZE_VARIANTS(0xb8400000),
370 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 20, 12,
371 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | IS_LOAD,
372 "ldur", "!0r, [!1X, #!2d]", kFixupNone),
373 ENCODING_MAP(WIDE(kA64Ldxr2rX), SIZE_VARIANTS(0x885f7c00),
374 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtUnused, -1, -1,
375 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1 | IS_LOAD,
376 "ldxr", "!0r, [!1X]", kFixupNone),
377 ENCODING_MAP(WIDE(kA64Lsl3rrr), SF_VARIANTS(0x1ac02000),
378 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16,
379 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
380 "lsl", "!0r, !1r, !2r", kFixupNone),
381 ENCODING_MAP(WIDE(kA64Lsr3rrd), CUSTOM_VARIANTS(0x53007c00, 0xd340fc00),
382 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtBitBlt, 21, 16,
383 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
384 "lsr", "!0r, !1r, #!2d", kFixupNone),
385 ENCODING_MAP(WIDE(kA64Lsr3rrr), SF_VARIANTS(0x1ac02400),
386 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16,
387 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
388 "lsr", "!0r, !1r, !2r", kFixupNone),
389 ENCODING_MAP(WIDE(kA64Movk3rdM), SF_VARIANTS(0x72800000),
390 kFmtRegR, 4, 0, kFmtBitBlt, 20, 5, kFmtBitBlt, 22, 21,
391 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE0,
392 "movk", "!0r, #!1d!2M", kFixupNone),
393 ENCODING_MAP(WIDE(kA64Movn3rdM), SF_VARIANTS(0x12800000),
394 kFmtRegR, 4, 0, kFmtBitBlt, 20, 5, kFmtBitBlt, 22, 21,
395 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0,
396 "movn", "!0r, #!1d!2M", kFixupNone),
397 ENCODING_MAP(WIDE(kA64Movz3rdM), SF_VARIANTS(0x52800000),
398 kFmtRegR, 4, 0, kFmtBitBlt, 20, 5, kFmtBitBlt, 22, 21,
399 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0,
400 "movz", "!0r, #!1d!2M", kFixupNone),
401 ENCODING_MAP(WIDE(kA64Mov2rr), SF_VARIANTS(0x2a0003e0),
402 kFmtRegR, 4, 0, kFmtRegR, 20, 16, kFmtUnused, -1, -1,
403 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
404 "mov", "!0r, !1r", kFixupNone),
405 ENCODING_MAP(WIDE(kA64Mvn2rr), SF_VARIANTS(0x2a2003e0),
406 kFmtRegR, 4, 0, kFmtRegR, 20, 16, kFmtUnused, -1, -1,
407 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
408 "mvn", "!0r, !1r", kFixupNone),
409 ENCODING_MAP(WIDE(kA64Mul3rrr), SF_VARIANTS(0x1b007c00),
410 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16,
411 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
412 "mul", "!0r, !1r, !2r", kFixupNone),
413 ENCODING_MAP(WIDE(kA64Neg3rro), SF_VARIANTS(0x4b0003e0),
414 kFmtRegR, 4, 0, kFmtRegR, 20, 16, kFmtShift, -1, -1,
415 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
416 "neg", "!0r, !1r!2o", kFixupNone),
417 ENCODING_MAP(WIDE(kA64Orr3Rrl), SF_VARIANTS(0x32000000),
418 kFmtRegROrSp, 4, 0, kFmtRegR, 9, 5, kFmtBitBlt, 22, 10,
419 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1,
420 "orr", "!0R, !1r, #!2l", kFixupNone),
421 ENCODING_MAP(WIDE(kA64Orr4rrro), SF_VARIANTS(0x2a000000),
422 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16,
423 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
424 "orr", "!0r, !1r, !2r!3o", kFixupNone),
425 ENCODING_MAP(kA64Ret, NO_VARIANTS(0xd65f03c0),
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]426 kFmtUnused, -1, -1, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]427 kFmtUnused, -1, -1, NO_OPERAND | IS_BRANCH,
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]428 "ret", "", kFixupNone),
429 ENCODING_MAP(WIDE(kA64Rev2rr), CUSTOM_VARIANTS(0x5ac00800, 0xdac00c00),
430 kFmtRegR, 11, 8, kFmtRegR, 19, 16, kFmtUnused, -1, -1,
431 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
432 "rev", "!0r, !1r", kFixupNone),
433 ENCODING_MAP(WIDE(kA64Rev162rr), SF_VARIANTS(0xfa90f0b0),
434 kFmtRegR, 11, 8, kFmtRegR, 19, 16, kFmtUnused, -1, -1,
435 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
436 "rev16", "!0r, !1r", kFixupNone),
437 ENCODING_MAP(WIDE(kA64Ror3rrr), SF_VARIANTS(0x1ac02c00),
438 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16,
439 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
440 "ror", "!0r, !1r, !2r", kFixupNone),
441 ENCODING_MAP(WIDE(kA64Sbc3rrr), SF_VARIANTS(0x5a000000),
442 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16,
443 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
444 "sbc", "!0r, !1r, !2r", kFixupNone),
445 ENCODING_MAP(WIDE(kA64Sbfm4rrdd), SF_N_VARIANTS(0x13000000),
446 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtBitBlt, 21, 16,
447 kFmtBitBlt, 15, 10, IS_QUAD_OP | REG_DEF0_USE1,
448 "sbfm", "!0r, !1r, #!2d, #!3d", kFixupNone),
449 ENCODING_MAP(FWIDE(kA64Scvtf2fw), FLOAT_VARIANTS(0x1e220000),
450 kFmtRegF, 4, 0, kFmtRegW, 9, 5, kFmtUnused, -1, -1,
451 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
452 "scvtf", "!0f, !1w", kFixupNone),
453 ENCODING_MAP(FWIDE(kA64Scvtf2fx), FLOAT_VARIANTS(0x9e220000),
454 kFmtRegF, 4, 0, kFmtRegX, 9, 5, kFmtUnused, -1, -1,
455 kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
456 "scvtf", "!0f, !1x", kFixupNone),
457 ENCODING_MAP(WIDE(kA64Sdiv3rrr), SF_VARIANTS(0x1ac00c00),
458 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16,
459 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
460 "sdiv", "!0r, !1r, !2r", kFixupNone),
461 ENCODING_MAP(WIDE(kA64Smaddl4xwwx), NO_VARIANTS(0x9b200000),
462 kFmtRegX, 4, 0, kFmtRegW, 9, 5, kFmtRegW, 20, 16,
463 kFmtRegX, -1, -1, IS_QUAD_OP | REG_DEF0_USE123,
464 "smaddl", "!0x, !1w, !2w, !3x", kFixupNone),
465 ENCODING_MAP(WIDE(kA64Stp4rrXD), SF_VARIANTS(0x29000000),
466 kFmtRegR, 4, 0, kFmtRegR, 14, 10, kFmtRegXOrSp, 9, 5,
467 kFmtBitBlt, 21, 15, IS_QUAD_OP | REG_DEF2 | REG_USE012 | IS_STORE,
468 "stp", "!0r, !1r, [!2X, #!3D]", kFixupNone),
469 ENCODING_MAP(WIDE(kA64StpPost4rrXD), CUSTOM_VARIANTS(0x28800000, 0xa8800000),
470 kFmtRegR, 4, 0, kFmtRegR, 14, 10, kFmtRegXOrSp, 9, 5,
471 kFmtBitBlt, 21, 15, IS_QUAD_OP | REG_DEF2 | REG_USE012 | IS_STORE,
472 "stp", "!0r, !1r, [!2X], #!3D", kFixupNone),
473 ENCODING_MAP(WIDE(kA64StpPre4rrXD), CUSTOM_VARIANTS(0x29800000, 0xa9800000),
474 kFmtRegR, 4, 0, kFmtRegR, 14, 10, kFmtRegXOrSp, 9, 5,
475 kFmtBitBlt, 21, 15, IS_QUAD_OP | REG_DEF2 | REG_USE012 | IS_STORE,
476 "stp", "!0r, !1r, [!2X, #!3D]!!", kFixupNone),
477 ENCODING_MAP(FWIDE(kA64Str3fXD), CUSTOM_VARIANTS(0xbd000000, 0xfd000000),
478 kFmtRegF, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10,
479 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE,
480 "str", "!0f, [!1X, #!2D]", kFixupNone),
481 ENCODING_MAP(FWIDE(kA64Str4fXxG), CUSTOM_VARIANTS(0xbc206800, 0xfc206800),
482 kFmtRegF, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16,
483 kFmtBitBlt, 12, 12, IS_QUAD_OP | REG_USE012 | IS_STORE,
484 "str", "!0f, [!1X, !2x!3G]", kFixupNone),
485 ENCODING_MAP(WIDE(kA64Str3rXD), SIZE_VARIANTS(0xb9000000),
486 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10,
487 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE,
488 "str", "!0r, [!1X, #!2D]", kFixupNone),
489 ENCODING_MAP(WIDE(kA64Str4rXxG), SIZE_VARIANTS(0xb8206800),
490 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16,
491 kFmtBitBlt, 12, 12, IS_QUAD_OP | REG_USE012 | IS_STORE,
492 "str", "!0r, [!1X, !2x!3G]", kFixupNone),
493 ENCODING_MAP(kA64Strb3wXd, NO_VARIANTS(0x39000000),
494 kFmtRegW, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10,
495 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE,
496 "strb", "!0w, [!1X, #!2d]", kFixupNone),
497 ENCODING_MAP(kA64Strb3wXx, NO_VARIANTS(0x38206800),
498 kFmtRegW, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16,
499 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE012 | IS_STORE,
500 "strb", "!0w, [!1X, !2x]", kFixupNone),
501 ENCODING_MAP(kA64Strh3wXF, NO_VARIANTS(0x79000000),
502 kFmtRegW, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 21, 10,
503 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE,
504 "strh", "!0w, [!1X, #!2F]", kFixupNone),
505 ENCODING_MAP(kA64Strh4wXxd, NO_VARIANTS(0x78206800),
506 kFmtRegW, 4, 0, kFmtRegXOrSp, 9, 5, kFmtRegX, 20, 16,
507 kFmtBitBlt, 12, 12, IS_QUAD_OP | REG_USE012 | IS_STORE,
508 "strh", "!0w, [!1X, !2x, lsl #!3d]", kFixupNone),
509 ENCODING_MAP(WIDE(kA64StrPost3rXd), SIZE_VARIANTS(0xb8000400),
510 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 20, 12,
511 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | REG_DEF1 | IS_STORE,
512 "str", "!0r, [!1X], #!2d", kFixupNone),
513 ENCODING_MAP(FWIDE(kA64Stur3fXd), CUSTOM_VARIANTS(0xbc000000, 0xfc000000),
514 kFmtRegF, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 20, 12,
515 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE,
516 "stur", "!0f, [!1X, #!2d]", kFixupNone),
517 ENCODING_MAP(WIDE(kA64Stur3rXd), SIZE_VARIANTS(0xb8000000),
518 kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5, kFmtBitBlt, 20, 12,
519 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE01 | IS_STORE,
520 "stur", "!0r, [!1X, #!2d]", kFixupNone),
521 ENCODING_MAP(WIDE(kA64Stxr3wrX), SIZE_VARIANTS(0x88007c00),
522 kFmtRegW, 20, 16, kFmtRegR, 4, 0, kFmtRegXOrSp, 9, 5,
523 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12 | IS_STORE,
524 "stxr", "!0w, !1r, [!2X]", kFixupNone),
525 ENCODING_MAP(WIDE(kA64Sub4RRdT), SF_VARIANTS(0x51000000),
526 kFmtRegROrSp, 4, 0, kFmtRegROrSp, 9, 5, kFmtBitBlt, 21, 10,
527 kFmtBitBlt, 23, 22, IS_QUAD_OP | REG_DEF0_USE1,
528 "sub", "!0R, !1R, #!2d!3T", kFixupNone),
529 ENCODING_MAP(WIDE(kA64Sub4rrro), SF_VARIANTS(0x4b000000),
530 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtRegR, 20, 16,
531 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
532 "sub", "!0r, !1r, !2r!3o", kFixupNone),
533 ENCODING_MAP(WIDE(kA64Subs3rRd), SF_VARIANTS(0x71000000),
534 kFmtRegR, 4, 0, kFmtRegROrSp, 9, 5, kFmtBitBlt, 21, 10,
535 kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES,
536 "subs", "!0r, !1R, #!2d", kFixupNone),
537 ENCODING_MAP(WIDE(kA64Tst3rro), SF_VARIANTS(0x6a000000),
538 kFmtRegR, 9, 5, kFmtRegR, 20, 16, kFmtShift, -1, -1,
539 kFmtUnused, -1, -1, IS_QUAD_OP | REG_USE01 | SETS_CCODES,
540 "tst", "!0r, !1r!2o", kFixupNone),
541 ENCODING_MAP(WIDE(kA64Ubfm4rrdd), SF_N_VARIANTS(0x53000000),
542 kFmtRegR, 4, 0, kFmtRegR, 9, 5, kFmtBitBlt, 21, 16,
543 kFmtBitBlt, 15, 10, IS_QUAD_OP | REG_DEF0_USE1,
544 "ubfm", "!0r, !1r, !2d, !3d", kFixupNone),
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]545};
546
547// new_lir replaces orig_lir in the pcrel_fixup list.
548void Arm64Mir2Lir::ReplaceFixup(LIR* prev_lir, LIR* orig_lir, LIR* new_lir) {
549 new_lir->u.a.pcrel_next = orig_lir->u.a.pcrel_next;
550 if (UNLIKELY(prev_lir == NULL)) {
551 first_fixup_ = new_lir;
552 } else {
553 prev_lir->u.a.pcrel_next = new_lir;
554 }
555 orig_lir->flags.fixup = kFixupNone;
556}
557
558// new_lir is inserted before orig_lir in the pcrel_fixup list.
559void Arm64Mir2Lir::InsertFixupBefore(LIR* prev_lir, LIR* orig_lir, LIR* new_lir) {
560 new_lir->u.a.pcrel_next = orig_lir;
561 if (UNLIKELY(prev_lir == NULL)) {
562 first_fixup_ = new_lir;
563 } else {
564 DCHECK(prev_lir->u.a.pcrel_next == orig_lir);
565 prev_lir->u.a.pcrel_next = new_lir;
566 }
567}
568
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]569/* Nop, used for aligning code. Nop is an alias for hint #0. */
570#define PADDING_NOP (UINT32_C(0xd503201f))
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]571
572uint8_t* Arm64Mir2Lir::EncodeLIRs(uint8_t* write_pos, LIR* lir) {
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]573 for (; lir != nullptr; lir = NEXT_LIR(lir)) {
574 bool opcode_is_wide = IS_WIDE(lir->opcode);
575 ArmOpcode opcode = UNWIDE(lir->opcode);
576
577 if (UNLIKELY(IsPseudoLirOp(opcode))) {
578 continue;
579 }
580
581 if (LIKELY(!lir->flags.is_nop)) {
582 const ArmEncodingMap *encoder = &EncodingMap[opcode];
583
584 // Select the right variant of the skeleton.
585 uint32_t bits = opcode_is_wide ? encoder->xskeleton : encoder->wskeleton;
586 DCHECK(!opcode_is_wide || IS_WIDE(encoder->opcode));
587
588 for (int i = 0; i < 4; i++) {
589 ArmEncodingKind kind = encoder->field_loc[i].kind;
590 uint32_t operand = lir->operands[i];
591 uint32_t value;
592
593 if (LIKELY(static_cast<unsigned>(kind) <= kFmtBitBlt)) {
594 // Note: this will handle kFmtReg* and kFmtBitBlt.
595
596 if (static_cast<unsigned>(kind) < kFmtBitBlt) {
597 bool is_zero = A64_REG_IS_ZR(operand);
598
599 if (kIsDebugBuild) {
600 // Register usage checks: First establish register usage requirements based on the
601 // format in `kind'.
602 bool want_float = false;
603 bool want_64_bit = false;
604 bool want_size_match = false;
605 bool want_zero = false;
606 switch (kind) {
607 case kFmtRegX:
608 want_64_bit = true;
609 // Intentional fall-through.
610 case kFmtRegW:
611 want_size_match = true;
612 // Intentional fall-through.
613 case kFmtRegR:
614 want_zero = true;
615 break;
616 case kFmtRegXOrSp:
617 want_64_bit = true;
618 // Intentional fall-through.
619 case kFmtRegWOrSp:
620 want_size_match = true;
621 break;
622 case kFmtRegROrSp:
623 break;
624 case kFmtRegD:
625 want_64_bit = true;
626 // Intentional fall-through.
627 case kFmtRegS:
628 want_size_match = true;
629 // Intentional fall-through.
630 case kFmtRegF:
631 want_float = true;
632 break;
633 default:
634 LOG(FATAL) << "Bad fmt for arg n. " << i << " of " << encoder->name
635 << " (" << kind << ")";
636 break;
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]637 }
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]638
639 // Now check that the requirements are satisfied.
Zheng Xuc8304302014-05-15 17:21:01 +0100[diff] [blame^]640 RegStorage reg(operand | RegStorage::kValid);
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]641 const char *expected = nullptr;
642 if (want_float) {
643 if (!reg.IsFloat()) {
644 expected = "float register";
645 } else if (want_size_match && (reg.IsDouble() != want_64_bit)) {
646 expected = (want_64_bit) ? "double register" : "single register";
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]647 }
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]648 } else {
649 if (reg.IsFloat()) {
650 expected = "core register";
651 } else if (want_size_match && (reg.Is64Bit() != want_64_bit)) {
652 expected = (want_64_bit) ? "x-register" : "w-register";
653 } else if (reg.GetRegNum() == 31 && is_zero == want_zero) {
654 expected = (want_zero) ? "zero-register" : "sp-register";
655 }
656 }
657
658 // TODO(Arm64): if !want_size_match, then we still should compare the size of the
659 // register with the size required by the instruction width (kA64Wide).
660
661 // Fail, if `expected' contains an unsatisfied requirement.
662 if (expected != nullptr) {
663 // TODO(Arm64): make this FATAL.
664 LOG(WARNING) << "Bad argument n. " << i << " of " << encoder->name
665 << ". Expected " << expected << ", got 0x" << std::hex << operand;
666 }
667 }
668
669 // TODO(Arm64): this may or may not be necessary, depending on how wzr, xzr are
670 // defined.
671 if (is_zero) {
672 operand = 31;
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]673 }
674 }
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]675
676 value = (operand << encoder->field_loc[i].start) &
677 ((1 << (encoder->field_loc[i].end + 1)) - 1);
678 bits |= value;
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]679 } else {
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]680 switch (kind) {
681 case kFmtSkip:
682 break; // Nothing to do, but continue to next.
683 case kFmtUnused:
684 i = 4; // Done, break out of the enclosing loop.
685 break;
686 case kFmtShift:
687 // Intentional fallthrough.
688 case kFmtExtend:
689 DCHECK_EQ((operand & (1 << 6)) == 0, kind == kFmtShift);
690 value = (operand & 0x3f) << 10;
691 value |= ((operand & 0x1c0) >> 6) << 21;
692 bits |= value;
693 break;
694 case kFmtImm21:
695 value = (operand & 0x3) << 29;
696 value |= ((operand & 0x1ffffc) >> 2) << 5;
697 bits |= value;
698 break;
699 default:
700 LOG(FATAL) << "Bad fmt for arg. " << i << " in " << encoder->name
701 << " (" << kind << ")";
702 }
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]703 }
704 }
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]705
706 DCHECK_EQ(encoder->size, 4);
707 write_pos[0] = (bits & 0xff);
708 write_pos[1] = ((bits >> 8) & 0xff);
709 write_pos[2] = ((bits >> 16) & 0xff);
710 write_pos[3] = ((bits >> 24) & 0xff);
711 write_pos += 4;
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]712 }
713 }
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]714
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]715 return write_pos;
716}
717
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]718// Align data offset on 8 byte boundary: it will only contain double-word items, as word immediates
719// are better set directly from the code (they will require no more than 2 instructions).
720#define ALIGNED_DATA_OFFSET(offset) (((offset) + 0x7) & ~0x7)
721
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]722// Assemble the LIR into binary instruction format.
723void Arm64Mir2Lir::AssembleLIR() {
724 LIR* lir;
725 LIR* prev_lir;
726 cu_->NewTimingSplit("Assemble");
727 int assembler_retries = 0;
728 CodeOffset starting_offset = LinkFixupInsns(first_lir_insn_, last_lir_insn_, 0);
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]729 data_offset_ = ALIGNED_DATA_OFFSET(starting_offset);
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]730 int32_t offset_adjustment;
731 AssignDataOffsets();
732
733 /*
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]734 * Note: generation must be 1 on first pass (to distinguish from initialized state of 0
735 * for non-visited nodes). Start at zero here, and bit will be flipped to 1 on entry to the loop.
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]736 */
737 int generation = 0;
738 while (true) {
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]739 // TODO(Arm64): check whether passes and offset adjustments are really necessary.
740 // Currently they aren't, as - in the fixups below - LIR are never inserted.
741 // Things can be different if jump ranges above 1 MB need to be supported.
742 // If they are not, then we can get rid of the assembler retry logic.
743
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]744 offset_adjustment = 0;
745 AssemblerStatus res = kSuccess; // Assume success
746 generation ^= 1;
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]747 // Note: nodes requiring possible fixup linked in ascending order.
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]748 lir = first_fixup_;
749 prev_lir = NULL;
750 while (lir != NULL) {
751 /*
752 * NOTE: the lir being considered here will be encoded following the switch (so long as
753 * we're not in a retry situation). However, any new non-pc_rel instructions inserted
754 * due to retry must be explicitly encoded at the time of insertion. Note that
755 * inserted instructions don't need use/def flags, but do need size and pc-rel status
756 * properly updated.
757 */
758 lir->offset += offset_adjustment;
759 // During pass, allows us to tell whether a node has been updated with offset_adjustment yet.
760 lir->flags.generation = generation;
761 switch (static_cast<FixupKind>(lir->flags.fixup)) {
762 case kFixupLabel:
763 case kFixupNone:
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]764 case kFixupVLoad:
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]765 break;
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]766 case kFixupT1Branch: {
767 LIR *target_lir = lir->target;
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]768 DCHECK(target_lir);
769 CodeOffset pc = lir->offset;
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]770 CodeOffset target = target_lir->offset +
771 ((target_lir->flags.generation == lir->flags.generation) ? 0 : offset_adjustment);
772 int32_t delta = target - pc;
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]773 if (!((delta & 0x3) == 0 && IS_SIGNED_IMM19(delta >> 2))) {
774 LOG(FATAL) << "Invalid jump range in kFixupT1Branch";
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]775 }
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]776 lir->operands[0] = delta >> 2;
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]777 break;
778 }
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]779 case kFixupLoad:
780 case kFixupCBxZ:
781 case kFixupCondBranch: {
782 LIR *target_lir = lir->target;
783 DCHECK(target_lir);
784 CodeOffset pc = lir->offset;
785 CodeOffset target = target_lir->offset +
786 ((target_lir->flags.generation == lir->flags.generation) ? 0 : offset_adjustment);
787 int32_t delta = target - pc;
788 if (!((delta & 0x3) == 0 && IS_SIGNED_IMM19(delta >> 2))) {
789 LOG(FATAL) << "Invalid jump range in kFixupLoad";
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]790 }
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]791 lir->operands[1] = delta >> 2;
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]792 break;
793 }
794 case kFixupAdr: {
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]795 LIR* target_lir = lir->target;
796 int32_t delta;
797 if (target_lir) {
798 CodeOffset target_offs = ((target_lir->flags.generation == lir->flags.generation) ?
799 0 : offset_adjustment) + target_lir->offset;
800 delta = target_offs - lir->offset;
801 } else if (lir->operands[2] >= 0) {
802 EmbeddedData* tab = reinterpret_cast<EmbeddedData*>(UnwrapPointer(lir->operands[2]));
803 delta = tab->offset + offset_adjustment - lir->offset;
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]804 } else {
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]805 // No fixup: this usage allows to retrieve the current PC.
806 delta = lir->operands[1];
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]807 }
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]808 if (!IS_SIGNED_IMM21(delta)) {
809 LOG(FATAL) << "Jump range above 1MB in kFixupAdr";
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]810 }
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]811 lir->operands[1] = delta;
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]812 break;
813 }
814 default:
815 LOG(FATAL) << "Unexpected case " << lir->flags.fixup;
816 }
817 prev_lir = lir;
818 lir = lir->u.a.pcrel_next;
819 }
820
821 if (res == kSuccess) {
822 break;
823 } else {
824 assembler_retries++;
825 if (assembler_retries > MAX_ASSEMBLER_RETRIES) {
826 CodegenDump();
827 LOG(FATAL) << "Assembler error - too many retries";
828 }
829 starting_offset += offset_adjustment;
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]830 data_offset_ = ALIGNED_DATA_OFFSET(starting_offset);
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]831 AssignDataOffsets();
832 }
833 }
834
835 // Build the CodeBuffer.
836 DCHECK_LE(data_offset_, total_size_);
837 code_buffer_.reserve(total_size_);
838 code_buffer_.resize(starting_offset);
839 uint8_t* write_pos = &code_buffer_[0];
840 write_pos = EncodeLIRs(write_pos, first_lir_insn_);
841 DCHECK_EQ(static_cast<CodeOffset>(write_pos - &code_buffer_[0]), starting_offset);
842
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]843 DCHECK_EQ(data_offset_, ALIGNED_DATA_OFFSET(code_buffer_.size()));
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]844
845 // Install literals
846 InstallLiteralPools();
847
848 // Install switch tables
849 InstallSwitchTables();
850
851 // Install fill array data
852 InstallFillArrayData();
853
854 // Create the mapping table and native offset to reference map.
855 cu_->NewTimingSplit("PcMappingTable");
856 CreateMappingTables();
857
858 cu_->NewTimingSplit("GcMap");
859 CreateNativeGcMap();
860}
861
862int Arm64Mir2Lir::GetInsnSize(LIR* lir) {
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]863 ArmOpcode opcode = UNWIDE(lir->opcode);
864 DCHECK(!IsPseudoLirOp(opcode));
865 return EncodingMap[opcode].size;
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]866}
867
868// Encode instruction bit pattern and assign offsets.
869uint32_t Arm64Mir2Lir::LinkFixupInsns(LIR* head_lir, LIR* tail_lir, uint32_t offset) {
870 LIR* end_lir = tail_lir->next;
871
872 LIR* last_fixup = NULL;
873 for (LIR* lir = head_lir; lir != end_lir; lir = NEXT_LIR(lir)) {
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]874 ArmOpcode opcode = UNWIDE(lir->opcode);
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]875 if (!lir->flags.is_nop) {
876 if (lir->flags.fixup != kFixupNone) {
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]877 if (!IsPseudoLirOp(opcode)) {
878 lir->flags.size = EncodingMap[opcode].size;
879 lir->flags.fixup = EncodingMap[opcode].fixup;
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]880 } else {
Matteo Franchine45fb9e2014-05-06 10:10:30 +0100[diff] [blame]881 DCHECK_NE(static_cast<int>(opcode), kPseudoPseudoAlign4);
Matteo Franchin43ec8732014-03-31 15:00:14 +0100[diff] [blame]882 lir->flags.size = 0;
883 lir->flags.fixup = kFixupLabel;
884 }
885 // Link into the fixup chain.
886 lir->flags.use_def_invalid = true;
887 lir->u.a.pcrel_next = NULL;
888 if (first_fixup_ == NULL) {
889 first_fixup_ = lir;
890 } else {
891 last_fixup->u.a.pcrel_next = lir;
892 }
893 last_fixup = lir;
894 lir->offset = offset;
895 }
896 offset += lir->flags.size;
897 }
898 }
899 return offset;
900}
901
902void Arm64Mir2Lir::AssignDataOffsets() {
903 /* Set up offsets for literals */
904 CodeOffset offset = data_offset_;
905
906 offset = AssignLiteralOffset(offset);
907
908 offset = AssignSwitchTablesOffset(offset);
909
910 total_size_ = AssignFillArrayDataOffset(offset);
911}
912
913} // namespace art