Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "codegen_x86.h" |
| 18 | #include "dex/quick/mir_to_lir-inl.h" |
| 19 | #include "x86_lir.h" |
| 20 | |
| 21 | namespace art { |
| 22 | |
| 23 | #define MAX_ASSEMBLER_RETRIES 50 |
| 24 | |
| 25 | const X86EncodingMap X86Mir2Lir::EncodingMap[kX86Last] = { |
| 26 | { kX8632BitData, kData, IS_UNARY_OP, { 0, 0, 0x00, 0, 0, 0, 0, 4 }, "data", "0x!0d" }, |
| 27 | { kX86Bkpt, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xCC, 0, 0, 0, 0, 0 }, "int 3", "" }, |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 28 | { kX86Nop, kNop, NO_OPERAND, { 0, 0, 0x90, 0, 0, 0, 0, 0 }, "nop", "" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 29 | |
| 30 | #define ENCODING_MAP(opname, mem_use, reg_def, uses_ccodes, \ |
| 31 | rm8_r8, rm32_r32, \ |
| 32 | r8_rm8, r32_rm32, \ |
| 33 | ax8_i8, ax32_i32, \ |
| 34 | rm8_i8, rm8_i8_modrm, \ |
| 35 | rm32_i32, rm32_i32_modrm, \ |
| 36 | rm32_i8, rm32_i8_modrm) \ |
| 37 | { kX86 ## opname ## 8MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8MR", "[!0r+!1d],!2r" }, \ |
| 38 | { kX86 ## opname ## 8AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ |
| 39 | { kX86 ## opname ## 8TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8TR", "fs:[!0d],!1r" }, \ |
| 40 | { kX86 ## opname ## 8RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RR", "!0r,!1r" }, \ |
| 41 | { kX86 ## opname ## 8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RM", "!0r,[!1r+!2d]" }, \ |
| 42 | { kX86 ## opname ## 8RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ |
| 43 | { kX86 ## opname ## 8RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RT", "!0r,fs:[!1d]" }, \ |
| 44 | { kX86 ## opname ## 8RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, ax8_i8, 1 }, #opname "8RI", "!0r,!1d" }, \ |
| 45 | { kX86 ## opname ## 8MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1 }, #opname "8MI", "[!0r+!1d],!2d" }, \ |
| 46 | { kX86 ## opname ## 8AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 47 | { kX86 ## opname ## 8TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1 }, #opname "8TI", "fs:[!0d],!1d" }, \ |
| 48 | \ |
| 49 | { kX86 ## opname ## 16MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16MR", "[!0r+!1d],!2r" }, \ |
| 50 | { kX86 ## opname ## 16AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ |
| 51 | { kX86 ## opname ## 16TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16TR", "fs:[!0d],!1r" }, \ |
| 52 | { kX86 ## opname ## 16RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RR", "!0r,!1r" }, \ |
| 53 | { kX86 ## opname ## 16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RM", "!0r,[!1r+!2d]" }, \ |
| 54 | { kX86 ## opname ## 16RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ |
| 55 | { kX86 ## opname ## 16RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RT", "!0r,fs:[!1d]" }, \ |
| 56 | { kX86 ## opname ## 16RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 2 }, #opname "16RI", "!0r,!1d" }, \ |
| 57 | { kX86 ## opname ## 16MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16MI", "[!0r+!1d],!2d" }, \ |
| 58 | { kX86 ## opname ## 16AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 59 | { kX86 ## opname ## 16TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16TI", "fs:[!0d],!1d" }, \ |
| 60 | { kX86 ## opname ## 16RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16RI8", "!0r,!1d" }, \ |
| 61 | { kX86 ## opname ## 16MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16MI8", "[!0r+!1d],!2d" }, \ |
| 62 | { kX86 ## opname ## 16AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 63 | { kX86 ## opname ## 16TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16TI8", "fs:[!0d],!1d" }, \ |
| 64 | \ |
| 65 | { kX86 ## opname ## 32MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32MR", "[!0r+!1d],!2r" }, \ |
| 66 | { kX86 ## opname ## 32AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ |
| 67 | { kX86 ## opname ## 32TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32TR", "fs:[!0d],!1r" }, \ |
| 68 | { kX86 ## opname ## 32RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RR", "!0r,!1r" }, \ |
| 69 | { kX86 ## opname ## 32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RM", "!0r,[!1r+!2d]" }, \ |
| 70 | { kX86 ## opname ## 32RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ |
| 71 | { kX86 ## opname ## 32RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RT", "!0r,fs:[!1d]" }, \ |
| 72 | { kX86 ## opname ## 32RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4 }, #opname "32RI", "!0r,!1d" }, \ |
| 73 | { kX86 ## opname ## 32MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32MI", "[!0r+!1d],!2d" }, \ |
| 74 | { kX86 ## opname ## 32AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 75 | { kX86 ## opname ## 32TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32TI", "fs:[!0d],!1d" }, \ |
| 76 | { kX86 ## opname ## 32RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32RI8", "!0r,!1d" }, \ |
| 77 | { kX86 ## opname ## 32MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32MI8", "[!0r+!1d],!2d" }, \ |
| 78 | { kX86 ## opname ## 32AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 79 | { kX86 ## opname ## 32TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32TI8", "fs:[!0d],!1d" }, \ |
| 80 | \ |
| 81 | { kX86 ## opname ## 64MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "64MR", "[!0r+!1d],!2r" }, \ |
| 82 | { kX86 ## opname ## 64AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "64AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ |
| 83 | { kX86 ## opname ## 64TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_r32, 0, 0, 0, 0, 0 }, #opname "64TR", "fs:[!0d],!1r" }, \ |
| 84 | { kX86 ## opname ## 64RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "64RR", "!0r,!1r" }, \ |
| 85 | { kX86 ## opname ## 64RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "64RM", "!0r,[!1r+!2d]" }, \ |
| 86 | { kX86 ## opname ## 64RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { REX_W, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "64RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ |
| 87 | { kX86 ## opname ## 64RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, r32_rm32, 0, 0, 0, 0, 0 }, #opname "64RT", "!0r,fs:[!1d]" }, \ |
| 88 | { kX86 ## opname ## 64RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4 }, #opname "64RI", "!0r,!1d" }, \ |
| 89 | { kX86 ## opname ## 64MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "64MI", "[!0r+!1d],!2d" }, \ |
| 90 | { kX86 ## opname ## 64AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "64AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 91 | { kX86 ## opname ## 64TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "64TI", "fs:[!0d],!1d" }, \ |
| 92 | { kX86 ## opname ## 64RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "64RI8", "!0r,!1d" }, \ |
| 93 | { kX86 ## opname ## 64MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "64MI8", "[!0r+!1d],!2d" }, \ |
| 94 | { kX86 ## opname ## 64AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "64AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 95 | { kX86 ## opname ## 64TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "64TI8", "fs:[!0d],!1d" } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 96 | |
| 97 | ENCODING_MAP(Add, IS_LOAD | IS_STORE, REG_DEF0, 0, |
| 98 | 0x00 /* RegMem8/Reg8 */, 0x01 /* RegMem32/Reg32 */, |
| 99 | 0x02 /* Reg8/RegMem8 */, 0x03 /* Reg32/RegMem32 */, |
| 100 | 0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */, |
| 101 | 0x80, 0x0 /* RegMem8/imm8 */, |
| 102 | 0x81, 0x0 /* RegMem32/imm32 */, 0x83, 0x0 /* RegMem32/imm8 */), |
| 103 | ENCODING_MAP(Or, IS_LOAD | IS_STORE, REG_DEF0, 0, |
| 104 | 0x08 /* RegMem8/Reg8 */, 0x09 /* RegMem32/Reg32 */, |
| 105 | 0x0A /* Reg8/RegMem8 */, 0x0B /* Reg32/RegMem32 */, |
| 106 | 0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */, |
| 107 | 0x80, 0x1 /* RegMem8/imm8 */, |
| 108 | 0x81, 0x1 /* RegMem32/imm32 */, 0x83, 0x1 /* RegMem32/imm8 */), |
| 109 | ENCODING_MAP(Adc, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES, |
| 110 | 0x10 /* RegMem8/Reg8 */, 0x11 /* RegMem32/Reg32 */, |
| 111 | 0x12 /* Reg8/RegMem8 */, 0x13 /* Reg32/RegMem32 */, |
| 112 | 0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */, |
| 113 | 0x80, 0x2 /* RegMem8/imm8 */, |
| 114 | 0x81, 0x2 /* RegMem32/imm32 */, 0x83, 0x2 /* RegMem32/imm8 */), |
| 115 | ENCODING_MAP(Sbb, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES, |
| 116 | 0x18 /* RegMem8/Reg8 */, 0x19 /* RegMem32/Reg32 */, |
| 117 | 0x1A /* Reg8/RegMem8 */, 0x1B /* Reg32/RegMem32 */, |
| 118 | 0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */, |
| 119 | 0x80, 0x3 /* RegMem8/imm8 */, |
| 120 | 0x81, 0x3 /* RegMem32/imm32 */, 0x83, 0x3 /* RegMem32/imm8 */), |
| 121 | ENCODING_MAP(And, IS_LOAD | IS_STORE, REG_DEF0, 0, |
| 122 | 0x20 /* RegMem8/Reg8 */, 0x21 /* RegMem32/Reg32 */, |
| 123 | 0x22 /* Reg8/RegMem8 */, 0x23 /* Reg32/RegMem32 */, |
| 124 | 0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */, |
| 125 | 0x80, 0x4 /* RegMem8/imm8 */, |
| 126 | 0x81, 0x4 /* RegMem32/imm32 */, 0x83, 0x4 /* RegMem32/imm8 */), |
| 127 | ENCODING_MAP(Sub, IS_LOAD | IS_STORE, REG_DEF0, 0, |
| 128 | 0x28 /* RegMem8/Reg8 */, 0x29 /* RegMem32/Reg32 */, |
| 129 | 0x2A /* Reg8/RegMem8 */, 0x2B /* Reg32/RegMem32 */, |
| 130 | 0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */, |
| 131 | 0x80, 0x5 /* RegMem8/imm8 */, |
| 132 | 0x81, 0x5 /* RegMem32/imm32 */, 0x83, 0x5 /* RegMem32/imm8 */), |
| 133 | ENCODING_MAP(Xor, IS_LOAD | IS_STORE, REG_DEF0, 0, |
| 134 | 0x30 /* RegMem8/Reg8 */, 0x31 /* RegMem32/Reg32 */, |
| 135 | 0x32 /* Reg8/RegMem8 */, 0x33 /* Reg32/RegMem32 */, |
| 136 | 0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */, |
| 137 | 0x80, 0x6 /* RegMem8/imm8 */, |
| 138 | 0x81, 0x6 /* RegMem32/imm32 */, 0x83, 0x6 /* RegMem32/imm8 */), |
| 139 | ENCODING_MAP(Cmp, IS_LOAD, 0, 0, |
| 140 | 0x38 /* RegMem8/Reg8 */, 0x39 /* RegMem32/Reg32 */, |
| 141 | 0x3A /* Reg8/RegMem8 */, 0x3B /* Reg32/RegMem32 */, |
| 142 | 0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */, |
| 143 | 0x80, 0x7 /* RegMem8/imm8 */, |
| 144 | 0x81, 0x7 /* RegMem32/imm32 */, 0x83, 0x7 /* RegMem32/imm8 */), |
| 145 | #undef ENCODING_MAP |
| 146 | |
| 147 | { kX86Imul16RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RRI", "!0r,!1r,!2d" }, |
| 148 | { kX86Imul16RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RMI", "!0r,[!1r+!2d],!3d" }, |
| 149 | { kX86Imul16RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, |
| 150 | |
| 151 | { kX86Imul32RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RRI", "!0r,!1r,!2d" }, |
| 152 | { kX86Imul32RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RMI", "!0r,[!1r+!2d],!3d" }, |
| 153 | { kX86Imul32RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, |
| 154 | { kX86Imul32RRI8, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RRI8", "!0r,!1r,!2d" }, |
| 155 | { kX86Imul32RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RMI8", "!0r,[!1r+!2d],!3d" }, |
| 156 | { kX86Imul32RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, |
| 157 | |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 158 | { kX86Imul64RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x69, 0, 0, 0, 0, 8 }, "Imul64RRI", "!0r,!1r,!2d" }, |
| 159 | { kX86Imul64RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x69, 0, 0, 0, 0, 8 }, "Imul64RMI", "!0r,[!1r+!2d],!3d" }, |
| 160 | { kX86Imul64RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { REX_W, 0, 0x69, 0, 0, 0, 0, 8 }, "Imul64RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, |
| 161 | { kX86Imul64RRI8, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul64RRI8", "!0r,!1r,!2d" }, |
| 162 | { kX86Imul64RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul64RMI8", "!0r,[!1r+!2d],!3d" }, |
| 163 | { kX86Imul64RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { REX_W, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul64RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, |
| 164 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 165 | { kX86Mov8MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8MR", "[!0r+!1d],!2r" }, |
| 166 | { kX86Mov8AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8AR", "[!0r+!1r<<!2d+!3d],!4r" }, |
| 167 | { kX86Mov8TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8TR", "fs:[!0d],!1r" }, |
| 168 | { kX86Mov8RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RR", "!0r,!1r" }, |
| 169 | { kX86Mov8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RM", "!0r,[!1r+!2d]" }, |
| 170 | { kX86Mov8RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
| 171 | { kX86Mov8RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RT", "!0r,fs:[!1d]" }, |
| 172 | { kX86Mov8RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB0, 0, 0, 0, 0, 1 }, "Mov8RI", "!0r,!1d" }, |
| 173 | { kX86Mov8MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8MI", "[!0r+!1d],!2d" }, |
| 174 | { kX86Mov8AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8AI", "[!0r+!1r<<!2d+!3d],!4d" }, |
| 175 | { kX86Mov8TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8TI", "fs:[!0d],!1d" }, |
| 176 | |
| 177 | { kX86Mov16MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16MR", "[!0r+!1d],!2r" }, |
| 178 | { kX86Mov16AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16AR", "[!0r+!1r<<!2d+!3d],!4r" }, |
| 179 | { kX86Mov16TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0x66, 0x89, 0, 0, 0, 0, 0 }, "Mov16TR", "fs:[!0d],!1r" }, |
| 180 | { kX86Mov16RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RR", "!0r,!1r" }, |
| 181 | { kX86Mov16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RM", "!0r,[!1r+!2d]" }, |
| 182 | { kX86Mov16RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
| 183 | { kX86Mov16RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0x66, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RT", "!0r,fs:[!1d]" }, |
| 184 | { kX86Mov16RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0x66, 0, 0xB8, 0, 0, 0, 0, 2 }, "Mov16RI", "!0r,!1d" }, |
| 185 | { kX86Mov16MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16MI", "[!0r+!1d],!2d" }, |
| 186 | { kX86Mov16AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16AI", "[!0r+!1r<<!2d+!3d],!4d" }, |
| 187 | { kX86Mov16TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0xC7, 0, 0, 0, 0, 2 }, "Mov16TI", "fs:[!0d],!1d" }, |
| 188 | |
| 189 | { kX86Mov32MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32MR", "[!0r+!1d],!2r" }, |
| 190 | { kX86Mov32AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32AR", "[!0r+!1r<<!2d+!3d],!4r" }, |
| 191 | { kX86Mov32TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32TR", "fs:[!0d],!1r" }, |
| 192 | { kX86Mov32RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RR", "!0r,!1r" }, |
| 193 | { kX86Mov32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RM", "!0r,[!1r+!2d]" }, |
| 194 | { kX86Mov32RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
| 195 | { kX86Mov32RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RT", "!0r,fs:[!1d]" }, |
| 196 | { kX86Mov32RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "Mov32RI", "!0r,!1d" }, |
| 197 | { kX86Mov32MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32MI", "[!0r+!1d],!2d" }, |
| 198 | { kX86Mov32AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32AI", "[!0r+!1r<<!2d+!3d],!4d" }, |
| 199 | { kX86Mov32TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32TI", "fs:[!0d],!1d" }, |
| 200 | |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 201 | { kX86Lea32RM, kRegMem, IS_TERTIARY_OP | IS_LOAD | REG_DEF0_USE1, { 0, 0, 0x8D, 0, 0, 0, 0, 0 }, "Lea32RM", "!0r,[!1r+!2d]" }, |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 202 | |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 203 | { kX86Lea32RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8D, 0, 0, 0, 0, 0 }, "Lea32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 204 | |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 205 | { kX86Mov64MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { REX_W, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov64MR", "[!0r+!1d],!2r" }, |
| 206 | { kX86Mov64AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { REX_W, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov64AR", "[!0r+!1r<<!2d+!3d],!4r" }, |
| 207 | { kX86Mov64TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, REX_W, 0x89, 0, 0, 0, 0, 0 }, "Mov64TR", "fs:[!0d],!1r" }, |
| 208 | { kX86Mov64RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov64RR", "!0r,!1r" }, |
| 209 | { kX86Mov64RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov64RM", "!0r,[!1r+!2d]" }, |
| 210 | { kX86Mov64RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov64RA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
| 211 | { kX86Mov64RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, REX_W, 0x8B, 0, 0, 0, 0, 0 }, "Mov64RT", "!0r,fs:[!1d]" }, |
| 212 | { kX86Mov64RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { REX_W, 0, 0xB8, 0, 0, 0, 0, 8 }, "Mov64RI", "!0r,!1d" }, |
| 213 | { kX86Mov64MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { REX_W, 0, 0xC7, 0, 0, 0, 0, 8 }, "Mov64MI", "[!0r+!1d],!2d" }, |
| 214 | { kX86Mov64AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { REX_W, 0, 0xC7, 0, 0, 0, 0, 8 }, "Mov64AI", "[!0r+!1r<<!2d+!3d],!4d" }, |
| 215 | { kX86Mov64TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, REX_W, 0xC7, 0, 0, 0, 0, 8 }, "Mov64TI", "fs:[!0d],!1d" }, |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 216 | |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 217 | { kX86Lea64RM, kRegMem, IS_TERTIARY_OP | IS_LOAD | REG_DEF0_USE1, { REX_W, 0, 0x8D, 0, 0, 0, 0, 0 }, "Lea64RM", "!0r,[!1r+!2d]" }, |
| 218 | |
| 219 | { kX86Lea64RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { REX_W, 0, 0x8D, 0, 0, 0, 0, 0 }, "Lea64RA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
| 220 | |
| 221 | { kX86Cmov32RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, {0, 0, 0x0F, 0x40, 0, 0, 0, 0}, "Cmovcc32RR", "!2c !0r,!1r" }, |
| 222 | { kX86Cmov64RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, {REX_W, 0, 0x0F, 0x40, 0, 0, 0, 0}, "Cmovcc64RR", "!2c !0r,!1r" }, |
| 223 | |
| 224 | { kX86Cmov32RMC, kRegMemCond, IS_QUAD_OP | IS_LOAD | REG_DEF0_USE01 | USES_CCODES, {0, 0, 0x0F, 0x40, 0, 0, 0, 0}, "Cmovcc32RM", "!3c !0r,[!1r+!2d]" }, |
| 225 | { kX86Cmov64RMC, kRegMemCond, IS_QUAD_OP | IS_LOAD | REG_DEF0_USE01 | USES_CCODES, {REX_W, 0, 0x0F, 0x40, 0, 0, 0, 0}, "Cmovcc64RM", "!3c !0r,[!1r+!2d]" }, |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 226 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 227 | #define SHIFT_ENCODING_MAP(opname, modrm_opcode) \ |
| 228 | { kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8RI", "!0r,!1d" }, \ |
| 229 | { kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8MI", "[!0r+!1d],!2d" }, \ |
| 230 | { kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 231 | { kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8RC", "!0r,cl" }, \ |
| 232 | { kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8MC", "[!0r+!1d],cl" }, \ |
| 233 | { kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \ |
| 234 | \ |
| 235 | { kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16RI", "!0r,!1d" }, \ |
| 236 | { kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16MI", "[!0r+!1d],!2d" }, \ |
| 237 | { kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 238 | { kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16RC", "!0r,cl" }, \ |
| 239 | { kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16MC", "[!0r+!1d],cl" }, \ |
| 240 | { kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \ |
| 241 | \ |
| 242 | { kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32RI", "!0r,!1d" }, \ |
| 243 | { kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32MI", "[!0r+!1d],!2d" }, \ |
| 244 | { kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 245 | { kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32RC", "!0r,cl" }, \ |
| 246 | { kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32MC", "[!0r+!1d],cl" }, \ |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 247 | { kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" }, \ |
| 248 | \ |
| 249 | { kX86 ## opname ## 64RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { REX_W, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "64RI", "!0r,!1d" }, \ |
| 250 | { kX86 ## opname ## 64MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { REX_W, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "64MI", "[!0r+!1d],!2d" }, \ |
| 251 | { kX86 ## opname ## 64AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { REX_W, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "64AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ |
| 252 | { kX86 ## opname ## 64RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { REX_W, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "64RC", "!0r,cl" }, \ |
| 253 | { kX86 ## opname ## 64MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { REX_W, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "64MC", "[!0r+!1d],cl" }, \ |
| 254 | { kX86 ## opname ## 64AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { REX_W, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "64AC", "[!0r+!1r<<!2d+!3d],cl" } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 255 | |
| 256 | SHIFT_ENCODING_MAP(Rol, 0x0), |
| 257 | SHIFT_ENCODING_MAP(Ror, 0x1), |
| 258 | SHIFT_ENCODING_MAP(Rcl, 0x2), |
| 259 | SHIFT_ENCODING_MAP(Rcr, 0x3), |
| 260 | SHIFT_ENCODING_MAP(Sal, 0x4), |
| 261 | SHIFT_ENCODING_MAP(Shr, 0x5), |
| 262 | SHIFT_ENCODING_MAP(Sar, 0x7), |
| 263 | #undef SHIFT_ENCODING_MAP |
| 264 | |
| 265 | { kX86Cmc, kNullary, NO_OPERAND, { 0, 0, 0xF5, 0, 0, 0, 0, 0}, "Cmc", "" }, |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 266 | { kX86Shld32RRI, kRegRegImmRev, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xA4, 0, 0, 0, 1}, "Shld32RRI", "!0r,!1r,!2d" }, |
| 267 | { kX86Shld32MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { 0, 0, 0x0F, 0xA4, 0, 0, 0, 1}, "Shld32MRI", "[!0r+!1d],!2r,!3d" }, |
| 268 | { kX86Shrd32RRI, kRegRegImmRev, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xAC, 0, 0, 0, 1}, "Shrd32RRI", "!0r,!1r,!2d" }, |
| 269 | { kX86Shrd32MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { 0, 0, 0x0F, 0xAC, 0, 0, 0, 1}, "Shrd32MRI", "[!0r+!1d],!2r,!3d" }, |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 270 | { kX86Shld64RRI, kRegRegImmRev, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { REX_W, 0, 0x0F, 0xA4, 0, 0, 0, 1}, "Shld64RRI", "!0r,!1r,!2d" }, |
| 271 | { kX86Shld64MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { REX_W, 0, 0x0F, 0xA4, 0, 0, 0, 1}, "Shld64MRI", "[!0r+!1d],!2r,!3d" }, |
| 272 | { kX86Shrd64RRI, kRegRegImmRev, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { REX_W, 0, 0x0F, 0xAC, 0, 0, 0, 1}, "Shrd64RRI", "!0r,!1r,!2d" }, |
| 273 | { kX86Shrd64MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { REX_W, 0, 0x0F, 0xAC, 0, 0, 0, 1}, "Shrd64MRI", "[!0r+!1d],!2r,!3d" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 274 | |
| 275 | { kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8RI", "!0r,!1d" }, |
| 276 | { kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8MI", "[!0r+!1d],!2d" }, |
| 277 | { kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" }, |
| 278 | { kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16RI", "!0r,!1d" }, |
| 279 | { kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16MI", "[!0r+!1d],!2d" }, |
| 280 | { kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" }, |
| 281 | { kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32RI", "!0r,!1d" }, |
| 282 | { kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32MI", "[!0r+!1d],!2d" }, |
| 283 | { kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" }, |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 284 | { kX86Test64RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { REX_W, 0, 0xF7, 0, 0, 0, 0, 8}, "Test64RI", "!0r,!1d" }, |
| 285 | { kX86Test64MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { REX_W, 0, 0xF7, 0, 0, 0, 0, 8}, "Test64MI", "[!0r+!1d],!2d" }, |
| 286 | { kX86Test64AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { REX_W, 0, 0xF7, 0, 0, 0, 0, 8}, "Test64AI", "[!0r+!1r<<!2d+!3d],!4d" }, |
| 287 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 288 | { kX86Test32RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0}, "Test32RR", "!0r,!1r" }, |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 289 | { kX86Test64RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { REX_W, 0, 0x85, 0, 0, 0, 0, 0}, "Test64RR", "!0r,!1r" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 290 | |
| 291 | #define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \ |
| 292 | reg, reg_kind, reg_flags, \ |
| 293 | mem, mem_kind, mem_flags, \ |
| 294 | arr, arr_kind, arr_flags, imm, \ |
| 295 | b_flags, hw_flags, w_flags, \ |
| 296 | b_format, hw_format, w_format) \ |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 297 | { kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #reg, b_format "!0r" }, \ |
| 298 | { kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #mem, b_format "[!0r+!1d]" }, \ |
| 299 | { kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #arr, b_format "[!0r+!1r<<!2d+!3d]" }, \ |
| 300 | { kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #reg, hw_format "!0r" }, \ |
| 301 | { kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #mem, hw_format "[!0r+!1d]" }, \ |
| 302 | { kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #arr, hw_format "[!0r+!1r<<!2d+!3d]" }, \ |
| 303 | { kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #reg, w_format "!0r" }, \ |
| 304 | { kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #mem, w_format "[!0r+!1d]" }, \ |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 305 | { kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #arr, w_format "[!0r+!1r<<!2d+!3d]" }, \ |
| 306 | { kX86 ## opname ## 64 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "64" #reg, w_format "!0r" }, \ |
| 307 | { kX86 ## opname ## 64 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "64" #mem, w_format "[!0r+!1d]" }, \ |
| 308 | { kX86 ## opname ## 64 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "64" #arr, w_format "[!0r+!1r<<!2d+!3d]" } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 309 | |
| 310 | UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""), |
| 311 | UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""), |
| 312 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 313 | UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"), |
| 314 | UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"), |
| 315 | UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"), |
| 316 | UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 317 | #undef UNARY_ENCODING_MAP |
| 318 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 319 | { kx86Cdq32Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { 0, 0, 0x99, 0, 0, 0, 0, 0 }, "Cdq", "" }, |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 320 | { kx86Cqo64Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { REX_W, 0, 0x99, 0, 0, 0, 0, 0 }, "Cqo", "" }, |
Vladimir Marko | a6fd8ba | 2013-12-13 10:53:49 +0000 | [diff] [blame] | 321 | { kX86Bswap32R, kRegOpcode, IS_UNARY_OP | REG_DEF0_USE0, { 0, 0, 0x0F, 0xC8, 0, 0, 0, 0 }, "Bswap32R", "!0r" }, |
| 322 | { kX86Push32R, kRegOpcode, IS_UNARY_OP | REG_USE0 | REG_USE_SP | REG_DEF_SP | IS_STORE, { 0, 0, 0x50, 0, 0, 0, 0, 0 }, "Push32R", "!0r" }, |
| 323 | { kX86Pop32R, kRegOpcode, IS_UNARY_OP | REG_DEF0 | REG_USE_SP | REG_DEF_SP | IS_LOAD, { 0, 0, 0x58, 0, 0, 0, 0, 0 }, "Pop32R", "!0r" }, |
Vladimir Marko | a8b4caf | 2013-10-24 15:08:57 +0100 | [diff] [blame] | 324 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 325 | #define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \ |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 326 | { kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \ |
| 327 | { kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \ |
| 328 | { kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 329 | |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 330 | #define EXT_0F_REX_W_ENCODING_MAP(opname, prefix, opcode, reg_def) \ |
| 331 | { kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, REX_W, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \ |
| 332 | { kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, REX_W, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \ |
| 333 | { kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, REX_W, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } |
| 334 | |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 335 | #define EXT_0F_ENCODING2_MAP(opname, prefix, opcode, opcode2, reg_def) \ |
| 336 | { kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, opcode2, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \ |
| 337 | { kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, opcode2, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \ |
| 338 | { kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, 0, 0x0F, opcode, opcode2, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } |
| 339 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 340 | EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0), |
| 341 | { kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdMR", "[!0r+!1d],!2r" }, |
| 342 | { kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" }, |
| 343 | |
| 344 | EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0), |
| 345 | { kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssMR", "[!0r+!1d],!2r" }, |
| 346 | { kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" }, |
| 347 | |
| 348 | EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0), |
| 349 | EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0), |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 350 | EXT_0F_REX_W_ENCODING_MAP(Cvtsqi2sd, 0xF2, 0x2A, REG_DEF0), |
| 351 | EXT_0F_REX_W_ENCODING_MAP(Cvtsqi2ss, 0xF3, 0x2A, REG_DEF0), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 352 | EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0), |
| 353 | EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0), |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 354 | EXT_0F_REX_W_ENCODING_MAP(Cvttsd2sqi, 0xF2, 0x2C, REG_DEF0), |
| 355 | EXT_0F_REX_W_ENCODING_MAP(Cvttss2sqi, 0xF3, 0x2C, REG_DEF0), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 356 | EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0), |
| 357 | EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0), |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 358 | EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES|REG_USE0), |
| 359 | EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES|REG_USE0), |
| 360 | EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES|REG_USE0), |
| 361 | EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES|REG_USE0), |
| 362 | EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0_USE0), |
| 363 | EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0_USE0), |
| 364 | EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0_USE0), |
| 365 | EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0_USE0), |
| 366 | EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0_USE0), |
| 367 | EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0_USE0), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 368 | EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0), |
| 369 | EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0), |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 370 | EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0_USE0), |
| 371 | EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0_USE0), |
| 372 | EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0_USE0), |
| 373 | EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0_USE0), |
| 374 | EXT_0F_ENCODING_MAP(Punpckldq, 0x66, 0x62, REG_DEF0_USE0), |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 375 | EXT_0F_ENCODING_MAP(Sqrtsd, 0xF2, 0x51, REG_DEF0_USE0), |
| 376 | EXT_0F_ENCODING2_MAP(Pmulld, 0x66, 0x38, 0x40, REG_DEF0_USE0), |
| 377 | EXT_0F_ENCODING_MAP(Pmullw, 0x66, 0xD5, REG_DEF0_USE0), |
| 378 | EXT_0F_ENCODING_MAP(Mulps, 0x00, 0x59, REG_DEF0_USE0), |
| 379 | EXT_0F_ENCODING_MAP(Mulpd, 0x66, 0x59, REG_DEF0_USE0), |
| 380 | EXT_0F_ENCODING_MAP(Paddb, 0x66, 0xFC, REG_DEF0_USE0), |
| 381 | EXT_0F_ENCODING_MAP(Paddw, 0x66, 0xFD, REG_DEF0_USE0), |
| 382 | EXT_0F_ENCODING_MAP(Paddd, 0x66, 0xFE, REG_DEF0_USE0), |
| 383 | EXT_0F_ENCODING_MAP(Addps, 0x00, 0x58, REG_DEF0_USE0), |
| 384 | EXT_0F_ENCODING_MAP(Addpd, 0xF2, 0x58, REG_DEF0_USE0), |
| 385 | EXT_0F_ENCODING_MAP(Psubb, 0x66, 0xF8, REG_DEF0_USE0), |
| 386 | EXT_0F_ENCODING_MAP(Psubw, 0x66, 0xF9, REG_DEF0_USE0), |
| 387 | EXT_0F_ENCODING_MAP(Psubd, 0x66, 0xFA, REG_DEF0_USE0), |
| 388 | EXT_0F_ENCODING_MAP(Subps, 0x00, 0x5C, REG_DEF0_USE0), |
| 389 | EXT_0F_ENCODING_MAP(Subpd, 0x66, 0x5C, REG_DEF0_USE0), |
| 390 | EXT_0F_ENCODING_MAP(Pand, 0x66, 0xDB, REG_DEF0_USE0), |
| 391 | EXT_0F_ENCODING_MAP(Por, 0x66, 0xEB, REG_DEF0_USE0), |
| 392 | EXT_0F_ENCODING_MAP(Pxor, 0x66, 0xEF, REG_DEF0_USE0), |
| 393 | EXT_0F_ENCODING2_MAP(Phaddw, 0x66, 0x38, 0x01, REG_DEF0_USE0), |
| 394 | EXT_0F_ENCODING2_MAP(Phaddd, 0x66, 0x38, 0x02, REG_DEF0_USE0), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 395 | |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 396 | { kX86PextrbRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x3A, 0x14, 0, 0, 1 }, "PextbRRI", "!0r,!1r,!2d" }, |
| 397 | { kX86PextrwRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0xC5, 0x00, 0, 0, 1 }, "PextwRRI", "!0r,!1r,!2d" }, |
| 398 | { kX86PextrdRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x3A, 0x16, 0, 0, 1 }, "PextdRRI", "!0r,!1r,!2d" }, |
| 399 | |
| 400 | { kX86PshuflwRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0xF2, 0, 0x0F, 0x70, 0, 0, 0, 1 }, "PshuflwRRI", "!0r,!1r,!2d" }, |
| 401 | { kX86PshufdRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x70, 0, 0, 0, 1 }, "PshuffRRI", "!0r,!1r,!2d" }, |
| 402 | |
| 403 | { kX86PsrawRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x71, 0, 4, 0, 1 }, "PsrawRI", "!0r,!1d" }, |
| 404 | { kX86PsradRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x72, 0, 4, 0, 1 }, "PsradRI", "!0r,!1d" }, |
| 405 | { kX86PsrlwRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x71, 0, 2, 0, 1 }, "PsrlwRI", "!0r,!1d" }, |
| 406 | { kX86PsrldRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x72, 0, 2, 0, 1 }, "PsrldRI", "!0r,!1d" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 407 | { kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1 }, "PsrlqRI", "!0r,!1d" }, |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 408 | { kX86PsllwRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x71, 0, 6, 0, 1 }, "PsllwRI", "!0r,!1d" }, |
| 409 | { kX86PslldRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x72, 0, 6, 0, 1 }, "PslldRI", "!0r,!1d" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 410 | { kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1 }, "PsllqRI", "!0r,!1d" }, |
Razvan A Lupusoru | 614c2b4 | 2014-01-28 17:05:21 -0800 | [diff] [blame] | 411 | |
Serguei Katkov | e90501d | 2014-03-12 15:56:54 +0700 | [diff] [blame] | 412 | { kX86Fild32M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDB, 0x00, 0, 0, 0, 0 }, "Fild32M", "[!0r,!1d]" }, |
| 413 | { kX86Fild64M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDF, 0x00, 0, 5, 0, 0 }, "Fild64M", "[!0r,!1d]" }, |
| 414 | { kX86Fstp32M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xD9, 0x00, 0, 3, 0, 0 }, "FstpsM", "[!0r,!1d]" }, |
| 415 | { kX86Fstp64M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDD, 0x00, 0, 3, 0, 0 }, "FstpdM", "[!0r,!1d]" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 416 | |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 417 | EXT_0F_ENCODING_MAP(Mova128, 0x66, 0x6F, REG_DEF0), |
| 418 | { kX86Mova128MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x6F, 0, 0, 0, 0 }, "Mova128MR", "[!0r+!1d],!2r" }, |
| 419 | { kX86Mova128AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x6F, 0, 0, 0, 0 }, "Mova128AR", "[!0r+!1r<<!2d+!3d],!4r" }, |
| 420 | |
| 421 | |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 422 | EXT_0F_ENCODING_MAP(Movups, 0x0, 0x10, REG_DEF0), |
| 423 | { kX86MovupsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovupsMR", "[!0r+!1d],!2r" }, |
| 424 | { kX86MovupsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovupsAR", "[!0r+!1r<<!2d+!3d],!4r" }, |
| 425 | |
| 426 | EXT_0F_ENCODING_MAP(Movaps, 0x0, 0x28, REG_DEF0), |
| 427 | { kX86MovapsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0 }, "MovapsMR", "[!0r+!1d],!2r" }, |
| 428 | { kX86MovapsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0 }, "MovapsAR", "[!0r+!1r<<!2d+!3d],!4r" }, |
| 429 | |
| 430 | { kX86MovlpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0 }, "MovlpsRM", "!0r,[!1r+!2d]" }, |
| 431 | { kX86MovlpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0 }, "MovlpsRA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
| 432 | { kX86MovlpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0 }, "MovlpsMR", "[!0r+!1d],!2r" }, |
| 433 | { kX86MovlpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0 }, "MovlpsAR", "[!0r+!1r<<!2d+!3d],!4r" }, |
| 434 | |
| 435 | { kX86MovhpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0 }, "MovhpsRM", "!0r,[!1r+!2d]" }, |
| 436 | { kX86MovhpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0 }, "MovhpsRA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
| 437 | { kX86MovhpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0 }, "MovhpsMR", "[!0r+!1d],!2r" }, |
| 438 | { kX86MovhpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0 }, "MovhpsAR", "[!0r+!1r<<!2d+!3d],!4r" }, |
| 439 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 440 | EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0), |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 441 | EXT_0F_REX_W_ENCODING_MAP(Movqxr, 0x66, 0x6E, REG_DEF0), |
| 442 | { kX86MovqrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE1, { 0x66, REX_W, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovqrxRR", "!0r,!1r" }, |
| 443 | { kX86MovqrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, REX_W, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovqrxMR", "[!0r+!1d],!2r" }, |
| 444 | { kX86MovqrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, REX_W, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovqrxAR", "[!0r+!1r<<!2d+!3d],!4r" }, |
| 445 | |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 446 | { kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxRR", "!0r,!1r" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 447 | { kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxMR", "[!0r+!1d],!2r" }, |
| 448 | { kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" }, |
| 449 | |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 450 | { kX86MovsxdRR, kRegReg, IS_BINARY_OP | REG_DEF0 | REG_USE1, { REX_W, 0, 0x63, 0, 0, 0, 0, 0 }, "MovsxdRR", "!0r,!1r" }, |
| 451 | { kX86MovsxdRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { REX_W, 0, 0x63, 0, 0, 0, 0, 0 }, "MovsxdRM", "!0r,[!1r+!2d]" }, |
| 452 | { kX86MovsxdRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE12, { REX_W, 0, 0x63, 0, 0, 0, 0, 0 }, "MovsxdRA", "!0r,[!1r+!2r<<!3d+!4d]" }, |
| 453 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 454 | { kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8R", "!1c !0r" }, |
| 455 | { kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8M", "!2c [!0r+!1d]" }, |
| 456 | { kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" }, |
| 457 | |
| 458 | // TODO: load/store? |
| 459 | // Encode the modrm opcode as an extra opcode byte to avoid computation during assembly. |
| 460 | { kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0 }, "Mfence", "" }, |
| 461 | |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 462 | EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES), |
| 463 | EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES), |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 464 | EXT_0F_ENCODING_MAP(Imul64, REX_W, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 465 | |
| 466 | { kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "!0r,!1r" }, |
| 467 | { kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1d],!2r" }, |
| 468 | { kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 469 | { kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1d],!2r" }, |
| 470 | { kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" }, |
Vladimir Marko | 70b797d | 2013-12-03 15:25:24 +0000 | [diff] [blame] | 471 | { kX86LockCmpxchg8bM, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1d]" }, |
| 472 | { kX86LockCmpxchg8bA, kArray, IS_STORE | IS_QUAD_OP | REG_USE01 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1r<<!2d+!3d]" }, |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 473 | { kX86XchgMR, kMemReg, IS_STORE | IS_LOAD | IS_TERTIARY_OP | REG_DEF2 | REG_USE02, { 0, 0, 0x87, 0, 0, 0, 0, 0 }, "Xchg", "[!0r+!1d],!2r" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 474 | |
| 475 | EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0), |
| 476 | EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0), |
| 477 | EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0), |
| 478 | EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0), |
| 479 | #undef EXT_0F_ENCODING_MAP |
| 480 | |
| 481 | { kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc8", "!1c !0t" }, |
| 482 | { kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0 }, "Jcc32", "!1c !0t" }, |
| 483 | { kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0 }, "Jmp8", "!0t" }, |
| 484 | { kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp32", "!0t" }, |
| 485 | { kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpR", "!0r" }, |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 486 | { kX86Jecxz8, kJmp, NO_OPERAND | IS_BRANCH | NEEDS_FIXUP | REG_USEC, { 0, 0, 0xE3, 0, 0, 0, 0, 0 }, "Jecxz", "!0t" }, |
Brian Carlstrom | 60d7a65 | 2014-03-13 18:10:08 -0700 | [diff] [blame] | 487 | { kX86JmpT, kJmp, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpT", "fs:[!0d]" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 488 | { kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "!0r" }, |
| 489 | { kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "[!0r+!1d]" }, |
| 490 | { kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "[!0r+!1r<<!2d+!3d]" }, |
| 491 | { kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallT", "fs:[!0d]" }, |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 492 | { kX86CallI, kCall, IS_UNARY_OP | IS_BRANCH, { 0, 0, 0xE8, 0, 0, 0, 0, 4 }, "CallI", "!0d" }, |
Brian Carlstrom | b1eba21 | 2013-07-17 18:07:19 -0700 | [diff] [blame] | 493 | { kX86Ret, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0 }, "Ret", "" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 494 | |
| 495 | { kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0 }, "StartOfMethod", "!0r" }, |
| 496 | { kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" }, |
| 497 | { kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "PcRelAdr", "!0r,!1d" }, |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 498 | { kX86RepneScasw, kPrefix2Nullary, NO_OPERAND | REG_USEA | REG_USEC | SETS_CCODES, { 0x66, 0xF2, 0xAF, 0, 0, 0, 0, 0 }, "RepNE ScasW", "" }, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 499 | }; |
| 500 | |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 501 | size_t X86Mir2Lir::ComputeSize(const X86EncodingMap* entry, int base, int displacement, |
| 502 | int reg_r, int reg_x, bool has_sib) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 503 | size_t size = 0; |
| 504 | if (entry->skeleton.prefix1 > 0) { |
| 505 | ++size; |
| 506 | if (entry->skeleton.prefix2 > 0) { |
| 507 | ++size; |
| 508 | } |
| 509 | } |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 510 | if ((NeedsRex(base) || NeedsRex(reg_r) || NeedsRex(reg_x)) && |
| 511 | entry->skeleton.prefix1 != REX_W && entry->skeleton.prefix2 != REX_W) { |
| 512 | ++size; // REX_R |
| 513 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 514 | ++size; // opcode |
| 515 | if (entry->skeleton.opcode == 0x0F) { |
| 516 | ++size; |
| 517 | if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { |
| 518 | ++size; |
| 519 | } |
| 520 | } |
| 521 | ++size; // modrm |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 522 | if (has_sib || LowRegisterBits(RegStorage::RegNum(base)) == rs_rX86_SP.GetRegNum() |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 523 | || (Gen64Bit() && entry->skeleton.prefix1 == THREAD_PREFIX)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 524 | // SP requires a SIB byte. |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 525 | // GS access also needs a SIB byte for absolute adressing in 64-bit mode. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 526 | ++size; |
| 527 | } |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 528 | if (displacement != 0 || LowRegisterBits(RegStorage::RegNum(base)) == rs_rBP.GetRegNum()) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 529 | // BP requires an explicit displacement, even when it's 0. |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 530 | if (entry->opcode != kX86Lea32RA && entry->opcode != kX86Lea64RA) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 531 | DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0ULL) << entry->name; |
| 532 | } |
| 533 | size += IS_SIMM8(displacement) ? 1 : 4; |
| 534 | } |
| 535 | size += entry->skeleton.immediate_bytes; |
| 536 | return size; |
| 537 | } |
| 538 | |
| 539 | int X86Mir2Lir::GetInsnSize(LIR* lir) { |
buzbee | 409fe94 | 2013-10-11 10:49:56 -0700 | [diff] [blame] | 540 | DCHECK(!IsPseudoLirOp(lir->opcode)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 541 | const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode]; |
| 542 | switch (entry->kind) { |
| 543 | case kData: |
| 544 | return 4; // 4 bytes of data |
| 545 | case kNop: |
| 546 | return lir->operands[0]; // length of nop is sole operand |
| 547 | case kNullary: |
| 548 | return 1; // 1 byte of opcode |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 549 | case kPrefix2Nullary: |
| 550 | return 3; // 1 byte of opcode + 2 prefixes |
Vladimir Marko | a8b4caf | 2013-10-24 15:08:57 +0100 | [diff] [blame] | 551 | case kRegOpcode: // lir operands - 0: reg |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 552 | // substract 1 for modrm |
| 553 | return ComputeSize(entry, 0, 0, lir->operands[0], NO_REG, false) - 1; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 554 | case kReg: // lir operands - 0: reg |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 555 | return ComputeSize(entry, 0, 0, lir->operands[0], NO_REG, false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 556 | case kMem: // lir operands - 0: base, 1: disp |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 557 | return ComputeSize(entry, lir->operands[0], lir->operands[1], NO_REG, NO_REG, false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 558 | case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 559 | return ComputeSize(entry, lir->operands[0], lir->operands[3], |
| 560 | NO_REG, lir->operands[1], true); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 561 | case kMemReg: // lir operands - 0: base, 1: disp, 2: reg |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 562 | return ComputeSize(entry, lir->operands[0], lir->operands[1], |
| 563 | lir->operands[2], NO_REG, false); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 564 | case kMemRegImm: // lir operands - 0: base, 1: disp, 2: reg 3: immediate |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 565 | return ComputeSize(entry, lir->operands[0], lir->operands[1], |
| 566 | lir->operands[2], NO_REG, false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 567 | case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 568 | return ComputeSize(entry, lir->operands[0], lir->operands[3], |
| 569 | lir->operands[4], lir->operands[1], true); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 570 | case kThreadReg: // lir operands - 0: disp, 1: reg |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 571 | return ComputeSize(entry, 0, lir->operands[0], lir->operands[1], NO_REG, false); |
| 572 | case kRegReg: // lir operands - 0: reg1, 1: reg2 |
| 573 | return ComputeSize(entry, 0, 0, lir->operands[0], lir->operands[1], false); |
| 574 | case kRegRegStore: // lir operands - 0: reg2, 1: reg1 |
| 575 | return ComputeSize(entry, 0, 0, lir->operands[1], lir->operands[0], false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 576 | case kRegMem: // lir operands - 0: reg, 1: base, 2: disp |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 577 | return ComputeSize(entry, lir->operands[1], lir->operands[2], |
| 578 | lir->operands[0], NO_REG, false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 579 | case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 580 | return ComputeSize(entry, lir->operands[1], lir->operands[4], |
| 581 | lir->operands[0], lir->operands[2], true); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 582 | case kRegThread: // lir operands - 0: reg, 1: disp |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 583 | // displacement size is always 32bit |
| 584 | return ComputeSize(entry, 0, 0x12345678, lir->operands[0], NO_REG, false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 585 | case kRegImm: { // lir operands - 0: reg, 1: immediate |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 586 | size_t size = ComputeSize(entry, 0, 0, lir->operands[0], NO_REG, false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 587 | if (entry->skeleton.ax_opcode == 0) { |
| 588 | return size; |
| 589 | } else { |
| 590 | // AX opcodes don't require the modrm byte. |
| 591 | int reg = lir->operands[0]; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 592 | return size - (RegStorage::RegNum(reg) == rs_rAX.GetRegNum() ? 1 : 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 593 | } |
| 594 | } |
| 595 | case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 596 | return ComputeSize(entry, lir->operands[0], lir->operands[1], |
| 597 | NO_REG, lir->operands[0], false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 598 | case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 599 | return ComputeSize(entry, lir->operands[0], lir->operands[3], |
| 600 | NO_REG, lir->operands[1], true); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 601 | case kThreadImm: // lir operands - 0: disp, 1: imm |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 602 | // displacement size is always 32bit |
| 603 | return ComputeSize(entry, 0, 0x12345678, NO_REG, NO_REG, false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 604 | case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 605 | case kRegRegImmRev: |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 606 | return ComputeSize(entry, 0, 0, lir->operands[0], lir->operands[1], false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 607 | case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 608 | return ComputeSize(entry, lir->operands[1], lir->operands[2], |
| 609 | lir->operands[0], NO_REG, false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 610 | case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 611 | return ComputeSize(entry, lir->operands[1], lir->operands[4], |
| 612 | lir->operands[0], lir->operands[2], true); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 613 | case kMovRegImm: // lir operands - 0: reg, 1: immediate |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 614 | return (entry->skeleton.prefix1 != 0 || NeedsRex(lir->operands[0])?1:0) + |
| 615 | 1 + entry->skeleton.immediate_bytes; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 616 | case kShiftRegImm: // lir operands - 0: reg, 1: immediate |
| 617 | // Shift by immediate one has a shorter opcode. |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 618 | return ComputeSize(entry, 0, 0, lir->operands[0], NO_REG, false) - |
| 619 | (lir->operands[1] == 1 ? 1 : 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 620 | case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate |
| 621 | // Shift by immediate one has a shorter opcode. |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 622 | return ComputeSize(entry, lir->operands[0], lir->operands[1], NO_REG, NO_REG, false) - |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 623 | (lir->operands[2] == 1 ? 1 : 0); |
| 624 | case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate |
| 625 | // Shift by immediate one has a shorter opcode. |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 626 | return ComputeSize(entry, lir->operands[0], lir->operands[3], |
| 627 | NO_REG, lir->operands[1], true) - |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 628 | (lir->operands[4] == 1 ? 1 : 0); |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 629 | case kShiftRegCl: // lir operands - 0: reg, 1: cl |
| 630 | return ComputeSize(entry, 0, 0, lir->operands[0], NO_REG, false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 631 | case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 632 | return ComputeSize(entry, lir->operands[0], lir->operands[1], NO_REG, NO_REG, false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 633 | case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 634 | return ComputeSize(entry, lir->operands[0], lir->operands[3], |
| 635 | lir->operands[4], lir->operands[1], true); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 636 | case kRegCond: // lir operands - 0: reg, 1: cond |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 637 | return ComputeSize(entry, 0, 0, lir->operands[0], NO_REG, false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 638 | case kMemCond: // lir operands - 0: base, 1: disp, 2: cond |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 639 | return ComputeSize(entry, lir->operands[0], lir->operands[1], NO_REG, NO_REG, false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 640 | case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 641 | return ComputeSize(entry, lir->operands[0], lir->operands[3], |
| 642 | NO_REG, lir->operands[1], true); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 643 | case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: cond |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 644 | return ComputeSize(entry, 0, 0, lir->operands[0], lir->operands[1], false); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 645 | case kRegMemCond: // lir operands - 0: reg, 1: reg, 2: disp, 3:cond |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 646 | return ComputeSize(entry, lir->operands[1], lir->operands[2], |
| 647 | lir->operands[0], lir->operands[1], false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 648 | case kJcc: |
| 649 | if (lir->opcode == kX86Jcc8) { |
| 650 | return 2; // opcode + rel8 |
| 651 | } else { |
| 652 | DCHECK(lir->opcode == kX86Jcc32); |
| 653 | return 6; // 2 byte opcode + rel32 |
| 654 | } |
| 655 | case kJmp: |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 656 | if (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jecxz8) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 657 | return 2; // opcode + rel8 |
| 658 | } else if (lir->opcode == kX86Jmp32) { |
| 659 | return 5; // opcode + rel32 |
Brian Carlstrom | 60d7a65 | 2014-03-13 18:10:08 -0700 | [diff] [blame] | 660 | } else if (lir->opcode == kX86JmpT) { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 661 | // displacement size is always 32bit |
| 662 | return ComputeSize(entry, 0, 0x12345678, NO_REG, NO_REG, false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 663 | } else { |
| 664 | DCHECK(lir->opcode == kX86JmpR); |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 665 | if (NeedsRex(lir->operands[0])) { |
| 666 | return 3; // REX.B + opcode + modrm |
| 667 | } else { |
| 668 | return 2; // opcode + modrm |
| 669 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 670 | } |
| 671 | case kCall: |
| 672 | switch (lir->opcode) { |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 673 | case kX86CallI: return 5; // opcode 0:disp |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 674 | case kX86CallR: return 2; // opcode modrm |
| 675 | case kX86CallM: // lir operands - 0: base, 1: disp |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 676 | return ComputeSize(entry, lir->operands[0], lir->operands[1], NO_REG, NO_REG, false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 677 | case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 678 | return ComputeSize(entry, lir->operands[0], lir->operands[3], |
| 679 | NO_REG, lir->operands[1], true); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 680 | case kX86CallT: // lir operands - 0: disp |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 681 | // displacement size is always 32bit |
| 682 | return ComputeSize(entry, 0, 0x12345678, NO_REG, NO_REG, false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 683 | default: |
| 684 | break; |
| 685 | } |
| 686 | break; |
| 687 | case kPcRel: |
| 688 | if (entry->opcode == kX86PcRelLoadRA) { |
| 689 | // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 690 | return ComputeSize(entry, lir->operands[1], 0x12345678, |
| 691 | lir->operands[0], lir->operands[2], true); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 692 | } else { |
| 693 | DCHECK(entry->opcode == kX86PcRelAdr); |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 694 | return 5; // opcode with reg + 4 byte immediate |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 695 | } |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 696 | case kMacro: // lir operands - 0: reg |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 697 | DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod)); |
| 698 | return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ + |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 699 | ComputeSize(&X86Mir2Lir::EncodingMap[Gen64Bit() ? kX86Sub64RI : kX86Sub32RI], 0, 0, |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 700 | lir->operands[0], NO_REG, false) - |
| 701 | // shorter ax encoding |
| 702 | (RegStorage::RegNum(lir->operands[0]) == rs_rAX.GetRegNum() ? 1 : 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 703 | default: |
| 704 | break; |
| 705 | } |
| 706 | UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name; |
| 707 | return 0; |
| 708 | } |
| 709 | |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 710 | void X86Mir2Lir::EmitPrefix(const X86EncodingMap* entry) { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 711 | EmitPrefix(entry, NO_REG, NO_REG, NO_REG); |
| 712 | } |
| 713 | |
| 714 | void X86Mir2Lir::EmitPrefix(const X86EncodingMap* entry, |
| 715 | uint8_t reg_r, uint8_t reg_x, uint8_t reg_b) { |
| 716 | // REX.WRXB |
| 717 | // W - 64-bit operand |
| 718 | // R - MODRM.reg |
| 719 | // X - SIB.index |
| 720 | // B - MODRM.rm/SIB.base |
| 721 | bool force = false; |
| 722 | bool w = (entry->skeleton.prefix1 == REX_W) || (entry->skeleton.prefix2 == REX_W); |
| 723 | bool r = NeedsRex(reg_r); |
| 724 | bool x = NeedsRex(reg_x); |
| 725 | bool b = NeedsRex(reg_b); |
| 726 | uint8_t rex = force ? 0x40 : 0; |
| 727 | if (w) { |
| 728 | rex |= 0x48; // REX.W000 |
| 729 | } |
| 730 | if (r) { |
| 731 | rex |= 0x44; // REX.0R00 |
| 732 | } |
| 733 | if (x) { |
| 734 | rex |= 0x42; // REX.00X0 |
| 735 | } |
| 736 | if (b) { |
| 737 | rex |= 0x41; // REX.000B |
| 738 | } |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 739 | if (entry->skeleton.prefix1 != 0) { |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 740 | if (Gen64Bit() && entry->skeleton.prefix1 == THREAD_PREFIX) { |
| 741 | // 64 bit adresses by GS, not FS |
| 742 | code_buffer_.push_back(THREAD_PREFIX_GS); |
| 743 | } else { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 744 | if (entry->skeleton.prefix1 == REX_W) { |
| 745 | rex |= entry->skeleton.prefix1; |
| 746 | code_buffer_.push_back(rex); |
| 747 | rex = 0; |
| 748 | } else { |
| 749 | code_buffer_.push_back(entry->skeleton.prefix1); |
| 750 | } |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 751 | } |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 752 | if (entry->skeleton.prefix2 != 0) { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 753 | if (entry->skeleton.prefix2 == REX_W) { |
| 754 | rex |= entry->skeleton.prefix2; |
| 755 | code_buffer_.push_back(rex); |
| 756 | rex = 0; |
| 757 | } else { |
| 758 | code_buffer_.push_back(entry->skeleton.prefix2); |
| 759 | } |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 760 | } |
| 761 | } else { |
| 762 | DCHECK_EQ(0, entry->skeleton.prefix2); |
| 763 | } |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 764 | if (rex != 0) { |
| 765 | code_buffer_.push_back(rex); |
| 766 | } |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 767 | } |
| 768 | |
| 769 | void X86Mir2Lir::EmitOpcode(const X86EncodingMap* entry) { |
| 770 | code_buffer_.push_back(entry->skeleton.opcode); |
| 771 | if (entry->skeleton.opcode == 0x0F) { |
| 772 | code_buffer_.push_back(entry->skeleton.extra_opcode1); |
| 773 | if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { |
| 774 | code_buffer_.push_back(entry->skeleton.extra_opcode2); |
| 775 | } else { |
| 776 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
| 777 | } |
| 778 | } else { |
| 779 | DCHECK_EQ(0, entry->skeleton.extra_opcode1); |
| 780 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
| 781 | } |
| 782 | } |
| 783 | |
| 784 | void X86Mir2Lir::EmitPrefixAndOpcode(const X86EncodingMap* entry) { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 785 | EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG); |
| 786 | } |
| 787 | |
| 788 | void X86Mir2Lir::EmitPrefixAndOpcode(const X86EncodingMap* entry, |
| 789 | uint8_t reg_r, uint8_t reg_x, uint8_t reg_b) { |
| 790 | EmitPrefix(entry, reg_r, reg_x, reg_b); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 791 | EmitOpcode(entry); |
| 792 | } |
| 793 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 794 | static uint8_t ModrmForDisp(int base, int disp) { |
| 795 | // BP requires an explicit disp, so do not omit it in the 0 case |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 796 | if (disp == 0 && RegStorage::RegNum(base) != rs_rBP.GetRegNum()) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 797 | return 0; |
| 798 | } else if (IS_SIMM8(disp)) { |
| 799 | return 1; |
| 800 | } else { |
| 801 | return 2; |
| 802 | } |
| 803 | } |
| 804 | |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 805 | void X86Mir2Lir::EmitDisp(uint8_t base, int disp) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 806 | // BP requires an explicit disp, so do not omit it in the 0 case |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 807 | if (disp == 0 && RegStorage::RegNum(base) != rs_rBP.GetRegNum()) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 808 | return; |
| 809 | } else if (IS_SIMM8(disp)) { |
| 810 | code_buffer_.push_back(disp & 0xFF); |
| 811 | } else { |
| 812 | code_buffer_.push_back(disp & 0xFF); |
| 813 | code_buffer_.push_back((disp >> 8) & 0xFF); |
| 814 | code_buffer_.push_back((disp >> 16) & 0xFF); |
| 815 | code_buffer_.push_back((disp >> 24) & 0xFF); |
| 816 | } |
| 817 | } |
| 818 | |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 819 | void X86Mir2Lir::EmitModrmThread(uint8_t reg_or_opcode) { |
| 820 | if (Gen64Bit()) { |
| 821 | // Absolute adressing for GS access. |
| 822 | uint8_t modrm = (0 << 6) | (reg_or_opcode << 3) | rs_rX86_SP.GetRegNum(); |
| 823 | code_buffer_.push_back(modrm); |
| 824 | uint8_t sib = (0/*TIMES_1*/ << 6) | (rs_rX86_SP.GetRegNum() << 3) | rs_rBP.GetRegNum(); |
| 825 | code_buffer_.push_back(sib); |
| 826 | } else { |
| 827 | uint8_t modrm = (0 << 6) | (reg_or_opcode << 3) | rs_rBP.GetRegNum(); |
| 828 | code_buffer_.push_back(modrm); |
| 829 | } |
| 830 | } |
| 831 | |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 832 | void X86Mir2Lir::EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int disp) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 833 | DCHECK_LT(RegStorage::RegNum(reg_or_opcode), 8); |
| 834 | DCHECK_LT(RegStorage::RegNum(base), 8); |
| 835 | uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (RegStorage::RegNum(reg_or_opcode) << 3) | |
| 836 | RegStorage::RegNum(base); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 837 | code_buffer_.push_back(modrm); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 838 | if (RegStorage::RegNum(base) == rs_rX86_SP.GetRegNum()) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 839 | // Special SIB for SP base |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 840 | code_buffer_.push_back(0 << 6 | rs_rX86_SP.GetRegNum() << 3 | rs_rX86_SP.GetRegNum()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 841 | } |
| 842 | EmitDisp(base, disp); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 843 | } |
| 844 | |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 845 | void X86Mir2Lir::EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, |
| 846 | int scale, int disp) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 847 | DCHECK_LT(RegStorage::RegNum(reg_or_opcode), 8); |
| 848 | uint8_t modrm = (ModrmForDisp(base, disp) << 6) | RegStorage::RegNum(reg_or_opcode) << 3 | |
| 849 | rs_rX86_SP.GetRegNum(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 850 | code_buffer_.push_back(modrm); |
| 851 | DCHECK_LT(scale, 4); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 852 | DCHECK_LT(RegStorage::RegNum(index), 8); |
| 853 | DCHECK_LT(RegStorage::RegNum(base), 8); |
| 854 | uint8_t sib = (scale << 6) | (RegStorage::RegNum(index) << 3) | RegStorage::RegNum(base); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 855 | code_buffer_.push_back(sib); |
| 856 | EmitDisp(base, disp); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 857 | } |
| 858 | |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 859 | void X86Mir2Lir::EmitImm(const X86EncodingMap* entry, int64_t imm) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 860 | switch (entry->skeleton.immediate_bytes) { |
| 861 | case 1: |
| 862 | DCHECK(IS_SIMM8(imm)); |
| 863 | code_buffer_.push_back(imm & 0xFF); |
| 864 | break; |
| 865 | case 2: |
| 866 | DCHECK(IS_SIMM16(imm)); |
| 867 | code_buffer_.push_back(imm & 0xFF); |
| 868 | code_buffer_.push_back((imm >> 8) & 0xFF); |
| 869 | break; |
| 870 | case 4: |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 871 | if (imm <0) { |
| 872 | CHECK_EQ((-imm) & 0x0FFFFFFFFl, -imm); |
| 873 | } else { |
| 874 | CHECK_EQ(imm & 0x0FFFFFFFFl, imm); |
| 875 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 876 | code_buffer_.push_back(imm & 0xFF); |
| 877 | code_buffer_.push_back((imm >> 8) & 0xFF); |
| 878 | code_buffer_.push_back((imm >> 16) & 0xFF); |
| 879 | code_buffer_.push_back((imm >> 24) & 0xFF); |
| 880 | break; |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 881 | case 8: |
| 882 | code_buffer_.push_back(imm & 0xFF); |
| 883 | code_buffer_.push_back((imm >> 8) & 0xFF); |
| 884 | code_buffer_.push_back((imm >> 16) & 0xFF); |
| 885 | code_buffer_.push_back((imm >> 24) & 0xFF); |
| 886 | code_buffer_.push_back((imm >> 32) & 0xFF); |
| 887 | code_buffer_.push_back((imm >> 40) & 0xFF); |
| 888 | code_buffer_.push_back((imm >> 48) & 0xFF); |
| 889 | code_buffer_.push_back((imm >> 56) & 0xFF); |
| 890 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 891 | default: |
| 892 | LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes |
| 893 | << ") for instruction: " << entry->name; |
| 894 | break; |
| 895 | } |
| 896 | } |
| 897 | |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 898 | void X86Mir2Lir::EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg) { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 899 | EmitPrefixAndOpcode(entry, reg, NO_REG, NO_REG); |
| 900 | reg = LowRegisterBits(reg); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 901 | // There's no 3-byte instruction with +rd |
| 902 | DCHECK(entry->skeleton.opcode != 0x0F || |
| 903 | (entry->skeleton.extra_opcode1 != 0x38 && entry->skeleton.extra_opcode1 != 0x3A)); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 904 | DCHECK(!RegStorage::IsFloat(reg)); |
| 905 | DCHECK_LT(RegStorage::RegNum(reg), 8); |
| 906 | code_buffer_.back() += RegStorage::RegNum(reg); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 907 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 908 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 909 | } |
| 910 | |
| 911 | void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, uint8_t reg) { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 912 | EmitPrefixAndOpcode(entry, reg, NO_REG, NO_REG); |
| 913 | reg = LowRegisterBits(reg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 914 | if (RegStorage::RegNum(reg) >= 4) { |
| 915 | DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " |
| 916 | << static_cast<int>(RegStorage::RegNum(reg)) |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 917 | << " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file); |
| 918 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 919 | DCHECK_LT(RegStorage::RegNum(reg), 8); |
| 920 | uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | RegStorage::RegNum(reg); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 921 | code_buffer_.push_back(modrm); |
| 922 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 923 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 924 | } |
| 925 | |
| 926 | void X86Mir2Lir::EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp) { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 927 | EmitPrefix(entry, NO_REG, NO_REG, base); |
| 928 | base = LowRegisterBits(base); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 929 | code_buffer_.push_back(entry->skeleton.opcode); |
| 930 | DCHECK_NE(0x0F, entry->skeleton.opcode); |
| 931 | DCHECK_EQ(0, entry->skeleton.extra_opcode1); |
| 932 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 933 | EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp); |
| 934 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 935 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 936 | } |
| 937 | |
| 938 | void X86Mir2Lir::EmitOpArray(const X86EncodingMap* entry, uint8_t base, uint8_t index, |
| 939 | int scale, int disp) { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 940 | EmitPrefixAndOpcode(entry, NO_REG, index, base); |
| 941 | index = LowRegisterBits(index); |
| 942 | base = LowRegisterBits(base); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 943 | EmitModrmSibDisp(entry->skeleton.modrm_opcode, base, index, scale, disp); |
| 944 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 945 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 946 | } |
| 947 | |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 948 | uint8_t X86Mir2Lir::LowRegisterBits(uint8_t reg) { |
| 949 | uint8_t res = reg; |
| 950 | res = reg & kRegNumMask32; // 3 bits |
| 951 | return res; |
| 952 | } |
| 953 | |
| 954 | bool X86Mir2Lir::NeedsRex(uint8_t reg) { |
| 955 | return RegStorage::RegNum(reg) > 7; |
| 956 | } |
| 957 | |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 958 | void X86Mir2Lir::EmitMemReg(const X86EncodingMap* entry, |
| 959 | uint8_t base, int disp, uint8_t reg) { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 960 | EmitPrefixAndOpcode(entry, reg, NO_REG, base); |
| 961 | reg = LowRegisterBits(reg); |
| 962 | base = LowRegisterBits(base); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 963 | if (RegStorage::RegNum(reg) >= 4) { |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 964 | DCHECK(strchr(entry->name, '8') == NULL || |
| 965 | entry->opcode == kX86Movzx8RM || entry->opcode == kX86Movsx8RM) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 966 | << entry->name << " " << static_cast<int>(RegStorage::RegNum(reg)) |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 967 | << " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file); |
| 968 | } |
| 969 | EmitModrmDisp(reg, base, disp); |
| 970 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 971 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 972 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 973 | } |
| 974 | |
| 975 | void X86Mir2Lir::EmitRegMem(const X86EncodingMap* entry, |
| 976 | uint8_t reg, uint8_t base, int disp) { |
| 977 | // Opcode will flip operands. |
| 978 | EmitMemReg(entry, base, disp, reg); |
| 979 | } |
| 980 | |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 981 | void X86Mir2Lir::EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, |
| 982 | uint8_t index, int scale, int disp) { |
| 983 | EmitPrefixAndOpcode(entry, reg, index, base); |
| 984 | reg = LowRegisterBits(reg); |
| 985 | index = LowRegisterBits(index); |
| 986 | base = LowRegisterBits(base); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 987 | EmitModrmSibDisp(reg, base, index, scale, disp); |
| 988 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 989 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 990 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 991 | } |
| 992 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 993 | void X86Mir2Lir::EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, |
| 994 | int disp, uint8_t reg) { |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 995 | // Opcode will flip operands. |
| 996 | EmitRegArray(entry, reg, base, index, scale, disp); |
| 997 | } |
| 998 | |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 999 | void X86Mir2Lir::EmitArrayImm(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, |
| 1000 | int disp, int32_t imm) { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1001 | EmitPrefixAndOpcode(entry, NO_REG, index, base); |
| 1002 | index = LowRegisterBits(index); |
| 1003 | base = LowRegisterBits(base); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1004 | EmitModrmSibDisp(entry->skeleton.modrm_opcode, base, index, scale, disp); |
| 1005 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
Mark Mendell | 9ed4277 | 2014-05-07 17:26:12 -0400 | [diff] [blame] | 1006 | EmitImm(entry, imm); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1007 | } |
| 1008 | |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1009 | void X86Mir2Lir::EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp) { |
| 1010 | DCHECK_NE(entry->skeleton.prefix1, 0); |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1011 | EmitPrefixAndOpcode(entry, reg, NO_REG, NO_REG); |
| 1012 | reg = LowRegisterBits(reg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1013 | if (RegStorage::RegNum(reg) >= 4) { |
| 1014 | DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " |
| 1015 | << static_cast<int>(RegStorage::RegNum(reg)) |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1016 | << " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file); |
| 1017 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1018 | DCHECK_LT(RegStorage::RegNum(reg), 8); |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 1019 | EmitModrmThread(RegStorage::RegNum(reg)); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1020 | code_buffer_.push_back(disp & 0xFF); |
| 1021 | code_buffer_.push_back((disp >> 8) & 0xFF); |
| 1022 | code_buffer_.push_back((disp >> 16) & 0xFF); |
| 1023 | code_buffer_.push_back((disp >> 24) & 0xFF); |
| 1024 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1025 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1026 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1027 | } |
| 1028 | |
| 1029 | void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2) { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1030 | EmitPrefixAndOpcode(entry, reg1, NO_REG, reg2); |
| 1031 | reg1 = LowRegisterBits(reg1); |
| 1032 | reg2 = LowRegisterBits(reg2); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1033 | DCHECK_LT(RegStorage::RegNum(reg1), 8); |
| 1034 | DCHECK_LT(RegStorage::RegNum(reg2), 8); |
| 1035 | uint8_t modrm = (3 << 6) | (RegStorage::RegNum(reg1) << 3) | RegStorage::RegNum(reg2); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1036 | code_buffer_.push_back(modrm); |
| 1037 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1038 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1039 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1040 | } |
| 1041 | |
| 1042 | void X86Mir2Lir::EmitRegRegImm(const X86EncodingMap* entry, |
| 1043 | uint8_t reg1, uint8_t reg2, int32_t imm) { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1044 | EmitPrefixAndOpcode(entry, reg1, NO_REG, reg2); |
| 1045 | reg1 = LowRegisterBits(reg1); |
| 1046 | reg2 = LowRegisterBits(reg2); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1047 | DCHECK_LT(RegStorage::RegNum(reg1), 8); |
| 1048 | DCHECK_LT(RegStorage::RegNum(reg2), 8); |
| 1049 | uint8_t modrm = (3 << 6) | (RegStorage::RegNum(reg1) << 3) | RegStorage::RegNum(reg2); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1050 | code_buffer_.push_back(modrm); |
| 1051 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1052 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1053 | EmitImm(entry, imm); |
| 1054 | } |
| 1055 | |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1056 | void X86Mir2Lir::EmitRegRegImmRev(const X86EncodingMap* entry, |
| 1057 | uint8_t reg1, uint8_t reg2, int32_t imm) { |
| 1058 | EmitRegRegImm(entry, reg2, reg1, imm); |
| 1059 | } |
| 1060 | |
| 1061 | void X86Mir2Lir::EmitRegMemImm(const X86EncodingMap* entry, |
| 1062 | uint8_t reg, uint8_t base, int disp, int32_t imm) { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1063 | EmitPrefixAndOpcode(entry, reg, NO_REG, base); |
| 1064 | reg = LowRegisterBits(reg); |
| 1065 | base = LowRegisterBits(base); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1066 | DCHECK(!RegStorage::IsFloat(reg)); |
| 1067 | DCHECK_LT(RegStorage::RegNum(reg), 8); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1068 | EmitModrmDisp(reg, base, disp); |
| 1069 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1070 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1071 | EmitImm(entry, imm); |
| 1072 | } |
| 1073 | |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1074 | void X86Mir2Lir::EmitMemRegImm(const X86EncodingMap* entry, |
| 1075 | uint8_t base, int disp, uint8_t reg, int32_t imm) { |
| 1076 | EmitRegMemImm(entry, reg, base, disp, imm); |
| 1077 | } |
| 1078 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1079 | void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1080 | EmitPrefix(entry, NO_REG, NO_REG, reg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1081 | if (RegStorage::RegNum(reg) == rs_rAX.GetRegNum() && entry->skeleton.ax_opcode != 0) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1082 | code_buffer_.push_back(entry->skeleton.ax_opcode); |
| 1083 | } else { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1084 | reg = LowRegisterBits(reg); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1085 | EmitOpcode(entry); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1086 | uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | RegStorage::RegNum(reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1087 | code_buffer_.push_back(modrm); |
| 1088 | } |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1089 | EmitImm(entry, imm); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1090 | } |
| 1091 | |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 1092 | void X86Mir2Lir::EmitMemImm(const X86EncodingMap* entry, uint8_t base, int disp, int32_t imm) { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1093 | EmitPrefixAndOpcode(entry, NO_REG, NO_REG, base); |
| 1094 | base = LowRegisterBits(base); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 1095 | EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp); |
| 1096 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1097 | EmitImm(entry, imm); |
| 1098 | } |
| 1099 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1100 | void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int disp, int imm) { |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1101 | EmitPrefixAndOpcode(entry); |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 1102 | EmitModrmThread(entry->skeleton.modrm_opcode); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1103 | code_buffer_.push_back(disp & 0xFF); |
| 1104 | code_buffer_.push_back((disp >> 8) & 0xFF); |
| 1105 | code_buffer_.push_back((disp >> 16) & 0xFF); |
| 1106 | code_buffer_.push_back((disp >> 24) & 0xFF); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1107 | EmitImm(entry, imm); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1108 | DCHECK_EQ(entry->skeleton.ax_opcode, 0); |
| 1109 | } |
| 1110 | |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 1111 | void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int64_t imm) { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1112 | EmitPrefix(entry, NO_REG, NO_REG, reg); |
| 1113 | reg = LowRegisterBits(reg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1114 | DCHECK_LT(RegStorage::RegNum(reg), 8); |
| 1115 | code_buffer_.push_back(0xB8 + RegStorage::RegNum(reg)); |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 1116 | switch (entry->skeleton.immediate_bytes) { |
| 1117 | case 4: |
| 1118 | code_buffer_.push_back(imm & 0xFF); |
| 1119 | code_buffer_.push_back((imm >> 8) & 0xFF); |
| 1120 | code_buffer_.push_back((imm >> 16) & 0xFF); |
| 1121 | code_buffer_.push_back((imm >> 24) & 0xFF); |
| 1122 | break; |
| 1123 | case 8: |
| 1124 | code_buffer_.push_back(imm & 0xFF); |
| 1125 | code_buffer_.push_back((imm >> 8) & 0xFF); |
| 1126 | code_buffer_.push_back((imm >> 16) & 0xFF); |
| 1127 | code_buffer_.push_back((imm >> 24) & 0xFF); |
| 1128 | code_buffer_.push_back((imm >> 32) & 0xFF); |
| 1129 | code_buffer_.push_back((imm >> 40) & 0xFF); |
| 1130 | code_buffer_.push_back((imm >> 48) & 0xFF); |
| 1131 | code_buffer_.push_back((imm >> 56) & 0xFF); |
| 1132 | break; |
| 1133 | default: |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1134 | LOG(FATAL) << "Unsupported immediate size for EmitMovRegImm: " |
| 1135 | << static_cast<uint32_t>(entry->skeleton.immediate_bytes); |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 1136 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1137 | } |
| 1138 | |
| 1139 | void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1140 | EmitPrefix(entry, NO_REG, NO_REG, reg); |
| 1141 | reg = LowRegisterBits(reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1142 | if (imm != 1) { |
| 1143 | code_buffer_.push_back(entry->skeleton.opcode); |
| 1144 | } else { |
| 1145 | // Shorter encoding for 1 bit shift |
| 1146 | code_buffer_.push_back(entry->skeleton.ax_opcode); |
| 1147 | } |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1148 | DCHECK_NE(0x0F, entry->skeleton.opcode); |
| 1149 | DCHECK_EQ(0, entry->skeleton.extra_opcode1); |
| 1150 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1151 | if (RegStorage::RegNum(reg) >= 4) { |
| 1152 | DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " |
| 1153 | << static_cast<int>(RegStorage::RegNum(reg)) |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1154 | << " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file); |
| 1155 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1156 | DCHECK_LT(RegStorage::RegNum(reg), 8); |
| 1157 | uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | RegStorage::RegNum(reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1158 | code_buffer_.push_back(modrm); |
| 1159 | if (imm != 1) { |
| 1160 | DCHECK_EQ(entry->skeleton.immediate_bytes, 1); |
| 1161 | DCHECK(IS_SIMM8(imm)); |
| 1162 | code_buffer_.push_back(imm & 0xFF); |
| 1163 | } |
| 1164 | } |
| 1165 | |
| 1166 | void X86Mir2Lir::EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1167 | DCHECK_EQ(cl, static_cast<uint8_t>(rs_rCX.GetReg())); |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1168 | EmitPrefix(entry, reg, NO_REG, NO_REG); |
| 1169 | reg = LowRegisterBits(reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1170 | code_buffer_.push_back(entry->skeleton.opcode); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1171 | DCHECK_NE(0x0F, entry->skeleton.opcode); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1172 | DCHECK_EQ(0, entry->skeleton.extra_opcode1); |
| 1173 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1174 | DCHECK_LT(RegStorage::RegNum(reg), 8); |
| 1175 | uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | RegStorage::RegNum(reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1176 | code_buffer_.push_back(modrm); |
| 1177 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1178 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1179 | } |
| 1180 | |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 1181 | void X86Mir2Lir::EmitShiftMemCl(const X86EncodingMap* entry, uint8_t base, |
| 1182 | int displacement, uint8_t cl) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1183 | DCHECK_EQ(cl, static_cast<uint8_t>(rs_rCX.GetReg())); |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1184 | EmitPrefix(entry, NO_REG, NO_REG, base); |
| 1185 | base = LowRegisterBits(base); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 1186 | code_buffer_.push_back(entry->skeleton.opcode); |
| 1187 | DCHECK_NE(0x0F, entry->skeleton.opcode); |
| 1188 | DCHECK_EQ(0, entry->skeleton.extra_opcode1); |
| 1189 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1190 | DCHECK_LT(RegStorage::RegNum(base), 8); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 1191 | EmitModrmDisp(entry->skeleton.modrm_opcode, base, displacement); |
| 1192 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1193 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1194 | } |
| 1195 | |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1196 | void X86Mir2Lir::EmitShiftMemImm(const X86EncodingMap* entry, uint8_t base, |
| 1197 | int displacement, int imm) { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1198 | EmitPrefix(entry, NO_REG, NO_REG, base); |
| 1199 | base = LowRegisterBits(base); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1200 | if (imm != 1) { |
| 1201 | code_buffer_.push_back(entry->skeleton.opcode); |
| 1202 | } else { |
| 1203 | // Shorter encoding for 1 bit shift |
| 1204 | code_buffer_.push_back(entry->skeleton.ax_opcode); |
| 1205 | } |
| 1206 | DCHECK_NE(0x0F, entry->skeleton.opcode); |
| 1207 | DCHECK_EQ(0, entry->skeleton.extra_opcode1); |
| 1208 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
| 1209 | EmitModrmDisp(entry->skeleton.modrm_opcode, base, displacement); |
| 1210 | if (imm != 1) { |
| 1211 | DCHECK_EQ(entry->skeleton.immediate_bytes, 1); |
| 1212 | DCHECK(IS_SIMM8(imm)); |
| 1213 | code_buffer_.push_back(imm & 0xFF); |
| 1214 | } |
| 1215 | } |
| 1216 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1217 | void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition) { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1218 | EmitPrefix(entry, reg, NO_REG, NO_REG); |
| 1219 | reg = LowRegisterBits(reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1220 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1221 | DCHECK_EQ(0x0F, entry->skeleton.opcode); |
| 1222 | code_buffer_.push_back(0x0F); |
| 1223 | DCHECK_EQ(0x90, entry->skeleton.extra_opcode1); |
| 1224 | code_buffer_.push_back(0x90 | condition); |
| 1225 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1226 | DCHECK_LT(RegStorage::RegNum(reg), 8); |
| 1227 | uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | RegStorage::RegNum(reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1228 | code_buffer_.push_back(modrm); |
| 1229 | DCHECK_EQ(entry->skeleton.immediate_bytes, 0); |
| 1230 | } |
| 1231 | |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1232 | void X86Mir2Lir::EmitMemCond(const X86EncodingMap* entry, uint8_t base, int displacement, |
| 1233 | uint8_t condition) { |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1234 | if (entry->skeleton.prefix1 != 0) { |
| 1235 | code_buffer_.push_back(entry->skeleton.prefix1); |
| 1236 | if (entry->skeleton.prefix2 != 0) { |
| 1237 | code_buffer_.push_back(entry->skeleton.prefix2); |
| 1238 | } |
| 1239 | } else { |
| 1240 | DCHECK_EQ(0, entry->skeleton.prefix2); |
| 1241 | } |
| 1242 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1243 | DCHECK_EQ(0x0F, entry->skeleton.opcode); |
| 1244 | code_buffer_.push_back(0x0F); |
| 1245 | DCHECK_EQ(0x90, entry->skeleton.extra_opcode1); |
| 1246 | code_buffer_.push_back(0x90 | condition); |
| 1247 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
| 1248 | EmitModrmDisp(entry->skeleton.modrm_opcode, base, displacement); |
| 1249 | DCHECK_EQ(entry->skeleton.immediate_bytes, 0); |
| 1250 | } |
| 1251 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1252 | void X86Mir2Lir::EmitRegRegCond(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, |
| 1253 | uint8_t condition) { |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 1254 | // Generate prefix and opcode without the condition |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1255 | EmitPrefixAndOpcode(entry, reg1, NO_REG, reg2); |
| 1256 | reg1 = LowRegisterBits(reg1); |
| 1257 | reg2 = LowRegisterBits(reg2); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 1258 | |
| 1259 | // Now add the condition. The last byte of opcode is the one that receives it. |
| 1260 | DCHECK_LE(condition, 0xF); |
| 1261 | code_buffer_.back() += condition; |
| 1262 | |
| 1263 | // Not expecting to have to encode immediate or do anything special for ModR/M since there are two registers. |
| 1264 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1265 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1266 | |
| 1267 | // Check that registers requested for encoding are sane. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1268 | DCHECK_LT(RegStorage::RegNum(reg1), 8); |
| 1269 | DCHECK_LT(RegStorage::RegNum(reg2), 8); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 1270 | |
| 1271 | // For register to register encoding, the mod is 3. |
| 1272 | const uint8_t mod = (3 << 6); |
| 1273 | |
| 1274 | // Encode the ModR/M byte now. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1275 | const uint8_t modrm = mod | (RegStorage::RegNum(reg1) << 3) | RegStorage::RegNum(reg2); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 1276 | code_buffer_.push_back(modrm); |
| 1277 | } |
| 1278 | |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1279 | void X86Mir2Lir::EmitRegMemCond(const X86EncodingMap* entry, uint8_t reg1, uint8_t base, |
| 1280 | int displacement, uint8_t condition) { |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1281 | // Generate prefix and opcode without the condition |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1282 | EmitPrefixAndOpcode(entry, reg1, NO_REG, base); |
| 1283 | reg1 = LowRegisterBits(reg1); |
| 1284 | base = LowRegisterBits(base); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1285 | |
| 1286 | // Now add the condition. The last byte of opcode is the one that receives it. |
| 1287 | DCHECK_LE(condition, 0xF); |
| 1288 | code_buffer_.back() += condition; |
| 1289 | |
| 1290 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1291 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1292 | |
| 1293 | // Check that registers requested for encoding are sane. |
| 1294 | DCHECK_LT(reg1, 8); |
| 1295 | DCHECK_LT(base, 8); |
| 1296 | |
| 1297 | EmitModrmDisp(reg1, base, displacement); |
| 1298 | } |
| 1299 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1300 | void X86Mir2Lir::EmitJmp(const X86EncodingMap* entry, int rel) { |
| 1301 | if (entry->opcode == kX86Jmp8) { |
| 1302 | DCHECK(IS_SIMM8(rel)); |
| 1303 | code_buffer_.push_back(0xEB); |
| 1304 | code_buffer_.push_back(rel & 0xFF); |
| 1305 | } else if (entry->opcode == kX86Jmp32) { |
| 1306 | code_buffer_.push_back(0xE9); |
| 1307 | code_buffer_.push_back(rel & 0xFF); |
| 1308 | code_buffer_.push_back((rel >> 8) & 0xFF); |
| 1309 | code_buffer_.push_back((rel >> 16) & 0xFF); |
| 1310 | code_buffer_.push_back((rel >> 24) & 0xFF); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1311 | } else if (entry->opcode == kX86Jecxz8) { |
| 1312 | DCHECK(IS_SIMM8(rel)); |
| 1313 | code_buffer_.push_back(0xE3); |
| 1314 | code_buffer_.push_back(rel & 0xFF); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1315 | } else { |
| 1316 | DCHECK(entry->opcode == kX86JmpR); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1317 | uint8_t reg = static_cast<uint8_t>(rel); |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1318 | EmitPrefix(entry, NO_REG, NO_REG, reg); |
| 1319 | code_buffer_.push_back(entry->skeleton.opcode); |
| 1320 | reg = LowRegisterBits(reg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1321 | DCHECK_LT(RegStorage::RegNum(reg), 8); |
| 1322 | uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | RegStorage::RegNum(reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1323 | code_buffer_.push_back(modrm); |
| 1324 | } |
| 1325 | } |
| 1326 | |
| 1327 | void X86Mir2Lir::EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc) { |
| 1328 | DCHECK_LT(cc, 16); |
| 1329 | if (entry->opcode == kX86Jcc8) { |
| 1330 | DCHECK(IS_SIMM8(rel)); |
| 1331 | code_buffer_.push_back(0x70 | cc); |
| 1332 | code_buffer_.push_back(rel & 0xFF); |
| 1333 | } else { |
| 1334 | DCHECK(entry->opcode == kX86Jcc32); |
| 1335 | code_buffer_.push_back(0x0F); |
| 1336 | code_buffer_.push_back(0x80 | cc); |
| 1337 | code_buffer_.push_back(rel & 0xFF); |
| 1338 | code_buffer_.push_back((rel >> 8) & 0xFF); |
| 1339 | code_buffer_.push_back((rel >> 16) & 0xFF); |
| 1340 | code_buffer_.push_back((rel >> 24) & 0xFF); |
| 1341 | } |
| 1342 | } |
| 1343 | |
| 1344 | void X86Mir2Lir::EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp) { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1345 | EmitPrefixAndOpcode(entry, NO_REG, NO_REG, base); |
| 1346 | base = LowRegisterBits(base); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1347 | EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1348 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1349 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1350 | } |
| 1351 | |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1352 | void X86Mir2Lir::EmitCallImmediate(const X86EncodingMap* entry, int disp) { |
| 1353 | EmitPrefixAndOpcode(entry); |
| 1354 | DCHECK_EQ(4, entry->skeleton.immediate_bytes); |
| 1355 | code_buffer_.push_back(disp & 0xFF); |
| 1356 | code_buffer_.push_back((disp >> 8) & 0xFF); |
| 1357 | code_buffer_.push_back((disp >> 16) & 0xFF); |
| 1358 | code_buffer_.push_back((disp >> 24) & 0xFF); |
| 1359 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1360 | } |
| 1361 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1362 | void X86Mir2Lir::EmitCallThread(const X86EncodingMap* entry, int disp) { |
| 1363 | DCHECK_NE(entry->skeleton.prefix1, 0); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1364 | EmitPrefixAndOpcode(entry); |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 1365 | EmitModrmThread(entry->skeleton.modrm_opcode); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1366 | code_buffer_.push_back(disp & 0xFF); |
| 1367 | code_buffer_.push_back((disp >> 8) & 0xFF); |
| 1368 | code_buffer_.push_back((disp >> 16) & 0xFF); |
| 1369 | code_buffer_.push_back((disp >> 24) & 0xFF); |
| 1370 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1371 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1372 | } |
| 1373 | |
| 1374 | void X86Mir2Lir::EmitPcRel(const X86EncodingMap* entry, uint8_t reg, |
| 1375 | int base_or_table, uint8_t index, int scale, int table_or_disp) { |
| 1376 | int disp; |
| 1377 | if (entry->opcode == kX86PcRelLoadRA) { |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1378 | Mir2Lir::EmbeddedData *tab_rec = |
| 1379 | reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(table_or_disp)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1380 | disp = tab_rec->offset; |
| 1381 | } else { |
| 1382 | DCHECK(entry->opcode == kX86PcRelAdr); |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1383 | Mir2Lir::EmbeddedData *tab_rec = |
| 1384 | reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(base_or_table)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1385 | disp = tab_rec->offset; |
| 1386 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1387 | if (entry->opcode == kX86PcRelLoadRA) { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1388 | EmitPrefix(entry, reg, index, base_or_table); |
| 1389 | reg = LowRegisterBits(reg); |
| 1390 | base_or_table = LowRegisterBits(base_or_table); |
| 1391 | index = LowRegisterBits(index); |
| 1392 | DCHECK_LT(RegStorage::RegNum(reg), 8); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1393 | code_buffer_.push_back(entry->skeleton.opcode); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1394 | DCHECK_NE(0x0F, entry->skeleton.opcode); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1395 | DCHECK_EQ(0, entry->skeleton.extra_opcode1); |
| 1396 | DCHECK_EQ(0, entry->skeleton.extra_opcode2); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1397 | uint8_t modrm = (2 << 6) | (RegStorage::RegNum(reg) << 3) | rs_rX86_SP.GetRegNum(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1398 | code_buffer_.push_back(modrm); |
| 1399 | DCHECK_LT(scale, 4); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1400 | DCHECK_LT(RegStorage::RegNum(index), 8); |
| 1401 | DCHECK_LT(RegStorage::RegNum(base_or_table), 8); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1402 | uint8_t base = static_cast<uint8_t>(base_or_table); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1403 | uint8_t sib = (scale << 6) | (RegStorage::RegNum(index) << 3) | RegStorage::RegNum(base); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1404 | code_buffer_.push_back(sib); |
| 1405 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1406 | } else { |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1407 | DCHECK_LT(RegStorage::RegNum(reg), 8); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1408 | code_buffer_.push_back(entry->skeleton.opcode + RegStorage::RegNum(reg)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1409 | } |
| 1410 | code_buffer_.push_back(disp & 0xFF); |
| 1411 | code_buffer_.push_back((disp >> 8) & 0xFF); |
| 1412 | code_buffer_.push_back((disp >> 16) & 0xFF); |
| 1413 | code_buffer_.push_back((disp >> 24) & 0xFF); |
| 1414 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1415 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1416 | } |
| 1417 | |
| 1418 | void X86Mir2Lir::EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset) { |
| 1419 | DCHECK(entry->opcode == kX86StartOfMethod) << entry->name; |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1420 | EmitPrefix(entry, reg, NO_REG, NO_REG); |
| 1421 | reg = LowRegisterBits(reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1422 | code_buffer_.push_back(0xE8); // call +0 |
| 1423 | code_buffer_.push_back(0); |
| 1424 | code_buffer_.push_back(0); |
| 1425 | code_buffer_.push_back(0); |
| 1426 | code_buffer_.push_back(0); |
| 1427 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1428 | DCHECK_LT(RegStorage::RegNum(reg), 8); |
| 1429 | code_buffer_.push_back(0x58 + RegStorage::RegNum(reg)); // pop reg |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1430 | |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 1431 | EmitRegImm(&X86Mir2Lir::EncodingMap[Gen64Bit() ? kX86Sub64RI : kX86Sub32RI], |
| 1432 | RegStorage::RegNum(reg), offset + 5 /* size of call +0 */); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1433 | } |
| 1434 | |
| 1435 | void X86Mir2Lir::EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) { |
| 1436 | UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " " |
| 1437 | << BuildInsnString(entry->fmt, lir, 0); |
| 1438 | for (int i = 0; i < GetInsnSize(lir); ++i) { |
| 1439 | code_buffer_.push_back(0xCC); // push breakpoint instruction - int 3 |
| 1440 | } |
| 1441 | } |
| 1442 | |
| 1443 | /* |
| 1444 | * Assemble the LIR into binary instruction format. Note that we may |
| 1445 | * discover that pc-relative displacements may not fit the selected |
| 1446 | * instruction. In those cases we will try to substitute a new code |
| 1447 | * sequence or request that the trace be shortened and retried. |
| 1448 | */ |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1449 | AssemblerStatus X86Mir2Lir::AssembleInstructions(CodeOffset start_addr) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1450 | LIR *lir; |
| 1451 | AssemblerStatus res = kSuccess; // Assume success |
| 1452 | |
| 1453 | const bool kVerbosePcFixup = false; |
| 1454 | for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) { |
buzbee | 409fe94 | 2013-10-11 10:49:56 -0700 | [diff] [blame] | 1455 | if (IsPseudoLirOp(lir->opcode)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1456 | continue; |
| 1457 | } |
| 1458 | |
| 1459 | if (lir->flags.is_nop) { |
| 1460 | continue; |
| 1461 | } |
| 1462 | |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 1463 | if (lir->flags.fixup != kFixupNone) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1464 | switch (lir->opcode) { |
| 1465 | case kX86Jcc8: { |
| 1466 | LIR *target_lir = lir->target; |
| 1467 | DCHECK(target_lir != NULL); |
| 1468 | int delta = 0; |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1469 | CodeOffset pc; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1470 | if (IS_SIMM8(lir->operands[0])) { |
| 1471 | pc = lir->offset + 2 /* opcode + rel8 */; |
| 1472 | } else { |
| 1473 | pc = lir->offset + 6 /* 2 byte opcode + rel32 */; |
| 1474 | } |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1475 | CodeOffset target = target_lir->offset; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1476 | delta = target - pc; |
| 1477 | if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) { |
| 1478 | if (kVerbosePcFixup) { |
| 1479 | LOG(INFO) << "Retry for JCC growth at " << lir->offset |
| 1480 | << " delta: " << delta << " old delta: " << lir->operands[0]; |
| 1481 | } |
| 1482 | lir->opcode = kX86Jcc32; |
| 1483 | SetupResourceMasks(lir); |
| 1484 | res = kRetryAll; |
| 1485 | } |
| 1486 | if (kVerbosePcFixup) { |
| 1487 | LOG(INFO) << "Source:"; |
| 1488 | DumpLIRInsn(lir, 0); |
| 1489 | LOG(INFO) << "Target:"; |
| 1490 | DumpLIRInsn(target_lir, 0); |
| 1491 | LOG(INFO) << "Delta " << delta; |
| 1492 | } |
| 1493 | lir->operands[0] = delta; |
| 1494 | break; |
| 1495 | } |
| 1496 | case kX86Jcc32: { |
| 1497 | LIR *target_lir = lir->target; |
| 1498 | DCHECK(target_lir != NULL); |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1499 | CodeOffset pc = lir->offset + 6 /* 2 byte opcode + rel32 */; |
| 1500 | CodeOffset target = target_lir->offset; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1501 | int delta = target - pc; |
| 1502 | if (kVerbosePcFixup) { |
| 1503 | LOG(INFO) << "Source:"; |
| 1504 | DumpLIRInsn(lir, 0); |
| 1505 | LOG(INFO) << "Target:"; |
| 1506 | DumpLIRInsn(target_lir, 0); |
| 1507 | LOG(INFO) << "Delta " << delta; |
| 1508 | } |
| 1509 | lir->operands[0] = delta; |
| 1510 | break; |
| 1511 | } |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1512 | case kX86Jecxz8: { |
| 1513 | LIR *target_lir = lir->target; |
| 1514 | DCHECK(target_lir != NULL); |
| 1515 | CodeOffset pc; |
| 1516 | pc = lir->offset + 2; // opcode + rel8 |
| 1517 | CodeOffset target = target_lir->offset; |
| 1518 | int delta = target - pc; |
| 1519 | lir->operands[0] = delta; |
| 1520 | DCHECK(IS_SIMM8(delta)); |
| 1521 | break; |
| 1522 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1523 | case kX86Jmp8: { |
| 1524 | LIR *target_lir = lir->target; |
| 1525 | DCHECK(target_lir != NULL); |
| 1526 | int delta = 0; |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1527 | CodeOffset pc; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1528 | if (IS_SIMM8(lir->operands[0])) { |
| 1529 | pc = lir->offset + 2 /* opcode + rel8 */; |
| 1530 | } else { |
| 1531 | pc = lir->offset + 5 /* opcode + rel32 */; |
| 1532 | } |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1533 | CodeOffset target = target_lir->offset; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1534 | delta = target - pc; |
| 1535 | if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && delta == 0) { |
| 1536 | // Useless branch |
buzbee | 252254b | 2013-09-08 16:20:53 -0700 | [diff] [blame] | 1537 | NopLIR(lir); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1538 | if (kVerbosePcFixup) { |
| 1539 | LOG(INFO) << "Retry for useless branch at " << lir->offset; |
| 1540 | } |
| 1541 | res = kRetryAll; |
| 1542 | } else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) { |
| 1543 | if (kVerbosePcFixup) { |
| 1544 | LOG(INFO) << "Retry for JMP growth at " << lir->offset; |
| 1545 | } |
| 1546 | lir->opcode = kX86Jmp32; |
| 1547 | SetupResourceMasks(lir); |
| 1548 | res = kRetryAll; |
| 1549 | } |
| 1550 | lir->operands[0] = delta; |
| 1551 | break; |
| 1552 | } |
| 1553 | case kX86Jmp32: { |
| 1554 | LIR *target_lir = lir->target; |
| 1555 | DCHECK(target_lir != NULL); |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 1556 | CodeOffset pc = lir->offset + 5 /* opcode + rel32 */; |
| 1557 | CodeOffset target = target_lir->offset; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1558 | int delta = target - pc; |
| 1559 | lir->operands[0] = delta; |
| 1560 | break; |
| 1561 | } |
| 1562 | default: |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 1563 | if (lir->flags.fixup == kFixupLoad) { |
| 1564 | LIR *target_lir = lir->target; |
| 1565 | DCHECK(target_lir != NULL); |
| 1566 | CodeOffset target = target_lir->offset; |
| 1567 | lir->operands[2] = target; |
| 1568 | int newSize = GetInsnSize(lir); |
| 1569 | if (newSize != lir->flags.size) { |
| 1570 | lir->flags.size = newSize; |
| 1571 | res = kRetryAll; |
| 1572 | } |
| 1573 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1574 | break; |
| 1575 | } |
| 1576 | } |
| 1577 | |
| 1578 | /* |
| 1579 | * If one of the pc-relative instructions expanded we'll have |
| 1580 | * to make another pass. Don't bother to fully assemble the |
| 1581 | * instruction. |
| 1582 | */ |
| 1583 | if (res != kSuccess) { |
| 1584 | continue; |
| 1585 | } |
| 1586 | CHECK_EQ(static_cast<size_t>(lir->offset), code_buffer_.size()); |
| 1587 | const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode]; |
| 1588 | size_t starting_cbuf_size = code_buffer_.size(); |
| 1589 | switch (entry->kind) { |
| 1590 | case kData: // 4 bytes of data |
| 1591 | code_buffer_.push_back(lir->operands[0]); |
| 1592 | break; |
| 1593 | case kNullary: // 1 byte of opcode |
| 1594 | DCHECK_EQ(0, entry->skeleton.prefix1); |
| 1595 | DCHECK_EQ(0, entry->skeleton.prefix2); |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1596 | EmitOpcode(entry); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1597 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1598 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1599 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1600 | break; |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1601 | case kPrefix2Nullary: // 1 byte of opcode + 2 prefixes. |
| 1602 | DCHECK_NE(0, entry->skeleton.prefix1); |
| 1603 | DCHECK_NE(0, entry->skeleton.prefix2); |
| 1604 | EmitPrefixAndOpcode(entry); |
| 1605 | DCHECK_EQ(0, entry->skeleton.modrm_opcode); |
| 1606 | DCHECK_EQ(0, entry->skeleton.ax_opcode); |
| 1607 | DCHECK_EQ(0, entry->skeleton.immediate_bytes); |
| 1608 | break; |
Vladimir Marko | a8b4caf | 2013-10-24 15:08:57 +0100 | [diff] [blame] | 1609 | case kRegOpcode: // lir operands - 0: reg |
| 1610 | EmitOpRegOpcode(entry, lir->operands[0]); |
| 1611 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1612 | case kReg: // lir operands - 0: reg |
| 1613 | EmitOpReg(entry, lir->operands[0]); |
| 1614 | break; |
| 1615 | case kMem: // lir operands - 0: base, 1: disp |
| 1616 | EmitOpMem(entry, lir->operands[0], lir->operands[1]); |
| 1617 | break; |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 1618 | case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp |
| 1619 | EmitOpArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3]); |
| 1620 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1621 | case kMemReg: // lir operands - 0: base, 1: disp, 2: reg |
| 1622 | EmitMemReg(entry, lir->operands[0], lir->operands[1], lir->operands[2]); |
| 1623 | break; |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 1624 | case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate |
| 1625 | EmitMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]); |
| 1626 | break; |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1627 | case kArrayImm: // lir operands - 0: base, 1: index, 2: disp, 3:scale, 4:immediate |
| 1628 | EmitArrayImm(entry, lir->operands[0], lir->operands[1], lir->operands[2], |
| 1629 | lir->operands[3], lir->operands[4]); |
| 1630 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1631 | case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg |
| 1632 | EmitArrayReg(entry, lir->operands[0], lir->operands[1], lir->operands[2], |
| 1633 | lir->operands[3], lir->operands[4]); |
| 1634 | break; |
| 1635 | case kRegMem: // lir operands - 0: reg, 1: base, 2: disp |
| 1636 | EmitRegMem(entry, lir->operands[0], lir->operands[1], lir->operands[2]); |
| 1637 | break; |
| 1638 | case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp |
| 1639 | EmitRegArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], |
| 1640 | lir->operands[3], lir->operands[4]); |
| 1641 | break; |
| 1642 | case kRegThread: // lir operands - 0: reg, 1: disp |
| 1643 | EmitRegThread(entry, lir->operands[0], lir->operands[1]); |
| 1644 | break; |
| 1645 | case kRegReg: // lir operands - 0: reg1, 1: reg2 |
| 1646 | EmitRegReg(entry, lir->operands[0], lir->operands[1]); |
| 1647 | break; |
| 1648 | case kRegRegStore: // lir operands - 0: reg2, 1: reg1 |
| 1649 | EmitRegReg(entry, lir->operands[1], lir->operands[0]); |
| 1650 | break; |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1651 | case kRegRegImmRev: |
| 1652 | EmitRegRegImmRev(entry, lir->operands[0], lir->operands[1], lir->operands[2]); |
| 1653 | break; |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1654 | case kMemRegImm: |
| 1655 | EmitMemRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2], |
| 1656 | lir->operands[3]); |
| 1657 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1658 | case kRegRegImm: |
| 1659 | EmitRegRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]); |
| 1660 | break; |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1661 | case kRegMemImm: |
| 1662 | EmitRegMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2], |
| 1663 | lir->operands[3]); |
| 1664 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1665 | case kRegImm: // lir operands - 0: reg, 1: immediate |
| 1666 | EmitRegImm(entry, lir->operands[0], lir->operands[1]); |
| 1667 | break; |
| 1668 | case kThreadImm: // lir operands - 0: disp, 1: immediate |
| 1669 | EmitThreadImm(entry, lir->operands[0], lir->operands[1]); |
| 1670 | break; |
| 1671 | case kMovRegImm: // lir operands - 0: reg, 1: immediate |
| 1672 | EmitMovRegImm(entry, lir->operands[0], lir->operands[1]); |
| 1673 | break; |
| 1674 | case kShiftRegImm: // lir operands - 0: reg, 1: immediate |
| 1675 | EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]); |
| 1676 | break; |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1677 | case kShiftMemImm: // lir operands - 0: base, 1: disp, 2:immediate |
| 1678 | EmitShiftMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]); |
| 1679 | break; |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 1680 | case kShiftRegCl: // lir operands - 0: reg, 1: cl |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1681 | EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]); |
| 1682 | break; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 1683 | case kShiftMemCl: // lir operands - 0: base, 1:displacement, 2: cl |
| 1684 | EmitShiftMemCl(entry, lir->operands[0], lir->operands[1], lir->operands[2]); |
| 1685 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1686 | case kRegCond: // lir operands - 0: reg, 1: condition |
| 1687 | EmitRegCond(entry, lir->operands[0], lir->operands[1]); |
| 1688 | break; |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1689 | case kMemCond: // lir operands - 0: base, 1: displacement, 2: condition |
| 1690 | EmitMemCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]); |
| 1691 | break; |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 1692 | case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: condition |
| 1693 | EmitRegRegCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]); |
| 1694 | break; |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1695 | case kRegMemCond: // lir operands - 0: reg, 1: reg, displacement, 3: condition |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1696 | EmitRegMemCond(entry, lir->operands[0], lir->operands[1], lir->operands[2], |
| 1697 | lir->operands[3]); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 1698 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1699 | case kJmp: // lir operands - 0: rel |
Brian Carlstrom | 60d7a65 | 2014-03-13 18:10:08 -0700 | [diff] [blame] | 1700 | if (entry->opcode == kX86JmpT) { |
| 1701 | // This works since the instruction format for jmp and call is basically the same and |
| 1702 | // EmitCallThread loads opcode info. |
| 1703 | EmitCallThread(entry, lir->operands[0]); |
| 1704 | } else { |
| 1705 | EmitJmp(entry, lir->operands[0]); |
| 1706 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1707 | break; |
| 1708 | case kJcc: // lir operands - 0: rel, 1: CC, target assigned |
| 1709 | EmitJcc(entry, lir->operands[0], lir->operands[1]); |
| 1710 | break; |
| 1711 | case kCall: |
| 1712 | switch (entry->opcode) { |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1713 | case kX86CallI: // lir operands - 0: disp |
| 1714 | EmitCallImmediate(entry, lir->operands[0]); |
| 1715 | break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1716 | case kX86CallM: // lir operands - 0: base, 1: disp |
| 1717 | EmitCallMem(entry, lir->operands[0], lir->operands[1]); |
| 1718 | break; |
| 1719 | case kX86CallT: // lir operands - 0: disp |
| 1720 | EmitCallThread(entry, lir->operands[0]); |
| 1721 | break; |
| 1722 | default: |
| 1723 | EmitUnimplemented(entry, lir); |
| 1724 | break; |
| 1725 | } |
| 1726 | break; |
| 1727 | case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table |
| 1728 | EmitPcRel(entry, lir->operands[0], lir->operands[1], lir->operands[2], |
| 1729 | lir->operands[3], lir->operands[4]); |
| 1730 | break; |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 1731 | case kMacro: // lir operands - 0: reg |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1732 | EmitMacro(entry, lir->operands[0], lir->offset); |
| 1733 | break; |
| 1734 | default: |
| 1735 | EmitUnimplemented(entry, lir); |
| 1736 | break; |
| 1737 | } |
| 1738 | CHECK_EQ(static_cast<size_t>(GetInsnSize(lir)), |
| 1739 | code_buffer_.size() - starting_cbuf_size) |
| 1740 | << "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name; |
| 1741 | } |
| 1742 | return res; |
| 1743 | } |
| 1744 | |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 1745 | // LIR offset assignment. |
| 1746 | // TODO: consolidate w/ Arm assembly mechanism. |
| 1747 | int X86Mir2Lir::AssignInsnOffsets() { |
| 1748 | LIR* lir; |
| 1749 | int offset = 0; |
| 1750 | |
| 1751 | for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) { |
| 1752 | lir->offset = offset; |
buzbee | 409fe94 | 2013-10-11 10:49:56 -0700 | [diff] [blame] | 1753 | if (LIKELY(!IsPseudoLirOp(lir->opcode))) { |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 1754 | if (!lir->flags.is_nop) { |
| 1755 | offset += lir->flags.size; |
| 1756 | } |
| 1757 | } else if (UNLIKELY(lir->opcode == kPseudoPseudoAlign4)) { |
| 1758 | if (offset & 0x2) { |
| 1759 | offset += 2; |
| 1760 | lir->operands[0] = 1; |
| 1761 | } else { |
| 1762 | lir->operands[0] = 0; |
| 1763 | } |
| 1764 | } |
| 1765 | /* Pseudo opcodes don't consume space */ |
| 1766 | } |
| 1767 | return offset; |
| 1768 | } |
| 1769 | |
| 1770 | /* |
| 1771 | * Walk the compilation unit and assign offsets to instructions |
| 1772 | * and literals and compute the total size of the compiled unit. |
| 1773 | * TODO: consolidate w/ Arm assembly mechanism. |
| 1774 | */ |
| 1775 | void X86Mir2Lir::AssignOffsets() { |
| 1776 | int offset = AssignInsnOffsets(); |
| 1777 | |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1778 | if (const_vectors_ != nullptr) { |
| 1779 | /* assign offsets to vector literals */ |
| 1780 | |
| 1781 | // First, get offset to 12 mod 16 to align to 16 byte boundary. |
| 1782 | // This will ensure that the vector is 16 byte aligned, as the procedure is |
| 1783 | // always aligned at at 4 mod 16. |
| 1784 | int align_size = (16-4) - (offset & 0xF); |
| 1785 | if (align_size < 0) { |
| 1786 | align_size += 16; |
| 1787 | } |
| 1788 | |
| 1789 | offset += align_size; |
| 1790 | |
| 1791 | // Now assign each literal the right offset. |
| 1792 | for (LIR *p = const_vectors_; p != nullptr; p = p->next) { |
| 1793 | p->offset = offset; |
| 1794 | offset += 16; |
| 1795 | } |
| 1796 | } |
| 1797 | |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 1798 | /* Const values have to be word aligned */ |
Andreas Gampe | 6601882 | 2014-05-05 20:47:19 -0700 | [diff] [blame] | 1799 | offset = RoundUp(offset, 4); |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 1800 | |
| 1801 | /* Set up offsets for literals */ |
| 1802 | data_offset_ = offset; |
| 1803 | |
| 1804 | offset = AssignLiteralOffset(offset); |
| 1805 | |
| 1806 | offset = AssignSwitchTablesOffset(offset); |
| 1807 | |
| 1808 | offset = AssignFillArrayDataOffset(offset); |
| 1809 | |
| 1810 | total_size_ = offset; |
| 1811 | } |
| 1812 | |
| 1813 | /* |
| 1814 | * Go over each instruction in the list and calculate the offset from the top |
| 1815 | * before sending them off to the assembler. If out-of-range branch distance is |
| 1816 | * seen rearrange the instructions a bit to correct it. |
| 1817 | * TODO: consolidate w/ Arm assembly mechanism. |
| 1818 | */ |
| 1819 | void X86Mir2Lir::AssembleLIR() { |
buzbee | a61f495 | 2013-08-23 14:27:06 -0700 | [diff] [blame] | 1820 | cu_->NewTimingSplit("Assemble"); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1821 | |
| 1822 | // We will remove the method address if we never ended up using it |
| 1823 | if (store_method_addr_ && !store_method_addr_used_) { |
| 1824 | setup_method_address_[0]->flags.is_nop = true; |
| 1825 | setup_method_address_[1]->flags.is_nop = true; |
| 1826 | } |
| 1827 | |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 1828 | AssignOffsets(); |
| 1829 | int assembler_retries = 0; |
| 1830 | /* |
| 1831 | * Assemble here. Note that we generate code with optimistic assumptions |
| 1832 | * and if found now to work, we'll have to redo the sequence and retry. |
| 1833 | */ |
| 1834 | |
| 1835 | while (true) { |
| 1836 | AssemblerStatus res = AssembleInstructions(0); |
| 1837 | if (res == kSuccess) { |
| 1838 | break; |
| 1839 | } else { |
| 1840 | assembler_retries++; |
| 1841 | if (assembler_retries > MAX_ASSEMBLER_RETRIES) { |
| 1842 | CodegenDump(); |
| 1843 | LOG(FATAL) << "Assembler error - too many retries"; |
| 1844 | } |
| 1845 | // Redo offsets and try again |
| 1846 | AssignOffsets(); |
| 1847 | code_buffer_.clear(); |
| 1848 | } |
| 1849 | } |
| 1850 | |
| 1851 | // Install literals |
| 1852 | InstallLiteralPools(); |
| 1853 | |
| 1854 | // Install switch tables |
| 1855 | InstallSwitchTables(); |
| 1856 | |
| 1857 | // Install fill array data |
| 1858 | InstallFillArrayData(); |
| 1859 | |
| 1860 | // Create the mapping table and native offset to reference map. |
buzbee | a61f495 | 2013-08-23 14:27:06 -0700 | [diff] [blame] | 1861 | cu_->NewTimingSplit("PcMappingTable"); |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 1862 | CreateMappingTables(); |
| 1863 | |
buzbee | a61f495 | 2013-08-23 14:27:06 -0700 | [diff] [blame] | 1864 | cu_->NewTimingSplit("GcMap"); |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 1865 | CreateNativeGcMap(); |
| 1866 | } |
| 1867 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1868 | } // namespace art |