XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1 | // Copyright (c) Facebook, Inc. and its affiliates. |
| 2 | // All rights reserved. |
| 3 | // |
| 4 | // Copyright 2019 Google LLC |
| 5 | // |
| 6 | // This source code is licensed under the BSD-style license found in the |
| 7 | // LICENSE file in the root directory of this source tree. |
| 8 | |
| 9 | #include <stdbool.h> |
| 10 | #include <stddef.h> |
| 11 | #include <stdint.h> |
Marat Dukhan | 04f03be | 2019-11-19 12:36:47 -0800 | [diff] [blame] | 12 | #include <string.h> |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 13 | |
| 14 | #include <pthread.h> |
| 15 | |
Marat Dukhan | d343c22 | 2019-10-07 09:22:14 -0700 | [diff] [blame] | 16 | #ifndef __EMSCRIPTEN__ |
| 17 | #include <cpuinfo.h> |
| 18 | #endif |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 19 | |
| 20 | #include <xnnpack.h> |
| 21 | #include <xnnpack/argmaxpool.h> |
| 22 | #include <xnnpack/avgpool.h> |
Marat Dukhan | 6972249 | 2019-11-11 19:55:50 -0800 | [diff] [blame] | 23 | #include <xnnpack/bilinear.h> |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 24 | #include <xnnpack/clamp.h> |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 25 | #include <xnnpack/common.h> |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 26 | #include <xnnpack/conv.h> |
| 27 | #include <xnnpack/dwconv.h> |
| 28 | #include <xnnpack/gavgpool.h> |
| 29 | #include <xnnpack/gemm.h> |
| 30 | #include <xnnpack/hswish.h> |
| 31 | #include <xnnpack/igemm.h> |
| 32 | #include <xnnpack/log.h> |
| 33 | #include <xnnpack/lut.h> |
| 34 | #include <xnnpack/maxpool.h> |
Marat Dukhan | 04f03be | 2019-11-19 12:36:47 -0800 | [diff] [blame] | 35 | #include <xnnpack/memory.h> |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 36 | #include <xnnpack/pad.h> |
| 37 | #include <xnnpack/params.h> |
| 38 | #include <xnnpack/pavgpool.h> |
| 39 | #include <xnnpack/prelu.h> |
| 40 | #include <xnnpack/rmax.h> |
| 41 | #include <xnnpack/spmm.h> |
| 42 | #include <xnnpack/unpool.h> |
| 43 | #include <xnnpack/vadd.h> |
Marat Dukhan | 1e782c4 | 2019-11-21 17:02:40 -0800 | [diff] [blame] | 44 | #include <xnnpack/vbinary.h> |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 45 | #include <xnnpack/vmulcaddc.h> |
Marat Dukhan | 1e782c4 | 2019-11-21 17:02:40 -0800 | [diff] [blame] | 46 | #include <xnnpack/vunary.h> |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 47 | #include <xnnpack/zip.h> |
| 48 | |
| 49 | #ifndef XNN_ENABLE_ASSEMBLY |
| 50 | #define XNN_ENABLE_ASSEMBLY 1 |
| 51 | #endif |
| 52 | |
| 53 | static pthread_once_t init_guard = PTHREAD_ONCE_INIT; |
| 54 | |
| 55 | struct xnn_parameters xnn_params = { |
| 56 | .initialized = false |
| 57 | }; |
| 58 | |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 59 | #if XNN_ARCH_PNACL || XNN_ARCH_ASMJS || XNN_ARCH_WASM || XNN_ARCH_WASMSIMD |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 60 | extern uint32_t xnn_stub_wasm_f32_sub(uint32_t a, uint32_t b); |
| 61 | #endif |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 62 | #if XNN_ARCH_PNACL || XNN_ARCH_WASM || XNN_ARCH_WASMSIMD |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 63 | extern uint32_t xnn_stub_wasm_f32_min(uint32_t a, uint32_t b); |
| 64 | #endif |
| 65 | |
| 66 | static void init(void) { |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 67 | #if XNN_ARCH_ARM |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 68 | if (!cpuinfo_has_arm_neon()) { |
| 69 | xnn_log_error("XNNPACK initialization failed: NEON is not supported"); |
| 70 | return; |
| 71 | } |
| 72 | |
| 73 | /**************************** Q8 micro-kernels ****************************/ |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 74 | #ifndef XNN_NO_Q8_OPERATORS |
| 75 | xnn_params.q8.gemm = (struct gemm_parameters) { |
| 76 | .gemm = (xnn_gemm_ukernel_function) xnn_q8_gemm_ukernel_4x8__neon, |
| 77 | .igemm = (xnn_igemm_ukernel_function) xnn_q8_igemm_ukernel_4x8__neon, |
| 78 | .mr = 4, |
| 79 | .nr = 8, |
| 80 | }; |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 81 | |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 82 | #if XNN_ENABLE_ASSEMBLY |
| 83 | xnn_params.q8.dwconv[0] = (struct dwconv_parameters) { |
| 84 | .up = (xnn_dwconv_up_ukernel_function) xnn_q8_dwconv_ukernel_up8x9__aarch32_neon, |
| 85 | .cr = 8, |
| 86 | .mr = 9, |
| 87 | }; |
| 88 | #else |
| 89 | xnn_params.q8.dwconv[0] = (struct dwconv_parameters) { |
| 90 | .up = (xnn_dwconv_up_ukernel_function) xnn_q8_dwconv_ukernel_up8x9__neon, |
| 91 | .cr = 8, |
| 92 | .mr = 9, |
| 93 | }; |
| 94 | #endif |
| 95 | xnn_params.q8.avgpool = (struct avgpool_parameters) { |
| 96 | .up = (xnn_avgpool_up_ukernel_function) xnn_q8_avgpool_ukernel_up9__neon, |
| 97 | .mp = (xnn_avgpool_mp_ukernel_function) xnn_q8_avgpool_ukernel_mp9p8q__neon, |
| 98 | .mr = 9, |
| 99 | .qr = 8, |
| 100 | }; |
| 101 | xnn_params.q8.gavgpool = (struct gavgpool_parameters) { |
| 102 | .up = (xnn_gavgpool_up_ukernel_function) xnn_q8_gavgpool_ukernel_up7__neon, |
| 103 | .mp = (xnn_gavgpool_mp_ukernel_function) xnn_q8_gavgpool_ukernel_mp7p7q__neon, |
| 104 | .mr = 7, |
| 105 | }; |
| 106 | xnn_params.q8.vadd = (xnn_vadd_ukernel_function) xnn_q8_vadd_ukernel__neon; |
| 107 | #endif // XNN_NO_Q8_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 108 | |
| 109 | /**************************** U8 micro-kernels ****************************/ |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 110 | #ifndef XNN_NO_U8_OPERATORS |
| 111 | xnn_params.u8.maxpool = (struct maxpool_parameters) { |
Marat Dukhan | 329da64 | 2019-11-19 21:44:39 -0800 | [diff] [blame] | 112 | .ukernel = (xnn_maxpool_ukernel_function) xnn_u8_maxpool_ukernel_9p8x__neon_c16, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 113 | .mr = 9, |
| 114 | .qr = 8, |
| 115 | }; |
| 116 | xnn_params.u8.clamp = (xnn_univector_ukernel_function) xnn_u8_clamp_ukernel__neon; |
| 117 | xnn_params.u8.rmax = xnn_u8_rmax_ukernel__neon; |
| 118 | xnn_params.u8.lut32norm = xnn_u8_lut32norm_ukernel__scalar; |
| 119 | #endif // XNN_NO_U8_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 120 | |
| 121 | /**************************** X8 micro-kernels ****************************/ |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 122 | #ifndef XNN_NO_X8_OPERATORS |
| 123 | xnn_params.x8.lut = xnn_x8_lut_ukernel__scalar; |
| 124 | xnn_params.x8.zip = (struct zip_parameters) { |
| 125 | .x2 = (xnn_zipc_ukernel_function) xnn_x8_zip_x2_ukernel__neon, |
| 126 | .x3 = (xnn_zipc_ukernel_function) xnn_x8_zip_x3_ukernel__neon, |
| 127 | .x4 = (xnn_zipc_ukernel_function) xnn_x8_zip_x4_ukernel__neon, |
| 128 | .xm = (xnn_zipv_ukernel_function) xnn_x8_zip_xm_ukernel__neon, |
| 129 | }; |
| 130 | #endif // XNN_NO_X8_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 131 | |
| 132 | /**************************** F32 micro-kernels ****************************/ |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 133 | #ifndef XNN_NO_F32_OPERATORS |
Frank Barchard | 3267092 | 2019-11-30 21:58:51 -0800 | [diff] [blame] | 134 | #if XNN_ENABLE_ASSEMBLY |
| 135 | xnn_params.f32.gemm = (struct gemm_parameters) { |
| 136 | .gemm = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_4x8__aarch32_neon_ld64, |
| 137 | .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_4x8__neon_lane_ld128, |
| 138 | .gemm1 = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_1x8__neon_lane_ld64, |
| 139 | .igemm1 = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_1x8__neon_lane_ld64, |
| 140 | .mr = 4, |
| 141 | .nr = 8, |
| 142 | }; |
| 143 | #else // XNN_ENABLE_ASSEMBLY |
| 144 | xnn_params.f32.gemm = (struct gemm_parameters) { |
| 145 | .gemm = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_4x8__neon_lane_ld128, |
| 146 | .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_4x8__neon_lane_ld128, |
| 147 | .gemm1 = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_1x8__neon_lane_ld64, |
| 148 | .igemm1 = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_1x8__neon_lane_ld64, |
| 149 | .mr = 4, |
| 150 | .nr = 8, |
| 151 | }; |
| 152 | #endif // XNN_ENABLE_ASSEMBLY |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 153 | xnn_params.f32.gemm2 = (struct gemm_parameters) { |
| 154 | .gemm = NULL, |
Frank Barchard | 91317c5 | 2019-11-22 10:54:35 -0800 | [diff] [blame] | 155 | .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_4x2__neon_lane_ld64, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 156 | .mr = 4, |
| 157 | .nr = 2, |
| 158 | }; |
| 159 | xnn_params.f32.dwconv[0] = (struct dwconv_parameters) { |
| 160 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up4x4__psimd, |
| 161 | .cr = 4, |
| 162 | .mr = 4, |
| 163 | }; |
| 164 | xnn_params.f32.dwconv[1] = (struct dwconv_parameters) { |
| 165 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up4x9__neon, |
| 166 | .cr = 4, |
| 167 | .mr = 9, |
| 168 | }; |
| 169 | xnn_params.f32.dwconv[2] = (struct dwconv_parameters) { |
| 170 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up4x25__psimd, |
| 171 | .cr = 4, |
| 172 | .mr = 25, |
| 173 | }; |
| 174 | xnn_params.f32.avgpool = (struct avgpool_parameters) { |
| 175 | .up = (xnn_avgpool_up_ukernel_function) xnn_f32_avgpool_ukernel_up9__neon, |
| 176 | .mp = (xnn_avgpool_mp_ukernel_function) xnn_f32_avgpool_ukernel_mp9p8q__neon, |
| 177 | .mr = 9, |
| 178 | .qr = 8, |
| 179 | }; |
| 180 | xnn_params.f32.pavgpool = (struct pavgpool_parameters) { |
| 181 | .up = (xnn_pavgpool_up_ukernel_function) xnn_f32_pavgpool_ukernel_up9__neon, |
| 182 | .mp = (xnn_pavgpool_mp_ukernel_function) xnn_f32_pavgpool_ukernel_mp9p8q__neon, |
| 183 | .mr = 9, |
| 184 | .qr = 8, |
| 185 | }; |
| 186 | xnn_params.f32.gavgpool = (struct gavgpool_parameters) { |
| 187 | .up = (xnn_gavgpool_up_ukernel_function) xnn_f32_gavgpool_ukernel_up7__neon, |
| 188 | .mp = (xnn_gavgpool_mp_ukernel_function) xnn_f32_gavgpool_ukernel_mp7p7q__neon, |
| 189 | .mr = 7, |
| 190 | }; |
| 191 | xnn_params.f32.maxpool = (struct maxpool_parameters) { |
Marat Dukhan | 329da64 | 2019-11-19 21:44:39 -0800 | [diff] [blame] | 192 | .ukernel = (xnn_maxpool_ukernel_function) xnn_f32_maxpool_ukernel_9p8x__psimd_c4, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 193 | .mr = 9, |
| 194 | .qr = 8, |
| 195 | }; |
| 196 | xnn_params.f32.argmaxpool[0] = (struct argmaxpool_parameters) { |
Marat Dukhan | 329da64 | 2019-11-19 21:44:39 -0800 | [diff] [blame] | 197 | .up = (xnn_argmaxpool_up_ukernel_function) xnn_f32_argmaxpool_ukernel_4x__psimd_c4, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 198 | .mr = 4, |
| 199 | }; |
| 200 | xnn_params.f32.argmaxpool[1] = (struct argmaxpool_parameters) { |
Marat Dukhan | 329da64 | 2019-11-19 21:44:39 -0800 | [diff] [blame] | 201 | .up = (xnn_argmaxpool_up_ukernel_function) xnn_f32_argmaxpool_ukernel_9x__psimd_c4, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 202 | .mr = 9, |
| 203 | }; |
| 204 | xnn_params.f32.argmaxpool[2] = (struct argmaxpool_parameters) { |
Marat Dukhan | 329da64 | 2019-11-19 21:44:39 -0800 | [diff] [blame] | 205 | .mp = (xnn_argmaxpool_mp_ukernel_function) xnn_f32_argmaxpool_ukernel_9p8x__psimd_c4, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 206 | .mr = 9, |
| 207 | .qr = 8, |
| 208 | }; |
Marat Dukhan | 6972249 | 2019-11-11 19:55:50 -0800 | [diff] [blame] | 209 | xnn_params.f32.bilinear = (struct bilinear_parameters) { |
| 210 | .ukernel = (xnn_bilinear_ukernel_function) xnn_f32_bilinear_ukernel__neon_c8, |
| 211 | .pixel_tile = 1, |
| 212 | .channel_tile = 8, |
| 213 | }; |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 214 | xnn_params.f32.clamp = (xnn_univector_ukernel_function) xnn_f32_clamp_ukernel__neon; |
| 215 | xnn_params.f32.hswish = (xnn_univector_ukernel_function) xnn_f32_hswish_ukernel__neon; |
| 216 | xnn_params.f32.prelu = (struct prelu_parameters) { |
Marat Dukhan | 69c3f2c | 2019-11-06 12:30:01 -0800 | [diff] [blame] | 217 | .ukernel = (xnn_prelu_ukernel_function) xnn_f32_prelu_ukernel__neon_2x8, |
| 218 | .row_tile = 2, |
| 219 | .channel_tile = 8, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 220 | }; |
Marat Dukhan | c07cb7f | 2019-11-14 15:32:05 -0800 | [diff] [blame] | 221 | xnn_params.f32.vadd = (xnn_vadd_ukernel_function) xnn_f32_vadd_ukernel__neon_x8; |
Marat Dukhan | 1e782c4 | 2019-11-21 17:02:40 -0800 | [diff] [blame] | 222 | xnn_params.f32.vmul = (struct vbinary_parameters) { |
| 223 | .op_ukernel = (xnn_vbinary_ukernel_function) xnn_f32_vmul_ukernel__neon_x8, |
| 224 | .opc_ukernel = (xnn_vbinary_ukernel_function) xnn_f32_vmulc_ukernel__neon_x8, |
| 225 | .ropc_ukernel = (xnn_vbinary_ukernel_function) xnn_f32_vmulc_ukernel__neon_x8, |
Marat Dukhan | ca2733c | 2019-11-15 23:21:17 -0800 | [diff] [blame] | 226 | .element_tile = 8, |
| 227 | }; |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 228 | xnn_params.f32.vmulcaddc = (struct vmulcaddc_parameters) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 229 | .ukernel = (xnn_vmulcaddc_ukernel_function) xnn_f32_vmulcaddc_ukernel_c4__neon_2x, |
| 230 | .channel_tile = 4, |
| 231 | .row_tile = 2, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 232 | }; |
| 233 | #endif // XNN_NO_F32_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 234 | |
| 235 | /**************************** X32 micro-kernels ****************************/ |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 236 | #ifndef XNN_NO_X32_OPERATORS |
| 237 | xnn_params.x32.pad = (struct pad_parameters) { |
| 238 | .ukernel = xnn_x32_pad_x2__neon, |
| 239 | .mr = 2, |
| 240 | }; |
| 241 | xnn_params.x32.unpool = (xnn_unpool_ukernel_function) xnn_x32_unpool_ukernel__psimd; |
| 242 | xnn_params.x32.zip = (struct zip_parameters) { |
| 243 | .x2 = (xnn_zipc_ukernel_function) xnn_x32_zip_x2_ukernel__neon, |
| 244 | .x3 = (xnn_zipc_ukernel_function) xnn_x32_zip_x3_ukernel__neon, |
| 245 | .x4 = (xnn_zipc_ukernel_function) xnn_x32_zip_x4_ukernel__neon, |
| 246 | .xm = (xnn_zipv_ukernel_function) xnn_x32_zip_xm_ukernel__neon, |
| 247 | }; |
| 248 | #endif // XNN_NO_X32_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 249 | |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 250 | #elif XNN_ARCH_ARM64 |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 251 | |
| 252 | /**************************** Q8 micro-kernels ****************************/ |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 253 | #ifndef XNN_NO_Q8_OPERATORS |
| 254 | xnn_params.q8.gemm = (struct gemm_parameters) { |
| 255 | .gemm = (xnn_gemm_ukernel_function) xnn_q8_gemm_ukernel_8x8__neon, |
| 256 | .igemm = (xnn_igemm_ukernel_function) xnn_q8_igemm_ukernel_8x8__neon, |
| 257 | .mr = 8, |
| 258 | .nr = 8, |
| 259 | }; |
| 260 | xnn_params.q8.dwconv[0] = (struct dwconv_parameters) { |
| 261 | .up = (xnn_dwconv_up_ukernel_function) xnn_q8_dwconv_ukernel_up8x9__neon, |
| 262 | .cr = 8, |
| 263 | .mr = 9, |
| 264 | }; |
| 265 | xnn_params.q8.avgpool = (struct avgpool_parameters) { |
| 266 | .up = (xnn_avgpool_up_ukernel_function) xnn_q8_avgpool_ukernel_up9__neon, |
| 267 | .mp = (xnn_avgpool_mp_ukernel_function) xnn_q8_avgpool_ukernel_mp9p8q__neon, |
| 268 | .mr = 9, |
| 269 | .qr = 8, |
| 270 | }; |
| 271 | xnn_params.q8.gavgpool = (struct gavgpool_parameters) { |
| 272 | .up = (xnn_gavgpool_up_ukernel_function) xnn_q8_gavgpool_ukernel_up7__neon, |
| 273 | .mp = (xnn_gavgpool_mp_ukernel_function) xnn_q8_gavgpool_ukernel_mp7p7q__neon, |
| 274 | .mr = 7, |
| 275 | }; |
| 276 | xnn_params.q8.vadd = (xnn_vadd_ukernel_function) xnn_q8_vadd_ukernel__neon; |
| 277 | #endif // XNN_NO_Q8_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 278 | |
| 279 | /**************************** U8 micro-kernels ****************************/ |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 280 | #ifndef XNN_NO_U8_OPERATORS |
| 281 | xnn_params.u8.maxpool = (struct maxpool_parameters) { |
Marat Dukhan | 329da64 | 2019-11-19 21:44:39 -0800 | [diff] [blame] | 282 | .ukernel = (xnn_maxpool_ukernel_function) xnn_u8_maxpool_ukernel_9p8x__neon_c16, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 283 | .mr = 9, |
| 284 | .qr = 8, |
| 285 | }; |
| 286 | xnn_params.u8.clamp = (xnn_univector_ukernel_function) xnn_u8_clamp_ukernel__neon; |
| 287 | xnn_params.u8.lut32norm = xnn_u8_lut32norm_ukernel__scalar; |
| 288 | xnn_params.u8.rmax = xnn_u8_rmax_ukernel__neon; |
| 289 | #endif // XNN_NO_U8_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 290 | |
| 291 | /**************************** X8 micro-kernels ****************************/ |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 292 | #ifndef XNN_NO_X8_OPERATORS |
| 293 | xnn_params.x8.lut = xnn_x8_lut_ukernel__scalar; |
| 294 | xnn_params.x8.zip = (struct zip_parameters) { |
| 295 | .x2 = (xnn_zipc_ukernel_function) xnn_x8_zip_x2_ukernel__neon, |
| 296 | .x3 = (xnn_zipc_ukernel_function) xnn_x8_zip_x3_ukernel__neon, |
| 297 | .x4 = (xnn_zipc_ukernel_function) xnn_x8_zip_x4_ukernel__neon, |
| 298 | .xm = (xnn_zipv_ukernel_function) xnn_x8_zip_xm_ukernel__neon, |
| 299 | }; |
| 300 | #endif // XNN_NO_X8_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 301 | |
| 302 | /**************************** F32 micro-kernels ****************************/ |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 303 | #ifndef XNN_NO_F32_OPERATORS |
| 304 | #if XNN_ENABLE_ASSEMBLY |
| 305 | switch (cpuinfo_get_core(0)->uarch) { |
| 306 | case cpuinfo_uarch_kryo: |
| 307 | xnn_params.f32.gemm = (struct gemm_parameters) { |
| 308 | .gemm = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_4x8__aarch64_neonfma_cortex_a57, |
| 309 | .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_4x8__aarch64_neonfma_cortex_a75, |
| 310 | .gemm1 = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_1x8__aarch64_neonfma_cortex_a75, |
| 311 | .igemm1 = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_1x8__aarch64_neonfma_cortex_a75, |
| 312 | .mr = 4, |
| 313 | .nr = 8, |
| 314 | }; |
| 315 | break; |
| 316 | case cpuinfo_uarch_cortex_a57: |
| 317 | xnn_params.f32.gemm = (struct gemm_parameters) { |
| 318 | .gemm = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_6x8__aarch64_neonfma_cortex_a57, |
| 319 | .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_6x8__aarch64_neonfma_cortex_a57, |
| 320 | .gemm1 = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_1x8__aarch64_neonfma_cortex_a57, |
| 321 | .igemm1 = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_1x8__aarch64_neonfma_cortex_a57, |
| 322 | .mr = 6, |
| 323 | .nr = 8, |
| 324 | }; |
| 325 | break; |
| 326 | case cpuinfo_uarch_cortex_a72: |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 327 | xnn_params.f32.gemm = (struct gemm_parameters) { |
| 328 | .gemm = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_4x8__aarch64_neonfma_cortex_a75, |
| 329 | .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_4x8__aarch64_neonfma_cortex_a75, |
| 330 | .gemm1 = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_1x8__aarch64_neonfma_cortex_a75, |
| 331 | .igemm1 = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_1x8__aarch64_neonfma_cortex_a75, |
| 332 | .mr = 4, |
| 333 | .nr = 8, |
| 334 | }; |
| 335 | break; |
| 336 | case cpuinfo_uarch_cortex_a75: |
Frank Barchard | 263bb09 | 2019-10-28 15:28:46 -0700 | [diff] [blame] | 337 | case cpuinfo_uarch_cortex_a76: |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 338 | case cpuinfo_uarch_meerkat_m3: |
| 339 | case (cpuinfo_uarch_meerkat_m3 + 1): |
| 340 | xnn_params.f32.gemm = (struct gemm_parameters) { |
| 341 | .gemm = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_6x8__aarch64_neonfma_cortex_a75, |
| 342 | .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_6x8__aarch64_neonfma_cortex_a75, |
| 343 | .gemm1 = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_1x8__aarch64_neonfma_cortex_a75, |
| 344 | .igemm1 = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_1x8__aarch64_neonfma_cortex_a75, |
| 345 | .mr = 6, |
| 346 | .nr = 8, |
| 347 | }; |
| 348 | break; |
Frank Barchard | df06d80 | 2019-11-20 15:53:46 -0800 | [diff] [blame] | 349 | |
| 350 | case cpuinfo_uarch_mongoose_m1: |
| 351 | case cpuinfo_uarch_mongoose_m2: |
| 352 | xnn_params.f32.gemm = (struct gemm_parameters) { |
| 353 | .gemm = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_6x8s4__neonfma, |
| 354 | .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_6x8s4__neonfma, |
| 355 | .gemm1 = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_1x8s4__neonfma, |
| 356 | .igemm1 = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_1x8s4__neonfma, |
| 357 | .mr = 6, |
| 358 | .nr = 8, |
| 359 | .log2_sr = 2, |
| 360 | }; |
| 361 | break; |
| 362 | |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 363 | case cpuinfo_uarch_cortex_a53: |
| 364 | case cpuinfo_uarch_cortex_a55: |
| 365 | xnn_params.f32.gemm = (struct gemm_parameters) { |
Frank Barchard | bd1d5d9 | 2019-10-30 15:53:30 -0700 | [diff] [blame] | 366 | .gemm = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_6x8__aarch64_neonfma_cortex_a53, |
| 367 | .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_6x8__aarch64_neonfma_cortex_a53, |
| 368 | .gemm1 = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_1x8__aarch64_neonfma_cortex_a53, |
| 369 | .igemm1 = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_1x8__aarch64_neonfma_cortex_a53, |
| 370 | .mr = 6, |
| 371 | .nr = 8, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 372 | }; |
| 373 | break; |
| 374 | case cpuinfo_uarch_cortex_a73: |
| 375 | xnn_params.f32.gemm = (struct gemm_parameters) { |
| 376 | .gemm = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_6x8__aarch64_neonfma_cortex_a73, |
| 377 | .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_6x8__aarch64_neonfma_cortex_a73, |
| 378 | .gemm1 = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_1x8__aarch64_neonfma_cortex_a75, |
| 379 | .igemm1 = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_1x8__aarch64_neonfma_cortex_a75, |
| 380 | .mr = 6, |
| 381 | .nr = 8, |
| 382 | }; |
| 383 | break; |
| 384 | default: |
| 385 | xnn_params.f32.gemm = (struct gemm_parameters) { |
Frank Barchard | 91317c5 | 2019-11-22 10:54:35 -0800 | [diff] [blame] | 386 | .gemm = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_6x8__neonfma_lane_ld64, |
| 387 | .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_6x8__neonfma_lane_ld64, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 388 | .gemm1 = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_1x8__aarch64_neonfma_cortex_a75, |
| 389 | .igemm1 = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_1x8__aarch64_neonfma_cortex_a75, |
Frank Barchard | 2af471b | 2019-10-16 19:10:32 -0700 | [diff] [blame] | 390 | .mr = 6, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 391 | .nr = 8, |
| 392 | }; |
| 393 | break; |
| 394 | } |
| 395 | #else // XNN_ENABLE_ASSEMBLY |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 396 | xnn_params.f32.gemm = (struct gemm_parameters) { |
Frank Barchard | 91317c5 | 2019-11-22 10:54:35 -0800 | [diff] [blame] | 397 | .gemm = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_6x8__neonfma_lane_ld64, |
| 398 | .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_6x8__neonfma_lane_ld64, |
| 399 | .gemm1 = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_1x8__neonfma_lane_ld64, |
| 400 | .igemm1 = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_1x8__neonfma_lane_ld64, |
Frank Barchard | 2af471b | 2019-10-16 19:10:32 -0700 | [diff] [blame] | 401 | .mr = 6, |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 402 | .nr = 8, |
| 403 | }; |
Frank Barchard | 3267092 | 2019-11-30 21:58:51 -0800 | [diff] [blame] | 404 | #endif // XNN_ENABLE_ASSEMBLY |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 405 | |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 406 | xnn_params.f32.gemm2 = (struct gemm_parameters) { |
| 407 | .gemm = NULL, |
Frank Barchard | 91317c5 | 2019-11-22 10:54:35 -0800 | [diff] [blame] | 408 | .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_4x2__neonfma_lane_ld64, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 409 | .mr = 4, |
| 410 | .nr = 2, |
| 411 | }; |
| 412 | xnn_params.f32.dwconv[0] = (struct dwconv_parameters) { |
| 413 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up4x4__psimd, |
| 414 | .cr = 4, |
| 415 | .mr = 4, |
| 416 | }; |
| 417 | switch (cpuinfo_get_core(0)->uarch) { |
| 418 | case cpuinfo_uarch_kryo: |
| 419 | xnn_params.f32.dwconv[1] = (struct dwconv_parameters) { |
| 420 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up4x9__neonfma, |
| 421 | .cr = 4, |
| 422 | .mr = 9, |
| 423 | }; |
| 424 | break; |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 425 | #if XNN_ENABLE_ASSEMBLY |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 426 | case cpuinfo_uarch_cortex_a53: |
| 427 | case cpuinfo_uarch_cortex_a55: |
| 428 | xnn_params.f32.dwconv[1] = (struct dwconv_parameters) { |
| 429 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up4x9__aarch64_neonfma_cortex_a55, |
| 430 | .cr = 4, |
| 431 | .mr = 9, |
| 432 | }; |
| 433 | break; |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 434 | #endif |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 435 | default: |
| 436 | xnn_params.f32.dwconv[1] = (struct dwconv_parameters) { |
| 437 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up8x9__neonfma, |
| 438 | .cr = 8, |
| 439 | .mr = 9, |
| 440 | }; |
| 441 | break; |
| 442 | } |
| 443 | xnn_params.f32.dwconv[2] = (struct dwconv_parameters) { |
| 444 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up4x25__psimd, |
| 445 | .cr = 4, |
| 446 | .mr = 25, |
| 447 | }; |
| 448 | xnn_params.f32.avgpool = (struct avgpool_parameters) { |
| 449 | .up = (xnn_avgpool_up_ukernel_function) xnn_f32_avgpool_ukernel_up9__neon, |
| 450 | .mp = (xnn_avgpool_mp_ukernel_function) xnn_f32_avgpool_ukernel_mp9p8q__neon, |
| 451 | .mr = 9, |
| 452 | .qr = 8, |
| 453 | }; |
| 454 | xnn_params.f32.pavgpool = (struct pavgpool_parameters) { |
| 455 | .up = (xnn_pavgpool_up_ukernel_function) xnn_f32_pavgpool_ukernel_up9__neon, |
| 456 | .mp = (xnn_pavgpool_mp_ukernel_function) xnn_f32_pavgpool_ukernel_mp9p8q__neon, |
| 457 | .mr = 9, |
| 458 | .qr = 8, |
| 459 | }; |
| 460 | xnn_params.f32.gavgpool = (struct gavgpool_parameters) { |
| 461 | .up = (xnn_gavgpool_up_ukernel_function) xnn_f32_gavgpool_ukernel_up7__neon, |
| 462 | .mp = (xnn_gavgpool_mp_ukernel_function) xnn_f32_gavgpool_ukernel_mp7p7q__neon, |
| 463 | .mr = 7, |
| 464 | }; |
| 465 | xnn_params.f32.maxpool = (struct maxpool_parameters) { |
Marat Dukhan | 329da64 | 2019-11-19 21:44:39 -0800 | [diff] [blame] | 466 | .ukernel = (xnn_maxpool_ukernel_function) xnn_f32_maxpool_ukernel_9p8x__psimd_c4, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 467 | .mr = 9, |
| 468 | .qr = 8, |
| 469 | }; |
| 470 | xnn_params.f32.argmaxpool[0] = (struct argmaxpool_parameters) { |
Marat Dukhan | 329da64 | 2019-11-19 21:44:39 -0800 | [diff] [blame] | 471 | .up = (xnn_argmaxpool_up_ukernel_function) xnn_f32_argmaxpool_ukernel_4x__psimd_c4, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 472 | .mr = 4, |
| 473 | }; |
| 474 | xnn_params.f32.argmaxpool[1] = (struct argmaxpool_parameters) { |
Marat Dukhan | 329da64 | 2019-11-19 21:44:39 -0800 | [diff] [blame] | 475 | .up = (xnn_argmaxpool_up_ukernel_function) xnn_f32_argmaxpool_ukernel_9x__psimd_c4, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 476 | .mr = 9, |
| 477 | }; |
| 478 | xnn_params.f32.argmaxpool[2] = (struct argmaxpool_parameters) { |
Marat Dukhan | 329da64 | 2019-11-19 21:44:39 -0800 | [diff] [blame] | 479 | .mp = (xnn_argmaxpool_mp_ukernel_function) xnn_f32_argmaxpool_ukernel_9p8x__psimd_c4, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 480 | .mr = 9, |
| 481 | .qr = 8, |
| 482 | }; |
Marat Dukhan | 6972249 | 2019-11-11 19:55:50 -0800 | [diff] [blame] | 483 | xnn_params.f32.bilinear = (struct bilinear_parameters) { |
| 484 | .ukernel = (xnn_bilinear_ukernel_function) xnn_f32_bilinear_ukernel__neonfma_c8, |
| 485 | .pixel_tile = 1, |
| 486 | .channel_tile = 8, |
| 487 | }; |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 488 | xnn_params.f32.clamp = (xnn_univector_ukernel_function) xnn_f32_clamp_ukernel__neon; |
| 489 | xnn_params.f32.hswish = (xnn_univector_ukernel_function) xnn_f32_hswish_ukernel__neonfma; |
Marat Dukhan | 14bec50 | 2019-11-18 11:35:31 -0800 | [diff] [blame] | 490 | xnn_params.f32.sigmoid = (xnn_univector_ukernel_function) xnn_f32_sigmoid_ukernel__neon_frac_p9_p10_nr1recps_x16; |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 491 | xnn_params.f32.prelu = (struct prelu_parameters) { |
Marat Dukhan | 69c3f2c | 2019-11-06 12:30:01 -0800 | [diff] [blame] | 492 | .ukernel = (xnn_prelu_ukernel_function) xnn_f32_prelu_ukernel__neon_2x8, |
| 493 | .row_tile = 2, |
| 494 | .channel_tile = 8, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 495 | }; |
Marat Dukhan | c07cb7f | 2019-11-14 15:32:05 -0800 | [diff] [blame] | 496 | xnn_params.f32.vadd = (xnn_vadd_ukernel_function) xnn_f32_vadd_ukernel__neon_x8; |
Marat Dukhan | 1e782c4 | 2019-11-21 17:02:40 -0800 | [diff] [blame] | 497 | xnn_params.f32.vmul = (struct vbinary_parameters) { |
| 498 | .op_ukernel = (xnn_vbinary_ukernel_function) xnn_f32_vmul_ukernel__neon_x8, |
| 499 | .opc_ukernel = (xnn_vbinary_ukernel_function) xnn_f32_vmulc_ukernel__neon_x8, |
| 500 | .ropc_ukernel = (xnn_vbinary_ukernel_function) xnn_f32_vmulc_ukernel__neon_x8, |
Marat Dukhan | ca2733c | 2019-11-15 23:21:17 -0800 | [diff] [blame] | 501 | .element_tile = 8, |
| 502 | }; |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 503 | xnn_params.f32.vmulcaddc = (struct vmulcaddc_parameters) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 504 | .ukernel = (xnn_vmulcaddc_ukernel_function) xnn_f32_vmulcaddc_ukernel_c4__neonfma_2x, |
| 505 | .channel_tile = 4, |
| 506 | .row_tile = 2, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 507 | }; |
Marat Dukhan | efc47b8 | 2019-11-18 09:25:38 -0800 | [diff] [blame] | 508 | #ifndef XNN_NO_NCHW_OPERATORS |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 509 | xnn_params.f32.spmm = (struct spmm_parameters) { |
Erich Elsen | 9cdade3 | 2019-10-16 05:26:59 -0700 | [diff] [blame] | 510 | .ukernel = (xnn_spmm_ukernel_function) xnn_f32_spmm_ukernel_16x1__neonfma_pipelined, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 511 | .mr = 16, |
| 512 | .nr = 1, |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 513 | }; |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 514 | xnn_params.f32.spmm2 = (struct spmm_parameters) { |
| 515 | .ukernel = (xnn_spmm_ukernel_function) xnn_f32_spmm_ukernel_16x2__neonfma, |
| 516 | .mr = 16, |
| 517 | .nr = 2, |
| 518 | }; |
| 519 | xnn_params.f32.spmm4 = (struct spmm_parameters) { |
| 520 | .ukernel = (xnn_spmm_ukernel_function) xnn_f32_spmm_ukernel_16x4__neonfma, |
| 521 | .mr = 16, |
| 522 | .nr = 4, |
| 523 | }; |
| 524 | xnn_params.f32.hwc2spchw_dconv3x3c3s2 = (struct hwc2spchw_dconv_parameters) { |
| 525 | .ukernel_with_symm_padding = |
| 526 | (xnn_conv_hwc2spchw_ukernel_function) xnn_f32_conv_hwc2spchw_ukernel_3x3s2p1c3x4__neonfma_2x2, |
| 527 | .output_channel_tile = 4, |
| 528 | .output_height_tile = 2, |
| 529 | .output_width_tile = 2, |
| 530 | }; |
| 531 | xnn_params.f32.spchw_dwconv3x3 = (struct spchw_dwconv_parameters) { |
| 532 | .ukernel = (xnn_dwconv_spchw_ukernel_function) xnn_f32_dwconv_spchw_ukernel_3x3p1__neonfma, |
| 533 | .input_width_tile = 4, |
| 534 | .output_width_tile = 4, |
| 535 | .output_height_tile = 3, |
| 536 | }; |
| 537 | xnn_params.f32.spchw_dwconv3x3s2 = (struct spchw_dwconv_parameters) { |
| 538 | .ukernel = (xnn_dwconv_spchw_ukernel_function) xnn_f32_dwconv_spchw_ukernel_3x3s2p1__neonfma, |
| 539 | .input_width_tile = 4, |
| 540 | .output_width_tile = 4, |
| 541 | .output_height_tile = 1, |
| 542 | }; |
Marat Dukhan | a99918a | 2019-11-15 14:40:12 -0800 | [diff] [blame] | 543 | xnn_params.f32.spchw_dwconv5x5 = (struct spchw_dwconv_parameters) { |
| 544 | .ukernel = (xnn_dwconv_spchw_ukernel_function) xnn_f32_dwconv_spchw_ukernel_5x5p2__neonfma, |
| 545 | .input_width_tile = 4, |
| 546 | .output_width_tile = 4, |
Erich Elsen | 4ad5115 | 2019-11-19 13:11:53 -0800 | [diff] [blame] | 547 | .output_height_tile = 3, |
Marat Dukhan | a99918a | 2019-11-15 14:40:12 -0800 | [diff] [blame] | 548 | }; |
| 549 | xnn_params.f32.spchw_dwconv5x5s2 = (struct spchw_dwconv_parameters) { |
| 550 | .ukernel = (xnn_dwconv_spchw_ukernel_function) xnn_f32_dwconv_spchw_ukernel_5x5s2p2__neonfma, |
| 551 | .input_width_tile = 4, |
| 552 | .output_width_tile = 4, |
| 553 | .output_height_tile = 1, |
| 554 | }; |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 555 | xnn_params.f32.spchw_gavgpool = (struct spchw_gavgpool_parameters) { |
| 556 | .ukernel = (xnn_gavgpool_spchw_ukernel_function) xnn_f32_gavgpool_spchw_ukernel__neon_x4, |
| 557 | .channel_tile = 4, |
| 558 | }; |
Marat Dukhan | efc47b8 | 2019-11-18 09:25:38 -0800 | [diff] [blame] | 559 | #endif // XNN_NO_NCHW_OPERATORS |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 560 | #endif // XNN_NO_F32_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 561 | |
| 562 | /**************************** X32 micro-kernels ****************************/ |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 563 | #ifndef XNN_NO_X32_OPERATORS |
| 564 | xnn_params.x32.pad = (struct pad_parameters) { |
| 565 | .ukernel = xnn_x32_pad_x2__neon, |
| 566 | .mr = 2, |
| 567 | }; |
| 568 | xnn_params.x32.unpool = (xnn_unpool_ukernel_function) xnn_x32_unpool_ukernel__psimd; |
| 569 | xnn_params.x32.zip = (struct zip_parameters) { |
| 570 | .x2 = (xnn_zipc_ukernel_function) xnn_x32_zip_x2_ukernel__neon, |
| 571 | .x3 = (xnn_zipc_ukernel_function) xnn_x32_zip_x3_ukernel__neon, |
| 572 | .x4 = (xnn_zipc_ukernel_function) xnn_x32_zip_x4_ukernel__neon, |
| 573 | .xm = (xnn_zipv_ukernel_function) xnn_x32_zip_xm_ukernel__neon, |
| 574 | }; |
| 575 | #endif // XNN_NO_X32_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 576 | |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 577 | #elif XNN_ARCH_X86 || XNN_ARCH_X86_64 |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 578 | if (!cpuinfo_has_x86_sse2()) { |
| 579 | xnn_log_error("XNNPACK initialization failed: SSE2 is not supported"); |
| 580 | return; |
| 581 | } |
| 582 | |
| 583 | /**************************** Q8 micro-kernels ****************************/ |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 584 | #ifndef XNN_NO_Q8_OPERATORS |
| 585 | xnn_params.q8.gemm = (struct gemm_parameters) { |
| 586 | .gemm = (xnn_gemm_ukernel_function) xnn_q8_gemm_ukernel_4x4c2__sse2, |
| 587 | .igemm = (xnn_igemm_ukernel_function) xnn_q8_igemm_ukernel_4x4c2__sse2, |
| 588 | .mr = 4, |
| 589 | .nr = 4, |
| 590 | .log2_kr = 1, |
| 591 | }; |
| 592 | xnn_params.q8.dwconv[0] = (struct dwconv_parameters) { |
| 593 | .up = (xnn_dwconv_up_ukernel_function) xnn_q8_dwconv_ukernel_up8x9__sse2, |
| 594 | .cr = 8, |
| 595 | .mr = 9, |
| 596 | }; |
| 597 | xnn_params.q8.avgpool = (struct avgpool_parameters) { |
| 598 | .up = (xnn_avgpool_up_ukernel_function) xnn_q8_avgpool_ukernel_up9__sse2, |
| 599 | .mp = (xnn_avgpool_mp_ukernel_function) xnn_q8_avgpool_ukernel_mp9p8q__sse2, |
| 600 | .mr = 9, |
| 601 | .qr = 8, |
| 602 | }; |
| 603 | xnn_params.q8.gavgpool = (struct gavgpool_parameters) { |
| 604 | .up = (xnn_gavgpool_up_ukernel_function) xnn_q8_gavgpool_ukernel_up7__sse2, |
| 605 | .mp = (xnn_gavgpool_mp_ukernel_function) xnn_q8_gavgpool_ukernel_mp7p7q__sse2, |
| 606 | .mr = 7, |
| 607 | }; |
| 608 | xnn_params.q8.vadd = (xnn_vadd_ukernel_function) xnn_q8_vadd_ukernel__sse2; |
| 609 | #endif // XNN_NO_Q8_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 610 | |
| 611 | /**************************** U8 micro-kernels ****************************/ |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 612 | #ifndef XNN_NO_U8_OPERATORS |
| 613 | xnn_params.u8.maxpool = (struct maxpool_parameters) { |
Marat Dukhan | 329da64 | 2019-11-19 21:44:39 -0800 | [diff] [blame] | 614 | .ukernel = (xnn_maxpool_ukernel_function) xnn_u8_maxpool_ukernel_9p8x__sse2_c16, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 615 | .mr = 9, |
| 616 | .qr = 8, |
| 617 | }; |
| 618 | xnn_params.u8.clamp = (xnn_univector_ukernel_function) xnn_u8_clamp_ukernel__sse2; |
| 619 | xnn_params.u8.lut32norm = xnn_u8_lut32norm_ukernel__scalar; |
| 620 | xnn_params.u8.rmax = xnn_u8_rmax_ukernel__sse2; |
| 621 | #endif // XNN_NO_U8_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 622 | |
| 623 | /**************************** X8 micro-kernels ****************************/ |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 624 | #ifndef XNN_NO_X8_OPERATORS |
| 625 | xnn_params.x8.lut = xnn_x8_lut_ukernel__scalar; |
| 626 | xnn_params.x8.zip = (struct zip_parameters) { |
| 627 | .x2 = (xnn_zipc_ukernel_function) xnn_x8_zip_x2_ukernel__sse2, |
| 628 | .x3 = (xnn_zipc_ukernel_function) xnn_x8_zip_x3_ukernel__sse2, |
| 629 | .x4 = (xnn_zipc_ukernel_function) xnn_x8_zip_x4_ukernel__sse2, |
| 630 | .xm = (xnn_zipv_ukernel_function) xnn_x8_zip_xm_ukernel__sse2, |
| 631 | }; |
| 632 | #endif // XNN_NO_X8_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 633 | |
| 634 | /**************************** F32 micro-kernels ****************************/ |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 635 | #ifndef XNN_NO_F32_OPERATORS |
Marat Dukhan | 0f349c4 | 2019-11-27 11:58:54 -0800 | [diff] [blame] | 636 | if (!XNN_PLATFORM_MOBILE && cpuinfo_has_x86_avx512f()) { |
| 637 | xnn_params.f32.gemm = (struct gemm_parameters) { |
| 638 | .gemm = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_7x16__avx512f_broadcast, |
| 639 | .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_7x16__avx512f_broadcast, |
| 640 | .gemm1 = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_1x16__avx512f_broadcast, |
| 641 | .igemm1 = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_1x16__avx512f_broadcast, |
| 642 | .mr = 7, |
| 643 | .nr = 16, |
| 644 | }; |
| 645 | } else if (!XNN_PLATFORM_MOBILE && cpuinfo_has_x86_fma3()) { |
Marat Dukhan | 1025ea3 | 2019-11-21 16:01:08 -0800 | [diff] [blame] | 646 | xnn_params.f32.gemm = (struct gemm_parameters) { |
| 647 | .gemm = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_7x8__fma3_broadcast, |
| 648 | .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_7x8__fma3_broadcast, |
| 649 | .gemm1 = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_1x8__fma3_broadcast, |
| 650 | .igemm1 = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_1x8__fma3_broadcast, |
| 651 | .mr = 7, |
| 652 | .nr = 8, |
| 653 | }; |
| 654 | } else if (!XNN_PLATFORM_MOBILE && cpuinfo_has_x86_avx()) { |
| 655 | xnn_params.f32.gemm = (struct gemm_parameters) { |
| 656 | .gemm = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_7x8__avx_broadcast, |
| 657 | .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_7x8__avx_broadcast, |
| 658 | .gemm1 = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_1x8__avx_broadcast, |
| 659 | .igemm1 = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_1x8__avx_broadcast, |
| 660 | .mr = 7, |
| 661 | .nr = 8, |
| 662 | }; |
| 663 | } else { |
| 664 | xnn_params.f32.gemm = (struct gemm_parameters) { |
| 665 | .gemm = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_4x8__sse_load1, |
| 666 | .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_4x8__sse_load1, |
| 667 | .gemm1 = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_1x8__sse_load1, |
| 668 | .igemm1 = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_1x8__sse_load1, |
| 669 | .mr = 4, |
| 670 | .nr = 8, |
| 671 | }; |
| 672 | } |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 673 | xnn_params.f32.gemm2 = (struct gemm_parameters) { |
| 674 | .gemm = NULL, |
| 675 | .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_4x2c4__sse, |
| 676 | .mr = 4, |
| 677 | .nr = 2, |
| 678 | .log2_kr = 2, |
| 679 | }; |
Marat Dukhan | 479f87e | 2019-11-27 15:17:06 -0800 | [diff] [blame] | 680 | if (!XNN_PLATFORM_MOBILE && cpuinfo_has_x86_avx512f()) { |
| 681 | xnn_params.f32.dwconv[0] = (struct dwconv_parameters) { |
| 682 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up16x4__avx512f, |
| 683 | .cr = 16, |
| 684 | .mr = 4, |
| 685 | }; |
| 686 | xnn_params.f32.dwconv[1] = (struct dwconv_parameters) { |
| 687 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up16x9__avx512f, |
| 688 | .cr = 16, |
| 689 | .mr = 9, |
| 690 | }; |
| 691 | xnn_params.f32.dwconv[2] = (struct dwconv_parameters) { |
| 692 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up16x25__avx512f, |
| 693 | .cr = 16, |
| 694 | .mr = 25, |
| 695 | }; |
| 696 | } else if (!XNN_PLATFORM_MOBILE && cpuinfo_has_x86_fma3()) { |
Marat Dukhan | 17ec5f3 | 2019-11-22 13:34:16 -0800 | [diff] [blame] | 697 | xnn_params.f32.dwconv[0] = (struct dwconv_parameters) { |
| 698 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up16x4__fma3, |
| 699 | .cr = 16, |
| 700 | .mr = 4, |
| 701 | }; |
| 702 | xnn_params.f32.dwconv[1] = (struct dwconv_parameters) { |
| 703 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up16x9__fma3, |
| 704 | .cr = 16, |
| 705 | .mr = 9, |
| 706 | }; |
| 707 | xnn_params.f32.dwconv[2] = (struct dwconv_parameters) { |
| 708 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up8x25__fma3, |
| 709 | .cr = 8, |
| 710 | .mr = 25, |
| 711 | }; |
| 712 | } else if (!XNN_PLATFORM_MOBILE && cpuinfo_has_x86_avx()) { |
| 713 | xnn_params.f32.dwconv[0] = (struct dwconv_parameters) { |
| 714 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up16x4__avx, |
| 715 | .cr = 16, |
| 716 | .mr = 4, |
| 717 | }; |
| 718 | xnn_params.f32.dwconv[1] = (struct dwconv_parameters) { |
| 719 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up16x9__avx, |
| 720 | .cr = 16, |
| 721 | .mr = 9, |
| 722 | }; |
| 723 | xnn_params.f32.dwconv[2] = (struct dwconv_parameters) { |
| 724 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up8x25__avx, |
| 725 | .cr = 8, |
| 726 | .mr = 25, |
| 727 | }; |
| 728 | } else { |
| 729 | xnn_params.f32.dwconv[0] = (struct dwconv_parameters) { |
| 730 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up8x4__sse, |
| 731 | .cr = 8, |
| 732 | .mr = 4, |
| 733 | }; |
| 734 | xnn_params.f32.dwconv[1] = (struct dwconv_parameters) { |
| 735 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up8x9__sse, |
| 736 | .cr = 8, |
| 737 | .mr = 9, |
| 738 | }; |
| 739 | xnn_params.f32.dwconv[2] = (struct dwconv_parameters) { |
| 740 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up8x25__sse, |
| 741 | .cr = 8, |
| 742 | .mr = 25, |
| 743 | }; |
| 744 | } |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 745 | xnn_params.f32.avgpool = (struct avgpool_parameters) { |
| 746 | .up = (xnn_avgpool_up_ukernel_function) xnn_f32_avgpool_ukernel_up9__sse, |
| 747 | .mp = (xnn_avgpool_mp_ukernel_function) xnn_f32_avgpool_ukernel_mp9p8q__sse, |
| 748 | .mr = 9, |
| 749 | .qr = 8, |
| 750 | }; |
| 751 | xnn_params.f32.pavgpool = (struct pavgpool_parameters) { |
| 752 | .up = (xnn_pavgpool_up_ukernel_function) xnn_f32_pavgpool_ukernel_up9__sse, |
| 753 | .mp = (xnn_pavgpool_mp_ukernel_function) xnn_f32_pavgpool_ukernel_mp9p8q__sse, |
| 754 | .mr = 9, |
| 755 | .qr = 8, |
| 756 | }; |
| 757 | xnn_params.f32.gavgpool = (struct gavgpool_parameters) { |
| 758 | .up = (xnn_gavgpool_up_ukernel_function) xnn_f32_gavgpool_ukernel_up7__sse, |
| 759 | .mp = (xnn_gavgpool_mp_ukernel_function) xnn_f32_gavgpool_ukernel_mp7p7q__sse, |
| 760 | .mr = 7, |
| 761 | }; |
| 762 | xnn_params.f32.maxpool = (struct maxpool_parameters) { |
Marat Dukhan | 329da64 | 2019-11-19 21:44:39 -0800 | [diff] [blame] | 763 | .ukernel = (xnn_maxpool_ukernel_function) xnn_f32_maxpool_ukernel_9p8x__sse_c4, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 764 | .mr = 9, |
| 765 | .qr = 8, |
| 766 | }; |
| 767 | xnn_params.f32.argmaxpool[0] = (struct argmaxpool_parameters) { |
Marat Dukhan | 329da64 | 2019-11-19 21:44:39 -0800 | [diff] [blame] | 768 | .up = (xnn_argmaxpool_up_ukernel_function) xnn_f32_argmaxpool_ukernel_4x__sse2_c4, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 769 | .mr = 4, |
| 770 | }; |
| 771 | xnn_params.f32.argmaxpool[1] = (struct argmaxpool_parameters) { |
Marat Dukhan | 329da64 | 2019-11-19 21:44:39 -0800 | [diff] [blame] | 772 | .up = (xnn_argmaxpool_up_ukernel_function) xnn_f32_argmaxpool_ukernel_9x__sse2_c4, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 773 | .mr = 9, |
| 774 | }; |
| 775 | xnn_params.f32.argmaxpool[2] = (struct argmaxpool_parameters) { |
Marat Dukhan | 329da64 | 2019-11-19 21:44:39 -0800 | [diff] [blame] | 776 | .mp = (xnn_argmaxpool_mp_ukernel_function) xnn_f32_argmaxpool_ukernel_9p8x__sse2_c4, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 777 | .mr = 9, |
| 778 | .qr = 8, |
| 779 | }; |
Marat Dukhan | 6972249 | 2019-11-11 19:55:50 -0800 | [diff] [blame] | 780 | xnn_params.f32.bilinear = (struct bilinear_parameters) { |
| 781 | .ukernel = (xnn_bilinear_ukernel_function) xnn_f32_bilinear_ukernel__sse_c8, |
| 782 | .pixel_tile = 1, |
| 783 | .channel_tile = 8, |
| 784 | }; |
Marat Dukhan | e2c3f29 | 2019-11-27 15:40:54 -0800 | [diff] [blame] | 785 | if (!XNN_PLATFORM_MOBILE && cpuinfo_has_x86_avx512f()) { |
| 786 | xnn_params.f32.clamp = (xnn_univector_ukernel_function) xnn_f32_clamp_ukernel__avx512f; |
| 787 | } else if (!XNN_PLATFORM_MOBILE && cpuinfo_has_x86_avx()) { |
| 788 | xnn_params.f32.clamp = (xnn_univector_ukernel_function) xnn_f32_clamp_ukernel__avx; |
| 789 | } else { |
| 790 | xnn_params.f32.clamp = (xnn_univector_ukernel_function) xnn_f32_clamp_ukernel__sse; |
| 791 | } |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 792 | xnn_params.f32.hswish = (xnn_univector_ukernel_function) xnn_f32_hswish_ukernel__sse; |
Marat Dukhan | 7bee751 | 2019-11-18 15:15:48 -0800 | [diff] [blame] | 793 | xnn_params.f32.sigmoid = (xnn_univector_ukernel_function) xnn_f32_sigmoid_ukernel__sse2_p5_div_x16; |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 794 | xnn_params.f32.prelu = (struct prelu_parameters) { |
Marat Dukhan | 69c3f2c | 2019-11-06 12:30:01 -0800 | [diff] [blame] | 795 | .ukernel = (xnn_prelu_ukernel_function) xnn_f32_prelu_ukernel__sse2_2x8, |
| 796 | .row_tile = 2, |
| 797 | .channel_tile = 8, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 798 | }; |
Marat Dukhan | c07cb7f | 2019-11-14 15:32:05 -0800 | [diff] [blame] | 799 | xnn_params.f32.vadd = (xnn_vadd_ukernel_function) xnn_f32_vadd_ukernel__sse_x8; |
Marat Dukhan | 1e782c4 | 2019-11-21 17:02:40 -0800 | [diff] [blame] | 800 | xnn_params.f32.vmul = (struct vbinary_parameters) { |
| 801 | .op_ukernel = (xnn_vbinary_ukernel_function) xnn_f32_vmul_ukernel__sse_x8, |
| 802 | .opc_ukernel = (xnn_vbinary_ukernel_function) xnn_f32_vmulc_ukernel__sse_x8, |
| 803 | .ropc_ukernel = (xnn_vbinary_ukernel_function) xnn_f32_vmulc_ukernel__sse_x8, |
Marat Dukhan | ca2733c | 2019-11-15 23:21:17 -0800 | [diff] [blame] | 804 | .element_tile = 8, |
| 805 | }; |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 806 | xnn_params.f32.vmulcaddc = (struct vmulcaddc_parameters) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 807 | .ukernel = (xnn_vmulcaddc_ukernel_function) xnn_f32_vmulcaddc_ukernel_c4__sse_2x, |
| 808 | .channel_tile = 4, |
| 809 | .row_tile = 2, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 810 | }; |
Marat Dukhan | efc47b8 | 2019-11-18 09:25:38 -0800 | [diff] [blame] | 811 | #ifndef XNN_NO_NCHW_OPERATORS |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 812 | xnn_params.f32.spmm = (struct spmm_parameters) { |
| 813 | .ukernel = (xnn_spmm_ukernel_function) xnn_f32_spmm_ukernel_4x1__sse, |
| 814 | .mr = 4, |
| 815 | .nr = 1, |
| 816 | }; |
| 817 | xnn_params.f32.spchw_dwconv3x3 = (struct spchw_dwconv_parameters) { |
| 818 | .ukernel = (xnn_dwconv_spchw_ukernel_function) xnn_f32_dwconv_spchw_ukernel_3x3p1__sse, |
| 819 | .input_width_tile = 4, |
| 820 | .output_width_tile = 4, |
| 821 | .output_height_tile = 1, |
| 822 | }; |
| 823 | xnn_params.f32.spchw_dwconv3x3s2 = (struct spchw_dwconv_parameters) { |
| 824 | .ukernel = (xnn_dwconv_spchw_ukernel_function) xnn_f32_dwconv_spchw_ukernel_3x3s2p1__sse, |
| 825 | .input_width_tile = 4, |
| 826 | .output_width_tile = 4, |
| 827 | .output_height_tile = 1, |
| 828 | }; |
| 829 | xnn_params.f32.spchw_gavgpool = (struct spchw_gavgpool_parameters) { |
| 830 | .ukernel = (xnn_gavgpool_spchw_ukernel_function) xnn_f32_gavgpool_spchw_ukernel__sse_x4, |
| 831 | .channel_tile = 4, |
| 832 | }; |
Marat Dukhan | efc47b8 | 2019-11-18 09:25:38 -0800 | [diff] [blame] | 833 | #endif // XNN_NO_NCHW_OPERATORS |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 834 | #endif // XNN_NO_F32_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 835 | |
| 836 | /**************************** X32 micro-kernels ****************************/ |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 837 | #ifndef XNN_NO_X32_OPERATORS |
| 838 | xnn_params.x32.pad = (struct pad_parameters) { |
| 839 | .ukernel = xnn_x32_pad_x2__sse2, |
| 840 | .mr = 2, |
| 841 | }; |
| 842 | xnn_params.x32.unpool = (xnn_unpool_ukernel_function) xnn_x32_unpool_ukernel__psimd; |
| 843 | xnn_params.x32.zip = (struct zip_parameters) { |
| 844 | .x2 = (xnn_zipc_ukernel_function) xnn_x32_zip_x2_ukernel__sse2, |
| 845 | .x3 = (xnn_zipc_ukernel_function) xnn_x32_zip_x3_ukernel__sse2, |
| 846 | .x4 = (xnn_zipc_ukernel_function) xnn_x32_zip_x4_ukernel__sse2, |
| 847 | .xm = (xnn_zipv_ukernel_function) xnn_x32_zip_xm_ukernel__sse2, |
| 848 | }; |
| 849 | #endif // XNN_NO_X32_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 850 | |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 851 | #elif XNN_ARCH_PNACL || XNN_ARCH_WASMSIMD |
Marat Dukhan | 466b523 | 2019-10-09 11:22:20 -0700 | [diff] [blame] | 852 | // Unlike most other architectures, on x86/x86-64 when floating-point instructions |
| 853 | // have no NaN arguments, but produce NaN output, the output NaN has sign bit set. |
| 854 | // We use it to distinguish x86/x86-64 from other architectures, by doing subtraction |
| 855 | // of two infinities (must produce NaN per IEEE 754 standard). |
| 856 | static volatile uint32_t minus_inf = UINT32_C(0xFF800000); |
| 857 | const bool is_wasm_x86 = (int32_t) xnn_stub_wasm_f32_sub(minus_inf, minus_inf) < 0; |
| 858 | |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 859 | /**************************** Q8 micro-kernels ****************************/ |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 860 | #ifndef XNN_NO_Q8_OPERATORS |
| 861 | xnn_params.q8.gemm = (struct gemm_parameters) { |
| 862 | .gemm = (xnn_gemm_ukernel_function) xnn_q8_gemm_ukernel_2x2__scalar, |
| 863 | .igemm = (xnn_igemm_ukernel_function) xnn_q8_igemm_ukernel_2x2__scalar, |
| 864 | .mr = 2, |
| 865 | .nr = 2, |
| 866 | }; |
| 867 | xnn_params.q8.dwconv[0] = (struct dwconv_parameters) { |
| 868 | .up = (xnn_dwconv_up_ukernel_function) xnn_q8_dwconv_ukernel_up1x9__scalar, |
| 869 | .cr = 1, |
| 870 | .mr = 9, |
| 871 | }; |
| 872 | xnn_params.q8.avgpool = (struct avgpool_parameters) { |
| 873 | .up = (xnn_avgpool_up_ukernel_function) xnn_q8_avgpool_ukernel_up9__scalar, |
| 874 | .mp = (xnn_avgpool_mp_ukernel_function) xnn_q8_avgpool_ukernel_mp9p8q__scalar, |
| 875 | .mr = 9, |
| 876 | .qr = 8, |
| 877 | }; |
| 878 | xnn_params.q8.gavgpool = (struct gavgpool_parameters) { |
| 879 | .up = (xnn_gavgpool_up_ukernel_function) xnn_q8_gavgpool_ukernel_up7__scalar, |
| 880 | .mp = (xnn_gavgpool_mp_ukernel_function) xnn_q8_gavgpool_ukernel_mp7p7q__scalar, |
| 881 | .mr = 7, |
| 882 | }; |
| 883 | xnn_params.q8.vadd = (xnn_vadd_ukernel_function) xnn_q8_vadd_ukernel__scalar; |
| 884 | #endif // XNN_NO_Q8_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 885 | |
| 886 | /**************************** U8 micro-kernels ****************************/ |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 887 | #ifndef XNN_NO_U8_OPERATORS |
| 888 | xnn_params.u8.maxpool = (struct maxpool_parameters) { |
Marat Dukhan | 329da64 | 2019-11-19 21:44:39 -0800 | [diff] [blame] | 889 | .ukernel = (xnn_maxpool_ukernel_function) xnn_u8_maxpool_ukernel_9p8x__scalar_c1, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 890 | .mr = 9, |
| 891 | .qr = 8, |
| 892 | }; |
| 893 | xnn_params.u8.clamp = (xnn_univector_ukernel_function) xnn_u8_clamp_ukernel__scalar; |
| 894 | xnn_params.u8.lut32norm = xnn_u8_lut32norm_ukernel__scalar; |
| 895 | xnn_params.u8.rmax = xnn_u8_rmax_ukernel__scalar; |
| 896 | #endif // XNN_NO_U8_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 897 | |
| 898 | /**************************** X8 micro-kernels ****************************/ |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 899 | #ifndef XNN_NO_X8_OPERATORS |
| 900 | xnn_params.x8.lut = xnn_x8_lut_ukernel__scalar; |
| 901 | xnn_params.x8.zip = (struct zip_parameters) { |
| 902 | .x2 = (xnn_zipc_ukernel_function) xnn_x8_zip_x2_ukernel__scalar, |
| 903 | .x3 = (xnn_zipc_ukernel_function) xnn_x8_zip_x3_ukernel__scalar, |
| 904 | .x4 = (xnn_zipc_ukernel_function) xnn_x8_zip_x4_ukernel__scalar, |
| 905 | .xm = (xnn_zipv_ukernel_function) xnn_x8_zip_xm_ukernel__scalar, |
| 906 | }; |
| 907 | #endif // XNN_NO_X8_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 908 | |
| 909 | /**************************** F32 micro-kernels ****************************/ |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 910 | #ifndef XNN_NO_F32_OPERATORS |
| 911 | if (is_wasm_x86) { |
| 912 | xnn_params.f32.gemm = (struct gemm_parameters) { |
Marat Dukhan | cb80197 | 2019-10-23 02:10:33 -0700 | [diff] [blame] | 913 | .gemm = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_4x8__psimd_splat, |
| 914 | .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_4x8__psimd_splat, |
| 915 | .gemm1 = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_1x8__psimd_splat, |
| 916 | .igemm1 = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_1x8__psimd_splat, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 917 | .mr = 4, |
| 918 | .nr = 8, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 919 | }; |
| 920 | } else { |
| 921 | xnn_params.f32.gemm = (struct gemm_parameters) { |
Marat Dukhan | cd945c6 | 2019-10-25 11:59:50 -0700 | [diff] [blame] | 922 | .gemm = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_6x8s4__psimd, |
| 923 | .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_6x8s4__psimd, |
| 924 | .gemm1 = (xnn_gemm_ukernel_function) xnn_f32_igemm_ukernel_1x8s4__psimd, |
| 925 | .igemm1 = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_1x8s4__psimd, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 926 | .mr = 6, |
| 927 | .nr = 8, |
Marat Dukhan | cd945c6 | 2019-10-25 11:59:50 -0700 | [diff] [blame] | 928 | .log2_sr = 2, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 929 | }; |
| 930 | } |
| 931 | xnn_params.f32.gemm2 = (struct gemm_parameters) { |
| 932 | .gemm = NULL, |
| 933 | .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_4x2c4__psimd, |
Marat Dukhan | 466b523 | 2019-10-09 11:22:20 -0700 | [diff] [blame] | 934 | .mr = 4, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 935 | .nr = 2, |
| 936 | .log2_kr = 2, |
Marat Dukhan | 466b523 | 2019-10-09 11:22:20 -0700 | [diff] [blame] | 937 | }; |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 938 | xnn_params.f32.dwconv[0] = (struct dwconv_parameters) { |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 939 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up4x4__psimd_acc2, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 940 | .cr = 4, |
| 941 | .mr = 4, |
Marat Dukhan | 466b523 | 2019-10-09 11:22:20 -0700 | [diff] [blame] | 942 | }; |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 943 | xnn_params.f32.dwconv[1] = (struct dwconv_parameters) { |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 944 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up4x9__psimd_acc2, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 945 | .cr = 4, |
| 946 | .mr = 9, |
| 947 | }; |
| 948 | xnn_params.f32.dwconv[2] = (struct dwconv_parameters) { |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 949 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up4x25__psimd_acc2, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 950 | .cr = 4, |
| 951 | .mr = 25, |
| 952 | }; |
| 953 | xnn_params.f32.avgpool = (struct avgpool_parameters) { |
| 954 | .up = (xnn_avgpool_up_ukernel_function) xnn_f32_avgpool_ukernel_up9__psimd, |
| 955 | .mp = (xnn_avgpool_mp_ukernel_function) xnn_f32_avgpool_ukernel_mp9p8q__psimd, |
| 956 | .mr = 9, |
| 957 | .qr = 8, |
| 958 | }; |
| 959 | xnn_params.f32.pavgpool = (struct pavgpool_parameters) { |
| 960 | .up = (xnn_pavgpool_up_ukernel_function) xnn_f32_pavgpool_ukernel_up9__psimd, |
| 961 | .mp = (xnn_pavgpool_mp_ukernel_function) xnn_f32_pavgpool_ukernel_mp9p8q__psimd, |
| 962 | .mr = 9, |
| 963 | .qr = 8, |
| 964 | }; |
| 965 | xnn_params.f32.gavgpool = (struct gavgpool_parameters) { |
| 966 | .up = (xnn_gavgpool_up_ukernel_function) xnn_f32_gavgpool_ukernel_up7__psimd, |
| 967 | .mp = (xnn_gavgpool_mp_ukernel_function) xnn_f32_gavgpool_ukernel_mp7p7q__psimd, |
| 968 | .mr = 7, |
| 969 | }; |
| 970 | xnn_params.f32.maxpool = (struct maxpool_parameters) { |
Marat Dukhan | 329da64 | 2019-11-19 21:44:39 -0800 | [diff] [blame] | 971 | .ukernel = (xnn_maxpool_ukernel_function) xnn_f32_maxpool_ukernel_9p8x__psimd_c4, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 972 | .mr = 9, |
| 973 | .qr = 8, |
| 974 | }; |
| 975 | xnn_params.f32.argmaxpool[0] = (struct argmaxpool_parameters) { |
Marat Dukhan | 329da64 | 2019-11-19 21:44:39 -0800 | [diff] [blame] | 976 | .up = (xnn_argmaxpool_up_ukernel_function) xnn_f32_argmaxpool_ukernel_4x__psimd_c4, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 977 | .mr = 4, |
| 978 | }; |
| 979 | xnn_params.f32.argmaxpool[1] = (struct argmaxpool_parameters) { |
Marat Dukhan | 329da64 | 2019-11-19 21:44:39 -0800 | [diff] [blame] | 980 | .up = (xnn_argmaxpool_up_ukernel_function) xnn_f32_argmaxpool_ukernel_9x__psimd_c4, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 981 | .mr = 9, |
| 982 | }; |
| 983 | xnn_params.f32.argmaxpool[2] = (struct argmaxpool_parameters) { |
Marat Dukhan | 329da64 | 2019-11-19 21:44:39 -0800 | [diff] [blame] | 984 | .mp = (xnn_argmaxpool_mp_ukernel_function) xnn_f32_argmaxpool_ukernel_9p8x__psimd_c4, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 985 | .mr = 9, |
| 986 | .qr = 8, |
| 987 | }; |
Marat Dukhan | 6972249 | 2019-11-11 19:55:50 -0800 | [diff] [blame] | 988 | xnn_params.f32.bilinear = (struct bilinear_parameters) { |
| 989 | .ukernel = (xnn_bilinear_ukernel_function) xnn_f32_bilinear_ukernel__psimd_c8, |
| 990 | .pixel_tile = 1, |
| 991 | .channel_tile = 8, |
| 992 | }; |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 993 | xnn_params.f32.clamp = (xnn_univector_ukernel_function) xnn_f32_clamp_ukernel__psimd; |
| 994 | xnn_params.f32.hswish = (xnn_univector_ukernel_function) xnn_f32_hswish_ukernel__psimd; |
| 995 | xnn_params.f32.prelu = (struct prelu_parameters) { |
Marat Dukhan | 69c3f2c | 2019-11-06 12:30:01 -0800 | [diff] [blame] | 996 | .ukernel = (xnn_prelu_ukernel_function) xnn_f32_prelu_ukernel__psimd_2x8, |
| 997 | .row_tile = 2, |
| 998 | .channel_tile = 8, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 999 | }; |
Marat Dukhan | c07cb7f | 2019-11-14 15:32:05 -0800 | [diff] [blame] | 1000 | xnn_params.f32.vadd = (xnn_vadd_ukernel_function) xnn_f32_vadd_ukernel__psimd_x8; |
Marat Dukhan | 1e782c4 | 2019-11-21 17:02:40 -0800 | [diff] [blame] | 1001 | xnn_params.f32.vmul = (struct vbinary_parameters) { |
| 1002 | .op_ukernel = (xnn_vbinary_ukernel_function) xnn_f32_vmul_ukernel__psimd_x8, |
| 1003 | .opc_ukernel = (xnn_vbinary_ukernel_function) xnn_f32_vmulc_ukernel__psimd_x8, |
| 1004 | .ropc_ukernel = (xnn_vbinary_ukernel_function) xnn_f32_vmulc_ukernel__psimd_x8, |
Marat Dukhan | ca2733c | 2019-11-15 23:21:17 -0800 | [diff] [blame] | 1005 | .element_tile = 8, |
| 1006 | }; |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 1007 | xnn_params.f32.vmulcaddc = (struct vmulcaddc_parameters) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1008 | .ukernel = (xnn_vmulcaddc_ukernel_function) xnn_f32_vmulcaddc_ukernel_c4__psimd_2x, |
| 1009 | .channel_tile = 4, |
| 1010 | .row_tile = 2, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 1011 | }; |
| 1012 | #endif // XNN_NO_F32_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1013 | |
| 1014 | /**************************** X32 micro-kernels ****************************/ |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 1015 | #ifndef XNN_NO_X32_OPERATORS |
| 1016 | xnn_params.x32.pad = (struct pad_parameters) { |
| 1017 | .ukernel = xnn_x32_pad_x2__psimd, |
| 1018 | .mr = 2, |
| 1019 | }; |
| 1020 | xnn_params.x32.unpool = (xnn_unpool_ukernel_function) xnn_x32_unpool_ukernel__psimd; |
| 1021 | xnn_params.x32.zip = (struct zip_parameters) { |
| 1022 | .x2 = (xnn_zipc_ukernel_function) xnn_x32_zip_x2_ukernel__psimd, |
| 1023 | .x3 = (xnn_zipc_ukernel_function) xnn_x32_zip_x3_ukernel__psimd, |
| 1024 | .x4 = (xnn_zipc_ukernel_function) xnn_x32_zip_x4_ukernel__psimd, |
| 1025 | .xm = (xnn_zipv_ukernel_function) xnn_x32_zip_xm_ukernel__psimd, |
| 1026 | }; |
| 1027 | #endif // XNN_NO_X32_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1028 | |
Marat Dukhan | 1dadbf7 | 2019-10-01 10:46:20 -0700 | [diff] [blame] | 1029 | #elif XNN_ARCH_WASM || XNN_ARCH_ASMJS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1030 | // Unlike most other architectures, on x86/x86-64 when floating-point instructions |
| 1031 | // have no NaN arguments, but produce NaN output, the output NaN has sign bit set. |
| 1032 | // We use it to distinguish x86/x86-64 from other architectures, by doing subtraction |
| 1033 | // of two infinities (must produce NaN per IEEE 754 standard). |
| 1034 | static volatile uint32_t minus_inf = UINT32_C(0xFF800000); |
| 1035 | const bool is_wasm_x86 = (int32_t) xnn_stub_wasm_f32_sub(minus_inf, minus_inf) < 0; |
| 1036 | |
| 1037 | /**************************** Q8 micro-kernels ****************************/ |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 1038 | #ifndef XNN_NO_Q8_OPERATORS |
| 1039 | xnn_params.q8.gemm = (struct gemm_parameters) { |
| 1040 | .gemm = (xnn_gemm_ukernel_function) xnn_q8_gemm_ukernel_2x2__scalar, |
| 1041 | .igemm = (xnn_igemm_ukernel_function) xnn_q8_igemm_ukernel_2x2__scalar, |
| 1042 | .mr = 2, |
| 1043 | .nr = 2, |
| 1044 | }; |
| 1045 | xnn_params.q8.dwconv[0] = (struct dwconv_parameters) { |
| 1046 | .up = (xnn_dwconv_up_ukernel_function) xnn_q8_dwconv_ukernel_up1x9__scalar, |
| 1047 | .cr = 1, |
| 1048 | .mr = 9, |
| 1049 | }; |
| 1050 | xnn_params.q8.avgpool = (struct avgpool_parameters) { |
| 1051 | .up = (xnn_avgpool_up_ukernel_function) xnn_q8_avgpool_ukernel_up9__scalar, |
| 1052 | .mp = (xnn_avgpool_mp_ukernel_function) xnn_q8_avgpool_ukernel_mp9p8q__scalar, |
| 1053 | .mr = 9, |
| 1054 | .qr = 8, |
| 1055 | }; |
| 1056 | xnn_params.q8.gavgpool = (struct gavgpool_parameters) { |
| 1057 | .up = (xnn_gavgpool_up_ukernel_function) xnn_q8_gavgpool_ukernel_up7__scalar, |
| 1058 | .mp = (xnn_gavgpool_mp_ukernel_function) xnn_q8_gavgpool_ukernel_mp7p7q__scalar, |
| 1059 | .mr = 7, |
| 1060 | }; |
| 1061 | xnn_params.q8.vadd = (xnn_vadd_ukernel_function) xnn_q8_vadd_ukernel__scalar; |
| 1062 | #endif // XNN_NO_Q8_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1063 | |
| 1064 | /**************************** U8 micro-kernels ****************************/ |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 1065 | #ifndef XNN_NO_U8_OPERATORS |
| 1066 | xnn_params.u8.maxpool = (struct maxpool_parameters) { |
Marat Dukhan | 329da64 | 2019-11-19 21:44:39 -0800 | [diff] [blame] | 1067 | .ukernel = (xnn_maxpool_ukernel_function) xnn_u8_maxpool_ukernel_9p8x__scalar_c1, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 1068 | .mr = 9, |
| 1069 | .qr = 8, |
| 1070 | }; |
| 1071 | xnn_params.u8.clamp = (xnn_univector_ukernel_function) xnn_u8_clamp_ukernel__scalar; |
| 1072 | xnn_params.u8.lut32norm = xnn_u8_lut32norm_ukernel__scalar; |
| 1073 | xnn_params.u8.rmax = xnn_u8_rmax_ukernel__scalar; |
| 1074 | #endif // XNN_NO_U8_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1075 | |
| 1076 | /**************************** X8 micro-kernels ****************************/ |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 1077 | #ifndef XNN_NO_X8_OPERATORS |
| 1078 | xnn_params.x8.lut = xnn_x8_lut_ukernel__scalar; |
| 1079 | xnn_params.x8.zip = (struct zip_parameters) { |
| 1080 | .x2 = (xnn_zipc_ukernel_function) xnn_x8_zip_x2_ukernel__scalar, |
| 1081 | .x3 = (xnn_zipc_ukernel_function) xnn_x8_zip_x3_ukernel__scalar, |
| 1082 | .x4 = (xnn_zipc_ukernel_function) xnn_x8_zip_x4_ukernel__scalar, |
| 1083 | .xm = (xnn_zipv_ukernel_function) xnn_x8_zip_xm_ukernel__scalar, |
| 1084 | }; |
| 1085 | #endif // XNN_NO_X8_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1086 | |
| 1087 | /**************************** F32 micro-kernels ****************************/ |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 1088 | #ifndef XNN_NO_F32_OPERATORS |
| 1089 | if (is_wasm_x86) { |
| 1090 | xnn_params.f32.gemm = (struct gemm_parameters) { |
| 1091 | .gemm = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_2x4__scalar, |
| 1092 | .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_2x4__scalar, |
| 1093 | .gemm1 = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_1x4__scalar, |
| 1094 | .igemm1 = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_1x4__scalar, |
| 1095 | .mr = 2, |
| 1096 | .nr = 4, |
| 1097 | }; |
| 1098 | } else { |
| 1099 | xnn_params.f32.gemm = (struct gemm_parameters) { |
| 1100 | .gemm = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_4x4__scalar, |
| 1101 | .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_4x4__scalar, |
| 1102 | .gemm1 = (xnn_gemm_ukernel_function) xnn_f32_gemm_ukernel_1x4__scalar, |
| 1103 | .igemm1 = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_1x4__scalar, |
| 1104 | .mr = 4, |
| 1105 | .nr = 4, |
| 1106 | }; |
| 1107 | } |
| 1108 | xnn_params.f32.gemm2 = (struct gemm_parameters) { |
| 1109 | .gemm = NULL, |
| 1110 | .igemm = (xnn_igemm_ukernel_function) xnn_f32_igemm_ukernel_4x2__scalar, |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1111 | .mr = 4, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 1112 | .nr = 2, |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1113 | }; |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 1114 | xnn_params.f32.dwconv[0] = (struct dwconv_parameters) { |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 1115 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up1x4__scalar_acc2, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 1116 | .cr = 1, |
| 1117 | .mr = 4, |
| 1118 | }; |
| 1119 | xnn_params.f32.dwconv[1] = (struct dwconv_parameters) { |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 1120 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up1x9__scalar_acc2, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 1121 | .cr = 1, |
| 1122 | .mr = 9, |
| 1123 | }; |
| 1124 | xnn_params.f32.dwconv[2] = (struct dwconv_parameters) { |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 1125 | .up = (xnn_dwconv_up_ukernel_function) xnn_f32_dwconv_ukernel_up1x25__scalar_acc2, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 1126 | .cr = 1, |
| 1127 | .mr = 25, |
| 1128 | }; |
| 1129 | xnn_params.f32.avgpool = (struct avgpool_parameters) { |
| 1130 | .up = (xnn_avgpool_up_ukernel_function) xnn_f32_avgpool_ukernel_up9__scalar, |
| 1131 | .mp = (xnn_avgpool_mp_ukernel_function) xnn_f32_avgpool_ukernel_mp9p8q__scalar, |
| 1132 | .mr = 9, |
| 1133 | .qr = 8, |
| 1134 | }; |
| 1135 | xnn_params.f32.pavgpool = (struct pavgpool_parameters) { |
| 1136 | .up = (xnn_pavgpool_up_ukernel_function) xnn_f32_pavgpool_ukernel_up9__scalar, |
| 1137 | .mp = (xnn_pavgpool_mp_ukernel_function) xnn_f32_pavgpool_ukernel_mp9p8q__scalar, |
| 1138 | .mr = 9, |
| 1139 | .qr = 8, |
| 1140 | }; |
| 1141 | xnn_params.f32.gavgpool = (struct gavgpool_parameters) { |
| 1142 | .up = (xnn_gavgpool_up_ukernel_function) xnn_f32_gavgpool_ukernel_up7__scalar, |
| 1143 | .mp = (xnn_gavgpool_mp_ukernel_function) xnn_f32_gavgpool_ukernel_mp7p7q__scalar, |
| 1144 | .mr = 7, |
| 1145 | }; |
| 1146 | xnn_params.f32.maxpool = (struct maxpool_parameters) { |
Marat Dukhan | 329da64 | 2019-11-19 21:44:39 -0800 | [diff] [blame] | 1147 | .ukernel = (xnn_maxpool_ukernel_function) xnn_f32_maxpool_ukernel_9p8x__scalar_c1, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 1148 | .mr = 9, |
| 1149 | .qr = 8, |
| 1150 | }; |
| 1151 | xnn_params.f32.argmaxpool[0] = (struct argmaxpool_parameters) { |
Marat Dukhan | 329da64 | 2019-11-19 21:44:39 -0800 | [diff] [blame] | 1152 | .up = (xnn_argmaxpool_up_ukernel_function) xnn_f32_argmaxpool_ukernel_4x__scalar_c1, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 1153 | .mr = 4, |
| 1154 | }; |
| 1155 | xnn_params.f32.argmaxpool[1] = (struct argmaxpool_parameters) { |
Marat Dukhan | 329da64 | 2019-11-19 21:44:39 -0800 | [diff] [blame] | 1156 | .up = (xnn_argmaxpool_up_ukernel_function) xnn_f32_argmaxpool_ukernel_9x__scalar_c1, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 1157 | .mr = 9, |
| 1158 | }; |
| 1159 | xnn_params.f32.argmaxpool[2] = (struct argmaxpool_parameters) { |
Marat Dukhan | 329da64 | 2019-11-19 21:44:39 -0800 | [diff] [blame] | 1160 | .mp = (xnn_argmaxpool_mp_ukernel_function) xnn_f32_argmaxpool_ukernel_9p8x__scalar_c1, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 1161 | .mr = 9, |
| 1162 | .qr = 8, |
| 1163 | }; |
Marat Dukhan | 6972249 | 2019-11-11 19:55:50 -0800 | [diff] [blame] | 1164 | xnn_params.f32.bilinear = (struct bilinear_parameters) { |
| 1165 | .ukernel = (xnn_bilinear_ukernel_function) xnn_f32_bilinear_ukernel__scalar_c2, |
| 1166 | .pixel_tile = 1, |
| 1167 | .channel_tile = 2, |
| 1168 | }; |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 1169 | xnn_params.f32.clamp = (xnn_univector_ukernel_function) xnn_f32_clamp_ukernel__scalar; |
| 1170 | xnn_params.f32.hswish = (xnn_univector_ukernel_function) xnn_f32_hswish_ukernel__scalar; |
| 1171 | xnn_params.f32.prelu = (struct prelu_parameters) { |
Marat Dukhan | 69c3f2c | 2019-11-06 12:30:01 -0800 | [diff] [blame] | 1172 | .ukernel = (xnn_prelu_ukernel_function) xnn_f32_prelu_ukernel__scalar_2x4, |
| 1173 | .row_tile = 4, |
| 1174 | .channel_tile = 4, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 1175 | }; |
Marat Dukhan | c07cb7f | 2019-11-14 15:32:05 -0800 | [diff] [blame] | 1176 | xnn_params.f32.vadd = (xnn_vadd_ukernel_function) xnn_f32_vadd_ukernel__scalar_x4; |
Marat Dukhan | 1e782c4 | 2019-11-21 17:02:40 -0800 | [diff] [blame] | 1177 | xnn_params.f32.vmul = (struct vbinary_parameters) { |
| 1178 | .op_ukernel = (xnn_vbinary_ukernel_function) xnn_f32_vmul_ukernel__scalar_x4, |
| 1179 | .opc_ukernel = (xnn_vbinary_ukernel_function) xnn_f32_vmulc_ukernel__scalar_x4, |
| 1180 | .ropc_ukernel = (xnn_vbinary_ukernel_function) xnn_f32_vmulc_ukernel__scalar_x4, |
Marat Dukhan | ca2733c | 2019-11-15 23:21:17 -0800 | [diff] [blame] | 1181 | .element_tile = 8, |
| 1182 | }; |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 1183 | xnn_params.f32.vmulcaddc = (struct vmulcaddc_parameters) { |
Marat Dukhan | 49e6ee9 | 2019-11-06 15:55:29 -0800 | [diff] [blame] | 1184 | .ukernel = (xnn_vmulcaddc_ukernel_function) xnn_f32_vmulcaddc_ukernel_c1__scalar_2x, |
| 1185 | .channel_tile = 1, |
| 1186 | .row_tile = 2, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 1187 | }; |
Marat Dukhan | efc47b8 | 2019-11-18 09:25:38 -0800 | [diff] [blame] | 1188 | #ifndef XNN_NO_NCHW_OPERATORS |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 1189 | xnn_params.f32.spmm = (struct spmm_parameters) { |
Marat Dukhan | bff791e | 2019-10-24 11:05:37 -0700 | [diff] [blame] | 1190 | .ukernel = (xnn_spmm_ukernel_function) xnn_f32_spmm_ukernel_8x1__scalar, |
| 1191 | .mr = 8, |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 1192 | .nr = 1, |
| 1193 | }; |
Erich Elsen | c6afd9b | 2019-10-24 16:10:53 -0700 | [diff] [blame] | 1194 | xnn_params.f32.spmm2 = (struct spmm_parameters) { |
| 1195 | .ukernel = (xnn_spmm_ukernel_function) xnn_f32_spmm_ukernel_8x2__scalar, |
| 1196 | .mr = 8, |
| 1197 | .nr = 2, |
| 1198 | }; |
| 1199 | xnn_params.f32.spmm4 = (struct spmm_parameters) { |
| 1200 | .ukernel = (xnn_spmm_ukernel_function) xnn_f32_spmm_ukernel_8x4__scalar, |
| 1201 | .mr = 8, |
| 1202 | .nr = 4, |
| 1203 | }; |
Marat Dukhan | 14fe0b2 | 2019-10-23 21:20:07 -0700 | [diff] [blame] | 1204 | xnn_params.f32.hwc2spchw_dconv3x3c3s2 = (struct hwc2spchw_dconv_parameters) { |
| 1205 | .ukernel_with_symm_padding = |
| 1206 | (xnn_conv_hwc2spchw_ukernel_function) xnn_f32_conv_hwc2spchw_ukernel_3x3s2p1c3x4__scalar_1x1, |
| 1207 | .output_channel_tile = 4, |
| 1208 | .output_height_tile = 1, |
| 1209 | .output_width_tile = 1, |
| 1210 | }; |
| 1211 | xnn_params.f32.spchw_dwconv3x3 = (struct spchw_dwconv_parameters) { |
| 1212 | .ukernel = (xnn_dwconv_spchw_ukernel_function) xnn_f32_dwconv_spchw_ukernel_3x3p1__scalar, |
| 1213 | .input_width_tile = 1, |
| 1214 | .output_width_tile = 1, |
| 1215 | .output_height_tile = 1, |
| 1216 | }; |
| 1217 | xnn_params.f32.spchw_dwconv3x3s2 = (struct spchw_dwconv_parameters) { |
| 1218 | .ukernel = (xnn_dwconv_spchw_ukernel_function) xnn_f32_dwconv_spchw_ukernel_3x3s2p1__scalar, |
| 1219 | .input_width_tile = 1, |
| 1220 | .output_width_tile = 1, |
| 1221 | .output_height_tile = 1, |
| 1222 | }; |
Marat Dukhan | a99918a | 2019-11-15 14:40:12 -0800 | [diff] [blame] | 1223 | xnn_params.f32.spchw_dwconv5x5 = (struct spchw_dwconv_parameters) { |
| 1224 | .ukernel = (xnn_dwconv_spchw_ukernel_function) xnn_f32_dwconv_spchw_ukernel_5x5p2__scalar, |
| 1225 | .input_width_tile = 1, |
| 1226 | .output_width_tile = 1, |
| 1227 | .output_height_tile = 1, |
| 1228 | }; |
| 1229 | xnn_params.f32.spchw_dwconv5x5s2 = (struct spchw_dwconv_parameters) { |
| 1230 | .ukernel = (xnn_dwconv_spchw_ukernel_function) xnn_f32_dwconv_spchw_ukernel_5x5s2p2__scalar, |
| 1231 | .input_width_tile = 1, |
| 1232 | .output_width_tile = 1, |
| 1233 | .output_height_tile = 1, |
| 1234 | }; |
Marat Dukhan | 14fe0b2 | 2019-10-23 21:20:07 -0700 | [diff] [blame] | 1235 | xnn_params.f32.spchw_gavgpool = (struct spchw_gavgpool_parameters) { |
| 1236 | .ukernel = (xnn_gavgpool_spchw_ukernel_function) xnn_f32_gavgpool_spchw_ukernel__scalar_x1, |
| 1237 | .channel_tile = 1, |
| 1238 | }; |
Marat Dukhan | efc47b8 | 2019-11-18 09:25:38 -0800 | [diff] [blame] | 1239 | #endif // XNN_NO_NCHW_OPERATORS |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 1240 | #endif // XNN_NO_F32_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1241 | |
| 1242 | /**************************** X32 micro-kernels ****************************/ |
Marat Dukhan | 8fe54e4 | 2019-10-10 14:12:59 -0700 | [diff] [blame] | 1243 | #ifndef XNN_NO_X32_OPERATORS |
| 1244 | xnn_params.x32.pad = (struct pad_parameters) { |
| 1245 | .ukernel = xnn_x32_pad_x2__scalar, |
| 1246 | .mr = 2, |
| 1247 | }; |
| 1248 | xnn_params.x32.unpool = (xnn_unpool_ukernel_function) xnn_x32_unpool_ukernel__scalar; |
| 1249 | xnn_params.x32.zip = (struct zip_parameters) { |
| 1250 | .x2 = (xnn_zipc_ukernel_function) xnn_x32_zip_x2_ukernel__scalar, |
| 1251 | .x3 = (xnn_zipc_ukernel_function) xnn_x32_zip_x3_ukernel__scalar, |
| 1252 | .x4 = (xnn_zipc_ukernel_function) xnn_x32_zip_x4_ukernel__scalar, |
| 1253 | .xm = (xnn_zipv_ukernel_function) xnn_x32_zip_xm_ukernel__scalar, |
| 1254 | }; |
| 1255 | #endif // XNN_NO_X32_OPERATORS |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1256 | |
| 1257 | #else |
| 1258 | #error "Unsupported architecture" |
| 1259 | #endif |
| 1260 | xnn_params.initialized = true; |
| 1261 | } |
| 1262 | |
Marat Dukhan | 04f03be | 2019-11-19 12:36:47 -0800 | [diff] [blame] | 1263 | enum xnn_status xnn_initialize(const struct xnn_allocator* allocator) { |
Marat Dukhan | d343c22 | 2019-10-07 09:22:14 -0700 | [diff] [blame] | 1264 | #ifndef __EMSCRIPTEN__ |
| 1265 | if (!cpuinfo_initialize()) { |
| 1266 | return xnn_status_out_of_memory; |
| 1267 | } |
| 1268 | #endif |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1269 | pthread_once(&init_guard, &init); |
| 1270 | if (xnn_params.initialized) { |
Marat Dukhan | 04f03be | 2019-11-19 12:36:47 -0800 | [diff] [blame] | 1271 | if (allocator != NULL) { |
| 1272 | memcpy(&xnn_params.allocator, allocator, sizeof(struct xnn_allocator)); |
| 1273 | } else { |
| 1274 | xnn_params.allocator.allocate = &xnn_allocate; |
| 1275 | xnn_params.allocator.reallocate = &xnn_reallocate; |
| 1276 | xnn_params.allocator.deallocate = &xnn_deallocate; |
| 1277 | xnn_params.allocator.aligned_allocate = &xnn_aligned_allocate; |
| 1278 | xnn_params.allocator.aligned_deallocate = &xnn_aligned_deallocate; |
| 1279 | } |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1280 | return xnn_status_success; |
| 1281 | } else { |
| 1282 | return xnn_status_unsupported_hardware; |
| 1283 | } |
| 1284 | } |
| 1285 | |
| 1286 | enum xnn_status xnn_deinitialize(void) { |
Marat Dukhan | d343c22 | 2019-10-07 09:22:14 -0700 | [diff] [blame] | 1287 | #ifndef __EMSCRIPTEN__ |
| 1288 | cpuinfo_deinitialize(); |
| 1289 | #endif |
XNNPACK Team | b455b12 | 2019-09-27 18:10:33 -0700 | [diff] [blame] | 1290 | return xnn_status_success; |
| 1291 | } |