Marat Dukhan | d77f77d | 2021-10-24 15:39:59 -0700 | [diff] [blame] | 1 | // Copyright 2021 Google LLC |
| 2 | // |
| 3 | // This source code is licensed under the BSD-style license found in the |
| 4 | // LICENSE file in the root directory of this source tree. |
| 5 | // |
| 6 | // Auto-generated file. Do not edit! |
| 7 | // Specification: test/f32-f16-vcvt.yaml |
| 8 | // Generator: tools/generate-vcvt-test.py |
| 9 | |
| 10 | |
| 11 | #include <gtest/gtest.h> |
| 12 | |
| 13 | #include <xnnpack/common.h> |
| 14 | #include <xnnpack/isa-checks.h> |
| 15 | |
| 16 | #include <xnnpack/vcvt.h> |
| 17 | #include "vcvt-microkernel-tester.h" |
| 18 | |
| 19 | |
| 20 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | 4edfdbf | 2021-11-09 13:47:11 -0800 | [diff] [blame] | 21 | TEST(F32_F16_VCVT__NEON_X8, batch_eq_8) { |
| 22 | TEST_REQUIRES_ARM_NEON; |
| 23 | VCvtMicrokernelTester() |
| 24 | .batch_size(8) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 25 | .Test(xnn_f32_f16_vcvt_ukernel__neon_x8, xnn_init_f32_f16_cvt_neon_params); |
Marat Dukhan | 4edfdbf | 2021-11-09 13:47:11 -0800 | [diff] [blame] | 26 | } |
| 27 | |
| 28 | TEST(F32_F16_VCVT__NEON_X8, batch_div_8) { |
| 29 | TEST_REQUIRES_ARM_NEON; |
| 30 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 31 | VCvtMicrokernelTester() |
| 32 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 33 | .Test(xnn_f32_f16_vcvt_ukernel__neon_x8, xnn_init_f32_f16_cvt_neon_params); |
Marat Dukhan | 4edfdbf | 2021-11-09 13:47:11 -0800 | [diff] [blame] | 34 | } |
| 35 | } |
| 36 | |
| 37 | TEST(F32_F16_VCVT__NEON_X8, batch_lt_8) { |
| 38 | TEST_REQUIRES_ARM_NEON; |
| 39 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 40 | VCvtMicrokernelTester() |
| 41 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 42 | .Test(xnn_f32_f16_vcvt_ukernel__neon_x8, xnn_init_f32_f16_cvt_neon_params); |
Marat Dukhan | 4edfdbf | 2021-11-09 13:47:11 -0800 | [diff] [blame] | 43 | } |
| 44 | } |
| 45 | |
| 46 | TEST(F32_F16_VCVT__NEON_X8, batch_gt_8) { |
| 47 | TEST_REQUIRES_ARM_NEON; |
| 48 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 49 | VCvtMicrokernelTester() |
| 50 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 51 | .Test(xnn_f32_f16_vcvt_ukernel__neon_x8, xnn_init_f32_f16_cvt_neon_params); |
Marat Dukhan | 4edfdbf | 2021-11-09 13:47:11 -0800 | [diff] [blame] | 52 | } |
| 53 | } |
| 54 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 55 | |
| 56 | |
| 57 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 58 | TEST(F32_F16_VCVT__NEON_X16, batch_eq_16) { |
| 59 | TEST_REQUIRES_ARM_NEON; |
| 60 | VCvtMicrokernelTester() |
| 61 | .batch_size(16) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 62 | .Test(xnn_f32_f16_vcvt_ukernel__neon_x16, xnn_init_f32_f16_cvt_neon_params); |
Marat Dukhan | 4edfdbf | 2021-11-09 13:47:11 -0800 | [diff] [blame] | 63 | } |
| 64 | |
| 65 | TEST(F32_F16_VCVT__NEON_X16, batch_div_16) { |
| 66 | TEST_REQUIRES_ARM_NEON; |
| 67 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 68 | VCvtMicrokernelTester() |
| 69 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 70 | .Test(xnn_f32_f16_vcvt_ukernel__neon_x16, xnn_init_f32_f16_cvt_neon_params); |
Marat Dukhan | 4edfdbf | 2021-11-09 13:47:11 -0800 | [diff] [blame] | 71 | } |
| 72 | } |
| 73 | |
| 74 | TEST(F32_F16_VCVT__NEON_X16, batch_lt_16) { |
| 75 | TEST_REQUIRES_ARM_NEON; |
| 76 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 77 | VCvtMicrokernelTester() |
| 78 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 79 | .Test(xnn_f32_f16_vcvt_ukernel__neon_x16, xnn_init_f32_f16_cvt_neon_params); |
Marat Dukhan | 4edfdbf | 2021-11-09 13:47:11 -0800 | [diff] [blame] | 80 | } |
| 81 | } |
| 82 | |
| 83 | TEST(F32_F16_VCVT__NEON_X16, batch_gt_16) { |
| 84 | TEST_REQUIRES_ARM_NEON; |
| 85 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 86 | VCvtMicrokernelTester() |
| 87 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 88 | .Test(xnn_f32_f16_vcvt_ukernel__neon_x16, xnn_init_f32_f16_cvt_neon_params); |
Marat Dukhan | 4edfdbf | 2021-11-09 13:47:11 -0800 | [diff] [blame] | 89 | } |
| 90 | } |
| 91 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 92 | |
| 93 | |
| 94 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 95 | TEST(F32_F16_VCVT__NEON_X24, batch_eq_24) { |
| 96 | TEST_REQUIRES_ARM_NEON; |
| 97 | VCvtMicrokernelTester() |
| 98 | .batch_size(24) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 99 | .Test(xnn_f32_f16_vcvt_ukernel__neon_x24, xnn_init_f32_f16_cvt_neon_params); |
Marat Dukhan | 4edfdbf | 2021-11-09 13:47:11 -0800 | [diff] [blame] | 100 | } |
| 101 | |
| 102 | TEST(F32_F16_VCVT__NEON_X24, batch_div_24) { |
| 103 | TEST_REQUIRES_ARM_NEON; |
| 104 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 105 | VCvtMicrokernelTester() |
| 106 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 107 | .Test(xnn_f32_f16_vcvt_ukernel__neon_x24, xnn_init_f32_f16_cvt_neon_params); |
Marat Dukhan | 4edfdbf | 2021-11-09 13:47:11 -0800 | [diff] [blame] | 108 | } |
| 109 | } |
| 110 | |
| 111 | TEST(F32_F16_VCVT__NEON_X24, batch_lt_24) { |
| 112 | TEST_REQUIRES_ARM_NEON; |
| 113 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 114 | VCvtMicrokernelTester() |
| 115 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 116 | .Test(xnn_f32_f16_vcvt_ukernel__neon_x24, xnn_init_f32_f16_cvt_neon_params); |
Marat Dukhan | 4edfdbf | 2021-11-09 13:47:11 -0800 | [diff] [blame] | 117 | } |
| 118 | } |
| 119 | |
| 120 | TEST(F32_F16_VCVT__NEON_X24, batch_gt_24) { |
| 121 | TEST_REQUIRES_ARM_NEON; |
| 122 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 123 | VCvtMicrokernelTester() |
| 124 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 125 | .Test(xnn_f32_f16_vcvt_ukernel__neon_x24, xnn_init_f32_f16_cvt_neon_params); |
Marat Dukhan | 4edfdbf | 2021-11-09 13:47:11 -0800 | [diff] [blame] | 126 | } |
| 127 | } |
| 128 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 129 | |
| 130 | |
| 131 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 132 | TEST(F32_F16_VCVT__NEON_X32, batch_eq_32) { |
| 133 | TEST_REQUIRES_ARM_NEON; |
| 134 | VCvtMicrokernelTester() |
| 135 | .batch_size(32) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 136 | .Test(xnn_f32_f16_vcvt_ukernel__neon_x32, xnn_init_f32_f16_cvt_neon_params); |
Marat Dukhan | 4edfdbf | 2021-11-09 13:47:11 -0800 | [diff] [blame] | 137 | } |
| 138 | |
| 139 | TEST(F32_F16_VCVT__NEON_X32, batch_div_32) { |
| 140 | TEST_REQUIRES_ARM_NEON; |
| 141 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 142 | VCvtMicrokernelTester() |
| 143 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 144 | .Test(xnn_f32_f16_vcvt_ukernel__neon_x32, xnn_init_f32_f16_cvt_neon_params); |
Marat Dukhan | 4edfdbf | 2021-11-09 13:47:11 -0800 | [diff] [blame] | 145 | } |
| 146 | } |
| 147 | |
| 148 | TEST(F32_F16_VCVT__NEON_X32, batch_lt_32) { |
| 149 | TEST_REQUIRES_ARM_NEON; |
| 150 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 151 | VCvtMicrokernelTester() |
| 152 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 153 | .Test(xnn_f32_f16_vcvt_ukernel__neon_x32, xnn_init_f32_f16_cvt_neon_params); |
Marat Dukhan | 4edfdbf | 2021-11-09 13:47:11 -0800 | [diff] [blame] | 154 | } |
| 155 | } |
| 156 | |
| 157 | TEST(F32_F16_VCVT__NEON_X32, batch_gt_32) { |
| 158 | TEST_REQUIRES_ARM_NEON; |
| 159 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 160 | VCvtMicrokernelTester() |
| 161 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 162 | .Test(xnn_f32_f16_vcvt_ukernel__neon_x32, xnn_init_f32_f16_cvt_neon_params); |
Marat Dukhan | 4edfdbf | 2021-11-09 13:47:11 -0800 | [diff] [blame] | 163 | } |
| 164 | } |
| 165 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 166 | |
| 167 | |
| 168 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | d77f77d | 2021-10-24 15:39:59 -0700 | [diff] [blame] | 169 | TEST(F32_F16_VCVT__NEONFP16_X8, batch_eq_8) { |
| 170 | TEST_REQUIRES_ARM_NEON_FP16; |
| 171 | VCvtMicrokernelTester() |
| 172 | .batch_size(8) |
| 173 | .Test(xnn_f32_f16_vcvt_ukernel__neonfp16_x8); |
| 174 | } |
| 175 | |
| 176 | TEST(F32_F16_VCVT__NEONFP16_X8, batch_div_8) { |
| 177 | TEST_REQUIRES_ARM_NEON_FP16; |
| 178 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 179 | VCvtMicrokernelTester() |
| 180 | .batch_size(batch_size) |
| 181 | .Test(xnn_f32_f16_vcvt_ukernel__neonfp16_x8); |
| 182 | } |
| 183 | } |
| 184 | |
| 185 | TEST(F32_F16_VCVT__NEONFP16_X8, batch_lt_8) { |
| 186 | TEST_REQUIRES_ARM_NEON_FP16; |
| 187 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 188 | VCvtMicrokernelTester() |
| 189 | .batch_size(batch_size) |
| 190 | .Test(xnn_f32_f16_vcvt_ukernel__neonfp16_x8); |
| 191 | } |
| 192 | } |
| 193 | |
| 194 | TEST(F32_F16_VCVT__NEONFP16_X8, batch_gt_8) { |
| 195 | TEST_REQUIRES_ARM_NEON_FP16; |
| 196 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 197 | VCvtMicrokernelTester() |
| 198 | .batch_size(batch_size) |
| 199 | .Test(xnn_f32_f16_vcvt_ukernel__neonfp16_x8); |
| 200 | } |
| 201 | } |
| 202 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 203 | |
| 204 | |
| 205 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 206 | TEST(F32_F16_VCVT__NEONFP16_X16, batch_eq_16) { |
| 207 | TEST_REQUIRES_ARM_NEON_FP16; |
| 208 | VCvtMicrokernelTester() |
| 209 | .batch_size(16) |
| 210 | .Test(xnn_f32_f16_vcvt_ukernel__neonfp16_x16); |
| 211 | } |
| 212 | |
| 213 | TEST(F32_F16_VCVT__NEONFP16_X16, batch_div_16) { |
| 214 | TEST_REQUIRES_ARM_NEON_FP16; |
| 215 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 216 | VCvtMicrokernelTester() |
| 217 | .batch_size(batch_size) |
| 218 | .Test(xnn_f32_f16_vcvt_ukernel__neonfp16_x16); |
| 219 | } |
| 220 | } |
| 221 | |
| 222 | TEST(F32_F16_VCVT__NEONFP16_X16, batch_lt_16) { |
| 223 | TEST_REQUIRES_ARM_NEON_FP16; |
| 224 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 225 | VCvtMicrokernelTester() |
| 226 | .batch_size(batch_size) |
| 227 | .Test(xnn_f32_f16_vcvt_ukernel__neonfp16_x16); |
| 228 | } |
| 229 | } |
| 230 | |
| 231 | TEST(F32_F16_VCVT__NEONFP16_X16, batch_gt_16) { |
| 232 | TEST_REQUIRES_ARM_NEON_FP16; |
| 233 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 234 | VCvtMicrokernelTester() |
| 235 | .batch_size(batch_size) |
| 236 | .Test(xnn_f32_f16_vcvt_ukernel__neonfp16_x16); |
| 237 | } |
| 238 | } |
| 239 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 240 | |
| 241 | |
| 242 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 243 | TEST(F32_F16_VCVT__SSE2_X8, batch_eq_8) { |
| 244 | TEST_REQUIRES_X86_SSE2; |
| 245 | VCvtMicrokernelTester() |
| 246 | .batch_size(8) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 247 | .Test(xnn_f32_f16_vcvt_ukernel__sse2_x8, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 248 | } |
| 249 | |
| 250 | TEST(F32_F16_VCVT__SSE2_X8, batch_div_8) { |
| 251 | TEST_REQUIRES_X86_SSE2; |
| 252 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 253 | VCvtMicrokernelTester() |
| 254 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 255 | .Test(xnn_f32_f16_vcvt_ukernel__sse2_x8, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 256 | } |
| 257 | } |
| 258 | |
| 259 | TEST(F32_F16_VCVT__SSE2_X8, batch_lt_8) { |
| 260 | TEST_REQUIRES_X86_SSE2; |
| 261 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 262 | VCvtMicrokernelTester() |
| 263 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 264 | .Test(xnn_f32_f16_vcvt_ukernel__sse2_x8, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 265 | } |
| 266 | } |
| 267 | |
| 268 | TEST(F32_F16_VCVT__SSE2_X8, batch_gt_8) { |
| 269 | TEST_REQUIRES_X86_SSE2; |
| 270 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 271 | VCvtMicrokernelTester() |
| 272 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 273 | .Test(xnn_f32_f16_vcvt_ukernel__sse2_x8, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 274 | } |
| 275 | } |
| 276 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 277 | |
| 278 | |
| 279 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 280 | TEST(F32_F16_VCVT__SSE2_X16, batch_eq_16) { |
| 281 | TEST_REQUIRES_X86_SSE2; |
| 282 | VCvtMicrokernelTester() |
| 283 | .batch_size(16) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 284 | .Test(xnn_f32_f16_vcvt_ukernel__sse2_x16, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 285 | } |
| 286 | |
| 287 | TEST(F32_F16_VCVT__SSE2_X16, batch_div_16) { |
| 288 | TEST_REQUIRES_X86_SSE2; |
| 289 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 290 | VCvtMicrokernelTester() |
| 291 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 292 | .Test(xnn_f32_f16_vcvt_ukernel__sse2_x16, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 293 | } |
| 294 | } |
| 295 | |
| 296 | TEST(F32_F16_VCVT__SSE2_X16, batch_lt_16) { |
| 297 | TEST_REQUIRES_X86_SSE2; |
| 298 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 299 | VCvtMicrokernelTester() |
| 300 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 301 | .Test(xnn_f32_f16_vcvt_ukernel__sse2_x16, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 302 | } |
| 303 | } |
| 304 | |
| 305 | TEST(F32_F16_VCVT__SSE2_X16, batch_gt_16) { |
| 306 | TEST_REQUIRES_X86_SSE2; |
| 307 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 308 | VCvtMicrokernelTester() |
| 309 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 310 | .Test(xnn_f32_f16_vcvt_ukernel__sse2_x16, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 311 | } |
| 312 | } |
| 313 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 314 | |
| 315 | |
| 316 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 317 | TEST(F32_F16_VCVT__SSE2_X24, batch_eq_24) { |
| 318 | TEST_REQUIRES_X86_SSE2; |
| 319 | VCvtMicrokernelTester() |
| 320 | .batch_size(24) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 321 | .Test(xnn_f32_f16_vcvt_ukernel__sse2_x24, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 322 | } |
| 323 | |
| 324 | TEST(F32_F16_VCVT__SSE2_X24, batch_div_24) { |
| 325 | TEST_REQUIRES_X86_SSE2; |
| 326 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 327 | VCvtMicrokernelTester() |
| 328 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 329 | .Test(xnn_f32_f16_vcvt_ukernel__sse2_x24, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 330 | } |
| 331 | } |
| 332 | |
| 333 | TEST(F32_F16_VCVT__SSE2_X24, batch_lt_24) { |
| 334 | TEST_REQUIRES_X86_SSE2; |
| 335 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 336 | VCvtMicrokernelTester() |
| 337 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 338 | .Test(xnn_f32_f16_vcvt_ukernel__sse2_x24, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 339 | } |
| 340 | } |
| 341 | |
| 342 | TEST(F32_F16_VCVT__SSE2_X24, batch_gt_24) { |
| 343 | TEST_REQUIRES_X86_SSE2; |
| 344 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 345 | VCvtMicrokernelTester() |
| 346 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 347 | .Test(xnn_f32_f16_vcvt_ukernel__sse2_x24, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 348 | } |
| 349 | } |
| 350 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 351 | |
| 352 | |
| 353 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 354 | TEST(F32_F16_VCVT__SSE2_X32, batch_eq_32) { |
| 355 | TEST_REQUIRES_X86_SSE2; |
| 356 | VCvtMicrokernelTester() |
| 357 | .batch_size(32) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 358 | .Test(xnn_f32_f16_vcvt_ukernel__sse2_x32, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 359 | } |
| 360 | |
| 361 | TEST(F32_F16_VCVT__SSE2_X32, batch_div_32) { |
| 362 | TEST_REQUIRES_X86_SSE2; |
| 363 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 364 | VCvtMicrokernelTester() |
| 365 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 366 | .Test(xnn_f32_f16_vcvt_ukernel__sse2_x32, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 367 | } |
| 368 | } |
| 369 | |
| 370 | TEST(F32_F16_VCVT__SSE2_X32, batch_lt_32) { |
| 371 | TEST_REQUIRES_X86_SSE2; |
| 372 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 373 | VCvtMicrokernelTester() |
| 374 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 375 | .Test(xnn_f32_f16_vcvt_ukernel__sse2_x32, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 376 | } |
| 377 | } |
| 378 | |
| 379 | TEST(F32_F16_VCVT__SSE2_X32, batch_gt_32) { |
| 380 | TEST_REQUIRES_X86_SSE2; |
| 381 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 382 | VCvtMicrokernelTester() |
| 383 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 384 | .Test(xnn_f32_f16_vcvt_ukernel__sse2_x32, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 385 | } |
| 386 | } |
| 387 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 388 | |
| 389 | |
| 390 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 391 | TEST(F32_F16_VCVT__SSE41_X8, batch_eq_8) { |
| 392 | TEST_REQUIRES_X86_SSE41; |
| 393 | VCvtMicrokernelTester() |
| 394 | .batch_size(8) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 395 | .Test(xnn_f32_f16_vcvt_ukernel__sse41_x8, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 396 | } |
| 397 | |
| 398 | TEST(F32_F16_VCVT__SSE41_X8, batch_div_8) { |
| 399 | TEST_REQUIRES_X86_SSE41; |
| 400 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 401 | VCvtMicrokernelTester() |
| 402 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 403 | .Test(xnn_f32_f16_vcvt_ukernel__sse41_x8, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 404 | } |
| 405 | } |
| 406 | |
| 407 | TEST(F32_F16_VCVT__SSE41_X8, batch_lt_8) { |
| 408 | TEST_REQUIRES_X86_SSE41; |
| 409 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 410 | VCvtMicrokernelTester() |
| 411 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 412 | .Test(xnn_f32_f16_vcvt_ukernel__sse41_x8, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 413 | } |
| 414 | } |
| 415 | |
| 416 | TEST(F32_F16_VCVT__SSE41_X8, batch_gt_8) { |
| 417 | TEST_REQUIRES_X86_SSE41; |
| 418 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 419 | VCvtMicrokernelTester() |
| 420 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 421 | .Test(xnn_f32_f16_vcvt_ukernel__sse41_x8, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 422 | } |
| 423 | } |
| 424 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 425 | |
| 426 | |
| 427 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 428 | TEST(F32_F16_VCVT__SSE41_X16, batch_eq_16) { |
| 429 | TEST_REQUIRES_X86_SSE41; |
| 430 | VCvtMicrokernelTester() |
| 431 | .batch_size(16) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 432 | .Test(xnn_f32_f16_vcvt_ukernel__sse41_x16, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 433 | } |
| 434 | |
| 435 | TEST(F32_F16_VCVT__SSE41_X16, batch_div_16) { |
| 436 | TEST_REQUIRES_X86_SSE41; |
| 437 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 438 | VCvtMicrokernelTester() |
| 439 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 440 | .Test(xnn_f32_f16_vcvt_ukernel__sse41_x16, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 441 | } |
| 442 | } |
| 443 | |
| 444 | TEST(F32_F16_VCVT__SSE41_X16, batch_lt_16) { |
| 445 | TEST_REQUIRES_X86_SSE41; |
| 446 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 447 | VCvtMicrokernelTester() |
| 448 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 449 | .Test(xnn_f32_f16_vcvt_ukernel__sse41_x16, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 450 | } |
| 451 | } |
| 452 | |
| 453 | TEST(F32_F16_VCVT__SSE41_X16, batch_gt_16) { |
| 454 | TEST_REQUIRES_X86_SSE41; |
| 455 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 456 | VCvtMicrokernelTester() |
| 457 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 458 | .Test(xnn_f32_f16_vcvt_ukernel__sse41_x16, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 459 | } |
| 460 | } |
| 461 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 462 | |
| 463 | |
| 464 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 465 | TEST(F32_F16_VCVT__SSE41_X24, batch_eq_24) { |
| 466 | TEST_REQUIRES_X86_SSE41; |
| 467 | VCvtMicrokernelTester() |
| 468 | .batch_size(24) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 469 | .Test(xnn_f32_f16_vcvt_ukernel__sse41_x24, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 470 | } |
| 471 | |
| 472 | TEST(F32_F16_VCVT__SSE41_X24, batch_div_24) { |
| 473 | TEST_REQUIRES_X86_SSE41; |
| 474 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 475 | VCvtMicrokernelTester() |
| 476 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 477 | .Test(xnn_f32_f16_vcvt_ukernel__sse41_x24, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 478 | } |
| 479 | } |
| 480 | |
| 481 | TEST(F32_F16_VCVT__SSE41_X24, batch_lt_24) { |
| 482 | TEST_REQUIRES_X86_SSE41; |
| 483 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 484 | VCvtMicrokernelTester() |
| 485 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 486 | .Test(xnn_f32_f16_vcvt_ukernel__sse41_x24, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 487 | } |
| 488 | } |
| 489 | |
| 490 | TEST(F32_F16_VCVT__SSE41_X24, batch_gt_24) { |
| 491 | TEST_REQUIRES_X86_SSE41; |
| 492 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 493 | VCvtMicrokernelTester() |
| 494 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 495 | .Test(xnn_f32_f16_vcvt_ukernel__sse41_x24, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 496 | } |
| 497 | } |
| 498 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 499 | |
| 500 | |
| 501 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 502 | TEST(F32_F16_VCVT__SSE41_X32, batch_eq_32) { |
| 503 | TEST_REQUIRES_X86_SSE41; |
| 504 | VCvtMicrokernelTester() |
| 505 | .batch_size(32) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 506 | .Test(xnn_f32_f16_vcvt_ukernel__sse41_x32, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 507 | } |
| 508 | |
| 509 | TEST(F32_F16_VCVT__SSE41_X32, batch_div_32) { |
| 510 | TEST_REQUIRES_X86_SSE41; |
| 511 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 512 | VCvtMicrokernelTester() |
| 513 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 514 | .Test(xnn_f32_f16_vcvt_ukernel__sse41_x32, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 515 | } |
| 516 | } |
| 517 | |
| 518 | TEST(F32_F16_VCVT__SSE41_X32, batch_lt_32) { |
| 519 | TEST_REQUIRES_X86_SSE41; |
| 520 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 521 | VCvtMicrokernelTester() |
| 522 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 523 | .Test(xnn_f32_f16_vcvt_ukernel__sse41_x32, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 524 | } |
| 525 | } |
| 526 | |
| 527 | TEST(F32_F16_VCVT__SSE41_X32, batch_gt_32) { |
| 528 | TEST_REQUIRES_X86_SSE41; |
| 529 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 530 | VCvtMicrokernelTester() |
| 531 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 532 | .Test(xnn_f32_f16_vcvt_ukernel__sse41_x32, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 533 | } |
| 534 | } |
| 535 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 536 | |
| 537 | |
| 538 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 539 | TEST(F32_F16_VCVT__AVX_X8, batch_eq_8) { |
| 540 | TEST_REQUIRES_X86_AVX; |
| 541 | VCvtMicrokernelTester() |
| 542 | .batch_size(8) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 543 | .Test(xnn_f32_f16_vcvt_ukernel__avx_x8, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 544 | } |
| 545 | |
| 546 | TEST(F32_F16_VCVT__AVX_X8, batch_div_8) { |
| 547 | TEST_REQUIRES_X86_AVX; |
| 548 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 549 | VCvtMicrokernelTester() |
| 550 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 551 | .Test(xnn_f32_f16_vcvt_ukernel__avx_x8, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 552 | } |
| 553 | } |
| 554 | |
| 555 | TEST(F32_F16_VCVT__AVX_X8, batch_lt_8) { |
| 556 | TEST_REQUIRES_X86_AVX; |
| 557 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 558 | VCvtMicrokernelTester() |
| 559 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 560 | .Test(xnn_f32_f16_vcvt_ukernel__avx_x8, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 561 | } |
| 562 | } |
| 563 | |
| 564 | TEST(F32_F16_VCVT__AVX_X8, batch_gt_8) { |
| 565 | TEST_REQUIRES_X86_AVX; |
| 566 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 567 | VCvtMicrokernelTester() |
| 568 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 569 | .Test(xnn_f32_f16_vcvt_ukernel__avx_x8, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 570 | } |
| 571 | } |
| 572 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 573 | |
| 574 | |
| 575 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 576 | TEST(F32_F16_VCVT__AVX_X16, batch_eq_16) { |
| 577 | TEST_REQUIRES_X86_AVX; |
| 578 | VCvtMicrokernelTester() |
| 579 | .batch_size(16) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 580 | .Test(xnn_f32_f16_vcvt_ukernel__avx_x16, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 581 | } |
| 582 | |
| 583 | TEST(F32_F16_VCVT__AVX_X16, batch_div_16) { |
| 584 | TEST_REQUIRES_X86_AVX; |
| 585 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 586 | VCvtMicrokernelTester() |
| 587 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 588 | .Test(xnn_f32_f16_vcvt_ukernel__avx_x16, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 589 | } |
| 590 | } |
| 591 | |
| 592 | TEST(F32_F16_VCVT__AVX_X16, batch_lt_16) { |
| 593 | TEST_REQUIRES_X86_AVX; |
| 594 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 595 | VCvtMicrokernelTester() |
| 596 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 597 | .Test(xnn_f32_f16_vcvt_ukernel__avx_x16, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 598 | } |
| 599 | } |
| 600 | |
| 601 | TEST(F32_F16_VCVT__AVX_X16, batch_gt_16) { |
| 602 | TEST_REQUIRES_X86_AVX; |
| 603 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 604 | VCvtMicrokernelTester() |
| 605 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 606 | .Test(xnn_f32_f16_vcvt_ukernel__avx_x16, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 607 | } |
| 608 | } |
| 609 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 610 | |
| 611 | |
| 612 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 613 | TEST(F32_F16_VCVT__AVX_X24, batch_eq_24) { |
| 614 | TEST_REQUIRES_X86_AVX; |
| 615 | VCvtMicrokernelTester() |
| 616 | .batch_size(24) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 617 | .Test(xnn_f32_f16_vcvt_ukernel__avx_x24, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 618 | } |
| 619 | |
| 620 | TEST(F32_F16_VCVT__AVX_X24, batch_div_24) { |
| 621 | TEST_REQUIRES_X86_AVX; |
| 622 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 623 | VCvtMicrokernelTester() |
| 624 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 625 | .Test(xnn_f32_f16_vcvt_ukernel__avx_x24, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 626 | } |
| 627 | } |
| 628 | |
| 629 | TEST(F32_F16_VCVT__AVX_X24, batch_lt_24) { |
| 630 | TEST_REQUIRES_X86_AVX; |
| 631 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 632 | VCvtMicrokernelTester() |
| 633 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 634 | .Test(xnn_f32_f16_vcvt_ukernel__avx_x24, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 635 | } |
| 636 | } |
| 637 | |
| 638 | TEST(F32_F16_VCVT__AVX_X24, batch_gt_24) { |
| 639 | TEST_REQUIRES_X86_AVX; |
| 640 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 641 | VCvtMicrokernelTester() |
| 642 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 643 | .Test(xnn_f32_f16_vcvt_ukernel__avx_x24, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 644 | } |
| 645 | } |
| 646 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 647 | |
| 648 | |
| 649 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 650 | TEST(F32_F16_VCVT__AVX_X32, batch_eq_32) { |
| 651 | TEST_REQUIRES_X86_AVX; |
| 652 | VCvtMicrokernelTester() |
| 653 | .batch_size(32) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 654 | .Test(xnn_f32_f16_vcvt_ukernel__avx_x32, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 655 | } |
| 656 | |
| 657 | TEST(F32_F16_VCVT__AVX_X32, batch_div_32) { |
| 658 | TEST_REQUIRES_X86_AVX; |
| 659 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 660 | VCvtMicrokernelTester() |
| 661 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 662 | .Test(xnn_f32_f16_vcvt_ukernel__avx_x32, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 663 | } |
| 664 | } |
| 665 | |
| 666 | TEST(F32_F16_VCVT__AVX_X32, batch_lt_32) { |
| 667 | TEST_REQUIRES_X86_AVX; |
| 668 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 669 | VCvtMicrokernelTester() |
| 670 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 671 | .Test(xnn_f32_f16_vcvt_ukernel__avx_x32, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 672 | } |
| 673 | } |
| 674 | |
| 675 | TEST(F32_F16_VCVT__AVX_X32, batch_gt_32) { |
| 676 | TEST_REQUIRES_X86_AVX; |
| 677 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 678 | VCvtMicrokernelTester() |
| 679 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 680 | .Test(xnn_f32_f16_vcvt_ukernel__avx_x32, xnn_init_f32_f16_cvt_sse2_params); |
Marat Dukhan | eb84423 | 2021-11-08 23:07:53 -0800 | [diff] [blame] | 681 | } |
| 682 | } |
| 683 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 684 | |
| 685 | |
| 686 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | d77f77d | 2021-10-24 15:39:59 -0700 | [diff] [blame] | 687 | TEST(F32_F16_VCVT__F16C_X8, batch_eq_8) { |
| 688 | TEST_REQUIRES_X86_F16C; |
| 689 | VCvtMicrokernelTester() |
| 690 | .batch_size(8) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 691 | .Test(xnn_f32_f16_vcvt_ukernel__f16c_x8, xnn_init_f32_f16_cvt_f16c_params); |
Marat Dukhan | d77f77d | 2021-10-24 15:39:59 -0700 | [diff] [blame] | 692 | } |
| 693 | |
| 694 | TEST(F32_F16_VCVT__F16C_X8, batch_div_8) { |
| 695 | TEST_REQUIRES_X86_F16C; |
| 696 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 697 | VCvtMicrokernelTester() |
| 698 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 699 | .Test(xnn_f32_f16_vcvt_ukernel__f16c_x8, xnn_init_f32_f16_cvt_f16c_params); |
Marat Dukhan | d77f77d | 2021-10-24 15:39:59 -0700 | [diff] [blame] | 700 | } |
| 701 | } |
| 702 | |
| 703 | TEST(F32_F16_VCVT__F16C_X8, batch_lt_8) { |
| 704 | TEST_REQUIRES_X86_F16C; |
| 705 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 706 | VCvtMicrokernelTester() |
| 707 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 708 | .Test(xnn_f32_f16_vcvt_ukernel__f16c_x8, xnn_init_f32_f16_cvt_f16c_params); |
Marat Dukhan | d77f77d | 2021-10-24 15:39:59 -0700 | [diff] [blame] | 709 | } |
| 710 | } |
| 711 | |
| 712 | TEST(F32_F16_VCVT__F16C_X8, batch_gt_8) { |
| 713 | TEST_REQUIRES_X86_F16C; |
| 714 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 715 | VCvtMicrokernelTester() |
| 716 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 717 | .Test(xnn_f32_f16_vcvt_ukernel__f16c_x8, xnn_init_f32_f16_cvt_f16c_params); |
Marat Dukhan | d77f77d | 2021-10-24 15:39:59 -0700 | [diff] [blame] | 718 | } |
| 719 | } |
| 720 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 721 | |
| 722 | |
| 723 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 724 | TEST(F32_F16_VCVT__F16C_X16, batch_eq_16) { |
| 725 | TEST_REQUIRES_X86_F16C; |
| 726 | VCvtMicrokernelTester() |
| 727 | .batch_size(16) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 728 | .Test(xnn_f32_f16_vcvt_ukernel__f16c_x16, xnn_init_f32_f16_cvt_f16c_params); |
Marat Dukhan | d77f77d | 2021-10-24 15:39:59 -0700 | [diff] [blame] | 729 | } |
| 730 | |
| 731 | TEST(F32_F16_VCVT__F16C_X16, batch_div_16) { |
| 732 | TEST_REQUIRES_X86_F16C; |
| 733 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 734 | VCvtMicrokernelTester() |
| 735 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 736 | .Test(xnn_f32_f16_vcvt_ukernel__f16c_x16, xnn_init_f32_f16_cvt_f16c_params); |
Marat Dukhan | d77f77d | 2021-10-24 15:39:59 -0700 | [diff] [blame] | 737 | } |
| 738 | } |
| 739 | |
| 740 | TEST(F32_F16_VCVT__F16C_X16, batch_lt_16) { |
| 741 | TEST_REQUIRES_X86_F16C; |
| 742 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 743 | VCvtMicrokernelTester() |
| 744 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 745 | .Test(xnn_f32_f16_vcvt_ukernel__f16c_x16, xnn_init_f32_f16_cvt_f16c_params); |
Marat Dukhan | d77f77d | 2021-10-24 15:39:59 -0700 | [diff] [blame] | 746 | } |
| 747 | } |
| 748 | |
| 749 | TEST(F32_F16_VCVT__F16C_X16, batch_gt_16) { |
| 750 | TEST_REQUIRES_X86_F16C; |
| 751 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 752 | VCvtMicrokernelTester() |
| 753 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 754 | .Test(xnn_f32_f16_vcvt_ukernel__f16c_x16, xnn_init_f32_f16_cvt_f16c_params); |
Marat Dukhan | d77f77d | 2021-10-24 15:39:59 -0700 | [diff] [blame] | 755 | } |
| 756 | } |
| 757 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 758 | |
| 759 | |
| 760 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 761 | TEST(F32_F16_VCVT__AVX512SKX_X16, batch_eq_16) { |
| 762 | TEST_REQUIRES_X86_AVX512SKX; |
| 763 | VCvtMicrokernelTester() |
| 764 | .batch_size(16) |
| 765 | .Test(xnn_f32_f16_vcvt_ukernel__avx512skx_x16); |
| 766 | } |
| 767 | |
| 768 | TEST(F32_F16_VCVT__AVX512SKX_X16, batch_div_16) { |
| 769 | TEST_REQUIRES_X86_AVX512SKX; |
| 770 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 771 | VCvtMicrokernelTester() |
| 772 | .batch_size(batch_size) |
| 773 | .Test(xnn_f32_f16_vcvt_ukernel__avx512skx_x16); |
| 774 | } |
| 775 | } |
| 776 | |
| 777 | TEST(F32_F16_VCVT__AVX512SKX_X16, batch_lt_16) { |
| 778 | TEST_REQUIRES_X86_AVX512SKX; |
| 779 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 780 | VCvtMicrokernelTester() |
| 781 | .batch_size(batch_size) |
| 782 | .Test(xnn_f32_f16_vcvt_ukernel__avx512skx_x16); |
| 783 | } |
| 784 | } |
| 785 | |
| 786 | TEST(F32_F16_VCVT__AVX512SKX_X16, batch_gt_16) { |
| 787 | TEST_REQUIRES_X86_AVX512SKX; |
| 788 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 789 | VCvtMicrokernelTester() |
| 790 | .batch_size(batch_size) |
| 791 | .Test(xnn_f32_f16_vcvt_ukernel__avx512skx_x16); |
| 792 | } |
| 793 | } |
| 794 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 795 | |
| 796 | |
| 797 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 798 | TEST(F32_F16_VCVT__AVX512SKX_X32, batch_eq_32) { |
| 799 | TEST_REQUIRES_X86_AVX512SKX; |
| 800 | VCvtMicrokernelTester() |
| 801 | .batch_size(32) |
| 802 | .Test(xnn_f32_f16_vcvt_ukernel__avx512skx_x32); |
| 803 | } |
| 804 | |
| 805 | TEST(F32_F16_VCVT__AVX512SKX_X32, batch_div_32) { |
| 806 | TEST_REQUIRES_X86_AVX512SKX; |
| 807 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 808 | VCvtMicrokernelTester() |
| 809 | .batch_size(batch_size) |
| 810 | .Test(xnn_f32_f16_vcvt_ukernel__avx512skx_x32); |
| 811 | } |
| 812 | } |
| 813 | |
| 814 | TEST(F32_F16_VCVT__AVX512SKX_X32, batch_lt_32) { |
| 815 | TEST_REQUIRES_X86_AVX512SKX; |
| 816 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 817 | VCvtMicrokernelTester() |
| 818 | .batch_size(batch_size) |
| 819 | .Test(xnn_f32_f16_vcvt_ukernel__avx512skx_x32); |
| 820 | } |
| 821 | } |
| 822 | |
| 823 | TEST(F32_F16_VCVT__AVX512SKX_X32, batch_gt_32) { |
| 824 | TEST_REQUIRES_X86_AVX512SKX; |
| 825 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 826 | VCvtMicrokernelTester() |
| 827 | .batch_size(batch_size) |
| 828 | .Test(xnn_f32_f16_vcvt_ukernel__avx512skx_x32); |
| 829 | } |
| 830 | } |
| 831 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | 22e31c8 | 2021-11-09 00:00:28 -0800 | [diff] [blame] | 832 | |
| 833 | |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 834 | #if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | 22e31c8 | 2021-11-09 00:00:28 -0800 | [diff] [blame] | 835 | TEST(F32_F16_VCVT__WASMSIMD_X8, batch_eq_8) { |
| 836 | VCvtMicrokernelTester() |
| 837 | .batch_size(8) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 838 | .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x8, xnn_init_f32_f16_cvt_wasmsimd_params); |
Marat Dukhan | 22e31c8 | 2021-11-09 00:00:28 -0800 | [diff] [blame] | 839 | } |
| 840 | |
| 841 | TEST(F32_F16_VCVT__WASMSIMD_X8, batch_div_8) { |
| 842 | for (size_t batch_size = 16; batch_size < 80; batch_size += 8) { |
| 843 | VCvtMicrokernelTester() |
| 844 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 845 | .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x8, xnn_init_f32_f16_cvt_wasmsimd_params); |
Marat Dukhan | 22e31c8 | 2021-11-09 00:00:28 -0800 | [diff] [blame] | 846 | } |
| 847 | } |
| 848 | |
| 849 | TEST(F32_F16_VCVT__WASMSIMD_X8, batch_lt_8) { |
| 850 | for (size_t batch_size = 1; batch_size < 8; batch_size++) { |
| 851 | VCvtMicrokernelTester() |
| 852 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 853 | .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x8, xnn_init_f32_f16_cvt_wasmsimd_params); |
Marat Dukhan | 22e31c8 | 2021-11-09 00:00:28 -0800 | [diff] [blame] | 854 | } |
| 855 | } |
| 856 | |
| 857 | TEST(F32_F16_VCVT__WASMSIMD_X8, batch_gt_8) { |
| 858 | for (size_t batch_size = 9; batch_size < 16; batch_size++) { |
| 859 | VCvtMicrokernelTester() |
| 860 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 861 | .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x8, xnn_init_f32_f16_cvt_wasmsimd_params); |
Marat Dukhan | 22e31c8 | 2021-11-09 00:00:28 -0800 | [diff] [blame] | 862 | } |
| 863 | } |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 864 | #endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | 22e31c8 | 2021-11-09 00:00:28 -0800 | [diff] [blame] | 865 | |
| 866 | |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 867 | #if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | 22e31c8 | 2021-11-09 00:00:28 -0800 | [diff] [blame] | 868 | TEST(F32_F16_VCVT__WASMSIMD_X16, batch_eq_16) { |
| 869 | VCvtMicrokernelTester() |
| 870 | .batch_size(16) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 871 | .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x16, xnn_init_f32_f16_cvt_wasmsimd_params); |
Marat Dukhan | 22e31c8 | 2021-11-09 00:00:28 -0800 | [diff] [blame] | 872 | } |
| 873 | |
| 874 | TEST(F32_F16_VCVT__WASMSIMD_X16, batch_div_16) { |
| 875 | for (size_t batch_size = 32; batch_size < 160; batch_size += 16) { |
| 876 | VCvtMicrokernelTester() |
| 877 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 878 | .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x16, xnn_init_f32_f16_cvt_wasmsimd_params); |
Marat Dukhan | 22e31c8 | 2021-11-09 00:00:28 -0800 | [diff] [blame] | 879 | } |
| 880 | } |
| 881 | |
| 882 | TEST(F32_F16_VCVT__WASMSIMD_X16, batch_lt_16) { |
| 883 | for (size_t batch_size = 1; batch_size < 16; batch_size++) { |
| 884 | VCvtMicrokernelTester() |
| 885 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 886 | .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x16, xnn_init_f32_f16_cvt_wasmsimd_params); |
Marat Dukhan | 22e31c8 | 2021-11-09 00:00:28 -0800 | [diff] [blame] | 887 | } |
| 888 | } |
| 889 | |
| 890 | TEST(F32_F16_VCVT__WASMSIMD_X16, batch_gt_16) { |
| 891 | for (size_t batch_size = 17; batch_size < 32; batch_size++) { |
| 892 | VCvtMicrokernelTester() |
| 893 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 894 | .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x16, xnn_init_f32_f16_cvt_wasmsimd_params); |
Marat Dukhan | 22e31c8 | 2021-11-09 00:00:28 -0800 | [diff] [blame] | 895 | } |
| 896 | } |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 897 | #endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | 22e31c8 | 2021-11-09 00:00:28 -0800 | [diff] [blame] | 898 | |
| 899 | |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 900 | #if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | 22e31c8 | 2021-11-09 00:00:28 -0800 | [diff] [blame] | 901 | TEST(F32_F16_VCVT__WASMSIMD_X24, batch_eq_24) { |
| 902 | VCvtMicrokernelTester() |
| 903 | .batch_size(24) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 904 | .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x24, xnn_init_f32_f16_cvt_wasmsimd_params); |
Marat Dukhan | 22e31c8 | 2021-11-09 00:00:28 -0800 | [diff] [blame] | 905 | } |
| 906 | |
| 907 | TEST(F32_F16_VCVT__WASMSIMD_X24, batch_div_24) { |
| 908 | for (size_t batch_size = 48; batch_size < 240; batch_size += 24) { |
| 909 | VCvtMicrokernelTester() |
| 910 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 911 | .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x24, xnn_init_f32_f16_cvt_wasmsimd_params); |
Marat Dukhan | 22e31c8 | 2021-11-09 00:00:28 -0800 | [diff] [blame] | 912 | } |
| 913 | } |
| 914 | |
| 915 | TEST(F32_F16_VCVT__WASMSIMD_X24, batch_lt_24) { |
| 916 | for (size_t batch_size = 1; batch_size < 24; batch_size++) { |
| 917 | VCvtMicrokernelTester() |
| 918 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 919 | .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x24, xnn_init_f32_f16_cvt_wasmsimd_params); |
Marat Dukhan | 22e31c8 | 2021-11-09 00:00:28 -0800 | [diff] [blame] | 920 | } |
| 921 | } |
| 922 | |
| 923 | TEST(F32_F16_VCVT__WASMSIMD_X24, batch_gt_24) { |
| 924 | for (size_t batch_size = 25; batch_size < 48; batch_size++) { |
| 925 | VCvtMicrokernelTester() |
| 926 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 927 | .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x24, xnn_init_f32_f16_cvt_wasmsimd_params); |
Marat Dukhan | 22e31c8 | 2021-11-09 00:00:28 -0800 | [diff] [blame] | 928 | } |
| 929 | } |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 930 | #endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | 22e31c8 | 2021-11-09 00:00:28 -0800 | [diff] [blame] | 931 | |
| 932 | |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 933 | #if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | 22e31c8 | 2021-11-09 00:00:28 -0800 | [diff] [blame] | 934 | TEST(F32_F16_VCVT__WASMSIMD_X32, batch_eq_32) { |
| 935 | VCvtMicrokernelTester() |
| 936 | .batch_size(32) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 937 | .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x32, xnn_init_f32_f16_cvt_wasmsimd_params); |
Marat Dukhan | 22e31c8 | 2021-11-09 00:00:28 -0800 | [diff] [blame] | 938 | } |
| 939 | |
| 940 | TEST(F32_F16_VCVT__WASMSIMD_X32, batch_div_32) { |
| 941 | for (size_t batch_size = 64; batch_size < 320; batch_size += 32) { |
| 942 | VCvtMicrokernelTester() |
| 943 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 944 | .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x32, xnn_init_f32_f16_cvt_wasmsimd_params); |
Marat Dukhan | 22e31c8 | 2021-11-09 00:00:28 -0800 | [diff] [blame] | 945 | } |
| 946 | } |
| 947 | |
| 948 | TEST(F32_F16_VCVT__WASMSIMD_X32, batch_lt_32) { |
| 949 | for (size_t batch_size = 1; batch_size < 32; batch_size++) { |
| 950 | VCvtMicrokernelTester() |
| 951 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 952 | .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x32, xnn_init_f32_f16_cvt_wasmsimd_params); |
Marat Dukhan | 22e31c8 | 2021-11-09 00:00:28 -0800 | [diff] [blame] | 953 | } |
| 954 | } |
| 955 | |
| 956 | TEST(F32_F16_VCVT__WASMSIMD_X32, batch_gt_32) { |
| 957 | for (size_t batch_size = 33; batch_size < 64; batch_size++) { |
| 958 | VCvtMicrokernelTester() |
| 959 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 960 | .Test(xnn_f32_f16_vcvt_ukernel__wasmsimd_x32, xnn_init_f32_f16_cvt_wasmsimd_params); |
Marat Dukhan | 22e31c8 | 2021-11-09 00:00:28 -0800 | [diff] [blame] | 961 | } |
| 962 | } |
Marat Dukhan | 4c61779 | 2021-12-21 15:47:58 -0800 | [diff] [blame] | 963 | #endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 964 | |
| 965 | |
| 966 | TEST(F32_F16_VCVT__SCALAR_BITCAST_X1, batch_eq_1) { |
| 967 | VCvtMicrokernelTester() |
| 968 | .batch_size(1) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 969 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x1, xnn_init_f32_f16_cvt_scalar_bitcast_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 970 | } |
| 971 | |
| 972 | TEST(F32_F16_VCVT__SCALAR_BITCAST_X1, batch_gt_1) { |
| 973 | for (size_t batch_size = 2; batch_size < 10; batch_size++) { |
| 974 | VCvtMicrokernelTester() |
| 975 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 976 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x1, xnn_init_f32_f16_cvt_scalar_bitcast_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 977 | } |
| 978 | } |
| 979 | |
Marat Dukhan | 4bdc9f5 | 2021-12-09 15:36:06 -0800 | [diff] [blame] | 980 | |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 981 | TEST(F32_F16_VCVT__SCALAR_BITCAST_X2, batch_eq_2) { |
| 982 | VCvtMicrokernelTester() |
| 983 | .batch_size(2) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 984 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x2, xnn_init_f32_f16_cvt_scalar_bitcast_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 985 | } |
| 986 | |
| 987 | TEST(F32_F16_VCVT__SCALAR_BITCAST_X2, batch_div_2) { |
| 988 | for (size_t batch_size = 4; batch_size < 20; batch_size += 2) { |
| 989 | VCvtMicrokernelTester() |
| 990 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 991 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x2, xnn_init_f32_f16_cvt_scalar_bitcast_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 992 | } |
| 993 | } |
| 994 | |
| 995 | TEST(F32_F16_VCVT__SCALAR_BITCAST_X2, batch_lt_2) { |
| 996 | for (size_t batch_size = 1; batch_size < 2; batch_size++) { |
| 997 | VCvtMicrokernelTester() |
| 998 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 999 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x2, xnn_init_f32_f16_cvt_scalar_bitcast_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1000 | } |
| 1001 | } |
| 1002 | |
| 1003 | TEST(F32_F16_VCVT__SCALAR_BITCAST_X2, batch_gt_2) { |
| 1004 | for (size_t batch_size = 3; batch_size < 4; batch_size++) { |
| 1005 | VCvtMicrokernelTester() |
| 1006 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 1007 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x2, xnn_init_f32_f16_cvt_scalar_bitcast_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1008 | } |
| 1009 | } |
| 1010 | |
Marat Dukhan | 4bdc9f5 | 2021-12-09 15:36:06 -0800 | [diff] [blame] | 1011 | |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1012 | TEST(F32_F16_VCVT__SCALAR_BITCAST_X3, batch_eq_3) { |
| 1013 | VCvtMicrokernelTester() |
| 1014 | .batch_size(3) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 1015 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x3, xnn_init_f32_f16_cvt_scalar_bitcast_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1016 | } |
| 1017 | |
| 1018 | TEST(F32_F16_VCVT__SCALAR_BITCAST_X3, batch_div_3) { |
| 1019 | for (size_t batch_size = 6; batch_size < 30; batch_size += 3) { |
| 1020 | VCvtMicrokernelTester() |
| 1021 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 1022 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x3, xnn_init_f32_f16_cvt_scalar_bitcast_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1023 | } |
| 1024 | } |
| 1025 | |
| 1026 | TEST(F32_F16_VCVT__SCALAR_BITCAST_X3, batch_lt_3) { |
| 1027 | for (size_t batch_size = 1; batch_size < 3; batch_size++) { |
| 1028 | VCvtMicrokernelTester() |
| 1029 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 1030 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x3, xnn_init_f32_f16_cvt_scalar_bitcast_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1031 | } |
| 1032 | } |
| 1033 | |
| 1034 | TEST(F32_F16_VCVT__SCALAR_BITCAST_X3, batch_gt_3) { |
| 1035 | for (size_t batch_size = 4; batch_size < 6; batch_size++) { |
| 1036 | VCvtMicrokernelTester() |
| 1037 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 1038 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x3, xnn_init_f32_f16_cvt_scalar_bitcast_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1039 | } |
| 1040 | } |
| 1041 | |
Marat Dukhan | 4bdc9f5 | 2021-12-09 15:36:06 -0800 | [diff] [blame] | 1042 | |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1043 | TEST(F32_F16_VCVT__SCALAR_BITCAST_X4, batch_eq_4) { |
| 1044 | VCvtMicrokernelTester() |
| 1045 | .batch_size(4) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 1046 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x4, xnn_init_f32_f16_cvt_scalar_bitcast_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1047 | } |
| 1048 | |
| 1049 | TEST(F32_F16_VCVT__SCALAR_BITCAST_X4, batch_div_4) { |
| 1050 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 1051 | VCvtMicrokernelTester() |
| 1052 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 1053 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x4, xnn_init_f32_f16_cvt_scalar_bitcast_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1054 | } |
| 1055 | } |
| 1056 | |
| 1057 | TEST(F32_F16_VCVT__SCALAR_BITCAST_X4, batch_lt_4) { |
| 1058 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 1059 | VCvtMicrokernelTester() |
| 1060 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 1061 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x4, xnn_init_f32_f16_cvt_scalar_bitcast_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1062 | } |
| 1063 | } |
| 1064 | |
| 1065 | TEST(F32_F16_VCVT__SCALAR_BITCAST_X4, batch_gt_4) { |
| 1066 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 1067 | VCvtMicrokernelTester() |
| 1068 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 1069 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_bitcast_x4, xnn_init_f32_f16_cvt_scalar_bitcast_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1070 | } |
| 1071 | } |
| 1072 | |
Marat Dukhan | 4bdc9f5 | 2021-12-09 15:36:06 -0800 | [diff] [blame] | 1073 | |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1074 | TEST(F32_F16_VCVT__SCALAR_FABSF_X1, batch_eq_1) { |
| 1075 | VCvtMicrokernelTester() |
| 1076 | .batch_size(1) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 1077 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x1, xnn_init_f32_f16_cvt_scalar_fabsf_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1078 | } |
| 1079 | |
| 1080 | TEST(F32_F16_VCVT__SCALAR_FABSF_X1, batch_gt_1) { |
| 1081 | for (size_t batch_size = 2; batch_size < 10; batch_size++) { |
| 1082 | VCvtMicrokernelTester() |
| 1083 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 1084 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x1, xnn_init_f32_f16_cvt_scalar_fabsf_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1085 | } |
| 1086 | } |
| 1087 | |
Marat Dukhan | 4bdc9f5 | 2021-12-09 15:36:06 -0800 | [diff] [blame] | 1088 | |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1089 | TEST(F32_F16_VCVT__SCALAR_FABSF_X2, batch_eq_2) { |
| 1090 | VCvtMicrokernelTester() |
| 1091 | .batch_size(2) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 1092 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x2, xnn_init_f32_f16_cvt_scalar_fabsf_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1093 | } |
| 1094 | |
| 1095 | TEST(F32_F16_VCVT__SCALAR_FABSF_X2, batch_div_2) { |
| 1096 | for (size_t batch_size = 4; batch_size < 20; batch_size += 2) { |
| 1097 | VCvtMicrokernelTester() |
| 1098 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 1099 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x2, xnn_init_f32_f16_cvt_scalar_fabsf_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1100 | } |
| 1101 | } |
| 1102 | |
| 1103 | TEST(F32_F16_VCVT__SCALAR_FABSF_X2, batch_lt_2) { |
| 1104 | for (size_t batch_size = 1; batch_size < 2; batch_size++) { |
| 1105 | VCvtMicrokernelTester() |
| 1106 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 1107 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x2, xnn_init_f32_f16_cvt_scalar_fabsf_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1108 | } |
| 1109 | } |
| 1110 | |
| 1111 | TEST(F32_F16_VCVT__SCALAR_FABSF_X2, batch_gt_2) { |
| 1112 | for (size_t batch_size = 3; batch_size < 4; batch_size++) { |
| 1113 | VCvtMicrokernelTester() |
| 1114 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 1115 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x2, xnn_init_f32_f16_cvt_scalar_fabsf_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1116 | } |
| 1117 | } |
| 1118 | |
Marat Dukhan | 4bdc9f5 | 2021-12-09 15:36:06 -0800 | [diff] [blame] | 1119 | |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1120 | TEST(F32_F16_VCVT__SCALAR_FABSF_X3, batch_eq_3) { |
| 1121 | VCvtMicrokernelTester() |
| 1122 | .batch_size(3) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 1123 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x3, xnn_init_f32_f16_cvt_scalar_fabsf_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1124 | } |
| 1125 | |
| 1126 | TEST(F32_F16_VCVT__SCALAR_FABSF_X3, batch_div_3) { |
| 1127 | for (size_t batch_size = 6; batch_size < 30; batch_size += 3) { |
| 1128 | VCvtMicrokernelTester() |
| 1129 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 1130 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x3, xnn_init_f32_f16_cvt_scalar_fabsf_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1131 | } |
| 1132 | } |
| 1133 | |
| 1134 | TEST(F32_F16_VCVT__SCALAR_FABSF_X3, batch_lt_3) { |
| 1135 | for (size_t batch_size = 1; batch_size < 3; batch_size++) { |
| 1136 | VCvtMicrokernelTester() |
| 1137 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 1138 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x3, xnn_init_f32_f16_cvt_scalar_fabsf_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1139 | } |
| 1140 | } |
| 1141 | |
| 1142 | TEST(F32_F16_VCVT__SCALAR_FABSF_X3, batch_gt_3) { |
| 1143 | for (size_t batch_size = 4; batch_size < 6; batch_size++) { |
| 1144 | VCvtMicrokernelTester() |
| 1145 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 1146 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x3, xnn_init_f32_f16_cvt_scalar_fabsf_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1147 | } |
| 1148 | } |
| 1149 | |
Marat Dukhan | 4bdc9f5 | 2021-12-09 15:36:06 -0800 | [diff] [blame] | 1150 | |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1151 | TEST(F32_F16_VCVT__SCALAR_FABSF_X4, batch_eq_4) { |
| 1152 | VCvtMicrokernelTester() |
| 1153 | .batch_size(4) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 1154 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x4, xnn_init_f32_f16_cvt_scalar_fabsf_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1155 | } |
| 1156 | |
| 1157 | TEST(F32_F16_VCVT__SCALAR_FABSF_X4, batch_div_4) { |
| 1158 | for (size_t batch_size = 8; batch_size < 40; batch_size += 4) { |
| 1159 | VCvtMicrokernelTester() |
| 1160 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 1161 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x4, xnn_init_f32_f16_cvt_scalar_fabsf_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1162 | } |
| 1163 | } |
| 1164 | |
| 1165 | TEST(F32_F16_VCVT__SCALAR_FABSF_X4, batch_lt_4) { |
| 1166 | for (size_t batch_size = 1; batch_size < 4; batch_size++) { |
| 1167 | VCvtMicrokernelTester() |
| 1168 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 1169 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x4, xnn_init_f32_f16_cvt_scalar_fabsf_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1170 | } |
| 1171 | } |
| 1172 | |
| 1173 | TEST(F32_F16_VCVT__SCALAR_FABSF_X4, batch_gt_4) { |
| 1174 | for (size_t batch_size = 5; batch_size < 8; batch_size++) { |
| 1175 | VCvtMicrokernelTester() |
| 1176 | .batch_size(batch_size) |
Marat Dukhan | b7c1b71 | 2021-12-30 07:23:57 -0800 | [diff] [blame] | 1177 | .Test(xnn_f32_f16_vcvt_ukernel__scalar_fabsf_x4, xnn_init_f32_f16_cvt_scalar_fabsf_params); |
Marat Dukhan | 1fe8995 | 2021-11-10 01:27:15 -0800 | [diff] [blame] | 1178 | } |
Marat Dukhan | 4bdc9f5 | 2021-12-09 15:36:06 -0800 | [diff] [blame] | 1179 | } |