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Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +01001#
Jeenu Viswambharanc877b412017-01-16 16:52:35 +00002# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +01003#
dp-arm82cb2c12017-05-03 09:38:09 +01004# SPDX-License-Identifier: BSD-3-Clause
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +01005#
6
7# Default, static values for build variables, listed in alphabetic order.
8# Dependencies between build options, if any, are handled in the top-level
9# Makefile, after this file is included. This ensures that the former is better
10# poised to handle dependencies, as all build variables would have a default
11# value by then.
12
13# The AArch32 Secure Payload to be built as BL32 image
14AARCH32_SP := none
15
16# The Target build architecture. Supported values are: aarch64, aarch32.
17ARCH := aarch64
18
Jeenu Viswambharanc877b412017-01-16 16:52:35 +000019# ARM Architecture major and minor versions: 8.0 by default.
20ARM_ARCH_MAJOR := 8
21ARM_ARCH_MINOR := 0
22
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +010023# Determine the version of ARM GIC architecture to use for interrupt management
24# in EL3. The platform port can change this value if needed.
25ARM_GIC_ARCH := 2
26
27# Flag used to indicate if ASM_ASSERTION should be enabled for the build.
28ASM_ASSERTION := 0
29
30# Base commit to perform code check on
31BASE_COMMIT := origin/master
32
33# By default, consider that the platform may release several CPUs out of reset.
34# The platform Makefile is free to override this value.
35COLD_BOOT_SINGLE_CPU := 0
36
37# For Chain of Trust
38CREATE_KEYS := 1
39
40# Build flag to include AArch32 registers in cpu context save and restore during
41# world switch. This flag must be set to 0 for AArch64-only platforms.
42CTX_INCLUDE_AARCH32_REGS := 1
43
44# Include FP registers in cpu context
45CTX_INCLUDE_FPREGS := 0
46
47# Debug build
48DEBUG := 0
49
50# Build platform
51DEFAULT_PLAT := fvp
52
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +010053# Flag to enable Performance Measurement Framework
54ENABLE_PMF := 0
55
56# Flag to enable PSCI STATs functionality
57ENABLE_PSCI_STAT := 0
58
59# Flag to enable runtime instrumentation using PMF
60ENABLE_RUNTIME_INSTRUMENTATION := 0
61
Douglas Raillard51faada2017-02-24 18:14:15 +000062# Flag to enable stack corruption protection
63ENABLE_STACK_PROTECTOR := 0
64
Jeenu Viswambharan21b818c2017-09-22 08:32:10 +010065# Flag to enable exception handling in EL3
66EL3_EXCEPTION_HANDLING := 0
67
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +010068# Build flag to treat usage of deprecated platform and framework APIs as error.
69ERROR_DEPRECATED := 0
70
Masahiro Yamada1c75d5d2016-12-25 13:52:22 +090071# Byte alignment that each component in FIP is aligned to
72FIP_ALIGN := 0
73
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +010074# Default FIP file name
75FIP_NAME := fip.bin
76
77# Default FWU_FIP file name
78FWU_FIP_NAME := fwu_fip.bin
79
80# For Chain of Trust
81GENERATE_COT := 0
82
Jeenu Viswambharan74dce7f2017-09-22 08:32:09 +010083# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By
84# default, they are for Secure EL1.
85GICV2_G0_FOR_EL3 := 0
86
Jeenu Viswambharan3c251af2017-01-04 13:51:42 +000087# Whether system coherency is managed in hardware, without explicit software
88# operations.
89HW_ASSISTED_COHERENCY := 0
90
Soby Mathew20917552017-08-31 11:49:32 +010091# Set the default algorithm for the generation of Trusted Board Boot keys
92KEY_ALG := rsa
93
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +010094# Flag to enable new version of image loading
95LOAD_IMAGE_V2 := 0
96
97# NS timer register save and restore
98NS_TIMER_SWITCH := 0
99
100# Build PL011 UART driver in minimal generic UART mode
101PL011_GENERIC_UART := 0
102
103# By default, consider that the platform's reset address is not programmable.
104# The platform Makefile is free to override this value.
105PROGRAMMABLE_RESET_ADDRESS := 0
106
107# Flag used to choose the power state format viz Extended State-ID or the
108# Original format.
109PSCI_EXTENDED_STATE_ID := 0
110
111# By default, BL1 acts as the reset handler, not BL31
112RESET_TO_BL31 := 0
113
114# For Chain of Trust
115SAVE_KEYS := 0
116
117# Whether code and read-only data should be put on separate memory pages. The
118# platform Makefile is free to override this value.
119SEPARATE_CODE_AND_RODATA := 0
120
121# SPD choice
122SPD := none
123
Antonio Nino Diaz2fccb222017-10-24 10:07:35 +0100124# For including the Secure Partition Manager
125ENABLE_SPM := 0
126
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +0100127# Flag to introduce an infinite loop in BL1 just before it exits into the next
128# image. This is meant to help debugging the post-BL2 phase.
129SPIN_ON_BL1_EXIT := 0
130
131# Flags to build TF with Trusted Boot support
132TRUSTED_BOARD_BOOT := 0
133
134# Build option to choose whether Trusted firmware uses Coherent memory or not.
135USE_COHERENT_MEM := 1
136
Masahiro Yamadabb41eb72017-05-22 12:11:24 +0900137# Use tbbr_oid.h instead of platform_oid.h
138USE_TBBR_DEFS = $(ERROR_DEPRECATED)
139
Jeenu Viswambharan2fae4b12016-10-24 14:31:51 +0100140# Build verbosity
141V := 0
Soby Mathewbcc3c492017-04-10 22:35:42 +0100142
143# Whether to enable D-Cache early during warm boot. This is usually
144# applicable for platforms wherein interconnect programming is not
145# required to enable cache coherency after warm reset (eg: single cluster
146# platforms).
147WARMBOOT_ENABLE_DCACHE_EARLY := 0
dp-armd832aee2017-05-23 09:32:49 +0100148
149# By default, enable Statistical Profiling Extensions.
150# The top level Makefile will disable this feature depending on
151# the target architecture and version number.
152ENABLE_SPE_FOR_LOWER_ELS := 1
153
154# SPE is enabled by default but only supported on AArch64 8.2 onwards.
155# Disable it in all other cases.
156ifeq (${ARCH},aarch32)
157 override ENABLE_SPE_FOR_LOWER_ELS := 0
158else
159 ifeq (${ARM_ARCH_MAJOR},8)
160 ifeq ($(ARM_ARCH_MINOR),$(filter $(ARM_ARCH_MINOR),0 1))
161 ENABLE_SPE_FOR_LOWER_ELS := 0
162 endif
163 endif
164endif