Robert Sloan | c9abfe4 | 2018-11-26 12:19:07 -0800 | [diff] [blame] | 1 | // This file is generated from a similarly-named Perl script in the BoringSSL |
| 2 | // source tree. Do not edit by hand. |
| 3 | |
Robert Sloan | 726e9d1 | 2018-09-11 11:45:04 -0700 | [diff] [blame] | 4 | #if defined(__has_feature) |
| 5 | #if __has_feature(memory_sanitizer) && !defined(OPENSSL_NO_ASM) |
| 6 | #define OPENSSL_NO_ASM |
| 7 | #endif |
| 8 | #endif |
| 9 | |
| 10 | #if !defined(OPENSSL_NO_ASM) |
| 11 | #if defined(BORINGSSL_PREFIX) |
| 12 | #include <boringssl_prefix_symbols_asm.h> |
| 13 | #endif |
Robert Sloan | 8ff0355 | 2017-06-14 12:40:58 -0700 | [diff] [blame] | 14 | #include <openssl/arm_arch.h> |
| 15 | |
| 16 | .text |
| 17 | #if defined(__thumb2__) |
| 18 | .syntax unified |
| 19 | .thumb |
| 20 | #else |
| 21 | .code 32 |
| 22 | #endif |
| 23 | |
| 24 | .globl _sha1_block_data_order |
| 25 | .private_extern _sha1_block_data_order |
| 26 | #ifdef __thumb2__ |
| 27 | .thumb_func _sha1_block_data_order |
| 28 | #endif |
| 29 | |
| 30 | .align 5 |
| 31 | _sha1_block_data_order: |
| 32 | #if __ARM_MAX_ARCH__>=7 |
| 33 | Lsha1_block: |
| 34 | adr r3,Lsha1_block |
| 35 | ldr r12,LOPENSSL_armcap |
| 36 | ldr r12,[r3,r12] @ OPENSSL_armcap_P |
| 37 | #ifdef __APPLE__ |
| 38 | ldr r12,[r12] |
| 39 | #endif |
| 40 | tst r12,#ARMV8_SHA1 |
| 41 | bne LARMv8 |
| 42 | tst r12,#ARMV7_NEON |
| 43 | bne LNEON |
| 44 | #endif |
| 45 | stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} |
| 46 | add r2,r1,r2,lsl#6 @ r2 to point at the end of r1 |
| 47 | ldmia r0,{r3,r4,r5,r6,r7} |
| 48 | Lloop: |
| 49 | ldr r8,LK_00_19 |
| 50 | mov r14,sp |
| 51 | sub sp,sp,#15*4 |
| 52 | mov r5,r5,ror#30 |
| 53 | mov r6,r6,ror#30 |
| 54 | mov r7,r7,ror#30 @ [6] |
| 55 | L_00_15: |
| 56 | #if __ARM_ARCH__<7 |
| 57 | ldrb r10,[r1,#2] |
| 58 | ldrb r9,[r1,#3] |
| 59 | ldrb r11,[r1,#1] |
| 60 | add r7,r8,r7,ror#2 @ E+=K_00_19 |
| 61 | ldrb r12,[r1],#4 |
| 62 | orr r9,r9,r10,lsl#8 |
| 63 | eor r10,r5,r6 @ F_xx_xx |
| 64 | orr r9,r9,r11,lsl#16 |
| 65 | add r7,r7,r3,ror#27 @ E+=ROR(A,27) |
| 66 | orr r9,r9,r12,lsl#24 |
| 67 | #else |
| 68 | ldr r9,[r1],#4 @ handles unaligned |
| 69 | add r7,r8,r7,ror#2 @ E+=K_00_19 |
| 70 | eor r10,r5,r6 @ F_xx_xx |
| 71 | add r7,r7,r3,ror#27 @ E+=ROR(A,27) |
| 72 | #ifdef __ARMEL__ |
| 73 | rev r9,r9 @ byte swap |
| 74 | #endif |
| 75 | #endif |
| 76 | and r10,r4,r10,ror#2 |
| 77 | add r7,r7,r9 @ E+=X[i] |
| 78 | eor r10,r10,r6,ror#2 @ F_00_19(B,C,D) |
| 79 | str r9,[r14,#-4]! |
| 80 | add r7,r7,r10 @ E+=F_00_19(B,C,D) |
| 81 | #if __ARM_ARCH__<7 |
| 82 | ldrb r10,[r1,#2] |
| 83 | ldrb r9,[r1,#3] |
| 84 | ldrb r11,[r1,#1] |
| 85 | add r6,r8,r6,ror#2 @ E+=K_00_19 |
| 86 | ldrb r12,[r1],#4 |
| 87 | orr r9,r9,r10,lsl#8 |
| 88 | eor r10,r4,r5 @ F_xx_xx |
| 89 | orr r9,r9,r11,lsl#16 |
| 90 | add r6,r6,r7,ror#27 @ E+=ROR(A,27) |
| 91 | orr r9,r9,r12,lsl#24 |
| 92 | #else |
| 93 | ldr r9,[r1],#4 @ handles unaligned |
| 94 | add r6,r8,r6,ror#2 @ E+=K_00_19 |
| 95 | eor r10,r4,r5 @ F_xx_xx |
| 96 | add r6,r6,r7,ror#27 @ E+=ROR(A,27) |
| 97 | #ifdef __ARMEL__ |
| 98 | rev r9,r9 @ byte swap |
| 99 | #endif |
| 100 | #endif |
| 101 | and r10,r3,r10,ror#2 |
| 102 | add r6,r6,r9 @ E+=X[i] |
| 103 | eor r10,r10,r5,ror#2 @ F_00_19(B,C,D) |
| 104 | str r9,[r14,#-4]! |
| 105 | add r6,r6,r10 @ E+=F_00_19(B,C,D) |
| 106 | #if __ARM_ARCH__<7 |
| 107 | ldrb r10,[r1,#2] |
| 108 | ldrb r9,[r1,#3] |
| 109 | ldrb r11,[r1,#1] |
| 110 | add r5,r8,r5,ror#2 @ E+=K_00_19 |
| 111 | ldrb r12,[r1],#4 |
| 112 | orr r9,r9,r10,lsl#8 |
| 113 | eor r10,r3,r4 @ F_xx_xx |
| 114 | orr r9,r9,r11,lsl#16 |
| 115 | add r5,r5,r6,ror#27 @ E+=ROR(A,27) |
| 116 | orr r9,r9,r12,lsl#24 |
| 117 | #else |
| 118 | ldr r9,[r1],#4 @ handles unaligned |
| 119 | add r5,r8,r5,ror#2 @ E+=K_00_19 |
| 120 | eor r10,r3,r4 @ F_xx_xx |
| 121 | add r5,r5,r6,ror#27 @ E+=ROR(A,27) |
| 122 | #ifdef __ARMEL__ |
| 123 | rev r9,r9 @ byte swap |
| 124 | #endif |
| 125 | #endif |
| 126 | and r10,r7,r10,ror#2 |
| 127 | add r5,r5,r9 @ E+=X[i] |
| 128 | eor r10,r10,r4,ror#2 @ F_00_19(B,C,D) |
| 129 | str r9,[r14,#-4]! |
| 130 | add r5,r5,r10 @ E+=F_00_19(B,C,D) |
| 131 | #if __ARM_ARCH__<7 |
| 132 | ldrb r10,[r1,#2] |
| 133 | ldrb r9,[r1,#3] |
| 134 | ldrb r11,[r1,#1] |
| 135 | add r4,r8,r4,ror#2 @ E+=K_00_19 |
| 136 | ldrb r12,[r1],#4 |
| 137 | orr r9,r9,r10,lsl#8 |
| 138 | eor r10,r7,r3 @ F_xx_xx |
| 139 | orr r9,r9,r11,lsl#16 |
| 140 | add r4,r4,r5,ror#27 @ E+=ROR(A,27) |
| 141 | orr r9,r9,r12,lsl#24 |
| 142 | #else |
| 143 | ldr r9,[r1],#4 @ handles unaligned |
| 144 | add r4,r8,r4,ror#2 @ E+=K_00_19 |
| 145 | eor r10,r7,r3 @ F_xx_xx |
| 146 | add r4,r4,r5,ror#27 @ E+=ROR(A,27) |
| 147 | #ifdef __ARMEL__ |
| 148 | rev r9,r9 @ byte swap |
| 149 | #endif |
| 150 | #endif |
| 151 | and r10,r6,r10,ror#2 |
| 152 | add r4,r4,r9 @ E+=X[i] |
| 153 | eor r10,r10,r3,ror#2 @ F_00_19(B,C,D) |
| 154 | str r9,[r14,#-4]! |
| 155 | add r4,r4,r10 @ E+=F_00_19(B,C,D) |
| 156 | #if __ARM_ARCH__<7 |
| 157 | ldrb r10,[r1,#2] |
| 158 | ldrb r9,[r1,#3] |
| 159 | ldrb r11,[r1,#1] |
| 160 | add r3,r8,r3,ror#2 @ E+=K_00_19 |
| 161 | ldrb r12,[r1],#4 |
| 162 | orr r9,r9,r10,lsl#8 |
| 163 | eor r10,r6,r7 @ F_xx_xx |
| 164 | orr r9,r9,r11,lsl#16 |
| 165 | add r3,r3,r4,ror#27 @ E+=ROR(A,27) |
| 166 | orr r9,r9,r12,lsl#24 |
| 167 | #else |
| 168 | ldr r9,[r1],#4 @ handles unaligned |
| 169 | add r3,r8,r3,ror#2 @ E+=K_00_19 |
| 170 | eor r10,r6,r7 @ F_xx_xx |
| 171 | add r3,r3,r4,ror#27 @ E+=ROR(A,27) |
| 172 | #ifdef __ARMEL__ |
| 173 | rev r9,r9 @ byte swap |
| 174 | #endif |
| 175 | #endif |
| 176 | and r10,r5,r10,ror#2 |
| 177 | add r3,r3,r9 @ E+=X[i] |
| 178 | eor r10,r10,r7,ror#2 @ F_00_19(B,C,D) |
| 179 | str r9,[r14,#-4]! |
| 180 | add r3,r3,r10 @ E+=F_00_19(B,C,D) |
| 181 | #if defined(__thumb2__) |
| 182 | mov r12,sp |
| 183 | teq r14,r12 |
| 184 | #else |
| 185 | teq r14,sp |
| 186 | #endif |
| 187 | bne L_00_15 @ [((11+4)*5+2)*3] |
| 188 | sub sp,sp,#25*4 |
| 189 | #if __ARM_ARCH__<7 |
| 190 | ldrb r10,[r1,#2] |
| 191 | ldrb r9,[r1,#3] |
| 192 | ldrb r11,[r1,#1] |
| 193 | add r7,r8,r7,ror#2 @ E+=K_00_19 |
| 194 | ldrb r12,[r1],#4 |
| 195 | orr r9,r9,r10,lsl#8 |
| 196 | eor r10,r5,r6 @ F_xx_xx |
| 197 | orr r9,r9,r11,lsl#16 |
| 198 | add r7,r7,r3,ror#27 @ E+=ROR(A,27) |
| 199 | orr r9,r9,r12,lsl#24 |
| 200 | #else |
| 201 | ldr r9,[r1],#4 @ handles unaligned |
| 202 | add r7,r8,r7,ror#2 @ E+=K_00_19 |
| 203 | eor r10,r5,r6 @ F_xx_xx |
| 204 | add r7,r7,r3,ror#27 @ E+=ROR(A,27) |
| 205 | #ifdef __ARMEL__ |
| 206 | rev r9,r9 @ byte swap |
| 207 | #endif |
| 208 | #endif |
| 209 | and r10,r4,r10,ror#2 |
| 210 | add r7,r7,r9 @ E+=X[i] |
| 211 | eor r10,r10,r6,ror#2 @ F_00_19(B,C,D) |
| 212 | str r9,[r14,#-4]! |
| 213 | add r7,r7,r10 @ E+=F_00_19(B,C,D) |
| 214 | ldr r9,[r14,#15*4] |
| 215 | ldr r10,[r14,#13*4] |
| 216 | ldr r11,[r14,#7*4] |
| 217 | add r6,r8,r6,ror#2 @ E+=K_xx_xx |
| 218 | ldr r12,[r14,#2*4] |
| 219 | eor r9,r9,r10 |
| 220 | eor r11,r11,r12 @ 1 cycle stall |
| 221 | eor r10,r4,r5 @ F_xx_xx |
| 222 | mov r9,r9,ror#31 |
| 223 | add r6,r6,r7,ror#27 @ E+=ROR(A,27) |
| 224 | eor r9,r9,r11,ror#31 |
| 225 | str r9,[r14,#-4]! |
| 226 | and r10,r3,r10,ror#2 @ F_xx_xx |
| 227 | @ F_xx_xx |
| 228 | add r6,r6,r9 @ E+=X[i] |
| 229 | eor r10,r10,r5,ror#2 @ F_00_19(B,C,D) |
| 230 | add r6,r6,r10 @ E+=F_00_19(B,C,D) |
| 231 | ldr r9,[r14,#15*4] |
| 232 | ldr r10,[r14,#13*4] |
| 233 | ldr r11,[r14,#7*4] |
| 234 | add r5,r8,r5,ror#2 @ E+=K_xx_xx |
| 235 | ldr r12,[r14,#2*4] |
| 236 | eor r9,r9,r10 |
| 237 | eor r11,r11,r12 @ 1 cycle stall |
| 238 | eor r10,r3,r4 @ F_xx_xx |
| 239 | mov r9,r9,ror#31 |
| 240 | add r5,r5,r6,ror#27 @ E+=ROR(A,27) |
| 241 | eor r9,r9,r11,ror#31 |
| 242 | str r9,[r14,#-4]! |
| 243 | and r10,r7,r10,ror#2 @ F_xx_xx |
| 244 | @ F_xx_xx |
| 245 | add r5,r5,r9 @ E+=X[i] |
| 246 | eor r10,r10,r4,ror#2 @ F_00_19(B,C,D) |
| 247 | add r5,r5,r10 @ E+=F_00_19(B,C,D) |
| 248 | ldr r9,[r14,#15*4] |
| 249 | ldr r10,[r14,#13*4] |
| 250 | ldr r11,[r14,#7*4] |
| 251 | add r4,r8,r4,ror#2 @ E+=K_xx_xx |
| 252 | ldr r12,[r14,#2*4] |
| 253 | eor r9,r9,r10 |
| 254 | eor r11,r11,r12 @ 1 cycle stall |
| 255 | eor r10,r7,r3 @ F_xx_xx |
| 256 | mov r9,r9,ror#31 |
| 257 | add r4,r4,r5,ror#27 @ E+=ROR(A,27) |
| 258 | eor r9,r9,r11,ror#31 |
| 259 | str r9,[r14,#-4]! |
| 260 | and r10,r6,r10,ror#2 @ F_xx_xx |
| 261 | @ F_xx_xx |
| 262 | add r4,r4,r9 @ E+=X[i] |
| 263 | eor r10,r10,r3,ror#2 @ F_00_19(B,C,D) |
| 264 | add r4,r4,r10 @ E+=F_00_19(B,C,D) |
| 265 | ldr r9,[r14,#15*4] |
| 266 | ldr r10,[r14,#13*4] |
| 267 | ldr r11,[r14,#7*4] |
| 268 | add r3,r8,r3,ror#2 @ E+=K_xx_xx |
| 269 | ldr r12,[r14,#2*4] |
| 270 | eor r9,r9,r10 |
| 271 | eor r11,r11,r12 @ 1 cycle stall |
| 272 | eor r10,r6,r7 @ F_xx_xx |
| 273 | mov r9,r9,ror#31 |
| 274 | add r3,r3,r4,ror#27 @ E+=ROR(A,27) |
| 275 | eor r9,r9,r11,ror#31 |
| 276 | str r9,[r14,#-4]! |
| 277 | and r10,r5,r10,ror#2 @ F_xx_xx |
| 278 | @ F_xx_xx |
| 279 | add r3,r3,r9 @ E+=X[i] |
| 280 | eor r10,r10,r7,ror#2 @ F_00_19(B,C,D) |
| 281 | add r3,r3,r10 @ E+=F_00_19(B,C,D) |
| 282 | |
| 283 | ldr r8,LK_20_39 @ [+15+16*4] |
| 284 | cmn sp,#0 @ [+3], clear carry to denote 20_39 |
| 285 | L_20_39_or_60_79: |
| 286 | ldr r9,[r14,#15*4] |
| 287 | ldr r10,[r14,#13*4] |
| 288 | ldr r11,[r14,#7*4] |
| 289 | add r7,r8,r7,ror#2 @ E+=K_xx_xx |
| 290 | ldr r12,[r14,#2*4] |
| 291 | eor r9,r9,r10 |
| 292 | eor r11,r11,r12 @ 1 cycle stall |
| 293 | eor r10,r5,r6 @ F_xx_xx |
| 294 | mov r9,r9,ror#31 |
| 295 | add r7,r7,r3,ror#27 @ E+=ROR(A,27) |
| 296 | eor r9,r9,r11,ror#31 |
| 297 | str r9,[r14,#-4]! |
| 298 | eor r10,r4,r10,ror#2 @ F_xx_xx |
| 299 | @ F_xx_xx |
| 300 | add r7,r7,r9 @ E+=X[i] |
| 301 | add r7,r7,r10 @ E+=F_20_39(B,C,D) |
| 302 | ldr r9,[r14,#15*4] |
| 303 | ldr r10,[r14,#13*4] |
| 304 | ldr r11,[r14,#7*4] |
| 305 | add r6,r8,r6,ror#2 @ E+=K_xx_xx |
| 306 | ldr r12,[r14,#2*4] |
| 307 | eor r9,r9,r10 |
| 308 | eor r11,r11,r12 @ 1 cycle stall |
| 309 | eor r10,r4,r5 @ F_xx_xx |
| 310 | mov r9,r9,ror#31 |
| 311 | add r6,r6,r7,ror#27 @ E+=ROR(A,27) |
| 312 | eor r9,r9,r11,ror#31 |
| 313 | str r9,[r14,#-4]! |
| 314 | eor r10,r3,r10,ror#2 @ F_xx_xx |
| 315 | @ F_xx_xx |
| 316 | add r6,r6,r9 @ E+=X[i] |
| 317 | add r6,r6,r10 @ E+=F_20_39(B,C,D) |
| 318 | ldr r9,[r14,#15*4] |
| 319 | ldr r10,[r14,#13*4] |
| 320 | ldr r11,[r14,#7*4] |
| 321 | add r5,r8,r5,ror#2 @ E+=K_xx_xx |
| 322 | ldr r12,[r14,#2*4] |
| 323 | eor r9,r9,r10 |
| 324 | eor r11,r11,r12 @ 1 cycle stall |
| 325 | eor r10,r3,r4 @ F_xx_xx |
| 326 | mov r9,r9,ror#31 |
| 327 | add r5,r5,r6,ror#27 @ E+=ROR(A,27) |
| 328 | eor r9,r9,r11,ror#31 |
| 329 | str r9,[r14,#-4]! |
| 330 | eor r10,r7,r10,ror#2 @ F_xx_xx |
| 331 | @ F_xx_xx |
| 332 | add r5,r5,r9 @ E+=X[i] |
| 333 | add r5,r5,r10 @ E+=F_20_39(B,C,D) |
| 334 | ldr r9,[r14,#15*4] |
| 335 | ldr r10,[r14,#13*4] |
| 336 | ldr r11,[r14,#7*4] |
| 337 | add r4,r8,r4,ror#2 @ E+=K_xx_xx |
| 338 | ldr r12,[r14,#2*4] |
| 339 | eor r9,r9,r10 |
| 340 | eor r11,r11,r12 @ 1 cycle stall |
| 341 | eor r10,r7,r3 @ F_xx_xx |
| 342 | mov r9,r9,ror#31 |
| 343 | add r4,r4,r5,ror#27 @ E+=ROR(A,27) |
| 344 | eor r9,r9,r11,ror#31 |
| 345 | str r9,[r14,#-4]! |
| 346 | eor r10,r6,r10,ror#2 @ F_xx_xx |
| 347 | @ F_xx_xx |
| 348 | add r4,r4,r9 @ E+=X[i] |
| 349 | add r4,r4,r10 @ E+=F_20_39(B,C,D) |
| 350 | ldr r9,[r14,#15*4] |
| 351 | ldr r10,[r14,#13*4] |
| 352 | ldr r11,[r14,#7*4] |
| 353 | add r3,r8,r3,ror#2 @ E+=K_xx_xx |
| 354 | ldr r12,[r14,#2*4] |
| 355 | eor r9,r9,r10 |
| 356 | eor r11,r11,r12 @ 1 cycle stall |
| 357 | eor r10,r6,r7 @ F_xx_xx |
| 358 | mov r9,r9,ror#31 |
| 359 | add r3,r3,r4,ror#27 @ E+=ROR(A,27) |
| 360 | eor r9,r9,r11,ror#31 |
| 361 | str r9,[r14,#-4]! |
| 362 | eor r10,r5,r10,ror#2 @ F_xx_xx |
| 363 | @ F_xx_xx |
| 364 | add r3,r3,r9 @ E+=X[i] |
| 365 | add r3,r3,r10 @ E+=F_20_39(B,C,D) |
| 366 | #if defined(__thumb2__) |
| 367 | mov r12,sp |
| 368 | teq r14,r12 |
| 369 | #else |
| 370 | teq r14,sp @ preserve carry |
| 371 | #endif |
| 372 | bne L_20_39_or_60_79 @ [+((12+3)*5+2)*4] |
| 373 | bcs L_done @ [+((12+3)*5+2)*4], spare 300 bytes |
| 374 | |
| 375 | ldr r8,LK_40_59 |
| 376 | sub sp,sp,#20*4 @ [+2] |
| 377 | L_40_59: |
| 378 | ldr r9,[r14,#15*4] |
| 379 | ldr r10,[r14,#13*4] |
| 380 | ldr r11,[r14,#7*4] |
| 381 | add r7,r8,r7,ror#2 @ E+=K_xx_xx |
| 382 | ldr r12,[r14,#2*4] |
| 383 | eor r9,r9,r10 |
| 384 | eor r11,r11,r12 @ 1 cycle stall |
| 385 | eor r10,r5,r6 @ F_xx_xx |
| 386 | mov r9,r9,ror#31 |
| 387 | add r7,r7,r3,ror#27 @ E+=ROR(A,27) |
| 388 | eor r9,r9,r11,ror#31 |
| 389 | str r9,[r14,#-4]! |
| 390 | and r10,r4,r10,ror#2 @ F_xx_xx |
| 391 | and r11,r5,r6 @ F_xx_xx |
| 392 | add r7,r7,r9 @ E+=X[i] |
| 393 | add r7,r7,r10 @ E+=F_40_59(B,C,D) |
| 394 | add r7,r7,r11,ror#2 |
| 395 | ldr r9,[r14,#15*4] |
| 396 | ldr r10,[r14,#13*4] |
| 397 | ldr r11,[r14,#7*4] |
| 398 | add r6,r8,r6,ror#2 @ E+=K_xx_xx |
| 399 | ldr r12,[r14,#2*4] |
| 400 | eor r9,r9,r10 |
| 401 | eor r11,r11,r12 @ 1 cycle stall |
| 402 | eor r10,r4,r5 @ F_xx_xx |
| 403 | mov r9,r9,ror#31 |
| 404 | add r6,r6,r7,ror#27 @ E+=ROR(A,27) |
| 405 | eor r9,r9,r11,ror#31 |
| 406 | str r9,[r14,#-4]! |
| 407 | and r10,r3,r10,ror#2 @ F_xx_xx |
| 408 | and r11,r4,r5 @ F_xx_xx |
| 409 | add r6,r6,r9 @ E+=X[i] |
| 410 | add r6,r6,r10 @ E+=F_40_59(B,C,D) |
| 411 | add r6,r6,r11,ror#2 |
| 412 | ldr r9,[r14,#15*4] |
| 413 | ldr r10,[r14,#13*4] |
| 414 | ldr r11,[r14,#7*4] |
| 415 | add r5,r8,r5,ror#2 @ E+=K_xx_xx |
| 416 | ldr r12,[r14,#2*4] |
| 417 | eor r9,r9,r10 |
| 418 | eor r11,r11,r12 @ 1 cycle stall |
| 419 | eor r10,r3,r4 @ F_xx_xx |
| 420 | mov r9,r9,ror#31 |
| 421 | add r5,r5,r6,ror#27 @ E+=ROR(A,27) |
| 422 | eor r9,r9,r11,ror#31 |
| 423 | str r9,[r14,#-4]! |
| 424 | and r10,r7,r10,ror#2 @ F_xx_xx |
| 425 | and r11,r3,r4 @ F_xx_xx |
| 426 | add r5,r5,r9 @ E+=X[i] |
| 427 | add r5,r5,r10 @ E+=F_40_59(B,C,D) |
| 428 | add r5,r5,r11,ror#2 |
| 429 | ldr r9,[r14,#15*4] |
| 430 | ldr r10,[r14,#13*4] |
| 431 | ldr r11,[r14,#7*4] |
| 432 | add r4,r8,r4,ror#2 @ E+=K_xx_xx |
| 433 | ldr r12,[r14,#2*4] |
| 434 | eor r9,r9,r10 |
| 435 | eor r11,r11,r12 @ 1 cycle stall |
| 436 | eor r10,r7,r3 @ F_xx_xx |
| 437 | mov r9,r9,ror#31 |
| 438 | add r4,r4,r5,ror#27 @ E+=ROR(A,27) |
| 439 | eor r9,r9,r11,ror#31 |
| 440 | str r9,[r14,#-4]! |
| 441 | and r10,r6,r10,ror#2 @ F_xx_xx |
| 442 | and r11,r7,r3 @ F_xx_xx |
| 443 | add r4,r4,r9 @ E+=X[i] |
| 444 | add r4,r4,r10 @ E+=F_40_59(B,C,D) |
| 445 | add r4,r4,r11,ror#2 |
| 446 | ldr r9,[r14,#15*4] |
| 447 | ldr r10,[r14,#13*4] |
| 448 | ldr r11,[r14,#7*4] |
| 449 | add r3,r8,r3,ror#2 @ E+=K_xx_xx |
| 450 | ldr r12,[r14,#2*4] |
| 451 | eor r9,r9,r10 |
| 452 | eor r11,r11,r12 @ 1 cycle stall |
| 453 | eor r10,r6,r7 @ F_xx_xx |
| 454 | mov r9,r9,ror#31 |
| 455 | add r3,r3,r4,ror#27 @ E+=ROR(A,27) |
| 456 | eor r9,r9,r11,ror#31 |
| 457 | str r9,[r14,#-4]! |
| 458 | and r10,r5,r10,ror#2 @ F_xx_xx |
| 459 | and r11,r6,r7 @ F_xx_xx |
| 460 | add r3,r3,r9 @ E+=X[i] |
| 461 | add r3,r3,r10 @ E+=F_40_59(B,C,D) |
| 462 | add r3,r3,r11,ror#2 |
| 463 | #if defined(__thumb2__) |
| 464 | mov r12,sp |
| 465 | teq r14,r12 |
| 466 | #else |
| 467 | teq r14,sp |
| 468 | #endif |
| 469 | bne L_40_59 @ [+((12+5)*5+2)*4] |
| 470 | |
| 471 | ldr r8,LK_60_79 |
| 472 | sub sp,sp,#20*4 |
| 473 | cmp sp,#0 @ set carry to denote 60_79 |
| 474 | b L_20_39_or_60_79 @ [+4], spare 300 bytes |
| 475 | L_done: |
| 476 | add sp,sp,#80*4 @ "deallocate" stack frame |
| 477 | ldmia r0,{r8,r9,r10,r11,r12} |
| 478 | add r3,r8,r3 |
| 479 | add r4,r9,r4 |
| 480 | add r5,r10,r5,ror#2 |
| 481 | add r6,r11,r6,ror#2 |
| 482 | add r7,r12,r7,ror#2 |
| 483 | stmia r0,{r3,r4,r5,r6,r7} |
| 484 | teq r1,r2 |
| 485 | bne Lloop @ [+18], total 1307 |
| 486 | |
| 487 | #if __ARM_ARCH__>=5 |
| 488 | ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,pc} |
| 489 | #else |
| 490 | ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} |
| 491 | tst lr,#1 |
| 492 | moveq pc,lr @ be binary compatible with V4, yet |
| 493 | .word 0xe12fff1e @ interoperable with Thumb ISA:-) |
| 494 | #endif |
| 495 | |
| 496 | |
| 497 | .align 5 |
| 498 | LK_00_19:.word 0x5a827999 |
| 499 | LK_20_39:.word 0x6ed9eba1 |
| 500 | LK_40_59:.word 0x8f1bbcdc |
| 501 | LK_60_79:.word 0xca62c1d6 |
| 502 | #if __ARM_MAX_ARCH__>=7 |
| 503 | LOPENSSL_armcap: |
| 504 | .word OPENSSL_armcap_P-Lsha1_block |
| 505 | #endif |
| 506 | .byte 83,72,65,49,32,98,108,111,99,107,32,116,114,97,110,115,102,111,114,109,32,102,111,114,32,65,82,77,118,52,47,78,69,79,78,47,65,82,77,118,56,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0 |
| 507 | .align 2 |
| 508 | .align 5 |
| 509 | #if __ARM_MAX_ARCH__>=7 |
| 510 | |
| 511 | |
| 512 | |
| 513 | #ifdef __thumb2__ |
| 514 | .thumb_func sha1_block_data_order_neon |
| 515 | #endif |
| 516 | .align 4 |
| 517 | sha1_block_data_order_neon: |
| 518 | LNEON: |
| 519 | stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} |
| 520 | add r2,r1,r2,lsl#6 @ r2 to point at the end of r1 |
| 521 | @ dmb @ errata #451034 on early Cortex A8 |
| 522 | @ vstmdb sp!,{d8-d15} @ ABI specification says so |
| 523 | mov r14,sp |
| 524 | sub r12,sp,#64 |
| 525 | adr r8,LK_00_19 |
| 526 | bic r12,r12,#15 @ align for 128-bit stores |
| 527 | |
| 528 | ldmia r0,{r3,r4,r5,r6,r7} @ load context |
| 529 | mov sp,r12 @ alloca |
| 530 | |
| 531 | vld1.8 {q0,q1},[r1]! @ handles unaligned |
| 532 | veor q15,q15,q15 |
| 533 | vld1.8 {q2,q3},[r1]! |
| 534 | vld1.32 {d28[],d29[]},[r8,:32]! @ load K_00_19 |
| 535 | vrev32.8 q0,q0 @ yes, even on |
| 536 | vrev32.8 q1,q1 @ big-endian... |
| 537 | vrev32.8 q2,q2 |
| 538 | vadd.i32 q8,q0,q14 |
| 539 | vrev32.8 q3,q3 |
| 540 | vadd.i32 q9,q1,q14 |
| 541 | vst1.32 {q8},[r12,:128]! |
| 542 | vadd.i32 q10,q2,q14 |
| 543 | vst1.32 {q9},[r12,:128]! |
| 544 | vst1.32 {q10},[r12,:128]! |
| 545 | ldr r9,[sp] @ big RAW stall |
| 546 | |
| 547 | Loop_neon: |
| 548 | vext.8 q8,q0,q1,#8 |
| 549 | bic r10,r6,r4 |
| 550 | add r7,r7,r9 |
| 551 | and r11,r5,r4 |
| 552 | vadd.i32 q13,q3,q14 |
| 553 | ldr r9,[sp,#4] |
| 554 | add r7,r7,r3,ror#27 |
| 555 | vext.8 q12,q3,q15,#4 |
| 556 | eor r11,r11,r10 |
| 557 | mov r4,r4,ror#2 |
| 558 | add r7,r7,r11 |
| 559 | veor q8,q8,q0 |
| 560 | bic r10,r5,r3 |
| 561 | add r6,r6,r9 |
| 562 | veor q12,q12,q2 |
| 563 | and r11,r4,r3 |
| 564 | ldr r9,[sp,#8] |
| 565 | veor q12,q12,q8 |
| 566 | add r6,r6,r7,ror#27 |
| 567 | eor r11,r11,r10 |
| 568 | vst1.32 {q13},[r12,:128]! |
| 569 | sub r12,r12,#64 |
| 570 | mov r3,r3,ror#2 |
| 571 | add r6,r6,r11 |
| 572 | vext.8 q13,q15,q12,#4 |
| 573 | bic r10,r4,r7 |
| 574 | add r5,r5,r9 |
| 575 | vadd.i32 q8,q12,q12 |
| 576 | and r11,r3,r7 |
| 577 | ldr r9,[sp,#12] |
| 578 | vsri.32 q8,q12,#31 |
| 579 | add r5,r5,r6,ror#27 |
| 580 | eor r11,r11,r10 |
| 581 | mov r7,r7,ror#2 |
| 582 | vshr.u32 q12,q13,#30 |
| 583 | add r5,r5,r11 |
| 584 | bic r10,r3,r6 |
| 585 | vshl.u32 q13,q13,#2 |
| 586 | add r4,r4,r9 |
| 587 | and r11,r7,r6 |
| 588 | veor q8,q8,q12 |
| 589 | ldr r9,[sp,#16] |
| 590 | add r4,r4,r5,ror#27 |
| 591 | veor q8,q8,q13 |
| 592 | eor r11,r11,r10 |
| 593 | mov r6,r6,ror#2 |
| 594 | add r4,r4,r11 |
| 595 | vext.8 q9,q1,q2,#8 |
| 596 | bic r10,r7,r5 |
| 597 | add r3,r3,r9 |
| 598 | and r11,r6,r5 |
| 599 | vadd.i32 q13,q8,q14 |
| 600 | ldr r9,[sp,#20] |
| 601 | vld1.32 {d28[],d29[]},[r8,:32]! |
| 602 | add r3,r3,r4,ror#27 |
| 603 | vext.8 q12,q8,q15,#4 |
| 604 | eor r11,r11,r10 |
| 605 | mov r5,r5,ror#2 |
| 606 | add r3,r3,r11 |
| 607 | veor q9,q9,q1 |
| 608 | bic r10,r6,r4 |
| 609 | add r7,r7,r9 |
| 610 | veor q12,q12,q3 |
| 611 | and r11,r5,r4 |
| 612 | ldr r9,[sp,#24] |
| 613 | veor q12,q12,q9 |
| 614 | add r7,r7,r3,ror#27 |
| 615 | eor r11,r11,r10 |
| 616 | vst1.32 {q13},[r12,:128]! |
| 617 | mov r4,r4,ror#2 |
| 618 | add r7,r7,r11 |
| 619 | vext.8 q13,q15,q12,#4 |
| 620 | bic r10,r5,r3 |
| 621 | add r6,r6,r9 |
| 622 | vadd.i32 q9,q12,q12 |
| 623 | and r11,r4,r3 |
| 624 | ldr r9,[sp,#28] |
| 625 | vsri.32 q9,q12,#31 |
| 626 | add r6,r6,r7,ror#27 |
| 627 | eor r11,r11,r10 |
| 628 | mov r3,r3,ror#2 |
| 629 | vshr.u32 q12,q13,#30 |
| 630 | add r6,r6,r11 |
| 631 | bic r10,r4,r7 |
| 632 | vshl.u32 q13,q13,#2 |
| 633 | add r5,r5,r9 |
| 634 | and r11,r3,r7 |
| 635 | veor q9,q9,q12 |
| 636 | ldr r9,[sp,#32] |
| 637 | add r5,r5,r6,ror#27 |
| 638 | veor q9,q9,q13 |
| 639 | eor r11,r11,r10 |
| 640 | mov r7,r7,ror#2 |
| 641 | add r5,r5,r11 |
| 642 | vext.8 q10,q2,q3,#8 |
| 643 | bic r10,r3,r6 |
| 644 | add r4,r4,r9 |
| 645 | and r11,r7,r6 |
| 646 | vadd.i32 q13,q9,q14 |
| 647 | ldr r9,[sp,#36] |
| 648 | add r4,r4,r5,ror#27 |
| 649 | vext.8 q12,q9,q15,#4 |
| 650 | eor r11,r11,r10 |
| 651 | mov r6,r6,ror#2 |
| 652 | add r4,r4,r11 |
| 653 | veor q10,q10,q2 |
| 654 | bic r10,r7,r5 |
| 655 | add r3,r3,r9 |
| 656 | veor q12,q12,q8 |
| 657 | and r11,r6,r5 |
| 658 | ldr r9,[sp,#40] |
| 659 | veor q12,q12,q10 |
| 660 | add r3,r3,r4,ror#27 |
| 661 | eor r11,r11,r10 |
| 662 | vst1.32 {q13},[r12,:128]! |
| 663 | mov r5,r5,ror#2 |
| 664 | add r3,r3,r11 |
| 665 | vext.8 q13,q15,q12,#4 |
| 666 | bic r10,r6,r4 |
| 667 | add r7,r7,r9 |
| 668 | vadd.i32 q10,q12,q12 |
| 669 | and r11,r5,r4 |
| 670 | ldr r9,[sp,#44] |
| 671 | vsri.32 q10,q12,#31 |
| 672 | add r7,r7,r3,ror#27 |
| 673 | eor r11,r11,r10 |
| 674 | mov r4,r4,ror#2 |
| 675 | vshr.u32 q12,q13,#30 |
| 676 | add r7,r7,r11 |
| 677 | bic r10,r5,r3 |
| 678 | vshl.u32 q13,q13,#2 |
| 679 | add r6,r6,r9 |
| 680 | and r11,r4,r3 |
| 681 | veor q10,q10,q12 |
| 682 | ldr r9,[sp,#48] |
| 683 | add r6,r6,r7,ror#27 |
| 684 | veor q10,q10,q13 |
| 685 | eor r11,r11,r10 |
| 686 | mov r3,r3,ror#2 |
| 687 | add r6,r6,r11 |
| 688 | vext.8 q11,q3,q8,#8 |
| 689 | bic r10,r4,r7 |
| 690 | add r5,r5,r9 |
| 691 | and r11,r3,r7 |
| 692 | vadd.i32 q13,q10,q14 |
| 693 | ldr r9,[sp,#52] |
| 694 | add r5,r5,r6,ror#27 |
| 695 | vext.8 q12,q10,q15,#4 |
| 696 | eor r11,r11,r10 |
| 697 | mov r7,r7,ror#2 |
| 698 | add r5,r5,r11 |
| 699 | veor q11,q11,q3 |
| 700 | bic r10,r3,r6 |
| 701 | add r4,r4,r9 |
| 702 | veor q12,q12,q9 |
| 703 | and r11,r7,r6 |
| 704 | ldr r9,[sp,#56] |
| 705 | veor q12,q12,q11 |
| 706 | add r4,r4,r5,ror#27 |
| 707 | eor r11,r11,r10 |
| 708 | vst1.32 {q13},[r12,:128]! |
| 709 | mov r6,r6,ror#2 |
| 710 | add r4,r4,r11 |
| 711 | vext.8 q13,q15,q12,#4 |
| 712 | bic r10,r7,r5 |
| 713 | add r3,r3,r9 |
| 714 | vadd.i32 q11,q12,q12 |
| 715 | and r11,r6,r5 |
| 716 | ldr r9,[sp,#60] |
| 717 | vsri.32 q11,q12,#31 |
| 718 | add r3,r3,r4,ror#27 |
| 719 | eor r11,r11,r10 |
| 720 | mov r5,r5,ror#2 |
| 721 | vshr.u32 q12,q13,#30 |
| 722 | add r3,r3,r11 |
| 723 | bic r10,r6,r4 |
| 724 | vshl.u32 q13,q13,#2 |
| 725 | add r7,r7,r9 |
| 726 | and r11,r5,r4 |
| 727 | veor q11,q11,q12 |
| 728 | ldr r9,[sp,#0] |
| 729 | add r7,r7,r3,ror#27 |
| 730 | veor q11,q11,q13 |
| 731 | eor r11,r11,r10 |
| 732 | mov r4,r4,ror#2 |
| 733 | add r7,r7,r11 |
| 734 | vext.8 q12,q10,q11,#8 |
| 735 | bic r10,r5,r3 |
| 736 | add r6,r6,r9 |
| 737 | and r11,r4,r3 |
| 738 | veor q0,q0,q8 |
| 739 | ldr r9,[sp,#4] |
| 740 | add r6,r6,r7,ror#27 |
| 741 | veor q0,q0,q1 |
| 742 | eor r11,r11,r10 |
| 743 | mov r3,r3,ror#2 |
| 744 | vadd.i32 q13,q11,q14 |
| 745 | add r6,r6,r11 |
| 746 | bic r10,r4,r7 |
| 747 | veor q12,q12,q0 |
| 748 | add r5,r5,r9 |
| 749 | and r11,r3,r7 |
| 750 | vshr.u32 q0,q12,#30 |
| 751 | ldr r9,[sp,#8] |
| 752 | add r5,r5,r6,ror#27 |
| 753 | vst1.32 {q13},[r12,:128]! |
| 754 | sub r12,r12,#64 |
| 755 | eor r11,r11,r10 |
| 756 | mov r7,r7,ror#2 |
| 757 | vsli.32 q0,q12,#2 |
| 758 | add r5,r5,r11 |
| 759 | bic r10,r3,r6 |
| 760 | add r4,r4,r9 |
| 761 | and r11,r7,r6 |
| 762 | ldr r9,[sp,#12] |
| 763 | add r4,r4,r5,ror#27 |
| 764 | eor r11,r11,r10 |
| 765 | mov r6,r6,ror#2 |
| 766 | add r4,r4,r11 |
| 767 | bic r10,r7,r5 |
| 768 | add r3,r3,r9 |
| 769 | and r11,r6,r5 |
| 770 | ldr r9,[sp,#16] |
| 771 | add r3,r3,r4,ror#27 |
| 772 | eor r11,r11,r10 |
| 773 | mov r5,r5,ror#2 |
| 774 | add r3,r3,r11 |
| 775 | vext.8 q12,q11,q0,#8 |
| 776 | eor r10,r4,r6 |
| 777 | add r7,r7,r9 |
| 778 | ldr r9,[sp,#20] |
| 779 | veor q1,q1,q9 |
| 780 | eor r11,r10,r5 |
| 781 | add r7,r7,r3,ror#27 |
| 782 | veor q1,q1,q2 |
| 783 | mov r4,r4,ror#2 |
| 784 | add r7,r7,r11 |
| 785 | vadd.i32 q13,q0,q14 |
| 786 | eor r10,r3,r5 |
| 787 | add r6,r6,r9 |
| 788 | veor q12,q12,q1 |
| 789 | ldr r9,[sp,#24] |
| 790 | eor r11,r10,r4 |
| 791 | vshr.u32 q1,q12,#30 |
| 792 | add r6,r6,r7,ror#27 |
| 793 | mov r3,r3,ror#2 |
| 794 | vst1.32 {q13},[r12,:128]! |
| 795 | add r6,r6,r11 |
| 796 | eor r10,r7,r4 |
| 797 | vsli.32 q1,q12,#2 |
| 798 | add r5,r5,r9 |
| 799 | ldr r9,[sp,#28] |
| 800 | eor r11,r10,r3 |
| 801 | add r5,r5,r6,ror#27 |
| 802 | mov r7,r7,ror#2 |
| 803 | add r5,r5,r11 |
| 804 | eor r10,r6,r3 |
| 805 | add r4,r4,r9 |
| 806 | ldr r9,[sp,#32] |
| 807 | eor r11,r10,r7 |
| 808 | add r4,r4,r5,ror#27 |
| 809 | mov r6,r6,ror#2 |
| 810 | add r4,r4,r11 |
| 811 | vext.8 q12,q0,q1,#8 |
| 812 | eor r10,r5,r7 |
| 813 | add r3,r3,r9 |
| 814 | ldr r9,[sp,#36] |
| 815 | veor q2,q2,q10 |
| 816 | eor r11,r10,r6 |
| 817 | add r3,r3,r4,ror#27 |
| 818 | veor q2,q2,q3 |
| 819 | mov r5,r5,ror#2 |
| 820 | add r3,r3,r11 |
| 821 | vadd.i32 q13,q1,q14 |
| 822 | eor r10,r4,r6 |
| 823 | vld1.32 {d28[],d29[]},[r8,:32]! |
| 824 | add r7,r7,r9 |
| 825 | veor q12,q12,q2 |
| 826 | ldr r9,[sp,#40] |
| 827 | eor r11,r10,r5 |
| 828 | vshr.u32 q2,q12,#30 |
| 829 | add r7,r7,r3,ror#27 |
| 830 | mov r4,r4,ror#2 |
| 831 | vst1.32 {q13},[r12,:128]! |
| 832 | add r7,r7,r11 |
| 833 | eor r10,r3,r5 |
| 834 | vsli.32 q2,q12,#2 |
| 835 | add r6,r6,r9 |
| 836 | ldr r9,[sp,#44] |
| 837 | eor r11,r10,r4 |
| 838 | add r6,r6,r7,ror#27 |
| 839 | mov r3,r3,ror#2 |
| 840 | add r6,r6,r11 |
| 841 | eor r10,r7,r4 |
| 842 | add r5,r5,r9 |
| 843 | ldr r9,[sp,#48] |
| 844 | eor r11,r10,r3 |
| 845 | add r5,r5,r6,ror#27 |
| 846 | mov r7,r7,ror#2 |
| 847 | add r5,r5,r11 |
| 848 | vext.8 q12,q1,q2,#8 |
| 849 | eor r10,r6,r3 |
| 850 | add r4,r4,r9 |
| 851 | ldr r9,[sp,#52] |
| 852 | veor q3,q3,q11 |
| 853 | eor r11,r10,r7 |
| 854 | add r4,r4,r5,ror#27 |
| 855 | veor q3,q3,q8 |
| 856 | mov r6,r6,ror#2 |
| 857 | add r4,r4,r11 |
| 858 | vadd.i32 q13,q2,q14 |
| 859 | eor r10,r5,r7 |
| 860 | add r3,r3,r9 |
| 861 | veor q12,q12,q3 |
| 862 | ldr r9,[sp,#56] |
| 863 | eor r11,r10,r6 |
| 864 | vshr.u32 q3,q12,#30 |
| 865 | add r3,r3,r4,ror#27 |
| 866 | mov r5,r5,ror#2 |
| 867 | vst1.32 {q13},[r12,:128]! |
| 868 | add r3,r3,r11 |
| 869 | eor r10,r4,r6 |
| 870 | vsli.32 q3,q12,#2 |
| 871 | add r7,r7,r9 |
| 872 | ldr r9,[sp,#60] |
| 873 | eor r11,r10,r5 |
| 874 | add r7,r7,r3,ror#27 |
| 875 | mov r4,r4,ror#2 |
| 876 | add r7,r7,r11 |
| 877 | eor r10,r3,r5 |
| 878 | add r6,r6,r9 |
| 879 | ldr r9,[sp,#0] |
| 880 | eor r11,r10,r4 |
| 881 | add r6,r6,r7,ror#27 |
| 882 | mov r3,r3,ror#2 |
| 883 | add r6,r6,r11 |
| 884 | vext.8 q12,q2,q3,#8 |
| 885 | eor r10,r7,r4 |
| 886 | add r5,r5,r9 |
| 887 | ldr r9,[sp,#4] |
| 888 | veor q8,q8,q0 |
| 889 | eor r11,r10,r3 |
| 890 | add r5,r5,r6,ror#27 |
| 891 | veor q8,q8,q9 |
| 892 | mov r7,r7,ror#2 |
| 893 | add r5,r5,r11 |
| 894 | vadd.i32 q13,q3,q14 |
| 895 | eor r10,r6,r3 |
| 896 | add r4,r4,r9 |
| 897 | veor q12,q12,q8 |
| 898 | ldr r9,[sp,#8] |
| 899 | eor r11,r10,r7 |
| 900 | vshr.u32 q8,q12,#30 |
| 901 | add r4,r4,r5,ror#27 |
| 902 | mov r6,r6,ror#2 |
| 903 | vst1.32 {q13},[r12,:128]! |
| 904 | sub r12,r12,#64 |
| 905 | add r4,r4,r11 |
| 906 | eor r10,r5,r7 |
| 907 | vsli.32 q8,q12,#2 |
| 908 | add r3,r3,r9 |
| 909 | ldr r9,[sp,#12] |
| 910 | eor r11,r10,r6 |
| 911 | add r3,r3,r4,ror#27 |
| 912 | mov r5,r5,ror#2 |
| 913 | add r3,r3,r11 |
| 914 | eor r10,r4,r6 |
| 915 | add r7,r7,r9 |
| 916 | ldr r9,[sp,#16] |
| 917 | eor r11,r10,r5 |
| 918 | add r7,r7,r3,ror#27 |
| 919 | mov r4,r4,ror#2 |
| 920 | add r7,r7,r11 |
| 921 | vext.8 q12,q3,q8,#8 |
| 922 | eor r10,r3,r5 |
| 923 | add r6,r6,r9 |
| 924 | ldr r9,[sp,#20] |
| 925 | veor q9,q9,q1 |
| 926 | eor r11,r10,r4 |
| 927 | add r6,r6,r7,ror#27 |
| 928 | veor q9,q9,q10 |
| 929 | mov r3,r3,ror#2 |
| 930 | add r6,r6,r11 |
| 931 | vadd.i32 q13,q8,q14 |
| 932 | eor r10,r7,r4 |
| 933 | add r5,r5,r9 |
| 934 | veor q12,q12,q9 |
| 935 | ldr r9,[sp,#24] |
| 936 | eor r11,r10,r3 |
| 937 | vshr.u32 q9,q12,#30 |
| 938 | add r5,r5,r6,ror#27 |
| 939 | mov r7,r7,ror#2 |
| 940 | vst1.32 {q13},[r12,:128]! |
| 941 | add r5,r5,r11 |
| 942 | eor r10,r6,r3 |
| 943 | vsli.32 q9,q12,#2 |
| 944 | add r4,r4,r9 |
| 945 | ldr r9,[sp,#28] |
| 946 | eor r11,r10,r7 |
| 947 | add r4,r4,r5,ror#27 |
| 948 | mov r6,r6,ror#2 |
| 949 | add r4,r4,r11 |
| 950 | eor r10,r5,r7 |
| 951 | add r3,r3,r9 |
| 952 | ldr r9,[sp,#32] |
| 953 | eor r11,r10,r6 |
| 954 | add r3,r3,r4,ror#27 |
| 955 | mov r5,r5,ror#2 |
| 956 | add r3,r3,r11 |
| 957 | vext.8 q12,q8,q9,#8 |
| 958 | add r7,r7,r9 |
| 959 | and r10,r5,r6 |
| 960 | ldr r9,[sp,#36] |
| 961 | veor q10,q10,q2 |
| 962 | add r7,r7,r3,ror#27 |
| 963 | eor r11,r5,r6 |
| 964 | veor q10,q10,q11 |
| 965 | add r7,r7,r10 |
| 966 | and r11,r11,r4 |
| 967 | vadd.i32 q13,q9,q14 |
| 968 | mov r4,r4,ror#2 |
| 969 | add r7,r7,r11 |
| 970 | veor q12,q12,q10 |
| 971 | add r6,r6,r9 |
| 972 | and r10,r4,r5 |
| 973 | vshr.u32 q10,q12,#30 |
| 974 | ldr r9,[sp,#40] |
| 975 | add r6,r6,r7,ror#27 |
| 976 | vst1.32 {q13},[r12,:128]! |
| 977 | eor r11,r4,r5 |
| 978 | add r6,r6,r10 |
| 979 | vsli.32 q10,q12,#2 |
| 980 | and r11,r11,r3 |
| 981 | mov r3,r3,ror#2 |
| 982 | add r6,r6,r11 |
| 983 | add r5,r5,r9 |
| 984 | and r10,r3,r4 |
| 985 | ldr r9,[sp,#44] |
| 986 | add r5,r5,r6,ror#27 |
| 987 | eor r11,r3,r4 |
| 988 | add r5,r5,r10 |
| 989 | and r11,r11,r7 |
| 990 | mov r7,r7,ror#2 |
| 991 | add r5,r5,r11 |
| 992 | add r4,r4,r9 |
| 993 | and r10,r7,r3 |
| 994 | ldr r9,[sp,#48] |
| 995 | add r4,r4,r5,ror#27 |
| 996 | eor r11,r7,r3 |
| 997 | add r4,r4,r10 |
| 998 | and r11,r11,r6 |
| 999 | mov r6,r6,ror#2 |
| 1000 | add r4,r4,r11 |
| 1001 | vext.8 q12,q9,q10,#8 |
| 1002 | add r3,r3,r9 |
| 1003 | and r10,r6,r7 |
| 1004 | ldr r9,[sp,#52] |
| 1005 | veor q11,q11,q3 |
| 1006 | add r3,r3,r4,ror#27 |
| 1007 | eor r11,r6,r7 |
| 1008 | veor q11,q11,q0 |
| 1009 | add r3,r3,r10 |
| 1010 | and r11,r11,r5 |
| 1011 | vadd.i32 q13,q10,q14 |
| 1012 | mov r5,r5,ror#2 |
| 1013 | vld1.32 {d28[],d29[]},[r8,:32]! |
| 1014 | add r3,r3,r11 |
| 1015 | veor q12,q12,q11 |
| 1016 | add r7,r7,r9 |
| 1017 | and r10,r5,r6 |
| 1018 | vshr.u32 q11,q12,#30 |
| 1019 | ldr r9,[sp,#56] |
| 1020 | add r7,r7,r3,ror#27 |
| 1021 | vst1.32 {q13},[r12,:128]! |
| 1022 | eor r11,r5,r6 |
| 1023 | add r7,r7,r10 |
| 1024 | vsli.32 q11,q12,#2 |
| 1025 | and r11,r11,r4 |
| 1026 | mov r4,r4,ror#2 |
| 1027 | add r7,r7,r11 |
| 1028 | add r6,r6,r9 |
| 1029 | and r10,r4,r5 |
| 1030 | ldr r9,[sp,#60] |
| 1031 | add r6,r6,r7,ror#27 |
| 1032 | eor r11,r4,r5 |
| 1033 | add r6,r6,r10 |
| 1034 | and r11,r11,r3 |
| 1035 | mov r3,r3,ror#2 |
| 1036 | add r6,r6,r11 |
| 1037 | add r5,r5,r9 |
| 1038 | and r10,r3,r4 |
| 1039 | ldr r9,[sp,#0] |
| 1040 | add r5,r5,r6,ror#27 |
| 1041 | eor r11,r3,r4 |
| 1042 | add r5,r5,r10 |
| 1043 | and r11,r11,r7 |
| 1044 | mov r7,r7,ror#2 |
| 1045 | add r5,r5,r11 |
| 1046 | vext.8 q12,q10,q11,#8 |
| 1047 | add r4,r4,r9 |
| 1048 | and r10,r7,r3 |
| 1049 | ldr r9,[sp,#4] |
| 1050 | veor q0,q0,q8 |
| 1051 | add r4,r4,r5,ror#27 |
| 1052 | eor r11,r7,r3 |
| 1053 | veor q0,q0,q1 |
| 1054 | add r4,r4,r10 |
| 1055 | and r11,r11,r6 |
| 1056 | vadd.i32 q13,q11,q14 |
| 1057 | mov r6,r6,ror#2 |
| 1058 | add r4,r4,r11 |
| 1059 | veor q12,q12,q0 |
| 1060 | add r3,r3,r9 |
| 1061 | and r10,r6,r7 |
| 1062 | vshr.u32 q0,q12,#30 |
| 1063 | ldr r9,[sp,#8] |
| 1064 | add r3,r3,r4,ror#27 |
| 1065 | vst1.32 {q13},[r12,:128]! |
| 1066 | sub r12,r12,#64 |
| 1067 | eor r11,r6,r7 |
| 1068 | add r3,r3,r10 |
| 1069 | vsli.32 q0,q12,#2 |
| 1070 | and r11,r11,r5 |
| 1071 | mov r5,r5,ror#2 |
| 1072 | add r3,r3,r11 |
| 1073 | add r7,r7,r9 |
| 1074 | and r10,r5,r6 |
| 1075 | ldr r9,[sp,#12] |
| 1076 | add r7,r7,r3,ror#27 |
| 1077 | eor r11,r5,r6 |
| 1078 | add r7,r7,r10 |
| 1079 | and r11,r11,r4 |
| 1080 | mov r4,r4,ror#2 |
| 1081 | add r7,r7,r11 |
| 1082 | add r6,r6,r9 |
| 1083 | and r10,r4,r5 |
| 1084 | ldr r9,[sp,#16] |
| 1085 | add r6,r6,r7,ror#27 |
| 1086 | eor r11,r4,r5 |
| 1087 | add r6,r6,r10 |
| 1088 | and r11,r11,r3 |
| 1089 | mov r3,r3,ror#2 |
| 1090 | add r6,r6,r11 |
| 1091 | vext.8 q12,q11,q0,#8 |
| 1092 | add r5,r5,r9 |
| 1093 | and r10,r3,r4 |
| 1094 | ldr r9,[sp,#20] |
| 1095 | veor q1,q1,q9 |
| 1096 | add r5,r5,r6,ror#27 |
| 1097 | eor r11,r3,r4 |
| 1098 | veor q1,q1,q2 |
| 1099 | add r5,r5,r10 |
| 1100 | and r11,r11,r7 |
| 1101 | vadd.i32 q13,q0,q14 |
| 1102 | mov r7,r7,ror#2 |
| 1103 | add r5,r5,r11 |
| 1104 | veor q12,q12,q1 |
| 1105 | add r4,r4,r9 |
| 1106 | and r10,r7,r3 |
| 1107 | vshr.u32 q1,q12,#30 |
| 1108 | ldr r9,[sp,#24] |
| 1109 | add r4,r4,r5,ror#27 |
| 1110 | vst1.32 {q13},[r12,:128]! |
| 1111 | eor r11,r7,r3 |
| 1112 | add r4,r4,r10 |
| 1113 | vsli.32 q1,q12,#2 |
| 1114 | and r11,r11,r6 |
| 1115 | mov r6,r6,ror#2 |
| 1116 | add r4,r4,r11 |
| 1117 | add r3,r3,r9 |
| 1118 | and r10,r6,r7 |
| 1119 | ldr r9,[sp,#28] |
| 1120 | add r3,r3,r4,ror#27 |
| 1121 | eor r11,r6,r7 |
| 1122 | add r3,r3,r10 |
| 1123 | and r11,r11,r5 |
| 1124 | mov r5,r5,ror#2 |
| 1125 | add r3,r3,r11 |
| 1126 | add r7,r7,r9 |
| 1127 | and r10,r5,r6 |
| 1128 | ldr r9,[sp,#32] |
| 1129 | add r7,r7,r3,ror#27 |
| 1130 | eor r11,r5,r6 |
| 1131 | add r7,r7,r10 |
| 1132 | and r11,r11,r4 |
| 1133 | mov r4,r4,ror#2 |
| 1134 | add r7,r7,r11 |
| 1135 | vext.8 q12,q0,q1,#8 |
| 1136 | add r6,r6,r9 |
| 1137 | and r10,r4,r5 |
| 1138 | ldr r9,[sp,#36] |
| 1139 | veor q2,q2,q10 |
| 1140 | add r6,r6,r7,ror#27 |
| 1141 | eor r11,r4,r5 |
| 1142 | veor q2,q2,q3 |
| 1143 | add r6,r6,r10 |
| 1144 | and r11,r11,r3 |
| 1145 | vadd.i32 q13,q1,q14 |
| 1146 | mov r3,r3,ror#2 |
| 1147 | add r6,r6,r11 |
| 1148 | veor q12,q12,q2 |
| 1149 | add r5,r5,r9 |
| 1150 | and r10,r3,r4 |
| 1151 | vshr.u32 q2,q12,#30 |
| 1152 | ldr r9,[sp,#40] |
| 1153 | add r5,r5,r6,ror#27 |
| 1154 | vst1.32 {q13},[r12,:128]! |
| 1155 | eor r11,r3,r4 |
| 1156 | add r5,r5,r10 |
| 1157 | vsli.32 q2,q12,#2 |
| 1158 | and r11,r11,r7 |
| 1159 | mov r7,r7,ror#2 |
| 1160 | add r5,r5,r11 |
| 1161 | add r4,r4,r9 |
| 1162 | and r10,r7,r3 |
| 1163 | ldr r9,[sp,#44] |
| 1164 | add r4,r4,r5,ror#27 |
| 1165 | eor r11,r7,r3 |
| 1166 | add r4,r4,r10 |
| 1167 | and r11,r11,r6 |
| 1168 | mov r6,r6,ror#2 |
| 1169 | add r4,r4,r11 |
| 1170 | add r3,r3,r9 |
| 1171 | and r10,r6,r7 |
| 1172 | ldr r9,[sp,#48] |
| 1173 | add r3,r3,r4,ror#27 |
| 1174 | eor r11,r6,r7 |
| 1175 | add r3,r3,r10 |
| 1176 | and r11,r11,r5 |
| 1177 | mov r5,r5,ror#2 |
| 1178 | add r3,r3,r11 |
| 1179 | vext.8 q12,q1,q2,#8 |
| 1180 | eor r10,r4,r6 |
| 1181 | add r7,r7,r9 |
| 1182 | ldr r9,[sp,#52] |
| 1183 | veor q3,q3,q11 |
| 1184 | eor r11,r10,r5 |
| 1185 | add r7,r7,r3,ror#27 |
| 1186 | veor q3,q3,q8 |
| 1187 | mov r4,r4,ror#2 |
| 1188 | add r7,r7,r11 |
| 1189 | vadd.i32 q13,q2,q14 |
| 1190 | eor r10,r3,r5 |
| 1191 | add r6,r6,r9 |
| 1192 | veor q12,q12,q3 |
| 1193 | ldr r9,[sp,#56] |
| 1194 | eor r11,r10,r4 |
| 1195 | vshr.u32 q3,q12,#30 |
| 1196 | add r6,r6,r7,ror#27 |
| 1197 | mov r3,r3,ror#2 |
| 1198 | vst1.32 {q13},[r12,:128]! |
| 1199 | add r6,r6,r11 |
| 1200 | eor r10,r7,r4 |
| 1201 | vsli.32 q3,q12,#2 |
| 1202 | add r5,r5,r9 |
| 1203 | ldr r9,[sp,#60] |
| 1204 | eor r11,r10,r3 |
| 1205 | add r5,r5,r6,ror#27 |
| 1206 | mov r7,r7,ror#2 |
| 1207 | add r5,r5,r11 |
| 1208 | eor r10,r6,r3 |
| 1209 | add r4,r4,r9 |
| 1210 | ldr r9,[sp,#0] |
| 1211 | eor r11,r10,r7 |
| 1212 | add r4,r4,r5,ror#27 |
| 1213 | mov r6,r6,ror#2 |
| 1214 | add r4,r4,r11 |
| 1215 | vadd.i32 q13,q3,q14 |
| 1216 | eor r10,r5,r7 |
| 1217 | add r3,r3,r9 |
| 1218 | vst1.32 {q13},[r12,:128]! |
| 1219 | sub r12,r12,#64 |
| 1220 | teq r1,r2 |
| 1221 | sub r8,r8,#16 |
| 1222 | it eq |
| 1223 | subeq r1,r1,#64 |
| 1224 | vld1.8 {q0,q1},[r1]! |
| 1225 | ldr r9,[sp,#4] |
| 1226 | eor r11,r10,r6 |
| 1227 | vld1.8 {q2,q3},[r1]! |
| 1228 | add r3,r3,r4,ror#27 |
| 1229 | mov r5,r5,ror#2 |
| 1230 | vld1.32 {d28[],d29[]},[r8,:32]! |
| 1231 | add r3,r3,r11 |
| 1232 | eor r10,r4,r6 |
| 1233 | vrev32.8 q0,q0 |
| 1234 | add r7,r7,r9 |
| 1235 | ldr r9,[sp,#8] |
| 1236 | eor r11,r10,r5 |
| 1237 | add r7,r7,r3,ror#27 |
| 1238 | mov r4,r4,ror#2 |
| 1239 | add r7,r7,r11 |
| 1240 | eor r10,r3,r5 |
| 1241 | add r6,r6,r9 |
| 1242 | ldr r9,[sp,#12] |
| 1243 | eor r11,r10,r4 |
| 1244 | add r6,r6,r7,ror#27 |
| 1245 | mov r3,r3,ror#2 |
| 1246 | add r6,r6,r11 |
| 1247 | eor r10,r7,r4 |
| 1248 | add r5,r5,r9 |
| 1249 | ldr r9,[sp,#16] |
| 1250 | eor r11,r10,r3 |
| 1251 | add r5,r5,r6,ror#27 |
| 1252 | mov r7,r7,ror#2 |
| 1253 | add r5,r5,r11 |
| 1254 | vrev32.8 q1,q1 |
| 1255 | eor r10,r6,r3 |
| 1256 | add r4,r4,r9 |
| 1257 | vadd.i32 q8,q0,q14 |
| 1258 | ldr r9,[sp,#20] |
| 1259 | eor r11,r10,r7 |
| 1260 | vst1.32 {q8},[r12,:128]! |
| 1261 | add r4,r4,r5,ror#27 |
| 1262 | mov r6,r6,ror#2 |
| 1263 | add r4,r4,r11 |
| 1264 | eor r10,r5,r7 |
| 1265 | add r3,r3,r9 |
| 1266 | ldr r9,[sp,#24] |
| 1267 | eor r11,r10,r6 |
| 1268 | add r3,r3,r4,ror#27 |
| 1269 | mov r5,r5,ror#2 |
| 1270 | add r3,r3,r11 |
| 1271 | eor r10,r4,r6 |
| 1272 | add r7,r7,r9 |
| 1273 | ldr r9,[sp,#28] |
| 1274 | eor r11,r10,r5 |
| 1275 | add r7,r7,r3,ror#27 |
| 1276 | mov r4,r4,ror#2 |
| 1277 | add r7,r7,r11 |
| 1278 | eor r10,r3,r5 |
| 1279 | add r6,r6,r9 |
| 1280 | ldr r9,[sp,#32] |
| 1281 | eor r11,r10,r4 |
| 1282 | add r6,r6,r7,ror#27 |
| 1283 | mov r3,r3,ror#2 |
| 1284 | add r6,r6,r11 |
| 1285 | vrev32.8 q2,q2 |
| 1286 | eor r10,r7,r4 |
| 1287 | add r5,r5,r9 |
| 1288 | vadd.i32 q9,q1,q14 |
| 1289 | ldr r9,[sp,#36] |
| 1290 | eor r11,r10,r3 |
| 1291 | vst1.32 {q9},[r12,:128]! |
| 1292 | add r5,r5,r6,ror#27 |
| 1293 | mov r7,r7,ror#2 |
| 1294 | add r5,r5,r11 |
| 1295 | eor r10,r6,r3 |
| 1296 | add r4,r4,r9 |
| 1297 | ldr r9,[sp,#40] |
| 1298 | eor r11,r10,r7 |
| 1299 | add r4,r4,r5,ror#27 |
| 1300 | mov r6,r6,ror#2 |
| 1301 | add r4,r4,r11 |
| 1302 | eor r10,r5,r7 |
| 1303 | add r3,r3,r9 |
| 1304 | ldr r9,[sp,#44] |
| 1305 | eor r11,r10,r6 |
| 1306 | add r3,r3,r4,ror#27 |
| 1307 | mov r5,r5,ror#2 |
| 1308 | add r3,r3,r11 |
| 1309 | eor r10,r4,r6 |
| 1310 | add r7,r7,r9 |
| 1311 | ldr r9,[sp,#48] |
| 1312 | eor r11,r10,r5 |
| 1313 | add r7,r7,r3,ror#27 |
| 1314 | mov r4,r4,ror#2 |
| 1315 | add r7,r7,r11 |
| 1316 | vrev32.8 q3,q3 |
| 1317 | eor r10,r3,r5 |
| 1318 | add r6,r6,r9 |
| 1319 | vadd.i32 q10,q2,q14 |
| 1320 | ldr r9,[sp,#52] |
| 1321 | eor r11,r10,r4 |
| 1322 | vst1.32 {q10},[r12,:128]! |
| 1323 | add r6,r6,r7,ror#27 |
| 1324 | mov r3,r3,ror#2 |
| 1325 | add r6,r6,r11 |
| 1326 | eor r10,r7,r4 |
| 1327 | add r5,r5,r9 |
| 1328 | ldr r9,[sp,#56] |
| 1329 | eor r11,r10,r3 |
| 1330 | add r5,r5,r6,ror#27 |
| 1331 | mov r7,r7,ror#2 |
| 1332 | add r5,r5,r11 |
| 1333 | eor r10,r6,r3 |
| 1334 | add r4,r4,r9 |
| 1335 | ldr r9,[sp,#60] |
| 1336 | eor r11,r10,r7 |
| 1337 | add r4,r4,r5,ror#27 |
| 1338 | mov r6,r6,ror#2 |
| 1339 | add r4,r4,r11 |
| 1340 | eor r10,r5,r7 |
| 1341 | add r3,r3,r9 |
| 1342 | eor r11,r10,r6 |
| 1343 | add r3,r3,r4,ror#27 |
| 1344 | mov r5,r5,ror#2 |
| 1345 | add r3,r3,r11 |
| 1346 | ldmia r0,{r9,r10,r11,r12} @ accumulate context |
| 1347 | add r3,r3,r9 |
| 1348 | ldr r9,[r0,#16] |
| 1349 | add r4,r4,r10 |
| 1350 | add r5,r5,r11 |
| 1351 | add r6,r6,r12 |
| 1352 | it eq |
| 1353 | moveq sp,r14 |
| 1354 | add r7,r7,r9 |
| 1355 | it ne |
| 1356 | ldrne r9,[sp] |
| 1357 | stmia r0,{r3,r4,r5,r6,r7} |
| 1358 | itt ne |
| 1359 | addne r12,sp,#3*16 |
| 1360 | bne Loop_neon |
| 1361 | |
| 1362 | @ vldmia sp!,{d8-d15} |
| 1363 | ldmia sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,pc} |
| 1364 | |
| 1365 | #endif |
| 1366 | #if __ARM_MAX_ARCH__>=7 |
| 1367 | |
| 1368 | # if defined(__thumb2__) |
| 1369 | # define INST(a,b,c,d) .byte c,d|0xf,a,b |
| 1370 | # else |
| 1371 | # define INST(a,b,c,d) .byte a,b,c,d|0x10 |
| 1372 | # endif |
| 1373 | |
| 1374 | #ifdef __thumb2__ |
| 1375 | .thumb_func sha1_block_data_order_armv8 |
| 1376 | #endif |
| 1377 | .align 5 |
| 1378 | sha1_block_data_order_armv8: |
| 1379 | LARMv8: |
| 1380 | vstmdb sp!,{d8,d9,d10,d11,d12,d13,d14,d15} @ ABI specification says so |
| 1381 | |
| 1382 | veor q1,q1,q1 |
| 1383 | adr r3,LK_00_19 |
| 1384 | vld1.32 {q0},[r0]! |
| 1385 | vld1.32 {d2[0]},[r0] |
| 1386 | sub r0,r0,#16 |
| 1387 | vld1.32 {d16[],d17[]},[r3,:32]! |
| 1388 | vld1.32 {d18[],d19[]},[r3,:32]! |
| 1389 | vld1.32 {d20[],d21[]},[r3,:32]! |
| 1390 | vld1.32 {d22[],d23[]},[r3,:32] |
| 1391 | |
| 1392 | Loop_v8: |
| 1393 | vld1.8 {q4,q5},[r1]! |
| 1394 | vld1.8 {q6,q7},[r1]! |
| 1395 | vrev32.8 q4,q4 |
| 1396 | vrev32.8 q5,q5 |
| 1397 | |
| 1398 | vadd.i32 q12,q8,q4 |
| 1399 | vrev32.8 q6,q6 |
| 1400 | vmov q14,q0 @ offload |
| 1401 | subs r2,r2,#1 |
| 1402 | |
| 1403 | vadd.i32 q13,q8,q5 |
| 1404 | vrev32.8 q7,q7 |
| 1405 | INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 0 |
| 1406 | INST(0x68,0x0c,0x02,0xe2) @ sha1c q0,q1,q12 |
| 1407 | vadd.i32 q12,q8,q6 |
| 1408 | INST(0x4c,0x8c,0x3a,0xe2) @ sha1su0 q4,q5,q6 |
| 1409 | INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 1 |
| 1410 | INST(0x6a,0x0c,0x06,0xe2) @ sha1c q0,q3,q13 |
| 1411 | vadd.i32 q13,q8,q7 |
| 1412 | INST(0x8e,0x83,0xba,0xf3) @ sha1su1 q4,q7 |
| 1413 | INST(0x4e,0xac,0x3c,0xe2) @ sha1su0 q5,q6,q7 |
| 1414 | INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 2 |
| 1415 | INST(0x68,0x0c,0x04,0xe2) @ sha1c q0,q2,q12 |
| 1416 | vadd.i32 q12,q8,q4 |
| 1417 | INST(0x88,0xa3,0xba,0xf3) @ sha1su1 q5,q4 |
| 1418 | INST(0x48,0xcc,0x3e,0xe2) @ sha1su0 q6,q7,q4 |
| 1419 | INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 3 |
| 1420 | INST(0x6a,0x0c,0x06,0xe2) @ sha1c q0,q3,q13 |
| 1421 | vadd.i32 q13,q9,q5 |
| 1422 | INST(0x8a,0xc3,0xba,0xf3) @ sha1su1 q6,q5 |
| 1423 | INST(0x4a,0xec,0x38,0xe2) @ sha1su0 q7,q4,q5 |
| 1424 | INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 4 |
| 1425 | INST(0x68,0x0c,0x04,0xe2) @ sha1c q0,q2,q12 |
| 1426 | vadd.i32 q12,q9,q6 |
| 1427 | INST(0x8c,0xe3,0xba,0xf3) @ sha1su1 q7,q6 |
| 1428 | INST(0x4c,0x8c,0x3a,0xe2) @ sha1su0 q4,q5,q6 |
| 1429 | INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 5 |
| 1430 | INST(0x6a,0x0c,0x16,0xe2) @ sha1p q0,q3,q13 |
| 1431 | vadd.i32 q13,q9,q7 |
| 1432 | INST(0x8e,0x83,0xba,0xf3) @ sha1su1 q4,q7 |
| 1433 | INST(0x4e,0xac,0x3c,0xe2) @ sha1su0 q5,q6,q7 |
| 1434 | INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 6 |
| 1435 | INST(0x68,0x0c,0x14,0xe2) @ sha1p q0,q2,q12 |
| 1436 | vadd.i32 q12,q9,q4 |
| 1437 | INST(0x88,0xa3,0xba,0xf3) @ sha1su1 q5,q4 |
| 1438 | INST(0x48,0xcc,0x3e,0xe2) @ sha1su0 q6,q7,q4 |
| 1439 | INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 7 |
| 1440 | INST(0x6a,0x0c,0x16,0xe2) @ sha1p q0,q3,q13 |
| 1441 | vadd.i32 q13,q9,q5 |
| 1442 | INST(0x8a,0xc3,0xba,0xf3) @ sha1su1 q6,q5 |
| 1443 | INST(0x4a,0xec,0x38,0xe2) @ sha1su0 q7,q4,q5 |
| 1444 | INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 8 |
| 1445 | INST(0x68,0x0c,0x14,0xe2) @ sha1p q0,q2,q12 |
| 1446 | vadd.i32 q12,q10,q6 |
| 1447 | INST(0x8c,0xe3,0xba,0xf3) @ sha1su1 q7,q6 |
| 1448 | INST(0x4c,0x8c,0x3a,0xe2) @ sha1su0 q4,q5,q6 |
| 1449 | INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 9 |
| 1450 | INST(0x6a,0x0c,0x16,0xe2) @ sha1p q0,q3,q13 |
| 1451 | vadd.i32 q13,q10,q7 |
| 1452 | INST(0x8e,0x83,0xba,0xf3) @ sha1su1 q4,q7 |
| 1453 | INST(0x4e,0xac,0x3c,0xe2) @ sha1su0 q5,q6,q7 |
| 1454 | INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 10 |
| 1455 | INST(0x68,0x0c,0x24,0xe2) @ sha1m q0,q2,q12 |
| 1456 | vadd.i32 q12,q10,q4 |
| 1457 | INST(0x88,0xa3,0xba,0xf3) @ sha1su1 q5,q4 |
| 1458 | INST(0x48,0xcc,0x3e,0xe2) @ sha1su0 q6,q7,q4 |
| 1459 | INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 11 |
| 1460 | INST(0x6a,0x0c,0x26,0xe2) @ sha1m q0,q3,q13 |
| 1461 | vadd.i32 q13,q10,q5 |
| 1462 | INST(0x8a,0xc3,0xba,0xf3) @ sha1su1 q6,q5 |
| 1463 | INST(0x4a,0xec,0x38,0xe2) @ sha1su0 q7,q4,q5 |
| 1464 | INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 12 |
| 1465 | INST(0x68,0x0c,0x24,0xe2) @ sha1m q0,q2,q12 |
| 1466 | vadd.i32 q12,q10,q6 |
| 1467 | INST(0x8c,0xe3,0xba,0xf3) @ sha1su1 q7,q6 |
| 1468 | INST(0x4c,0x8c,0x3a,0xe2) @ sha1su0 q4,q5,q6 |
| 1469 | INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 13 |
| 1470 | INST(0x6a,0x0c,0x26,0xe2) @ sha1m q0,q3,q13 |
| 1471 | vadd.i32 q13,q11,q7 |
| 1472 | INST(0x8e,0x83,0xba,0xf3) @ sha1su1 q4,q7 |
| 1473 | INST(0x4e,0xac,0x3c,0xe2) @ sha1su0 q5,q6,q7 |
| 1474 | INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 14 |
| 1475 | INST(0x68,0x0c,0x24,0xe2) @ sha1m q0,q2,q12 |
| 1476 | vadd.i32 q12,q11,q4 |
| 1477 | INST(0x88,0xa3,0xba,0xf3) @ sha1su1 q5,q4 |
| 1478 | INST(0x48,0xcc,0x3e,0xe2) @ sha1su0 q6,q7,q4 |
| 1479 | INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 15 |
| 1480 | INST(0x6a,0x0c,0x16,0xe2) @ sha1p q0,q3,q13 |
| 1481 | vadd.i32 q13,q11,q5 |
| 1482 | INST(0x8a,0xc3,0xba,0xf3) @ sha1su1 q6,q5 |
| 1483 | INST(0x4a,0xec,0x38,0xe2) @ sha1su0 q7,q4,q5 |
| 1484 | INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 16 |
| 1485 | INST(0x68,0x0c,0x14,0xe2) @ sha1p q0,q2,q12 |
| 1486 | vadd.i32 q12,q11,q6 |
| 1487 | INST(0x8c,0xe3,0xba,0xf3) @ sha1su1 q7,q6 |
| 1488 | INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 17 |
| 1489 | INST(0x6a,0x0c,0x16,0xe2) @ sha1p q0,q3,q13 |
| 1490 | vadd.i32 q13,q11,q7 |
| 1491 | |
| 1492 | INST(0xc0,0x62,0xb9,0xf3) @ sha1h q3,q0 @ 18 |
| 1493 | INST(0x68,0x0c,0x14,0xe2) @ sha1p q0,q2,q12 |
| 1494 | |
| 1495 | INST(0xc0,0x42,0xb9,0xf3) @ sha1h q2,q0 @ 19 |
| 1496 | INST(0x6a,0x0c,0x16,0xe2) @ sha1p q0,q3,q13 |
| 1497 | |
| 1498 | vadd.i32 q1,q1,q2 |
| 1499 | vadd.i32 q0,q0,q14 |
| 1500 | bne Loop_v8 |
| 1501 | |
| 1502 | vst1.32 {q0},[r0]! |
| 1503 | vst1.32 {d2[0]},[r0] |
| 1504 | |
| 1505 | vldmia sp!,{d8,d9,d10,d11,d12,d13,d14,d15} |
| 1506 | bx lr @ bx lr |
| 1507 | |
| 1508 | #endif |
| 1509 | #if __ARM_MAX_ARCH__>=7 |
| 1510 | .comm _OPENSSL_armcap_P,4 |
| 1511 | .non_lazy_symbol_pointer |
| 1512 | OPENSSL_armcap_P: |
| 1513 | .indirect_symbol _OPENSSL_armcap_P |
| 1514 | .long 0 |
| 1515 | .private_extern _OPENSSL_armcap_P |
| 1516 | #endif |
Robert Sloan | 726e9d1 | 2018-09-11 11:45:04 -0700 | [diff] [blame] | 1517 | #endif // !OPENSSL_NO_ASM |