Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1 | //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This class prints an ARM MCInst to a .s file. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
Nguyen Anh Quynh | 8598a21 | 2014-05-14 11:26:41 +0800 | [diff] [blame] | 14 | /* Capstone Disassembly Engine */ |
Nguyen Anh Quynh | bfcaba5 | 2015-03-04 17:45:23 +0800 | [diff] [blame] | 15 | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ |
Nguyen Anh Quynh | 8598a21 | 2014-05-14 11:26:41 +0800 | [diff] [blame] | 16 | |
| 17 | #ifdef CAPSTONE_HAS_ARM |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 18 | |
| 19 | #include <stdio.h> // DEBUG |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 20 | #include <stdlib.h> |
| 21 | #include <string.h> |
tandasat | 45e5eab | 2016-05-11 21:48:32 -0700 | [diff] [blame] | 22 | #include <capstone/platform.h> |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 23 | |
| 24 | #include "ARMInstPrinter.h" |
| 25 | #include "ARMAddressingModes.h" |
| 26 | #include "ARMBaseInfo.h" |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 27 | #include "ARMDisassembler.h" |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 28 | #include "../../MCInst.h" |
| 29 | #include "../../SStream.h" |
| 30 | #include "../../MCRegisterInfo.h" |
| 31 | #include "../../utils.h" |
Nguyen Anh Quynh | 3732725 | 2014-01-20 09:47:21 +0800 | [diff] [blame] | 32 | #include "ARMMapping.h" |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 33 | |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 34 | #define GET_SUBTARGETINFO_ENUM |
| 35 | #include "ARMGenSubtargetInfo.inc" |
| 36 | |
Nguyen Anh Quynh | 256090a | 2016-03-14 13:52:23 +0800 | [diff] [blame] | 37 | |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 38 | static void printRegName(cs_struct *h, SStream *OS, unsigned RegNo); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 39 | |
| 40 | // Autogenerated by tblgen. |
| 41 | static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI); |
| 42 | static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); |
| 43 | static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O); |
| 44 | static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O); |
| 45 | |
| 46 | static void printAddrModeTBB(MCInst *MI, unsigned OpNum, SStream *O); |
| 47 | static void printAddrModeTBH(MCInst *MI, unsigned OpNum, SStream *O); |
| 48 | static void printAddrMode2Operand(MCInst *MI, unsigned OpNum, SStream *O); |
| 49 | static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned OpNum, SStream *O); |
| 50 | static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); |
| 51 | static void printAddrMode3Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0); |
| 52 | static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 53 | static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O, bool AlwaysPrintImm0); |
| 54 | static void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O); |
| 55 | static void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O); |
| 56 | static void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O); |
| 57 | static void printAddrMode5Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0); |
| 58 | static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O); |
| 59 | static void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O); |
| 60 | static void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); |
| 61 | |
| 62 | static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O); |
| 63 | static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O); |
| 64 | static void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O); |
| 65 | static void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O); |
| 66 | static void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O); |
| 67 | static void printAdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned); |
| 68 | static void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O); |
| 69 | static void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O); |
| 70 | static void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O); |
| 71 | static void printThumbAddrModeRROperand(MCInst *MI, unsigned OpNum, SStream *O); |
| 72 | static void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned Scale); |
| 73 | static void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned OpNum, SStream *O); |
| 74 | static void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned OpNum, SStream *O); |
| 75 | static void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned OpNum, SStream *O); |
| 76 | static void printThumbAddrModeSPOperand(MCInst *MI, unsigned OpNum, SStream *O); |
| 77 | static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O); |
| 78 | static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0); |
| 79 | static void printT2AddrModeImm8Operand(MCInst *MI, unsigned OpNum, SStream *O, bool); |
| 80 | static void printT2AddrModeImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O, bool); |
| 81 | static void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, SStream *O); |
| 82 | static void printT2AddrModeImm8OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); |
| 83 | static void printT2AddrModeImm8s4OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); |
| 84 | static void printT2AddrModeSoRegOperand(MCInst *MI, unsigned OpNum, SStream *O); |
| 85 | static void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O); |
| 86 | static void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O); |
| 87 | static void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O); |
| 88 | static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O); |
| 89 | static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O); |
| 90 | static void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O); |
| 91 | static void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O); |
| 92 | static void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O); |
| 93 | static void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O); |
| 94 | static void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O); |
| 95 | static void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O); |
| 96 | static void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O); |
| 97 | static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O); |
| 98 | static void printNEONModImmOperand(MCInst *MI, unsigned OpNum, SStream *O); |
| 99 | static void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O); |
| 100 | static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O); |
| 101 | static void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *MRI); |
| 102 | static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O); |
| 103 | static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O); |
| 104 | static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O); |
| 105 | static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O); |
| 106 | static void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O); |
| 107 | static void printVectorListTwo(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *MRI); |
| 108 | static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *RI); |
| 109 | static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O); |
| 110 | static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O); |
| 111 | static void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O); |
| 112 | static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *RI); |
| 113 | static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O); |
| 114 | static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O); |
| 115 | static void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *MRI); |
| 116 | static void printVectorListThreeSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O); |
| 117 | static void printVectorListFourSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O); |
| 118 | static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O); |
| 119 | static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O); |
Nguyen Anh Quynh | d1fc2bd | 2015-03-03 16:26:32 +0800 | [diff] [blame] | 120 | static void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O); |
| 121 | static void printModImmOperand(MCInst *MI, unsigned OpNum, SStream *O); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 122 | |
| 123 | static void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O); |
| 124 | |
Nguyen Anh Quynh | 53a059b | 2015-06-08 21:51:19 +0800 | [diff] [blame] | 125 | #ifndef CAPSTONE_DIET |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 126 | // copy & normalize access info |
| 127 | static uint8_t get_op_access(cs_struct *h, unsigned int id, unsigned int index) |
| 128 | { |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 129 | uint8_t *arr = ARM_get_op_access(h, id); |
| 130 | |
| 131 | if (arr[index] == CS_AC_IGNORE) |
| 132 | return 0; |
| 133 | |
| 134 | return arr[index]; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 135 | } |
Nguyen Anh Quynh | 53a059b | 2015-06-08 21:51:19 +0800 | [diff] [blame] | 136 | #endif |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 137 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 138 | static void set_mem_access(MCInst *MI, bool status) |
| 139 | { |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 140 | if (MI->csh->detail != CS_OPT_ON) |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 141 | return; |
| 142 | |
Nguyen Anh Quynh | 19b0de3 | 2013-12-31 22:40:04 +0800 | [diff] [blame] | 143 | MI->csh->doing_mem = status; |
| 144 | if (status) { |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 145 | #ifndef CAPSTONE_DIET |
| 146 | uint8_t access; |
| 147 | #endif |
| 148 | |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 149 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM; |
| 150 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_INVALID; |
| 151 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID; |
| 152 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1; |
| 153 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 154 | |
| 155 | #ifndef CAPSTONE_DIET |
| 156 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
| 157 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 158 | MI->ac_idx++; |
| 159 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 160 | } else { |
| 161 | // done, create the next operand slot |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 162 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 163 | } |
| 164 | } |
| 165 | |
Nguyen Anh Quynh | ebe2443 | 2014-06-17 13:56:01 +0800 | [diff] [blame] | 166 | static void op_addImm(MCInst *MI, int v) |
| 167 | { |
Nguyen Anh Quynh | 73eb5d5 | 2014-06-17 18:08:29 +0800 | [diff] [blame] | 168 | if (MI->csh->detail) { |
| 169 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; |
| 170 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v; |
| 171 | MI->flat_insn->detail->arm.op_count++; |
| 172 | } |
Nguyen Anh Quynh | ebe2443 | 2014-06-17 13:56:01 +0800 | [diff] [blame] | 173 | } |
| 174 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 175 | #define GET_INSTRINFO_ENUM |
| 176 | #include "ARMGenInstrInfo.inc" |
| 177 | |
| 178 | //#define PRINT_ALIAS_INSTR |
| 179 | #include "ARMGenAsmWriter.inc" |
| 180 | |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 181 | void ARM_getRegName(cs_struct *handle, int value) |
| 182 | { |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 183 | if (value == CS_OPT_SYNTAX_NOREGNAME) { |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 184 | handle->get_regname = getRegisterName2; |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 185 | handle->reg_name = ARM_reg_name2;; |
| 186 | } else { |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 187 | handle->get_regname = getRegisterName; |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 188 | handle->reg_name = ARM_reg_name;; |
| 189 | } |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 190 | } |
| 191 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 192 | /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing. |
| 193 | /// |
| 194 | /// getSORegOffset returns an integer from 0-31, representing '32' as 0. |
| 195 | static unsigned translateShiftImm(unsigned imm) |
| 196 | { |
| 197 | // lsr #32 and asr #32 exist, but should be encoded as a 0. |
| 198 | //assert((imm & ~0x1f) == 0 && "Invalid shift encoding"); |
| 199 | if (imm == 0) |
| 200 | return 32; |
| 201 | return imm; |
| 202 | } |
| 203 | |
| 204 | /// Prints the shift value with an immediate value. |
Nguyen Anh Quynh | 8c1104b | 2014-06-10 00:39:06 +0700 | [diff] [blame] | 205 | static void printRegImmShift(MCInst *MI, SStream *O, ARM_AM_ShiftOpc ShOpc, unsigned ShImm) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 206 | { |
| 207 | if (ShOpc == ARM_AM_no_shift || (ShOpc == ARM_AM_lsl && !ShImm)) |
| 208 | return; |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 209 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 210 | |
| 211 | //assert (!(ShOpc == ARM_AM_ror && !ShImm) && "Cannot have ror #0"); |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 212 | SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc)); |
Nguyen Anh Quynh | c70442e | 2014-06-01 11:35:34 +0700 | [diff] [blame] | 213 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 26dfbc6 | 2014-07-31 18:24:51 +0800 | [diff] [blame] | 214 | if (MI->csh->doing_mem) |
| 215 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)ShOpc; |
| 216 | else |
| 217 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = (arm_shifter)ShOpc; |
Nguyen Anh Quynh | c70442e | 2014-06-01 11:35:34 +0700 | [diff] [blame] | 218 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 219 | |
| 220 | if (ShOpc != ARM_AM_rrx) { |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 221 | SStream_concat0(O, " "); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 222 | SStream_concat(O, "#%u", translateShiftImm(ShImm)); |
Nguyen Anh Quynh | c70442e | 2014-06-01 11:35:34 +0700 | [diff] [blame] | 223 | if (MI->csh->detail) { |
| 224 | if (MI->csh->doing_mem) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 225 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = translateShiftImm(ShImm); |
Nguyen Anh Quynh | c70442e | 2014-06-01 11:35:34 +0700 | [diff] [blame] | 226 | else |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 227 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = translateShiftImm(ShImm); |
Nguyen Anh Quynh | c70442e | 2014-06-01 11:35:34 +0700 | [diff] [blame] | 228 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 229 | } |
| 230 | } |
| 231 | |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 232 | static void printRegName(cs_struct *h, SStream *OS, unsigned RegNo) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 233 | { |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 234 | #ifndef CAPSTONE_DIET |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 235 | SStream_concat0(OS, h->get_regname(RegNo)); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 236 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 237 | } |
| 238 | |
| 239 | static name_map insn_update_flgs[] = { |
| 240 | { ARM_INS_CMN, "cmn" }, |
| 241 | { ARM_INS_CMP, "cmp" }, |
| 242 | { ARM_INS_TEQ, "teq" }, |
| 243 | { ARM_INS_TST, "tst" }, |
| 244 | |
| 245 | { ARM_INS_ADC, "adcs" }, |
| 246 | { ARM_INS_ADD, "adds" }, |
| 247 | { ARM_INS_AND, "ands" }, |
| 248 | { ARM_INS_ASR, "asrs" }, |
| 249 | { ARM_INS_BIC, "bics" }, |
| 250 | { ARM_INS_EOR, "eors" }, |
| 251 | { ARM_INS_LSL, "lsls" }, |
| 252 | { ARM_INS_LSR, "lsrs" }, |
| 253 | { ARM_INS_MLA, "mlas" }, |
| 254 | { ARM_INS_MOV, "movs" }, |
| 255 | { ARM_INS_MUL, "muls" }, |
| 256 | { ARM_INS_MVN, "mvns" }, |
| 257 | { ARM_INS_ORN, "orns" }, |
| 258 | { ARM_INS_ORR, "orrs" }, |
| 259 | { ARM_INS_ROR, "rors" }, |
| 260 | { ARM_INS_RRX, "rrxs" }, |
| 261 | { ARM_INS_RSB, "rsbs" }, |
| 262 | { ARM_INS_RSC, "rscs" }, |
| 263 | { ARM_INS_SBC, "sbcs" }, |
| 264 | { ARM_INS_SMLAL, "smlals" }, |
| 265 | { ARM_INS_SMULL, "smulls" }, |
| 266 | { ARM_INS_SUB, "subs" }, |
| 267 | { ARM_INS_UMLAL, "umlals" }, |
| 268 | { ARM_INS_UMULL, "umulls" }, |
| 269 | }; |
| 270 | |
Nguyen Anh Quynh | 6456481 | 2014-05-19 16:46:31 +0800 | [diff] [blame] | 271 | void ARM_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 272 | { |
Nguyen Anh Quynh | 5ef633c | 2014-01-04 10:41:17 +0800 | [diff] [blame] | 273 | if (((cs_struct *)ud)->detail != CS_OPT_ON) |
| 274 | return; |
| 275 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 276 | // check if this insn requests write-back |
Nguyen Anh Quynh | 03e5e10 | 2015-01-21 12:15:14 +0800 | [diff] [blame] | 277 | if (mci->writeback || (strrchr(insn_asm, '!')) != NULL) { |
Nguyen Anh Quynh | 4fe224b | 2013-12-24 16:49:36 +0800 | [diff] [blame] | 278 | insn->detail->arm.writeback = true; |
Nguyen Anh Quynh | 5719eb5 | 2015-01-21 12:16:15 +0800 | [diff] [blame] | 279 | } else if (mci->csh->mode & CS_MODE_THUMB) { |
Nguyen Anh Quynh | 03e5e10 | 2015-01-21 12:15:14 +0800 | [diff] [blame] | 280 | // handle some special instructions with writeback |
Nguyen Anh Quynh | 483e101 | 2016-08-09 23:19:04 +0800 | [diff] [blame] | 281 | //printf(">> Opcode = %u\n", mci->Opcode); |
Nguyen Anh Quynh | 03e5e10 | 2015-01-21 12:15:14 +0800 | [diff] [blame] | 282 | switch(mci->Opcode) { |
| 283 | default: |
| 284 | break; |
| 285 | case ARM_t2LDC2L_PRE: |
| 286 | case ARM_t2LDC2_PRE: |
| 287 | case ARM_t2LDCL_PRE: |
| 288 | case ARM_t2LDC_PRE: |
| 289 | |
| 290 | case ARM_t2LDRB_PRE: |
| 291 | case ARM_t2LDRD_PRE: |
| 292 | case ARM_t2LDRH_PRE: |
| 293 | case ARM_t2LDRSB_PRE: |
| 294 | case ARM_t2LDRSH_PRE: |
| 295 | case ARM_t2LDR_PRE: |
| 296 | |
| 297 | case ARM_t2STC2L_PRE: |
| 298 | case ARM_t2STC2_PRE: |
| 299 | case ARM_t2STCL_PRE: |
| 300 | case ARM_t2STC_PRE: |
| 301 | |
| 302 | case ARM_t2STRB_PRE: |
| 303 | case ARM_t2STRD_PRE: |
| 304 | case ARM_t2STRH_PRE: |
| 305 | case ARM_t2STR_PRE: |
| 306 | |
| 307 | case ARM_t2LDC2L_POST: |
| 308 | case ARM_t2LDC2_POST: |
| 309 | case ARM_t2LDCL_POST: |
| 310 | case ARM_t2LDC_POST: |
| 311 | |
| 312 | case ARM_t2LDRB_POST: |
| 313 | case ARM_t2LDRD_POST: |
| 314 | case ARM_t2LDRH_POST: |
| 315 | case ARM_t2LDRSB_POST: |
| 316 | case ARM_t2LDRSH_POST: |
| 317 | case ARM_t2LDR_POST: |
| 318 | |
| 319 | case ARM_t2STC2L_POST: |
| 320 | case ARM_t2STC2_POST: |
| 321 | case ARM_t2STCL_POST: |
| 322 | case ARM_t2STC_POST: |
| 323 | |
| 324 | case ARM_t2STRB_POST: |
| 325 | case ARM_t2STRD_POST: |
| 326 | case ARM_t2STRH_POST: |
| 327 | case ARM_t2STR_POST: |
| 328 | insn->detail->arm.writeback = true; |
| 329 | break; |
| 330 | } |
| 331 | } else { // ARM mode |
| 332 | // handle some special instructions with writeback |
Nguyen Anh Quynh | 483e101 | 2016-08-09 23:19:04 +0800 | [diff] [blame] | 333 | //printf(">> Opcode = %u\n", mci->Opcode); |
Nguyen Anh Quynh | 03e5e10 | 2015-01-21 12:15:14 +0800 | [diff] [blame] | 334 | switch(mci->Opcode) { |
| 335 | default: |
| 336 | break; |
| 337 | case ARM_LDC2L_PRE: |
| 338 | case ARM_LDC2_PRE: |
| 339 | case ARM_LDCL_PRE: |
| 340 | case ARM_LDC_PRE: |
| 341 | |
| 342 | case ARM_LDRD_PRE: |
| 343 | case ARM_LDRH_PRE: |
| 344 | case ARM_LDRSB_PRE: |
| 345 | case ARM_LDRSH_PRE: |
| 346 | |
| 347 | case ARM_STC2L_PRE: |
| 348 | case ARM_STC2_PRE: |
| 349 | case ARM_STCL_PRE: |
| 350 | case ARM_STC_PRE: |
| 351 | |
| 352 | case ARM_STRD_PRE: |
| 353 | case ARM_STRH_PRE: |
| 354 | |
| 355 | case ARM_LDC2L_POST: |
| 356 | case ARM_LDC2_POST: |
| 357 | case ARM_LDCL_POST: |
| 358 | case ARM_LDC_POST: |
| 359 | |
| 360 | case ARM_LDRBT_POST: |
| 361 | case ARM_LDRD_POST: |
| 362 | case ARM_LDRH_POST: |
| 363 | case ARM_LDRSB_POST: |
| 364 | case ARM_LDRSH_POST: |
| 365 | |
| 366 | case ARM_STC2L_POST: |
| 367 | case ARM_STC2_POST: |
| 368 | case ARM_STCL_POST: |
| 369 | case ARM_STC_POST: |
| 370 | |
| 371 | case ARM_STRBT_POST: |
| 372 | case ARM_STRD_POST: |
| 373 | case ARM_STRH_POST: |
Nguyen Anh Quynh | 58fbf2f | 2015-01-21 12:25:36 +0800 | [diff] [blame] | 374 | |
| 375 | case ARM_LDRB_POST_IMM: |
| 376 | case ARM_LDR_POST_IMM: |
Nguyen Anh Quynh | 483e101 | 2016-08-09 23:19:04 +0800 | [diff] [blame] | 377 | case ARM_LDR_POST_REG: |
Nguyen Anh Quynh | 58fbf2f | 2015-01-21 12:25:36 +0800 | [diff] [blame] | 378 | case ARM_STRB_POST_IMM: |
| 379 | case ARM_STR_POST_IMM: |
| 380 | |
Nguyen Anh Quynh | 03e5e10 | 2015-01-21 12:15:14 +0800 | [diff] [blame] | 381 | insn->detail->arm.writeback = true; |
| 382 | break; |
| 383 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 384 | } |
| 385 | |
| 386 | // check if this insn requests update flags |
Nguyen Anh Quynh | 4fe224b | 2013-12-24 16:49:36 +0800 | [diff] [blame] | 387 | if (insn->detail->arm.update_flags == false) { |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 388 | // some insn still update flags, regardless of tabgen info |
Nguyen Anh Quynh | f6c7cbc | 2014-03-12 12:50:54 +0800 | [diff] [blame] | 389 | unsigned int i, j; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 390 | |
| 391 | for (i = 0; i < ARR_SIZE(insn_update_flgs); i++) { |
Nguyen Anh Quynh | 4fe224b | 2013-12-24 16:49:36 +0800 | [diff] [blame] | 392 | if (insn->id == insn_update_flgs[i].id && |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 393 | !strncmp(insn_asm, insn_update_flgs[i].name, |
| 394 | strlen(insn_update_flgs[i].name))) { |
Nguyen Anh Quynh | 4fe224b | 2013-12-24 16:49:36 +0800 | [diff] [blame] | 395 | insn->detail->arm.update_flags = true; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 396 | // we have to update regs_write array as well |
Nguyen Anh Quynh | 4fe224b | 2013-12-24 16:49:36 +0800 | [diff] [blame] | 397 | for (j = 0; j < ARR_SIZE(insn->detail->regs_write); j++) { |
| 398 | if (insn->detail->regs_write[j] == 0) { |
| 399 | insn->detail->regs_write[j] = ARM_REG_CPSR; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 400 | break; |
| 401 | } |
| 402 | } |
| 403 | break; |
| 404 | } |
| 405 | } |
| 406 | } |
Nguyen Anh Quynh | 48b6cb4 | 2014-06-01 09:45:19 +0700 | [diff] [blame] | 407 | |
| 408 | // instruction should not have invalid CC |
| 409 | if (insn->detail->arm.cc == ARM_CC_INVALID) { |
| 410 | insn->detail->arm.cc = ARM_CC_AL; |
| 411 | } |
| 412 | |
Nguyen Anh Quynh | 6eb55cf | 2014-06-01 10:03:14 +0700 | [diff] [blame] | 413 | // manual fix for some special instructions |
| 414 | // printf(">>> id: %u, mcid: %u\n", insn->id, mci->Opcode); |
| 415 | switch(mci->Opcode) { |
| 416 | default: |
| 417 | break; |
| 418 | case ARM_MOVPCLR: |
| 419 | insn->detail->arm.operands[0].type = ARM_OP_REG; |
| 420 | insn->detail->arm.operands[0].reg = ARM_REG_PC; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 421 | insn->detail->arm.operands[0].access = CS_AC_READ; |
Nguyen Anh Quynh | 6eb55cf | 2014-06-01 10:03:14 +0700 | [diff] [blame] | 422 | insn->detail->arm.operands[1].type = ARM_OP_REG; |
| 423 | insn->detail->arm.operands[1].reg = ARM_REG_LR; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 424 | insn->detail->arm.operands[1].access = CS_AC_WRITE; |
Nguyen Anh Quynh | 6eb55cf | 2014-06-01 10:03:14 +0700 | [diff] [blame] | 425 | insn->detail->arm.op_count = 2; |
| 426 | break; |
| 427 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 428 | } |
| 429 | |
| 430 | void ARM_printInst(MCInst *MI, SStream *O, void *Info) |
| 431 | { |
| 432 | MCRegisterInfo *MRI = (MCRegisterInfo *)Info; |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 433 | unsigned Opcode = MCInst_getOpcode(MI), tmp, i, pubOpcode; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 434 | |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 435 | |
Nguyen Anh Quynh | 91a1cb4 | 2015-05-02 11:38:34 +0800 | [diff] [blame] | 436 | // printf(">>> Opcode 0: %u\n", MCInst_getOpcode(MI)); |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 437 | switch(Opcode) { |
| 438 | // Check for HINT instructions w/ canonical names. |
| 439 | case ARM_HINT: |
| 440 | case ARM_tHINT: |
| 441 | case ARM_t2HINT: |
| 442 | switch (MCOperand_getImm(MCInst_getOperand(MI, 0))) { |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 443 | case 0: SStream_concat0(O, "nop"); pubOpcode = ARM_INS_NOP; break; |
| 444 | case 1: SStream_concat0(O, "yield"); pubOpcode = ARM_INS_YIELD; break; |
| 445 | case 2: SStream_concat0(O, "wfe"); pubOpcode = ARM_INS_WFE; break; |
| 446 | case 3: SStream_concat0(O, "wfi"); pubOpcode = ARM_INS_WFI; break; |
| 447 | case 4: SStream_concat0(O, "sev"); pubOpcode = ARM_INS_SEV; break; |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 448 | case 5: |
Nguyen Anh Quynh | 2593e22 | 2014-11-10 16:35:38 +0800 | [diff] [blame] | 449 | if ((ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops)) { |
| 450 | SStream_concat0(O, "sevl"); |
| 451 | pubOpcode = ARM_INS_SEVL; |
| 452 | break; |
| 453 | } |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 454 | // Fallthrough for non-v8 |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 455 | default: |
| 456 | // Anything else should just print normally. |
| 457 | printInstruction(MI, O, MRI); |
| 458 | return; |
| 459 | } |
| 460 | printPredicateOperand(MI, 1, O); |
| 461 | if (Opcode == ARM_t2HINT) |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 462 | SStream_concat0(O, ".w"); |
| 463 | |
| 464 | MCInst_setOpcodePub(MI, pubOpcode); |
| 465 | |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 466 | return; |
| 467 | |
| 468 | // Check for MOVs and print canonical forms, instead. |
| 469 | case ARM_MOVsr: { |
| 470 | // FIXME: Thumb variants? |
Nguyen Anh Quynh | 52a6b8b | 2015-05-02 11:46:53 +0800 | [diff] [blame] | 471 | unsigned int opc; |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 472 | MCOperand *Dst = MCInst_getOperand(MI, 0); |
| 473 | MCOperand *MO1 = MCInst_getOperand(MI, 1); |
| 474 | MCOperand *MO2 = MCInst_getOperand(MI, 2); |
| 475 | MCOperand *MO3 = MCInst_getOperand(MI, 3); |
| 476 | |
Nguyen Anh Quynh | 52a6b8b | 2015-05-02 11:46:53 +0800 | [diff] [blame] | 477 | opc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3)); |
| 478 | SStream_concat0(O, ARM_AM_getShiftOpcStr(opc)); |
| 479 | switch(opc) { |
| 480 | default: |
| 481 | break; |
| 482 | case ARM_AM_asr: |
| 483 | MCInst_setOpcodePub(MI, ARM_INS_ASR); |
| 484 | break; |
| 485 | case ARM_AM_lsl: |
| 486 | MCInst_setOpcodePub(MI, ARM_INS_LSL); |
| 487 | break; |
| 488 | case ARM_AM_lsr: |
| 489 | MCInst_setOpcodePub(MI, ARM_INS_LSR); |
| 490 | break; |
| 491 | case ARM_AM_ror: |
| 492 | MCInst_setOpcodePub(MI, ARM_INS_ROR); |
| 493 | break; |
| 494 | case ARM_AM_rrx: |
| 495 | MCInst_setOpcodePub(MI, ARM_INS_RRX); |
| 496 | break; |
| 497 | } |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 498 | printSBitModifierOperand(MI, 6, O); |
| 499 | printPredicateOperand(MI, 4, O); |
| 500 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 501 | SStream_concat0(O, "\t"); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 502 | printRegName(MI->csh, O, MCOperand_getReg(Dst)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 503 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 504 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 505 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 506 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_WRITE; |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 507 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 508 | } |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 509 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 510 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 511 | printRegName(MI->csh, O, MCOperand_getReg(MO1)); |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 512 | |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 513 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 514 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 515 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 516 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 517 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 518 | } |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 519 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 520 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 521 | printRegName(MI->csh, O, MCOperand_getReg(MO2)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 522 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 523 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 524 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO2); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 525 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 526 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 527 | } |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 528 | //assert(ARM_AM_getSORegOffset(MO3.getImm()) == 0); |
| 529 | return; |
| 530 | } |
| 531 | |
| 532 | case ARM_MOVsi: { |
| 533 | // FIXME: Thumb variants? |
Nguyen Anh Quynh | 91a1cb4 | 2015-05-02 11:38:34 +0800 | [diff] [blame] | 534 | unsigned int opc; |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 535 | MCOperand *Dst = MCInst_getOperand(MI, 0); |
| 536 | MCOperand *MO1 = MCInst_getOperand(MI, 1); |
| 537 | MCOperand *MO2 = MCInst_getOperand(MI, 2); |
| 538 | |
Nguyen Anh Quynh | 91a1cb4 | 2015-05-02 11:38:34 +0800 | [diff] [blame] | 539 | opc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)); |
| 540 | SStream_concat0(O, ARM_AM_getShiftOpcStr(opc)); |
| 541 | switch(opc) { |
| 542 | default: |
| 543 | break; |
| 544 | case ARM_AM_asr: |
| 545 | MCInst_setOpcodePub(MI, ARM_INS_ASR); |
| 546 | break; |
| 547 | case ARM_AM_lsl: |
| 548 | MCInst_setOpcodePub(MI, ARM_INS_LSL); |
| 549 | break; |
| 550 | case ARM_AM_lsr: |
| 551 | MCInst_setOpcodePub(MI, ARM_INS_LSR); |
| 552 | break; |
| 553 | case ARM_AM_ror: |
| 554 | MCInst_setOpcodePub(MI, ARM_INS_ROR); |
| 555 | break; |
| 556 | case ARM_AM_rrx: |
| 557 | MCInst_setOpcodePub(MI, ARM_INS_RRX); |
| 558 | break; |
| 559 | } |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 560 | printSBitModifierOperand(MI, 5, O); |
| 561 | printPredicateOperand(MI, 3, O); |
| 562 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 563 | SStream_concat0(O, "\t"); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 564 | printRegName(MI->csh, O, MCOperand_getReg(Dst)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 565 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 566 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 567 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 568 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_WRITE; |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 569 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 570 | } |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 571 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 572 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 573 | printRegName(MI->csh, O, MCOperand_getReg(MO1)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 574 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 575 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 576 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 577 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 578 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 579 | } |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 580 | |
Nguyen Anh Quynh | 52a6b8b | 2015-05-02 11:46:53 +0800 | [diff] [blame] | 581 | if (opc == ARM_AM_rrx) { |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 582 | //printAnnotation(O, Annot); |
| 583 | return; |
| 584 | } |
| 585 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 586 | SStream_concat0(O, ", "); |
Axel 0vercl0k Souchet | 779d4c7 | 2014-05-08 23:44:49 +0100 | [diff] [blame] | 587 | tmp = translateShiftImm(getSORegOffset((unsigned int)MCOperand_getImm(MO2))); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 588 | if (tmp > HEX_THRESHOLD) |
| 589 | SStream_concat(O, "#0x%x", tmp); |
| 590 | else |
| 591 | SStream_concat(O, "#%u", tmp); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 592 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 593 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = |
Nguyen Anh Quynh | 52a6b8b | 2015-05-02 11:46:53 +0800 | [diff] [blame] | 594 | (arm_shifter)opc; |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 595 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 596 | } |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 597 | return; |
| 598 | } |
| 599 | |
| 600 | // A8.6.123 PUSH |
| 601 | case ARM_STMDB_UPD: |
| 602 | case ARM_t2STMDB_UPD: |
| 603 | if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP && |
| 604 | MCInst_getNumOperands(MI) > 5) { |
| 605 | // Should only print PUSH if there are at least two registers in the list. |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 606 | SStream_concat0(O, "push"); |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 607 | MCInst_setOpcodePub(MI, ARM_INS_PUSH); |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 608 | printPredicateOperand(MI, 2, O); |
| 609 | if (Opcode == ARM_t2STMDB_UPD) |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 610 | SStream_concat0(O, ".w"); |
| 611 | SStream_concat0(O, "\t"); |
Nguyen Anh Quynh | ba82977 | 2016-08-15 20:00:40 +0800 | [diff] [blame] | 612 | |
| 613 | if (MI->csh->detail) { |
| 614 | MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP; |
| 615 | MI->flat_insn->detail->regs_read_count++; |
| 616 | MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP; |
| 617 | MI->flat_insn->detail->regs_write_count++; |
| 618 | } |
| 619 | |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 620 | printRegisterList(MI, 4, O); |
| 621 | return; |
| 622 | } |
| 623 | break; |
| 624 | |
| 625 | case ARM_STR_PRE_IMM: |
| 626 | if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP && |
| 627 | MCOperand_getImm(MCInst_getOperand(MI, 3)) == -4) { |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 628 | SStream_concat0(O, "push"); |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 629 | MCInst_setOpcodePub(MI, ARM_INS_PUSH); |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 630 | printPredicateOperand(MI, 4, O); |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 631 | SStream_concat0(O, "\t{"); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 632 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 1))); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 633 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 634 | #ifndef CAPSTONE_DIET |
| 635 | uint8_t access; |
| 636 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 637 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 638 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 1)); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 639 | #ifndef CAPSTONE_DIET |
| 640 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
| 641 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 642 | MI->ac_idx++; |
| 643 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 644 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 645 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 646 | SStream_concat0(O, "}"); |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 647 | return; |
| 648 | } |
| 649 | break; |
| 650 | |
| 651 | // A8.6.122 POP |
| 652 | case ARM_LDMIA_UPD: |
| 653 | case ARM_t2LDMIA_UPD: |
| 654 | if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP && |
| 655 | MCInst_getNumOperands(MI) > 5) { |
| 656 | // Should only print POP if there are at least two registers in the list. |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 657 | SStream_concat0(O, "pop"); |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 658 | MCInst_setOpcodePub(MI, ARM_INS_POP); |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 659 | printPredicateOperand(MI, 2, O); |
| 660 | if (Opcode == ARM_t2LDMIA_UPD) |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 661 | SStream_concat0(O, ".w"); |
| 662 | SStream_concat0(O, "\t"); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 663 | if (MI->csh->detail) { |
| 664 | MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP; |
| 665 | MI->flat_insn->detail->regs_read_count++; |
| 666 | MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP; |
| 667 | MI->flat_insn->detail->regs_write_count++; |
| 668 | } |
| 669 | |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 670 | printRegisterList(MI, 4, O); |
| 671 | return; |
| 672 | } |
| 673 | break; |
| 674 | |
| 675 | case ARM_LDR_POST_IMM: |
Nguyen Anh Quynh | 3caf837 | 2014-11-27 14:34:40 +0800 | [diff] [blame] | 676 | if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP) { |
| 677 | MCOperand *MO2 = MCInst_getOperand(MI, 4); |
| 678 | if ((getAM2Op((unsigned int)MCOperand_getImm(MO2)) == ARM_AM_add && |
| 679 | getAM2Offset((unsigned int)MCOperand_getImm(MO2)) == 4) || |
| 680 | MCOperand_getImm(MO2) == 4) { |
| 681 | SStream_concat0(O, "pop"); |
| 682 | MCInst_setOpcodePub(MI, ARM_INS_POP); |
| 683 | printPredicateOperand(MI, 5, O); |
| 684 | SStream_concat0(O, "\t{"); |
| 685 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 0))); |
| 686 | if (MI->csh->detail) { |
| 687 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 688 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0)); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 689 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; |
Nguyen Anh Quynh | 3caf837 | 2014-11-27 14:34:40 +0800 | [diff] [blame] | 690 | MI->flat_insn->detail->arm.op_count++; |
| 691 | } |
| 692 | SStream_concat0(O, "}"); |
| 693 | return; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 694 | } |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 695 | } |
| 696 | break; |
| 697 | |
| 698 | // A8.6.355 VPUSH |
| 699 | case ARM_VSTMSDB_UPD: |
| 700 | case ARM_VSTMDDB_UPD: |
| 701 | if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) { |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 702 | SStream_concat0(O, "vpush"); |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 703 | MCInst_setOpcodePub(MI, ARM_INS_VPUSH); |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 704 | printPredicateOperand(MI, 2, O); |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 705 | SStream_concat0(O, "\t"); |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 706 | printRegisterList(MI, 4, O); |
| 707 | return; |
| 708 | } |
| 709 | break; |
| 710 | |
| 711 | // A8.6.354 VPOP |
| 712 | case ARM_VLDMSIA_UPD: |
| 713 | case ARM_VLDMDIA_UPD: |
| 714 | if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) { |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 715 | SStream_concat0(O, "vpop"); |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 716 | MCInst_setOpcodePub(MI, ARM_INS_VPOP); |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 717 | printPredicateOperand(MI, 2, O); |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 718 | SStream_concat0(O, "\t"); |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 719 | printRegisterList(MI, 4, O); |
| 720 | return; |
| 721 | } |
| 722 | break; |
| 723 | |
| 724 | case ARM_tLDMIA: { |
Nguyen Anh Quynh | 8cdafda | 2014-11-11 22:30:30 +0800 | [diff] [blame] | 725 | bool Writeback = true; |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 726 | unsigned BaseReg = MCOperand_getReg(MCInst_getOperand(MI, 0)); |
| 727 | unsigned i; |
| 728 | for (i = 3; i < MCInst_getNumOperands(MI); ++i) { |
| 729 | if (MCOperand_getReg(MCInst_getOperand(MI, i)) == BaseReg) |
| 730 | Writeback = false; |
| 731 | } |
| 732 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 733 | SStream_concat0(O, "ldm"); |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 734 | MCInst_setOpcodePub(MI, ARM_INS_LDM); |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 735 | |
| 736 | printPredicateOperand(MI, 1, O); |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 737 | SStream_concat0(O, "\t"); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 738 | printRegName(MI->csh, O, BaseReg); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 739 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 740 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 741 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = BaseReg; |
Nguyen Anh Quynh | 8e7f1d0 | 2016-08-17 16:19:21 +0800 | [diff] [blame] | 742 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ | CS_AC_WRITE; |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 743 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 744 | } |
Nguyen Anh Quynh | 03e5e10 | 2015-01-21 12:15:14 +0800 | [diff] [blame] | 745 | if (Writeback) { |
| 746 | MI->writeback = true; |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 747 | SStream_concat0(O, "!"); |
Nguyen Anh Quynh | 03e5e10 | 2015-01-21 12:15:14 +0800 | [diff] [blame] | 748 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 749 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 750 | printRegisterList(MI, 3, O); |
| 751 | return; |
| 752 | } |
| 753 | |
| 754 | // Combine 2 GPRs from disassember into a GPRPair to match with instr def. |
| 755 | // ldrexd/strexd require even/odd GPR pair. To enforce this constraint, |
| 756 | // a single GPRPair reg operand is used in the .td file to replace the two |
| 757 | // GPRs. However, when decoding them, the two GRPs cannot be automatically |
| 758 | // expressed as a GPRPair, so we have to manually merge them. |
| 759 | // FIXME: We would really like to be able to tablegen'erate this. |
| 760 | case ARM_LDREXD: |
| 761 | case ARM_STREXD: |
| 762 | case ARM_LDAEXD: |
| 763 | case ARM_STLEXD: { |
Nguyen Anh Quynh | 26dfbc6 | 2014-07-31 18:24:51 +0800 | [diff] [blame] | 764 | MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI, ARM_GPRRegClassID); |
| 765 | bool isStore = Opcode == ARM_STREXD || Opcode == ARM_STLEXD; |
Nguyen Anh Quynh | 26dfbc6 | 2014-07-31 18:24:51 +0800 | [diff] [blame] | 766 | unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, isStore ? 1 : 0)); |
Nguyen Anh Quynh | d1fc2bd | 2015-03-03 16:26:32 +0800 | [diff] [blame] | 767 | |
Nguyen Anh Quynh | 26dfbc6 | 2014-07-31 18:24:51 +0800 | [diff] [blame] | 768 | if (MCRegisterClass_contains(MRC, Reg)) { |
| 769 | MCInst NewMI; |
Nguyen Anh Quynh | 5e2e660 | 2014-05-30 17:43:36 +0800 | [diff] [blame] | 770 | |
Nguyen Anh Quynh | 26dfbc6 | 2014-07-31 18:24:51 +0800 | [diff] [blame] | 771 | MCInst_Init(&NewMI); |
| 772 | MCInst_setOpcode(&NewMI, Opcode); |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 773 | |
Nguyen Anh Quynh | 26dfbc6 | 2014-07-31 18:24:51 +0800 | [diff] [blame] | 774 | if (isStore) |
| 775 | MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, 0)); |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 776 | |
Nguyen Anh Quynh | 26dfbc6 | 2014-07-31 18:24:51 +0800 | [diff] [blame] | 777 | MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(MRI, Reg, ARM_gsub_0, |
| 778 | MCRegisterInfo_getRegClass(MRI, ARM_GPRPairRegClassID))); |
Nguyen Anh Quynh | 9678705 | 2014-06-10 13:59:55 +0700 | [diff] [blame] | 779 | |
Nguyen Anh Quynh | 26dfbc6 | 2014-07-31 18:24:51 +0800 | [diff] [blame] | 780 | // Copy the rest operands into NewMI. |
| 781 | for(i = isStore ? 3 : 2; i < MCInst_getNumOperands(MI); ++i) |
| 782 | MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i)); |
Nguyen Anh Quynh | 9678705 | 2014-06-10 13:59:55 +0700 | [diff] [blame] | 783 | |
Nguyen Anh Quynh | 26dfbc6 | 2014-07-31 18:24:51 +0800 | [diff] [blame] | 784 | printInstruction(&NewMI, O, MRI); |
| 785 | return; |
Nguyen Anh Quynh | 173ed2b | 2013-12-01 22:19:27 +0800 | [diff] [blame] | 786 | } |
Nguyen Anh Quynh | d1fc2bd | 2015-03-03 16:26:32 +0800 | [diff] [blame] | 787 | break; |
Nguyen Anh Quynh | 26dfbc6 | 2014-07-31 18:24:51 +0800 | [diff] [blame] | 788 | } |
Nguyen Anh Quynh | d1fc2bd | 2015-03-03 16:26:32 +0800 | [diff] [blame] | 789 | // B9.3.3 ERET (Thumb) |
| 790 | // For a target that has Virtualization Extensions, ERET is the preferred |
| 791 | // disassembly of SUBS PC, LR, #0 |
| 792 | case ARM_t2SUBS_PC_LR: { |
| 793 | MCOperand *opc = MCInst_getOperand(MI, 0); |
| 794 | if (MCInst_getNumOperands(MI) == 3 && |
| 795 | MCOperand_isImm(opc) && |
| 796 | MCOperand_getImm(opc) == 0 && |
| 797 | (ARM_getFeatureBits(MI->csh->mode) & ARM_FeatureVirtualization)) { |
| 798 | SStream_concat0(O, "eret"); |
| 799 | MCInst_setOpcodePub(MI, ARM_INS_ERET); |
| 800 | printPredicateOperand(MI, 1, O); |
| 801 | return; |
| 802 | } |
| 803 | break; |
| 804 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 805 | } |
| 806 | |
| 807 | //if (printAliasInstr(MI, O, MRI)) |
| 808 | // printInstruction(MI, O, MRI); |
| 809 | printInstruction(MI, O, MRI); |
| 810 | } |
| 811 | |
| 812 | static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) |
| 813 | { |
Nguyen Anh Quynh | bb0744d | 2014-05-12 13:41:49 +0800 | [diff] [blame] | 814 | int32_t imm; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 815 | MCOperand *Op = MCInst_getOperand(MI, OpNo); |
| 816 | if (MCOperand_isReg(Op)) { |
| 817 | unsigned Reg = MCOperand_getReg(Op); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 818 | printRegName(MI->csh, O, Reg); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 819 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 19b0de3 | 2013-12-31 22:40:04 +0800 | [diff] [blame] | 820 | if (MI->csh->doing_mem) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 821 | if (MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base == ARM_REG_INVALID) |
| 822 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = Reg; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 823 | else |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 824 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = Reg; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 825 | } else { |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 826 | #ifndef CAPSTONE_DIET |
| 827 | uint8_t access; |
| 828 | #endif |
| 829 | |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 830 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 831 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 832 | #ifndef CAPSTONE_DIET |
| 833 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
| 834 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 835 | MI->ac_idx++; |
| 836 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 837 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 838 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 839 | } |
| 840 | } else if (MCOperand_isImm(Op)) { |
Nguyen Anh Quynh | 0c235e1 | 2014-07-31 21:16:54 +0800 | [diff] [blame] | 841 | unsigned int opc = MCInst_getOpcode(MI); |
flyingsymbols | 298d413 | 2014-06-30 01:45:40 -0400 | [diff] [blame] | 842 | |
Axel 0vercl0k Souchet | 779d4c7 | 2014-05-08 23:44:49 +0100 | [diff] [blame] | 843 | imm = (int32_t)MCOperand_getImm(Op); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 844 | |
Nguyen Anh Quynh | 79e1dcb | 2014-05-07 14:12:50 +0800 | [diff] [blame] | 845 | // relative branch only has relative offset, so we have to update it |
| 846 | // to reflect absolute address. |
| 847 | // Note: in ARM, PC is always 2 instructions ahead, so we have to |
| 848 | // add 8 in ARM mode, or 4 in Thumb mode |
Nguyen Anh Quynh | bc80b3d | 2014-05-09 17:31:41 +0800 | [diff] [blame] | 849 | // printf(">> opcode: %u\n", MCInst_getOpcode(MI)); |
flyingsymbols | 298d413 | 2014-06-30 01:45:40 -0400 | [diff] [blame] | 850 | if (ARM_rel_branch(MI->csh, opc)) { |
Nguyen Anh Quynh | 79e1dcb | 2014-05-07 14:12:50 +0800 | [diff] [blame] | 851 | // only do this for relative branch |
flyingsymbols | 298d413 | 2014-06-30 01:45:40 -0400 | [diff] [blame] | 852 | if (MI->csh->mode & CS_MODE_THUMB) { |
Nguyen Anh Quynh | 79e1dcb | 2014-05-07 14:12:50 +0800 | [diff] [blame] | 853 | imm += (int32_t)MI->address + 4; |
Nguyen Anh Quynh | 26dfbc6 | 2014-07-31 18:24:51 +0800 | [diff] [blame] | 854 | if (ARM_blx_to_arm_mode(MI->csh, opc)) { |
Nguyen Anh Quynh | 0c235e1 | 2014-07-31 21:16:54 +0800 | [diff] [blame] | 855 | // here need to align down to the nearest 4-byte address |
reyalpchdk | 8b12b71 | 2016-01-16 21:32:09 -0800 | [diff] [blame] | 856 | imm &= ~3; |
Nguyen Anh Quynh | 26dfbc6 | 2014-07-31 18:24:51 +0800 | [diff] [blame] | 857 | } |
| 858 | } else { |
Nguyen Anh Quynh | 79e1dcb | 2014-05-07 14:12:50 +0800 | [diff] [blame] | 859 | imm += (int32_t)MI->address + 8; |
Nguyen Anh Quynh | 26dfbc6 | 2014-07-31 18:24:51 +0800 | [diff] [blame] | 860 | } |
Nguyen Anh Quynh | 79e1dcb | 2014-05-07 14:12:50 +0800 | [diff] [blame] | 861 | |
Nguyen Anh Quynh | 256090a | 2016-03-14 13:52:23 +0800 | [diff] [blame] | 862 | printUInt32Bang(O, imm); |
Nguyen Anh Quynh | ffff756 | 2014-03-26 16:21:31 +0800 | [diff] [blame] | 863 | } else { |
Nguyen Anh Quynh | 278e727 | 2014-11-11 12:50:43 +0800 | [diff] [blame] | 864 | switch(MI->flat_insn->id) { |
| 865 | default: |
Nguyen Anh Quynh | 256090a | 2016-03-14 13:52:23 +0800 | [diff] [blame] | 866 | if (MI->csh->imm_unsigned) |
| 867 | printUInt32Bang(O, imm); |
| 868 | else |
| 869 | printInt32Bang(O, imm); |
Nguyen Anh Quynh | 278e727 | 2014-11-11 12:50:43 +0800 | [diff] [blame] | 870 | break; |
| 871 | case ARM_INS_AND: |
| 872 | case ARM_INS_ORR: |
| 873 | case ARM_INS_EOR: |
| 874 | case ARM_INS_BIC: |
Nguyen Anh Quynh | a2934a7 | 2014-11-25 21:02:18 +0800 | [diff] [blame] | 875 | case ARM_INS_MVN: |
Nguyen Anh Quynh | 278e727 | 2014-11-11 12:50:43 +0800 | [diff] [blame] | 876 | // do not print number in negative form |
Nguyen Anh Quynh | 256090a | 2016-03-14 13:52:23 +0800 | [diff] [blame] | 877 | printUInt32Bang(O, imm); |
Nguyen Anh Quynh | 278e727 | 2014-11-11 12:50:43 +0800 | [diff] [blame] | 878 | break; |
| 879 | } |
Nguyen Anh Quynh | ffff756 | 2014-03-26 16:21:31 +0800 | [diff] [blame] | 880 | } |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 881 | |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 882 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 19b0de3 | 2013-12-31 22:40:04 +0800 | [diff] [blame] | 883 | if (MI->csh->doing_mem) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 884 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = imm; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 885 | else { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 886 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; |
| 887 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm; |
| 888 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 889 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 890 | } |
| 891 | } |
| 892 | } |
| 893 | |
| 894 | static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O) |
| 895 | { |
| 896 | MCOperand *MO1 = MCInst_getOperand(MI, OpNum); |
Nguyen Anh Quynh | bb0744d | 2014-05-12 13:41:49 +0800 | [diff] [blame] | 897 | int32_t OffImm; |
Nguyen Anh Quynh | 42706a3 | 2014-05-09 07:33:35 +0800 | [diff] [blame] | 898 | bool isSub; |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 899 | SStream_concat0(O, "[pc, "); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 900 | |
Axel 0vercl0k Souchet | 779d4c7 | 2014-05-08 23:44:49 +0100 | [diff] [blame] | 901 | OffImm = (int32_t)MCOperand_getImm(MO1); |
| 902 | isSub = OffImm < 0; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 903 | |
| 904 | // Special value for #-0. All others are normal. |
| 905 | if (OffImm == INT32_MIN) |
| 906 | OffImm = 0; |
| 907 | if (isSub) { |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 908 | SStream_concat(O, "#-0x%x", -OffImm); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 909 | } else { |
Nguyen Anh Quynh | 256090a | 2016-03-14 13:52:23 +0800 | [diff] [blame] | 910 | printUInt32Bang(O, OffImm); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 911 | } |
| 912 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 913 | SStream_concat0(O, "]"); |
Nguyen Anh Quynh | bb71c13 | 2014-06-01 10:14:31 +0700 | [diff] [blame] | 914 | |
| 915 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 916 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM; |
| 917 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_PC; |
| 918 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID; |
| 919 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1; |
| 920 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 921 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 922 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | bb71c13 | 2014-06-01 10:14:31 +0700 | [diff] [blame] | 923 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 924 | } |
| 925 | |
| 926 | // so_reg is a 4-operand unit corresponding to register forms of the A5.1 |
| 927 | // "Addressing Mode 1 - Data-processing operands" forms. This includes: |
| 928 | // REG 0 0 - e.g. R5 |
| 929 | // REG REG 0,SH_OPC - e.g. R5, ROR R3 |
| 930 | // REG 0 IMM,SH_OPC - e.g. R5, LSL #3 |
| 931 | static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O) |
| 932 | { |
| 933 | MCOperand *MO1 = MCInst_getOperand(MI, OpNum); |
| 934 | MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); |
| 935 | MCOperand *MO3 = MCInst_getOperand(MI, OpNum+2); |
Nguyen Anh Quynh | 42706a3 | 2014-05-09 07:33:35 +0800 | [diff] [blame] | 936 | ARM_AM_ShiftOpc ShOpc; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 937 | |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 938 | printRegName(MI->csh, O, MCOperand_getReg(MO1)); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 939 | |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 940 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 941 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 942 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 943 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 944 | |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 945 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (MCOperand_getImm(MO3) & 7) + ARM_SFT_ASR_REG - 1; |
| 946 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 947 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 948 | |
| 949 | // Print the shift opc. |
Axel 0vercl0k Souchet | 779d4c7 | 2014-05-08 23:44:49 +0100 | [diff] [blame] | 950 | ShOpc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3)); |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 951 | SStream_concat0(O, ", "); |
| 952 | SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc)); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 953 | if (ShOpc == ARM_AM_rrx) |
| 954 | return; |
| 955 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 956 | SStream_concat0(O, " "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 957 | printRegName(MI->csh, O, MCOperand_getReg(MO2)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 958 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 959 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = MCOperand_getReg(MO2); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 960 | //assert(ARM_AM_getSORegOffset(MO3.getImm()) == 0); |
| 961 | } |
| 962 | |
| 963 | static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O) |
| 964 | { |
| 965 | MCOperand *MO1 = MCInst_getOperand(MI, OpNum); |
| 966 | MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); |
| 967 | |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 968 | printRegName(MI->csh, O, MCOperand_getReg(MO1)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 969 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 970 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 971 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 972 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 973 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = MCOperand_getImm(MO2) & 7; |
| 974 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = (unsigned int)MCOperand_getImm(MO2) >> 3; |
| 975 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 976 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 977 | |
| 978 | // Print the shift opc. |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 979 | printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)), |
Nguyen Anh Quynh | 8c1104b | 2014-06-10 00:39:06 +0700 | [diff] [blame] | 980 | getSORegOffset((unsigned int)MCOperand_getImm(MO2))); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 981 | } |
| 982 | |
| 983 | //===--------------------------------------------------------------------===// |
| 984 | // Addressing Mode #2 |
| 985 | //===--------------------------------------------------------------------===// |
| 986 | |
| 987 | static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O) |
| 988 | { |
| 989 | MCOperand *MO1 = MCInst_getOperand(MI, Op); |
| 990 | MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); |
| 991 | MCOperand *MO3 = MCInst_getOperand(MI, Op + 2); |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 992 | ARM_AM_AddrOpc subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO3)); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 993 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 994 | SStream_concat0(O, "["); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 995 | set_mem_access(MI, true); |
| 996 | |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 997 | printRegName(MI->csh, O, MCOperand_getReg(MO1)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 998 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 999 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1000 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1001 | |
| 1002 | if (!MCOperand_getReg(MO2)) { |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 1003 | unsigned tmp = getAM2Offset((unsigned int)MCOperand_getImm(MO3)); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1004 | if (tmp) { // Don't print +0. |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 1005 | subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO3)); |
| 1006 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1007 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1008 | if (tmp > HEX_THRESHOLD) |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 1009 | SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), tmp); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1010 | else |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 1011 | SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), tmp); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1012 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1013 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)getAM2Op((unsigned int)MCOperand_getImm(MO3)); |
| 1014 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = tmp; |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 1015 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1016 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1017 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1018 | SStream_concat0(O, "]"); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1019 | set_mem_access(MI, false); |
| 1020 | return; |
| 1021 | } |
| 1022 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1023 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 1024 | SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted)); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 1025 | printRegName(MI->csh, O, MCOperand_getReg(MO2)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1026 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1027 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 1028 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1029 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1030 | |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 1031 | printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO3)), |
Nguyen Anh Quynh | 8c1104b | 2014-06-10 00:39:06 +0700 | [diff] [blame] | 1032 | getAM2Offset((unsigned int)MCOperand_getImm(MO3))); |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1033 | SStream_concat0(O, "]"); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1034 | set_mem_access(MI, false); |
| 1035 | } |
| 1036 | |
| 1037 | static void printAddrModeTBB(MCInst *MI, unsigned Op, SStream *O) |
| 1038 | { |
| 1039 | MCOperand *MO1 = MCInst_getOperand(MI, Op); |
| 1040 | MCOperand *MO2 = MCInst_getOperand(MI, Op+1); |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1041 | SStream_concat0(O, "["); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1042 | set_mem_access(MI, true); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 1043 | printRegName(MI->csh, O, MCOperand_getReg(MO1)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1044 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1045 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1046 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 1047 | printRegName(MI->csh, O, MCOperand_getReg(MO2)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1048 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1049 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1050 | SStream_concat0(O, "]"); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1051 | set_mem_access(MI, false); |
| 1052 | } |
| 1053 | |
| 1054 | static void printAddrModeTBH(MCInst *MI, unsigned Op, SStream *O) |
| 1055 | { |
| 1056 | MCOperand *MO1 = MCInst_getOperand(MI, Op); |
| 1057 | MCOperand *MO2 = MCInst_getOperand(MI, Op+1); |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1058 | SStream_concat0(O, "["); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1059 | set_mem_access(MI, true); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 1060 | printRegName(MI->csh, O, MCOperand_getReg(MO1)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1061 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1062 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1063 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 1064 | printRegName(MI->csh, O, MCOperand_getReg(MO2)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1065 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1066 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1067 | SStream_concat0(O, ", lsl #1]"); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1068 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 706b808 | 2015-01-12 15:27:29 +0800 | [diff] [blame] | 1069 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.lshift = 1; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1070 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1071 | set_mem_access(MI, false); |
| 1072 | } |
| 1073 | |
| 1074 | static void printAddrMode2Operand(MCInst *MI, unsigned Op, SStream *O) |
| 1075 | { |
| 1076 | MCOperand *MO1 = MCInst_getOperand(MI, Op); |
| 1077 | |
| 1078 | if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. |
| 1079 | printOperand(MI, Op, O); |
| 1080 | return; |
| 1081 | } |
| 1082 | |
| 1083 | printAM2PreOrOffsetIndexOp(MI, Op, O); |
| 1084 | } |
| 1085 | |
| 1086 | static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) |
| 1087 | { |
| 1088 | MCOperand *MO1 = MCInst_getOperand(MI, OpNum); |
| 1089 | MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 1090 | ARM_AM_AddrOpc subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO2)); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1091 | |
| 1092 | if (!MCOperand_getReg(MO1)) { |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 1093 | unsigned ImmOffs = getAM2Offset((unsigned int)MCOperand_getImm(MO2)); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1094 | if (ImmOffs > HEX_THRESHOLD) |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1095 | SStream_concat(O, "#%s0x%x", |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 1096 | ARM_AM_getAddrOpcStr(subtracted), ImmOffs); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1097 | else |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1098 | SStream_concat(O, "#%s%u", |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 1099 | ARM_AM_getAddrOpcStr(subtracted), ImmOffs); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1100 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1101 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; |
| 1102 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs; |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 1103 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1104 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1105 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1106 | return; |
| 1107 | } |
| 1108 | |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 1109 | SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted)); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 1110 | printRegName(MI->csh, O, MCOperand_getReg(MO1)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1111 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1112 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 1113 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 1114 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 1115 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1116 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1117 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1118 | |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 1119 | printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO2)), |
Nguyen Anh Quynh | 8c1104b | 2014-06-10 00:39:06 +0700 | [diff] [blame] | 1120 | getAM2Offset((unsigned int)MCOperand_getImm(MO2))); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1121 | } |
| 1122 | |
| 1123 | //===--------------------------------------------------------------------===// |
| 1124 | // Addressing Mode #3 |
| 1125 | //===--------------------------------------------------------------------===// |
| 1126 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1127 | static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O, |
| 1128 | bool AlwaysPrintImm0) |
| 1129 | { |
| 1130 | MCOperand *MO1 = MCInst_getOperand(MI, Op); |
| 1131 | MCOperand *MO2 = MCInst_getOperand(MI, Op+1); |
| 1132 | MCOperand *MO3 = MCInst_getOperand(MI, Op+2); |
Nguyen Anh Quynh | ed43e24 | 2015-08-15 14:16:39 +0800 | [diff] [blame] | 1133 | ARM_AM_AddrOpc sign = getAM3Op((unsigned int)MCOperand_getImm(MO3)); |
Nguyen Anh Quynh | bb0744d | 2014-05-12 13:41:49 +0800 | [diff] [blame] | 1134 | unsigned ImmOffs; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1135 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1136 | SStream_concat0(O, "["); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1137 | set_mem_access(MI, true); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 1138 | printRegName(MI->csh, O, MCOperand_getReg(MO1)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1139 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1140 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1141 | |
| 1142 | if (MCOperand_getReg(MO2)) { |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1143 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | ed43e24 | 2015-08-15 14:16:39 +0800 | [diff] [blame] | 1144 | SStream_concat0(O, ARM_AM_getAddrOpcStr(sign)); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 1145 | printRegName(MI->csh, O, MCOperand_getReg(MO2)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1146 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1147 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); |
Nguyen Anh Quynh | ed43e24 | 2015-08-15 14:16:39 +0800 | [diff] [blame] | 1148 | if (!sign) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1149 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = -1; |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 1150 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true; |
| 1151 | } |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1152 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1153 | SStream_concat0(O, "]"); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1154 | set_mem_access(MI, false); |
| 1155 | return; |
| 1156 | } |
| 1157 | |
| 1158 | //If the op is sub we have to print the immediate even if it is 0 |
Axel 0vercl0k Souchet | 779d4c7 | 2014-05-08 23:44:49 +0100 | [diff] [blame] | 1159 | ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO3)); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1160 | |
Nguyen Anh Quynh | ed43e24 | 2015-08-15 14:16:39 +0800 | [diff] [blame] | 1161 | if (AlwaysPrintImm0 || ImmOffs || (sign == ARM_AM_sub)) { |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1162 | if (ImmOffs > HEX_THRESHOLD) |
Nguyen Anh Quynh | ed43e24 | 2015-08-15 14:16:39 +0800 | [diff] [blame] | 1163 | SStream_concat(O, ", #%s0x%x", ARM_AM_getAddrOpcStr(sign), ImmOffs); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1164 | else |
Nguyen Anh Quynh | ed43e24 | 2015-08-15 14:16:39 +0800 | [diff] [blame] | 1165 | SStream_concat(O, ", #%s%u", ARM_AM_getAddrOpcStr(sign), ImmOffs); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1166 | } |
Nguyen Anh Quynh | 6677b99 | 2013-12-08 22:20:35 +0800 | [diff] [blame] | 1167 | |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1168 | if (MI->csh->detail) { |
Nguyen Anh Quynh | ed43e24 | 2015-08-15 14:16:39 +0800 | [diff] [blame] | 1169 | if (!sign) { |
Nguyen Anh Quynh | ddf5488 | 2015-08-19 22:36:09 +0800 | [diff] [blame] | 1170 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs; |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 1171 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true; |
| 1172 | } else |
Nguyen Anh Quynh | ddf5488 | 2015-08-19 22:36:09 +0800 | [diff] [blame] | 1173 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = (int)ImmOffs; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1174 | } |
Nguyen Anh Quynh | 6677b99 | 2013-12-08 22:20:35 +0800 | [diff] [blame] | 1175 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1176 | SStream_concat0(O, "]"); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1177 | set_mem_access(MI, false); |
| 1178 | } |
| 1179 | |
| 1180 | static void printAddrMode3Operand(MCInst *MI, unsigned Op, SStream *O, |
| 1181 | bool AlwaysPrintImm0) |
| 1182 | { |
| 1183 | MCOperand *MO1 = MCInst_getOperand(MI, Op); |
| 1184 | if (!MCOperand_isReg(MO1)) { // For label symbolic references. |
| 1185 | printOperand(MI, Op, O); |
| 1186 | return; |
| 1187 | } |
| 1188 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1189 | printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0); |
| 1190 | } |
| 1191 | |
| 1192 | static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) |
| 1193 | { |
| 1194 | MCOperand *MO1 = MCInst_getOperand(MI, OpNum); |
| 1195 | MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 1196 | ARM_AM_AddrOpc subtracted = getAM3Op((unsigned int)MCOperand_getImm(MO2)); |
Nguyen Anh Quynh | bb0744d | 2014-05-12 13:41:49 +0800 | [diff] [blame] | 1197 | unsigned ImmOffs; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1198 | |
| 1199 | if (MCOperand_getReg(MO1)) { |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 1200 | SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted)); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 1201 | printRegName(MI->csh, O, MCOperand_getReg(MO1)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1202 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1203 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
Nguyen Anh Quynh | 8693fcd | 2014-06-17 13:28:33 +0800 | [diff] [blame] | 1204 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 1205 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 1206 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1207 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1208 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1209 | return; |
| 1210 | } |
| 1211 | |
Axel 0vercl0k Souchet | 779d4c7 | 2014-05-08 23:44:49 +0100 | [diff] [blame] | 1212 | ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO2)); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1213 | if (ImmOffs > HEX_THRESHOLD) |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 1214 | SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), ImmOffs); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1215 | else |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 1216 | SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), ImmOffs); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1217 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1218 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; |
Nguyen Anh Quynh | 6677b99 | 2013-12-08 22:20:35 +0800 | [diff] [blame] | 1219 | |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 1220 | if (subtracted) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1221 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs; |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 1222 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true; |
| 1223 | } else |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1224 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = -(int)ImmOffs; |
Nguyen Anh Quynh | 6677b99 | 2013-12-08 22:20:35 +0800 | [diff] [blame] | 1225 | |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1226 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1227 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1228 | } |
| 1229 | |
| 1230 | static void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O) |
| 1231 | { |
| 1232 | MCOperand *MO = MCInst_getOperand(MI, OpNum); |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 1233 | unsigned Imm = (unsigned int)MCOperand_getImm(MO); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1234 | if ((Imm & 0xff) > HEX_THRESHOLD) |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1235 | SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), (Imm & 0xff)); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1236 | else |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1237 | SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), (Imm & 0xff)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1238 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1239 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; |
| 1240 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm & 0xff; |
| 1241 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1242 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1243 | } |
| 1244 | |
| 1245 | static void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O) |
| 1246 | { |
| 1247 | MCOperand *MO1 = MCInst_getOperand(MI, OpNum); |
| 1248 | MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); |
| 1249 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1250 | SStream_concat0(O, (MCOperand_getImm(MO2) ? "" : "-")); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 1251 | printRegName(MI->csh, O, MCOperand_getReg(MO1)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1252 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1253 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 1254 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 1255 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1256 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1257 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1258 | } |
| 1259 | |
| 1260 | static void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O) |
| 1261 | { |
| 1262 | MCOperand *MO = MCInst_getOperand(MI, OpNum); |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 1263 | unsigned Imm = (unsigned int)MCOperand_getImm(MO); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1264 | if (((Imm & 0xff) << 2) > HEX_THRESHOLD) |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1265 | SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2)); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1266 | else |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1267 | SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2)); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1268 | } |
| 1269 | |
| 1270 | static void printAddrMode5Operand(MCInst *MI, unsigned OpNum, SStream *O, |
| 1271 | bool AlwaysPrintImm0) |
| 1272 | { |
Nguyen Anh Quynh | 6acaaa5 | 2014-11-10 17:41:05 +0800 | [diff] [blame] | 1273 | unsigned ImmOffs; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1274 | MCOperand *MO1 = MCInst_getOperand(MI, OpNum); |
| 1275 | MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); |
Nguyen Anh Quynh | 6acaaa5 | 2014-11-10 17:41:05 +0800 | [diff] [blame] | 1276 | ARM_AM_AddrOpc subtracted = ARM_AM_getAM5Op((unsigned int)MCOperand_getImm(MO2)); |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 1277 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1278 | if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. |
| 1279 | printOperand(MI, OpNum, O); |
| 1280 | return; |
| 1281 | } |
| 1282 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1283 | SStream_concat0(O, "["); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 1284 | printRegName(MI->csh, O, MCOperand_getReg(MO1)); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1285 | |
Nguyen Anh Quynh | b79d915 | 2014-06-01 10:48:55 +0700 | [diff] [blame] | 1286 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1287 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM; |
| 1288 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); |
| 1289 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID; |
| 1290 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1; |
| 1291 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 1292 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; |
Nguyen Anh Quynh | b79d915 | 2014-06-01 10:48:55 +0700 | [diff] [blame] | 1293 | } |
| 1294 | |
Axel 0vercl0k Souchet | 779d4c7 | 2014-05-08 23:44:49 +0100 | [diff] [blame] | 1295 | ImmOffs = ARM_AM_getAM5Offset((unsigned int)MCOperand_getImm(MO2)); |
Nguyen Anh Quynh | 6acaaa5 | 2014-11-10 17:41:05 +0800 | [diff] [blame] | 1296 | if (AlwaysPrintImm0 || ImmOffs || subtracted == ARM_AM_sub) { |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1297 | if (ImmOffs * 4 > HEX_THRESHOLD) |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1298 | SStream_concat(O, ", #%s0x%x", |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 1299 | ARM_AM_getAddrOpcStr(subtracted), |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1300 | ImmOffs * 4); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1301 | else |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1302 | SStream_concat(O, ", #%s%u", |
Nguyen Anh Quynh | 8fb2eab | 2014-10-06 20:27:25 +0800 | [diff] [blame] | 1303 | ARM_AM_getAddrOpcStr(subtracted), |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1304 | ImmOffs * 4); |
Nguyen Anh Quynh | a04ee4f | 2014-06-01 10:52:01 +0700 | [diff] [blame] | 1305 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 6acaaa5 | 2014-11-10 17:41:05 +0800 | [diff] [blame] | 1306 | if (subtracted) |
| 1307 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = ImmOffs * 4; |
| 1308 | else |
Nguyen Anh Quynh | 51888c3 | 2014-11-11 23:59:23 +0800 | [diff] [blame] | 1309 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs * 4; |
Nguyen Anh Quynh | a04ee4f | 2014-06-01 10:52:01 +0700 | [diff] [blame] | 1310 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1311 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1312 | SStream_concat0(O, "]"); |
Nguyen Anh Quynh | b79d915 | 2014-06-01 10:48:55 +0700 | [diff] [blame] | 1313 | |
| 1314 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1315 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | b79d915 | 2014-06-01 10:48:55 +0700 | [diff] [blame] | 1316 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1317 | } |
| 1318 | |
| 1319 | static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O) |
| 1320 | { |
| 1321 | MCOperand *MO1 = MCInst_getOperand(MI, OpNum); |
| 1322 | MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); |
Nguyen Anh Quynh | bb0744d | 2014-05-12 13:41:49 +0800 | [diff] [blame] | 1323 | unsigned tmp; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1324 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1325 | SStream_concat0(O, "["); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1326 | set_mem_access(MI, true); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 1327 | printRegName(MI->csh, O, MCOperand_getReg(MO1)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1328 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1329 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); |
Axel 0vercl0k Souchet | 779d4c7 | 2014-05-08 23:44:49 +0100 | [diff] [blame] | 1330 | tmp = (unsigned int)MCOperand_getImm(MO2); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1331 | if (tmp) { |
| 1332 | if (tmp << 3 > HEX_THRESHOLD) |
| 1333 | SStream_concat(O, ":0x%x", (tmp << 3)); |
| 1334 | else |
| 1335 | SStream_concat(O, ":%u", (tmp << 3)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1336 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1337 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp << 3; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1338 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1339 | SStream_concat0(O, "]"); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1340 | set_mem_access(MI, false); |
| 1341 | } |
| 1342 | |
| 1343 | static void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O) |
| 1344 | { |
| 1345 | MCOperand *MO1 = MCInst_getOperand(MI, OpNum); |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1346 | SStream_concat0(O, "["); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1347 | set_mem_access(MI, true); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 1348 | printRegName(MI->csh, O, MCOperand_getReg(MO1)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1349 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1350 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1351 | SStream_concat0(O, "]"); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1352 | set_mem_access(MI, false); |
| 1353 | } |
| 1354 | |
| 1355 | static void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) |
| 1356 | { |
| 1357 | MCOperand *MO = MCInst_getOperand(MI, OpNum); |
Nguyen Anh Quynh | 03e5e10 | 2015-01-21 12:15:14 +0800 | [diff] [blame] | 1358 | if (MCOperand_getReg(MO) == 0) { |
| 1359 | MI->writeback = true; |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1360 | SStream_concat0(O, "!"); |
Nguyen Anh Quynh | 03e5e10 | 2015-01-21 12:15:14 +0800 | [diff] [blame] | 1361 | } else { |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1362 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 1363 | printRegName(MI->csh, O, MCOperand_getReg(MO)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1364 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1365 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 1366 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 1367 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1368 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1369 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1370 | } |
| 1371 | } |
| 1372 | |
| 1373 | static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O) |
| 1374 | { |
| 1375 | MCOperand *MO = MCInst_getOperand(MI, OpNum); |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 1376 | uint32_t v = ~(uint32_t)MCOperand_getImm(MO); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1377 | int32_t lsb = CountTrailingZeros_32(v); |
| 1378 | int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb; |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1379 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1380 | //assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!"); |
Nguyen Anh Quynh | 256090a | 2016-03-14 13:52:23 +0800 | [diff] [blame] | 1381 | printUInt32Bang(O, lsb); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1382 | |
| 1383 | if (width > HEX_THRESHOLD) |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1384 | SStream_concat(O, ", #0x%x", width); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1385 | else |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1386 | SStream_concat(O, ", #%u", width); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1387 | |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1388 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1389 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; |
| 1390 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = lsb; |
| 1391 | MI->flat_insn->detail->arm.op_count++; |
| 1392 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; |
| 1393 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = width; |
| 1394 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1395 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1396 | } |
| 1397 | |
| 1398 | static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O) |
| 1399 | { |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 1400 | unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | 8cdafda | 2014-11-11 22:30:30 +0800 | [diff] [blame] | 1401 | SStream_concat0(O, ARM_MB_MemBOptToString(val + 1, |
Nguyen Anh Quynh | 106e0f1 | 2015-05-24 21:33:17 +0800 | [diff] [blame] | 1402 | (ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops) != 0)); |
Nguyen Anh Quynh | 8cdafda | 2014-11-11 22:30:30 +0800 | [diff] [blame] | 1403 | |
| 1404 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 51888c3 | 2014-11-11 23:59:23 +0800 | [diff] [blame] | 1405 | MI->flat_insn->detail->arm.mem_barrier = (arm_mem_barrier)(val + 1); |
Nguyen Anh Quynh | 8cdafda | 2014-11-11 22:30:30 +0800 | [diff] [blame] | 1406 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1407 | } |
| 1408 | |
| 1409 | void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O) |
| 1410 | { |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 1411 | unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1412 | SStream_concat0(O, ARM_ISB_InstSyncBOptToString(val)); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1413 | } |
| 1414 | |
| 1415 | static void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O) |
| 1416 | { |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 1417 | unsigned ShiftOp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1418 | bool isASR = (ShiftOp & (1 << 5)) != 0; |
| 1419 | unsigned Amt = ShiftOp & 0x1f; |
| 1420 | if (isASR) { |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1421 | unsigned tmp = Amt == 0 ? 32 : Amt; |
| 1422 | if (tmp > HEX_THRESHOLD) |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1423 | SStream_concat(O, ", asr #0x%x", tmp); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1424 | else |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1425 | SStream_concat(O, ", asr #%u", tmp); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1426 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1427 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR; |
| 1428 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1429 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1430 | } else if (Amt) { |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1431 | if (Amt > HEX_THRESHOLD) |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1432 | SStream_concat(O, ", lsl #0x%x", Amt); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1433 | else |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1434 | SStream_concat(O, ", lsl #%u", Amt); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1435 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1436 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL; |
| 1437 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Amt; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1438 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1439 | } |
| 1440 | } |
| 1441 | |
| 1442 | static void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O) |
| 1443 | { |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 1444 | unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1445 | if (Imm == 0) |
| 1446 | return; |
| 1447 | //assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!"); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1448 | if (Imm > HEX_THRESHOLD) |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1449 | SStream_concat(O, ", lsl #0x%x", Imm); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1450 | else |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1451 | SStream_concat(O, ", lsl #%u", Imm); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1452 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1453 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL; |
| 1454 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1455 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1456 | } |
| 1457 | |
| 1458 | static void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O) |
| 1459 | { |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 1460 | unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1461 | // A shift amount of 32 is encoded as 0. |
| 1462 | if (Imm == 0) |
| 1463 | Imm = 32; |
| 1464 | //assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!"); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1465 | if (Imm > HEX_THRESHOLD) |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1466 | SStream_concat(O, ", asr #0x%x", Imm); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1467 | else |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1468 | SStream_concat(O, ", asr #%u", Imm); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1469 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1470 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR; |
| 1471 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1472 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1473 | } |
| 1474 | |
| 1475 | // FIXME: push {r1, r2, r3, ...} can exceed the number of operands in MCInst struct |
| 1476 | static void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O) |
| 1477 | { |
Nguyen Anh Quynh | 42706a3 | 2014-05-09 07:33:35 +0800 | [diff] [blame] | 1478 | unsigned i, e; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 1479 | #ifndef CAPSTONE_DIET |
Ole André Vadla Ravnås | d2e6b5a | 2015-04-23 12:19:38 +0200 | [diff] [blame] | 1480 | uint8_t access = 0; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 1481 | #endif |
| 1482 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1483 | SStream_concat0(O, "{"); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 1484 | |
| 1485 | #ifndef CAPSTONE_DIET |
| 1486 | if (MI->csh->detail) { |
| 1487 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
| 1488 | } |
| 1489 | #endif |
| 1490 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1491 | for (i = OpNum, e = MCInst_getNumOperands(MI); i != e; ++i) { |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1492 | if (i != OpNum) SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 1493 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, i))); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1494 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1495 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 1496 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, i)); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 1497 | #ifndef CAPSTONE_DIET |
| 1498 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 1499 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1500 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1501 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1502 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1503 | SStream_concat0(O, "}"); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 1504 | |
| 1505 | #ifndef CAPSTONE_DIET |
| 1506 | if (MI->csh->detail) { |
| 1507 | MI->ac_idx++; |
| 1508 | } |
| 1509 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1510 | } |
| 1511 | |
| 1512 | static void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O, |
| 1513 | MCRegisterInfo *MRI) |
| 1514 | { |
| 1515 | unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 1516 | printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_0)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1517 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1518 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 1519 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_0); |
| 1520 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1521 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1522 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 1523 | printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_1)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1524 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1525 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 1526 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_1); |
| 1527 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1528 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1529 | } |
| 1530 | |
| 1531 | // SETEND BE/LE |
| 1532 | static void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O) |
| 1533 | { |
| 1534 | MCOperand *Op = MCInst_getOperand(MI, OpNum); |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 1535 | if (MCOperand_getImm(Op)) { |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1536 | SStream_concat0(O, "be"); |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 1537 | if (MI->csh->detail) { |
| 1538 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SETEND; |
| 1539 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].setend = ARM_SETEND_BE; |
| 1540 | MI->flat_insn->detail->arm.op_count++; |
| 1541 | } |
| 1542 | } else { |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1543 | SStream_concat0(O, "le"); |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 1544 | if (MI->csh->detail) { |
| 1545 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SETEND; |
| 1546 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].setend = ARM_SETEND_LE; |
| 1547 | MI->flat_insn->detail->arm.op_count++; |
| 1548 | } |
| 1549 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1550 | } |
| 1551 | |
| 1552 | static void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O) |
| 1553 | { |
| 1554 | MCOperand *Op = MCInst_getOperand(MI, OpNum); |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 1555 | unsigned int mode = (unsigned int)MCOperand_getImm(Op); |
| 1556 | |
| 1557 | SStream_concat0(O, ARM_PROC_IModToString(mode)); |
| 1558 | |
| 1559 | if (MI->csh->detail) { |
| 1560 | MI->flat_insn->detail->arm.cps_mode = mode; |
| 1561 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1562 | } |
| 1563 | |
| 1564 | static void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O) |
| 1565 | { |
| 1566 | MCOperand *Op = MCInst_getOperand(MI, OpNum); |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 1567 | unsigned IFlags = (unsigned int)MCOperand_getImm(Op); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1568 | int i; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1569 | |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 1570 | for (i = 2; i >= 0; --i) |
| 1571 | if (IFlags & (1 << i)) { |
| 1572 | SStream_concat0(O, ARM_PROC_IFlagsToString(1 << i)); |
| 1573 | } |
| 1574 | |
| 1575 | if (IFlags == 0) { |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1576 | SStream_concat0(O, "none"); |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 1577 | IFlags = ARM_CPSFLAG_NONE; |
| 1578 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1579 | |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1580 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 1581 | MI->flat_insn->detail->arm.cps_flag = IFlags; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1582 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1583 | } |
| 1584 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1585 | static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O) |
| 1586 | { |
| 1587 | MCOperand *Op = MCInst_getOperand(MI, OpNum); |
Nguyen Anh Quynh | 07c92ec | 2014-08-26 15:35:11 +0800 | [diff] [blame] | 1588 | unsigned SpecRegRBit = (unsigned)MCOperand_getImm(Op) >> 4; |
Nguyen Anh Quynh | b52f11f | 2014-08-13 22:38:15 +0800 | [diff] [blame] | 1589 | unsigned Mask = MCOperand_getImm(Op) & 0xf; |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 1590 | unsigned reg; |
Nguyen Anh Quynh | d1fc2bd | 2015-03-03 16:26:32 +0800 | [diff] [blame] | 1591 | uint64_t FeatureBits = ARM_getFeatureBits(MI->csh->mode); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1592 | |
Nguyen Anh Quynh | d1fc2bd | 2015-03-03 16:26:32 +0800 | [diff] [blame] | 1593 | if (FeatureBits & ARM_FeatureMClass) { |
Nguyen Anh Quynh | 07c92ec | 2014-08-26 15:35:11 +0800 | [diff] [blame] | 1594 | unsigned SYSm = (unsigned)MCOperand_getImm(Op); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1595 | unsigned Opcode = MCInst_getOpcode(MI); |
Nguyen Anh Quynh | d1fc2bd | 2015-03-03 16:26:32 +0800 | [diff] [blame] | 1596 | |
| 1597 | // For writes, handle extended mask bits if the DSP extension is present. |
| 1598 | if (Opcode == ARM_t2MSR_M && (FeatureBits & ARM_FeatureDSPThumb2)) { |
| 1599 | switch (SYSm) { |
| 1600 | case 0x400: SStream_concat0(O, "apsr_g"); ARM_addSysReg(MI, ARM_SYSREG_APSR_G); return; |
| 1601 | case 0xc00: SStream_concat0(O, "apsr_nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQG); return; |
| 1602 | case 0x401: SStream_concat0(O, "iapsr_g"); ARM_addSysReg(MI, ARM_SYSREG_IAPSR_G); return; |
| 1603 | case 0xc01: SStream_concat0(O, "iapsr_nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_IAPSR_NZCVQG); return; |
| 1604 | case 0x402: SStream_concat0(O, "eapsr_g"); ARM_addSysReg(MI, ARM_SYSREG_EAPSR_G); return; |
| 1605 | case 0xc02: SStream_concat0(O, "eapsr_nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_EAPSR_NZCVQG); return; |
| 1606 | case 0x403: SStream_concat0(O, "xpsr_g"); ARM_addSysReg(MI, ARM_SYSREG_XPSR_G); return; |
| 1607 | case 0xc03: SStream_concat0(O, "xpsr_nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_XPSR_NZCVQG); return; |
| 1608 | } |
| 1609 | } |
| 1610 | |
| 1611 | // Handle the basic 8-bit mask. |
| 1612 | SYSm &= 0xff; |
| 1613 | |
| 1614 | if (Opcode == ARM_t2MSR_M && (FeatureBits & ARM_HasV7Ops)) { |
| 1615 | // ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an |
| 1616 | // alias for MSR APSR_nzcvq. |
| 1617 | switch (SYSm) { |
| 1618 | case 0: SStream_concat0(O, "apsr_nzcvq"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQ); return; |
| 1619 | case 1: SStream_concat0(O, "iapsr_nzcvq"); ARM_addSysReg(MI, ARM_SYSREG_IAPSR_NZCVQ); return; |
| 1620 | case 2: SStream_concat0(O, "eapsr_nzcvq"); ARM_addSysReg(MI, ARM_SYSREG_EAPSR_NZCVQ); return; |
| 1621 | case 3: SStream_concat0(O, "xpsr_nzcvq"); ARM_addSysReg(MI, ARM_SYSREG_XPSR_NZCVQ); return; |
| 1622 | } |
| 1623 | } |
| 1624 | |
| 1625 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1626 | switch (SYSm) { |
Nguyen Anh Quynh | b52f11f | 2014-08-13 22:38:15 +0800 | [diff] [blame] | 1627 | default: //llvm_unreachable("Unexpected mask value!"); |
Nguyen Anh Quynh | 7e25609 | 2015-03-03 18:28:10 +0800 | [diff] [blame] | 1628 | case 0: SStream_concat0(O, "apsr"); ARM_addSysReg(MI, ARM_SYSREG_APSR); return; |
| 1629 | case 1: SStream_concat0(O, "iapsr"); ARM_addSysReg(MI, ARM_SYSREG_IAPSR); return; |
| 1630 | case 2: SStream_concat0(O, "eapsr"); ARM_addSysReg(MI, ARM_SYSREG_EAPSR); return; |
| 1631 | case 3: SStream_concat0(O, "xpsr"); ARM_addSysReg(MI, ARM_SYSREG_XPSR); return; |
| 1632 | case 5: SStream_concat0(O, "ipsr"); ARM_addSysReg(MI, ARM_SYSREG_IPSR); return; |
| 1633 | case 6: SStream_concat0(O, "epsr"); ARM_addSysReg(MI, ARM_SYSREG_EPSR); return; |
| 1634 | case 7: SStream_concat0(O, "iepsr"); ARM_addSysReg(MI, ARM_SYSREG_IEPSR); return; |
| 1635 | case 8: SStream_concat0(O, "msp"); ARM_addSysReg(MI, ARM_SYSREG_MSP); return; |
| 1636 | case 9: SStream_concat0(O, "psp"); ARM_addSysReg(MI, ARM_SYSREG_PSP); return; |
| 1637 | case 16: SStream_concat0(O, "primask"); ARM_addSysReg(MI, ARM_SYSREG_PRIMASK); return; |
| 1638 | case 17: SStream_concat0(O, "basepri"); ARM_addSysReg(MI, ARM_SYSREG_BASEPRI); return; |
| 1639 | case 18: SStream_concat0(O, "basepri_max"); ARM_addSysReg(MI, ARM_SYSREG_BASEPRI_MAX); return; |
| 1640 | case 19: SStream_concat0(O, "faultmask"); ARM_addSysReg(MI, ARM_SYSREG_FAULTMASK); return; |
| 1641 | case 20: SStream_concat0(O, "control"); ARM_addSysReg(MI, ARM_SYSREG_CONTROL); return; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1642 | } |
| 1643 | } |
Nguyen Anh Quynh | b52f11f | 2014-08-13 22:38:15 +0800 | [diff] [blame] | 1644 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1645 | // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as |
| 1646 | // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively. |
| 1647 | if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) { |
Nguyen Anh Quynh | d865f39 | 2014-11-10 16:38:17 +0800 | [diff] [blame] | 1648 | SStream_concat0(O, "apsr_"); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1649 | switch (Mask) { |
Nguyen Anh Quynh | b52f11f | 2014-08-13 22:38:15 +0800 | [diff] [blame] | 1650 | default: // llvm_unreachable("Unexpected mask value!"); |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 1651 | case 4: SStream_concat0(O, "g"); ARM_addSysReg(MI, ARM_SYSREG_APSR_G); return; |
| 1652 | case 8: SStream_concat0(O, "nzcvq"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQ); return; |
| 1653 | case 12: SStream_concat0(O, "nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQG); return; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1654 | } |
| 1655 | } |
| 1656 | |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 1657 | reg = 0; |
| 1658 | if (SpecRegRBit) { |
Nguyen Anh Quynh | d865f39 | 2014-11-10 16:38:17 +0800 | [diff] [blame] | 1659 | SStream_concat0(O, "spsr"); |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 1660 | if (Mask) { |
| 1661 | SStream_concat0(O, "_"); |
| 1662 | if (Mask & 8) { |
| 1663 | SStream_concat0(O, "f"); |
| 1664 | reg += ARM_SYSREG_SPSR_F; |
| 1665 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1666 | |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 1667 | if (Mask & 4) { |
| 1668 | SStream_concat0(O, "s"); |
| 1669 | reg += ARM_SYSREG_SPSR_S; |
| 1670 | } |
| 1671 | |
| 1672 | if (Mask & 2) { |
| 1673 | SStream_concat0(O, "x"); |
| 1674 | reg += ARM_SYSREG_SPSR_X; |
| 1675 | } |
| 1676 | |
| 1677 | if (Mask & 1) { |
| 1678 | SStream_concat0(O, "c"); |
| 1679 | reg += ARM_SYSREG_SPSR_C; |
| 1680 | } |
| 1681 | ARM_addSysReg(MI, reg); |
| 1682 | } |
| 1683 | } else { |
Nguyen Anh Quynh | d865f39 | 2014-11-10 16:38:17 +0800 | [diff] [blame] | 1684 | SStream_concat0(O, "cpsr"); |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 1685 | if (Mask) { |
| 1686 | SStream_concat0(O, "_"); |
| 1687 | if (Mask & 8) { |
| 1688 | SStream_concat0(O, "f"); |
| 1689 | reg += ARM_SYSREG_CPSR_F; |
| 1690 | } |
| 1691 | |
| 1692 | if (Mask & 4) { |
| 1693 | SStream_concat0(O, "s"); |
| 1694 | reg += ARM_SYSREG_CPSR_S; |
| 1695 | } |
| 1696 | |
| 1697 | if (Mask & 2) { |
| 1698 | SStream_concat0(O, "x"); |
| 1699 | reg += ARM_SYSREG_CPSR_X; |
| 1700 | } |
| 1701 | |
| 1702 | if (Mask & 1) { |
| 1703 | SStream_concat0(O, "c"); |
| 1704 | reg += ARM_SYSREG_CPSR_C; |
| 1705 | } |
| 1706 | ARM_addSysReg(MI, reg); |
| 1707 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1708 | } |
| 1709 | } |
| 1710 | |
Nguyen Anh Quynh | d1fc2bd | 2015-03-03 16:26:32 +0800 | [diff] [blame] | 1711 | static void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O) |
| 1712 | { |
Nguyen Anh Quynh | 586e439 | 2016-03-08 00:49:15 +0800 | [diff] [blame] | 1713 | uint32_t Banked = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | d1fc2bd | 2015-03-03 16:26:32 +0800 | [diff] [blame] | 1714 | uint32_t R = (Banked & 0x20) >> 5; |
| 1715 | uint32_t SysM = Banked & 0x1f; |
| 1716 | char *RegNames[] = { |
| 1717 | "r8_usr", "r9_usr", "r10_usr", "r11_usr", "r12_usr", "sp_usr", "lr_usr", "", |
| 1718 | "r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "sp_fiq", "lr_fiq", "", |
| 1719 | "lr_irq", "sp_irq", "lr_svc", "sp_svc", "lr_abt", "sp_abt", "lr_und", "sp_und", |
| 1720 | "", "", "", "", "lr_mon", "sp_mon", "elr_hyp", "sp_hyp" |
| 1721 | }; |
Nguyen Anh Quynh | 7e25609 | 2015-03-03 18:28:10 +0800 | [diff] [blame] | 1722 | arm_sysreg RegIds[] = { |
| 1723 | ARM_SYSREG_R8_USR, ARM_SYSREG_R9_USR, ARM_SYSREG_R10_USR, |
| 1724 | ARM_SYSREG_R11_USR, ARM_SYSREG_R12_USR, ARM_SYSREG_SP_USR, |
| 1725 | ARM_SYSREG_LR_USR, 0, ARM_SYSREG_R8_FIQ, ARM_SYSREG_R9_FIQ, |
| 1726 | ARM_SYSREG_R10_FIQ, ARM_SYSREG_R11_FIQ, ARM_SYSREG_R12_FIQ, |
| 1727 | ARM_SYSREG_SP_FIQ, ARM_SYSREG_LR_FIQ, 0, ARM_SYSREG_LR_IRQ, |
| 1728 | ARM_SYSREG_SP_IRQ, ARM_SYSREG_LR_SVC, ARM_SYSREG_SP_SVC, |
| 1729 | ARM_SYSREG_LR_ABT, ARM_SYSREG_SP_ABT, ARM_SYSREG_LR_UND, |
| 1730 | ARM_SYSREG_SP_UND, 0, 0, 0, 0, ARM_SYSREG_LR_MON, ARM_SYSREG_SP_MON, |
| 1731 | ARM_SYSREG_ELR_HYP, ARM_SYSREG_SP_HYP, |
| 1732 | }; |
Nguyen Anh Quynh | d1fc2bd | 2015-03-03 16:26:32 +0800 | [diff] [blame] | 1733 | char *Name = RegNames[SysM]; |
| 1734 | |
| 1735 | // Nothing much we can do about this, the encodings are specified in B9.2.3 of |
| 1736 | // the ARM ARM v7C, and are all over the shop. |
| 1737 | if (R) { |
| 1738 | SStream_concat0(O, "SPSR_"); |
| 1739 | |
| 1740 | switch(SysM) { |
| 1741 | default: // llvm_unreachable("Invalid banked SPSR register"); |
Nguyen Anh Quynh | 7e25609 | 2015-03-03 18:28:10 +0800 | [diff] [blame] | 1742 | case 0x0e: SStream_concat0(O, "fiq"); ARM_addSysReg(MI, ARM_SYSREG_SPSR_FIQ); return; |
| 1743 | case 0x10: SStream_concat0(O, "irq"); ARM_addSysReg(MI, ARM_SYSREG_SPSR_IRQ); return; |
| 1744 | case 0x12: SStream_concat0(O, "svc"); ARM_addSysReg(MI, ARM_SYSREG_SPSR_SVC); return; |
| 1745 | case 0x14: SStream_concat0(O, "abt"); ARM_addSysReg(MI, ARM_SYSREG_SPSR_ABT); return; |
| 1746 | case 0x16: SStream_concat0(O, "und"); ARM_addSysReg(MI, ARM_SYSREG_SPSR_UND); return; |
| 1747 | case 0x1c: SStream_concat0(O, "mon"); ARM_addSysReg(MI, ARM_SYSREG_SPSR_MON); return; |
| 1748 | case 0x1e: SStream_concat0(O, "hyp"); ARM_addSysReg(MI, ARM_SYSREG_SPSR_HYP); return; |
Nguyen Anh Quynh | d1fc2bd | 2015-03-03 16:26:32 +0800 | [diff] [blame] | 1749 | } |
| 1750 | } |
| 1751 | |
| 1752 | //assert(!R && "should have dealt with SPSR regs"); |
| 1753 | //assert(Name[0] && "invalid banked register operand"); |
| 1754 | |
| 1755 | SStream_concat0(O, Name); |
Nguyen Anh Quynh | 7e25609 | 2015-03-03 18:28:10 +0800 | [diff] [blame] | 1756 | ARM_addSysReg(MI, RegIds[SysM]); |
Nguyen Anh Quynh | d1fc2bd | 2015-03-03 16:26:32 +0800 | [diff] [blame] | 1757 | } |
| 1758 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1759 | static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) |
| 1760 | { |
| 1761 | ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
| 1762 | // Handle the undefined 15 CC value here for printing so we don't abort(). |
| 1763 | if ((unsigned)CC == 15) { |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1764 | SStream_concat0(O, "<und>"); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1765 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1766 | MI->flat_insn->detail->arm.cc = ARM_CC_INVALID; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1767 | } else { |
| 1768 | if (CC != ARMCC_AL) { |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1769 | SStream_concat0(O, ARMCC_ARMCondCodeToString(CC)); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1770 | } |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1771 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1772 | MI->flat_insn->detail->arm.cc = CC + 1; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1773 | } |
| 1774 | } |
| 1775 | |
| 1776 | // TODO: test this |
| 1777 | static void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) |
| 1778 | { |
| 1779 | ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1780 | SStream_concat0(O, ARMCC_ARMCondCodeToString(CC)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1781 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1782 | MI->flat_insn->detail->arm.cc = CC + 1; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1783 | } |
| 1784 | |
| 1785 | static void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O) |
| 1786 | { |
| 1787 | if (MCOperand_getReg(MCInst_getOperand(MI, OpNum))) { |
| 1788 | //assert(MCOperand_getReg(MCInst_getOperand(MI, OpNum)) == ARM_CPSR && |
| 1789 | // "Expect ARM CPSR register!"); |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 1790 | SStream_concat0(O, "s"); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1791 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1792 | MI->flat_insn->detail->arm.update_flags = true; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1793 | } |
| 1794 | } |
| 1795 | |
| 1796 | static void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O) |
| 1797 | { |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 1798 | unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1799 | if (tmp > HEX_THRESHOLD) |
| 1800 | SStream_concat(O, "0x%x", tmp); |
| 1801 | else |
| 1802 | SStream_concat(O, "%u", tmp); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1803 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 19b0de3 | 2013-12-31 22:40:04 +0800 | [diff] [blame] | 1804 | if (MI->csh->doing_mem) { |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 1805 | MI->flat_insn->detail->arm.op_count--; |
tandasat | 45e5eab | 2016-05-11 21:48:32 -0700 | [diff] [blame] | 1806 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].neon_lane = (int8_t)tmp; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 1807 | MI->ac_idx--; // consecutive operands share the same access right |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1808 | } else { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1809 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; |
| 1810 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; |
| 1811 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1812 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1813 | } |
| 1814 | } |
| 1815 | |
| 1816 | static void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O) |
| 1817 | { |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 1818 | unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
| 1819 | |
| 1820 | SStream_concat(O, "p%u", imm); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1821 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1822 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_PIMM; |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 1823 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm; |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1824 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1825 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1826 | } |
| 1827 | |
| 1828 | static void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O) |
| 1829 | { |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 1830 | unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
| 1831 | |
| 1832 | SStream_concat(O, "c%u", imm); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1833 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1834 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_CIMM; |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 1835 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm; |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1836 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1837 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1838 | } |
| 1839 | |
| 1840 | static void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O) |
| 1841 | { |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 1842 | unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1843 | if (tmp > HEX_THRESHOLD) |
| 1844 | SStream_concat(O, "{0x%x}", tmp); |
| 1845 | else |
| 1846 | SStream_concat(O, "{%u}", tmp); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1847 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1848 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; |
| 1849 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; |
| 1850 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1851 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1852 | } |
| 1853 | |
| 1854 | static void printAdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned scale) |
| 1855 | { |
| 1856 | MCOperand *MO = MCInst_getOperand(MI, OpNum); |
| 1857 | |
| 1858 | int32_t OffImm = (int32_t)MCOperand_getImm(MO) << scale; |
| 1859 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1860 | if (OffImm == INT32_MIN) { |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1861 | SStream_concat0(O, "#-0"); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1862 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1863 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; |
| 1864 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0; |
| 1865 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1866 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1867 | } else { |
| 1868 | if (OffImm < 0) |
Nguyen Anh Quynh | 741a9de | 2013-11-28 16:02:08 +0800 | [diff] [blame] | 1869 | SStream_concat(O, "#-0x%x", -OffImm); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1870 | else { |
| 1871 | if (OffImm > HEX_THRESHOLD) |
| 1872 | SStream_concat(O, "#0x%x", OffImm); |
| 1873 | else |
| 1874 | SStream_concat(O, "#%u", OffImm); |
| 1875 | } |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1876 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1877 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; |
| 1878 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm; |
| 1879 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1880 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1881 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1882 | } |
| 1883 | |
| 1884 | static void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O) |
| 1885 | { |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 1886 | unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)) * 4; |
Nguyen Anh Quynh | 256090a | 2016-03-14 13:52:23 +0800 | [diff] [blame] | 1887 | |
| 1888 | printUInt32Bang(O, tmp); |
| 1889 | |
Nguyen Anh Quynh | aa078a1 | 2014-01-23 22:29:04 +0800 | [diff] [blame] | 1890 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1891 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; |
| 1892 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; |
| 1893 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | aa078a1 | 2014-01-23 22:29:04 +0800 | [diff] [blame] | 1894 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1895 | } |
| 1896 | |
| 1897 | static void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O) |
| 1898 | { |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 1899 | unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1900 | unsigned tmp = Imm == 0 ? 32 : Imm; |
Nguyen Anh Quynh | 256090a | 2016-03-14 13:52:23 +0800 | [diff] [blame] | 1901 | |
| 1902 | printUInt32Bang(O, tmp); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 1903 | |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1904 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1905 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; |
| 1906 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; |
| 1907 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 1908 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1909 | } |
| 1910 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1911 | static void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O) |
| 1912 | { |
| 1913 | // (3 - the number of trailing zeros) is the number of then / else. |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 1914 | unsigned Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
| 1915 | unsigned Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum-1)); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1916 | unsigned CondBit0 = Firstcond & 1; |
| 1917 | unsigned NumTZ = CountTrailingZeros_32(Mask); |
| 1918 | //assert(NumTZ <= 3 && "Invalid IT mask!"); |
| 1919 | unsigned Pos, e; |
| 1920 | for (Pos = 3, e = NumTZ; Pos > e; --Pos) { |
| 1921 | bool T = ((Mask >> Pos) & 1) == CondBit0; |
| 1922 | if (T) |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1923 | SStream_concat0(O, "t"); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1924 | else |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1925 | SStream_concat0(O, "e"); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1926 | } |
| 1927 | } |
| 1928 | |
| 1929 | static void printThumbAddrModeRROperand(MCInst *MI, unsigned Op, SStream *O) |
| 1930 | { |
| 1931 | MCOperand *MO1 = MCInst_getOperand(MI, Op); |
| 1932 | MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); |
Nguyen Anh Quynh | bb0744d | 2014-05-12 13:41:49 +0800 | [diff] [blame] | 1933 | unsigned RegNum; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1934 | |
| 1935 | if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. |
| 1936 | printOperand(MI, Op, O); |
| 1937 | return; |
| 1938 | } |
| 1939 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1940 | SStream_concat0(O, "["); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1941 | set_mem_access(MI, true); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 1942 | printRegName(MI->csh, O, MCOperand_getReg(MO1)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1943 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1944 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); |
Axel 0vercl0k Souchet | 779d4c7 | 2014-05-08 23:44:49 +0100 | [diff] [blame] | 1945 | RegNum = MCOperand_getReg(MO2); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1946 | if (RegNum) { |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1947 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 1948 | printRegName(MI->csh, O, RegNum); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1949 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1950 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = RegNum; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1951 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1952 | SStream_concat0(O, "]"); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1953 | set_mem_access(MI, false); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1954 | } |
| 1955 | |
| 1956 | static void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned Op, SStream *O, |
| 1957 | unsigned Scale) |
| 1958 | { |
| 1959 | MCOperand *MO1 = MCInst_getOperand(MI, Op); |
| 1960 | MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); |
Nguyen Anh Quynh | bb0744d | 2014-05-12 13:41:49 +0800 | [diff] [blame] | 1961 | unsigned ImmOffs, tmp; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1962 | |
| 1963 | if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. |
| 1964 | printOperand(MI, Op, O); |
| 1965 | return; |
| 1966 | } |
| 1967 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1968 | SStream_concat0(O, "["); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1969 | set_mem_access(MI, true); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 1970 | printRegName(MI->csh, O, MCOperand_getReg(MO1)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1971 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1972 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); |
Axel 0vercl0k Souchet | 779d4c7 | 2014-05-08 23:44:49 +0100 | [diff] [blame] | 1973 | ImmOffs = (unsigned int)MCOperand_getImm(MO2); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1974 | if (ImmOffs) { |
Axel 0vercl0k Souchet | 779d4c7 | 2014-05-08 23:44:49 +0100 | [diff] [blame] | 1975 | tmp = ImmOffs * Scale; |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1976 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 256090a | 2016-03-14 13:52:23 +0800 | [diff] [blame] | 1977 | printUInt32Bang(O, tmp); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 1978 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 1979 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1980 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 1981 | SStream_concat0(O, "]"); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1982 | set_mem_access(MI, false); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1983 | } |
| 1984 | |
| 1985 | static void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned Op, SStream *O) |
| 1986 | { |
| 1987 | printThumbAddrModeImm5SOperand(MI, Op, O, 1); |
| 1988 | } |
| 1989 | |
| 1990 | static void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned Op, SStream *O) |
| 1991 | { |
| 1992 | printThumbAddrModeImm5SOperand(MI, Op, O, 2); |
| 1993 | } |
| 1994 | |
| 1995 | static void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned Op, SStream *O) |
| 1996 | { |
| 1997 | printThumbAddrModeImm5SOperand(MI, Op, O, 4); |
| 1998 | } |
| 1999 | |
| 2000 | static void printThumbAddrModeSPOperand(MCInst *MI, unsigned Op, SStream *O) |
| 2001 | { |
| 2002 | printThumbAddrModeImm5SOperand(MI, Op, O, 4); |
| 2003 | } |
| 2004 | |
| 2005 | // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2 |
| 2006 | // register with shift forms. |
| 2007 | // REG 0 0 - e.g. R5 |
| 2008 | // REG IMM, SH_OPC - e.g. R5, LSL #3 |
| 2009 | static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O) |
| 2010 | { |
| 2011 | MCOperand *MO1 = MCInst_getOperand(MI, OpNum); |
| 2012 | MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); |
| 2013 | |
| 2014 | unsigned Reg = MCOperand_getReg(MO1); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2015 | printRegName(MI->csh, O, Reg); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2016 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2017 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2018 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2019 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2020 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2021 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2022 | |
| 2023 | // Print the shift opc. |
| 2024 | //assert(MO2.isImm() && "Not a valid t2_so_reg value!"); |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 2025 | printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)), |
Nguyen Anh Quynh | 8c1104b | 2014-06-10 00:39:06 +0700 | [diff] [blame] | 2026 | getSORegOffset((unsigned int)MCOperand_getImm(MO2))); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2027 | } |
| 2028 | |
| 2029 | static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum, |
| 2030 | SStream *O, bool AlwaysPrintImm0) |
| 2031 | { |
| 2032 | MCOperand *MO1 = MCInst_getOperand(MI, OpNum); |
| 2033 | MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); |
Nguyen Anh Quynh | aa078a1 | 2014-01-23 22:29:04 +0800 | [diff] [blame] | 2034 | int32_t OffImm; |
| 2035 | bool isSub; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2036 | |
| 2037 | if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. |
| 2038 | printOperand(MI, OpNum, O); |
| 2039 | return; |
| 2040 | } |
| 2041 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2042 | SStream_concat0(O, "["); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2043 | set_mem_access(MI, true); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2044 | printRegName(MI->csh, O, MCOperand_getReg(MO1)); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2045 | |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2046 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2047 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2048 | |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 2049 | OffImm = (int32_t)MCOperand_getImm(MO2); |
| 2050 | isSub = OffImm < 0; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2051 | // Special value for #-0. All others are normal. |
| 2052 | if (OffImm == INT32_MIN) |
| 2053 | OffImm = 0; |
| 2054 | if (isSub) { |
Nguyen Anh Quynh | a247dc1 | 2014-04-12 00:19:42 +0800 | [diff] [blame] | 2055 | if (OffImm < -HEX_THRESHOLD) |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2056 | SStream_concat(O, ", #-0x%x", -OffImm); |
Nguyen Anh Quynh | a247dc1 | 2014-04-12 00:19:42 +0800 | [diff] [blame] | 2057 | else |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2058 | SStream_concat(O, ", #-%u", -OffImm); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2059 | } else if (AlwaysPrintImm0 || OffImm > 0) { |
Nguyen Anh Quynh | ffff756 | 2014-03-26 16:21:31 +0800 | [diff] [blame] | 2060 | if (OffImm >= 0) { |
| 2061 | if (OffImm > HEX_THRESHOLD) |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2062 | SStream_concat(O, ", #0x%x", OffImm); |
Nguyen Anh Quynh | ffff756 | 2014-03-26 16:21:31 +0800 | [diff] [blame] | 2063 | else |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2064 | SStream_concat(O, ", #%u", OffImm); |
Nguyen Anh Quynh | ffff756 | 2014-03-26 16:21:31 +0800 | [diff] [blame] | 2065 | } else { |
| 2066 | if (OffImm < -HEX_THRESHOLD) |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2067 | SStream_concat(O, ", #-0x%x", -OffImm); |
Nguyen Anh Quynh | ffff756 | 2014-03-26 16:21:31 +0800 | [diff] [blame] | 2068 | else |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2069 | SStream_concat(O, ", #-%u", -OffImm); |
Nguyen Anh Quynh | ffff756 | 2014-03-26 16:21:31 +0800 | [diff] [blame] | 2070 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2071 | } |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2072 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2073 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm; |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2074 | SStream_concat0(O, "]"); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2075 | set_mem_access(MI, false); |
| 2076 | } |
| 2077 | |
| 2078 | static void printT2AddrModeImm8Operand(MCInst *MI, unsigned OpNum, SStream *O, |
| 2079 | bool AlwaysPrintImm0) |
| 2080 | { |
| 2081 | MCOperand *MO1 = MCInst_getOperand(MI, OpNum); |
| 2082 | MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); |
Nguyen Anh Quynh | aa078a1 | 2014-01-23 22:29:04 +0800 | [diff] [blame] | 2083 | int32_t OffImm; |
| 2084 | bool isSub; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2085 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2086 | SStream_concat0(O, "["); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2087 | set_mem_access(MI, true); |
| 2088 | |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2089 | printRegName(MI->csh, O, MCOperand_getReg(MO1)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2090 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2091 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2092 | |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 2093 | OffImm = (int32_t)MCOperand_getImm(MO2); |
| 2094 | isSub = OffImm < 0; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2095 | // Don't print +0. |
| 2096 | if (OffImm == INT32_MIN) |
| 2097 | OffImm = 0; |
| 2098 | |
| 2099 | if (isSub) |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2100 | SStream_concat(O, ", #-0x%x", -OffImm); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 2101 | else if (AlwaysPrintImm0 || OffImm > 0) { |
| 2102 | if (OffImm > HEX_THRESHOLD) |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2103 | SStream_concat(O, ", #0x%x", OffImm); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 2104 | else |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2105 | SStream_concat(O, ", #%u", OffImm); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 2106 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2107 | |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2108 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2109 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm; |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2110 | SStream_concat0(O, "]"); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2111 | set_mem_access(MI, false); |
| 2112 | } |
| 2113 | |
| 2114 | static void printT2AddrModeImm8s4Operand(MCInst *MI, |
| 2115 | unsigned OpNum, SStream *O, bool AlwaysPrintImm0) |
| 2116 | { |
| 2117 | MCOperand *MO1 = MCInst_getOperand(MI, OpNum); |
| 2118 | MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); |
Nguyen Anh Quynh | aa078a1 | 2014-01-23 22:29:04 +0800 | [diff] [blame] | 2119 | int32_t OffImm; |
| 2120 | bool isSub; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2121 | |
| 2122 | if (!MCOperand_isReg(MO1)) { // For label symbolic references. |
| 2123 | printOperand(MI, OpNum, O); |
| 2124 | return; |
| 2125 | } |
| 2126 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2127 | SStream_concat0(O, "["); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2128 | set_mem_access(MI, true); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2129 | printRegName(MI->csh, O, MCOperand_getReg(MO1)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2130 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2131 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2132 | |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 2133 | OffImm = (int32_t)MCOperand_getImm(MO2); |
| 2134 | isSub = OffImm < 0; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2135 | |
| 2136 | //assert(((OffImm & 0x3) == 0) && "Not a valid immediate!"); |
| 2137 | |
| 2138 | // Don't print +0. |
| 2139 | if (OffImm == INT32_MIN) |
| 2140 | OffImm = 0; |
| 2141 | if (isSub) { |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2142 | SStream_concat(O, ", #-0x%x", -OffImm); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2143 | } else if (AlwaysPrintImm0 || OffImm > 0) { |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 2144 | if (OffImm > HEX_THRESHOLD) |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2145 | SStream_concat(O, ", #0x%x", OffImm); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 2146 | else |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2147 | SStream_concat(O, ", #%u", OffImm); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2148 | } |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2149 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2150 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2151 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2152 | SStream_concat0(O, "]"); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2153 | set_mem_access(MI, false); |
| 2154 | } |
| 2155 | |
| 2156 | static void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, SStream *O) |
| 2157 | { |
| 2158 | MCOperand *MO1 = MCInst_getOperand(MI, OpNum); |
| 2159 | MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); |
Nguyen Anh Quynh | bb0744d | 2014-05-12 13:41:49 +0800 | [diff] [blame] | 2160 | unsigned tmp; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2161 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2162 | SStream_concat0(O, "["); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2163 | set_mem_access(MI, true); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2164 | printRegName(MI->csh, O, MCOperand_getReg(MO1)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2165 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2166 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2167 | if (MCOperand_getImm(MO2)) { |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2168 | SStream_concat0(O, ", "); |
Axel 0vercl0k Souchet | 779d4c7 | 2014-05-08 23:44:49 +0100 | [diff] [blame] | 2169 | tmp = (unsigned int)MCOperand_getImm(MO2) * 4; |
Nguyen Anh Quynh | 256090a | 2016-03-14 13:52:23 +0800 | [diff] [blame] | 2170 | printUInt32Bang(O, tmp); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2171 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2172 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2173 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2174 | SStream_concat0(O, "]"); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2175 | set_mem_access(MI, false); |
| 2176 | } |
| 2177 | |
| 2178 | static void printT2AddrModeImm8OffsetOperand(MCInst *MI, |
| 2179 | unsigned OpNum, SStream *O) |
| 2180 | { |
| 2181 | MCOperand *MO1 = MCInst_getOperand(MI, OpNum); |
| 2182 | int32_t OffImm = (int32_t)MCOperand_getImm(MO1); |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2183 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2184 | if (OffImm == INT32_MIN) { |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2185 | SStream_concat0(O, "#-0"); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2186 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2187 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; |
| 2188 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0; |
| 2189 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2190 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2191 | } else { |
Nguyen Anh Quynh | 256090a | 2016-03-14 13:52:23 +0800 | [diff] [blame] | 2192 | printInt32Bang(O, OffImm); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2193 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2194 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; |
| 2195 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm; |
| 2196 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2197 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2198 | } |
| 2199 | } |
| 2200 | |
| 2201 | static void printT2AddrModeImm8s4OffsetOperand(MCInst *MI, |
| 2202 | unsigned OpNum, SStream *O) |
| 2203 | { |
| 2204 | MCOperand *MO1 = MCInst_getOperand(MI, OpNum); |
| 2205 | int32_t OffImm = (int32_t)MCOperand_getImm(MO1); |
| 2206 | |
| 2207 | //assert(((OffImm & 0x3) == 0) && "Not a valid immediate!"); |
| 2208 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2209 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2210 | if (OffImm == INT32_MIN) { |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2211 | SStream_concat0(O, "#-0"); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2212 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2213 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; |
| 2214 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0; |
| 2215 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2216 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2217 | } else { |
Nguyen Anh Quynh | 256090a | 2016-03-14 13:52:23 +0800 | [diff] [blame] | 2218 | printInt32Bang(O, OffImm); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2219 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2220 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; |
| 2221 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm; |
| 2222 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2223 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2224 | } |
| 2225 | } |
| 2226 | |
| 2227 | static void printT2AddrModeSoRegOperand(MCInst *MI, |
| 2228 | unsigned OpNum, SStream *O) |
| 2229 | { |
| 2230 | MCOperand *MO1 = MCInst_getOperand(MI, OpNum); |
| 2231 | MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); |
| 2232 | MCOperand *MO3 = MCInst_getOperand(MI, OpNum+2); |
Nguyen Anh Quynh | bb0744d | 2014-05-12 13:41:49 +0800 | [diff] [blame] | 2233 | unsigned ShAmt; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2234 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2235 | SStream_concat0(O, "["); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2236 | set_mem_access(MI, true); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2237 | printRegName(MI->csh, O, MCOperand_getReg(MO1)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2238 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2239 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2240 | |
| 2241 | //assert(MCOperand_getReg(MO2.getReg() && "Invalid so_reg load / store address!"); |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2242 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2243 | printRegName(MI->csh, O, MCOperand_getReg(MO2)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2244 | if (MI->csh->detail) |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2245 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2246 | |
Axel 0vercl0k Souchet | 779d4c7 | 2014-05-08 23:44:49 +0100 | [diff] [blame] | 2247 | ShAmt = (unsigned int)MCOperand_getImm(MO3); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2248 | if (ShAmt) { |
| 2249 | //assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!"); |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2250 | SStream_concat0(O, ", lsl "); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2251 | SStream_concat(O, "#%d", ShAmt); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2252 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 706b808 | 2015-01-12 15:27:29 +0800 | [diff] [blame] | 2253 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.lshift = ShAmt; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2254 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2255 | } |
| 2256 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2257 | SStream_concat0(O, "]"); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2258 | set_mem_access(MI, false); |
| 2259 | } |
| 2260 | |
| 2261 | static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O) |
| 2262 | { |
| 2263 | MCOperand *MO = MCInst_getOperand(MI, OpNum); |
Nguyen Anh Quynh | 2ac5d79 | 2014-11-10 21:46:34 +0800 | [diff] [blame] | 2264 | SStream_concat(O, "#%e", getFPImmFloat((unsigned int)MCOperand_getImm(MO))); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2265 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2266 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_FP; |
| 2267 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].fp = getFPImmFloat((unsigned int)MCOperand_getImm(MO)); |
| 2268 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2269 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2270 | } |
| 2271 | |
| 2272 | static void printNEONModImmOperand(MCInst *MI, unsigned OpNum, SStream *O) |
| 2273 | { |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 2274 | unsigned EncodedImm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2275 | unsigned EltBits; |
| 2276 | uint64_t Val = ARM_AM_decodeNEONModImm(EncodedImm, &EltBits); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 2277 | if (Val > HEX_THRESHOLD) |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2278 | SStream_concat(O, "#0x%"PRIx64, Val); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 2279 | else |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2280 | SStream_concat(O, "#%"PRIu64, Val); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2281 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2282 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; |
| 2283 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = (unsigned int)Val; |
| 2284 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2285 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2286 | } |
| 2287 | |
| 2288 | static void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O) |
| 2289 | { |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 2290 | unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 2291 | if (Imm + 1 > HEX_THRESHOLD) |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2292 | SStream_concat(O, "#0x%x", Imm + 1); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 2293 | else |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2294 | SStream_concat(O, "#%u", Imm + 1); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2295 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2296 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; |
| 2297 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm + 1; |
| 2298 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2299 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2300 | } |
| 2301 | |
| 2302 | static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O) |
| 2303 | { |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 2304 | unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2305 | if (Imm == 0) |
| 2306 | return; |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2307 | SStream_concat0(O, ", ror #"); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2308 | switch (Imm) { |
| 2309 | default: //assert (0 && "illegal ror immediate!"); |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2310 | case 1: SStream_concat0(O, "8"); break; |
| 2311 | case 2: SStream_concat0(O, "16"); break; |
| 2312 | case 3: SStream_concat0(O, "24"); break; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2313 | } |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2314 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2315 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ROR; |
| 2316 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm * 8; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2317 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2318 | } |
| 2319 | |
Nguyen Anh Quynh | d1fc2bd | 2015-03-03 16:26:32 +0800 | [diff] [blame] | 2320 | static void printModImmOperand(MCInst *MI, unsigned OpNum, SStream *O) |
| 2321 | { |
| 2322 | MCOperand *Op = MCInst_getOperand(MI, OpNum); |
| 2323 | unsigned Bits = MCOperand_getImm(Op) & 0xFF; |
| 2324 | unsigned Rot = (MCOperand_getImm(Op) & 0xF00) >> 7; |
| 2325 | int32_t Rotated; |
| 2326 | |
| 2327 | bool PrintUnsigned = false; |
| 2328 | switch (MCInst_getOpcode(MI)) { |
| 2329 | case ARM_MOVi: |
| 2330 | // Movs to PC should be treated unsigned |
| 2331 | PrintUnsigned = (MCOperand_getReg(MCInst_getOperand(MI, OpNum - 1)) == ARM_PC); |
| 2332 | break; |
| 2333 | case ARM_MSRi: |
| 2334 | // Movs to special registers should be treated unsigned |
| 2335 | PrintUnsigned = true; |
| 2336 | break; |
| 2337 | } |
| 2338 | |
| 2339 | Rotated = rotr32(Bits, Rot); |
| 2340 | if (getSOImmVal(Rotated) == MCOperand_getImm(Op)) { |
| 2341 | // #rot has the least possible value |
Nguyen Anh Quynh | e0329dd | 2015-03-08 00:29:20 +0800 | [diff] [blame] | 2342 | if (PrintUnsigned) { |
| 2343 | if (Rotated > HEX_THRESHOLD || Rotated < -HEX_THRESHOLD) |
| 2344 | SStream_concat(O, "#0x%x", Rotated); |
| 2345 | else |
| 2346 | SStream_concat(O, "#%u", Rotated); |
| 2347 | } else if (Rotated >= 0) { |
Nguyen Anh Quynh | b8b8348 | 2015-03-07 00:26:24 +0800 | [diff] [blame] | 2348 | if (Rotated > HEX_THRESHOLD) |
| 2349 | SStream_concat(O, "#0x%x", Rotated); |
| 2350 | else |
| 2351 | SStream_concat(O, "#%u", Rotated); |
| 2352 | } else { |
| 2353 | SStream_concat(O, "#0x%x", Rotated); |
| 2354 | } |
Nguyen Anh Quynh | 7e25609 | 2015-03-03 18:28:10 +0800 | [diff] [blame] | 2355 | if (MI->csh->detail) { |
| 2356 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; |
| 2357 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Rotated; |
| 2358 | MI->flat_insn->detail->arm.op_count++; |
| 2359 | } |
Nguyen Anh Quynh | d1fc2bd | 2015-03-03 16:26:32 +0800 | [diff] [blame] | 2360 | return; |
| 2361 | } |
| 2362 | |
| 2363 | // Explicit #bits, #rot implied |
Nguyen Anh Quynh | 7e25609 | 2015-03-03 18:28:10 +0800 | [diff] [blame] | 2364 | SStream_concat(O, "#%u, #%u", Bits, Rot); |
| 2365 | if (MI->csh->detail) { |
| 2366 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; |
| 2367 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Bits; |
| 2368 | MI->flat_insn->detail->arm.op_count++; |
| 2369 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; |
| 2370 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Rot; |
| 2371 | MI->flat_insn->detail->arm.op_count++; |
| 2372 | } |
Nguyen Anh Quynh | d1fc2bd | 2015-03-03 16:26:32 +0800 | [diff] [blame] | 2373 | } |
| 2374 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2375 | static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O) |
| 2376 | { |
Nguyen Anh Quynh | bb0744d | 2014-05-12 13:41:49 +0800 | [diff] [blame] | 2377 | unsigned tmp; |
| 2378 | |
Axel 0vercl0k Souchet | 779d4c7 | 2014-05-08 23:44:49 +0100 | [diff] [blame] | 2379 | tmp = 16 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | 256090a | 2016-03-14 13:52:23 +0800 | [diff] [blame] | 2380 | printUInt32Bang(O, tmp); |
| 2381 | |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2382 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2383 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; |
| 2384 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; |
| 2385 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2386 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2387 | } |
| 2388 | |
| 2389 | static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O) |
| 2390 | { |
Nguyen Anh Quynh | bb0744d | 2014-05-12 13:41:49 +0800 | [diff] [blame] | 2391 | unsigned tmp; |
| 2392 | |
Axel 0vercl0k Souchet | 779d4c7 | 2014-05-08 23:44:49 +0100 | [diff] [blame] | 2393 | tmp = 32 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | 256090a | 2016-03-14 13:52:23 +0800 | [diff] [blame] | 2394 | printUInt32Bang(O, tmp); |
| 2395 | |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2396 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2397 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; |
| 2398 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; |
| 2399 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2400 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2401 | } |
| 2402 | |
| 2403 | static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O) |
| 2404 | { |
Alex Ionescu | 46018db | 2014-01-22 09:45:00 -0800 | [diff] [blame] | 2405 | unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 2406 | if (tmp > HEX_THRESHOLD) |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2407 | SStream_concat(O, "[0x%x]", tmp); |
Nguyen Anh Quynh | 462f291 | 2013-12-11 17:35:27 +0800 | [diff] [blame] | 2408 | else |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2409 | SStream_concat(O, "[%u]", tmp); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2410 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 2411 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].vector_index = tmp; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2412 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2413 | } |
| 2414 | |
| 2415 | static void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O) |
| 2416 | { |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2417 | SStream_concat0(O, "{"); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2418 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2419 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2420 | #ifndef CAPSTONE_DIET |
| 2421 | uint8_t access; |
| 2422 | |
| 2423 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
| 2424 | #endif |
| 2425 | |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2426 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2427 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2428 | #ifndef CAPSTONE_DIET |
| 2429 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2430 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2431 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2432 | |
| 2433 | #ifndef CAPSTONE_DIET |
| 2434 | MI->ac_idx++; |
| 2435 | #endif |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2436 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2437 | SStream_concat0(O, "}"); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2438 | } |
| 2439 | |
| 2440 | static void printVectorListTwo(MCInst *MI, unsigned OpNum, |
| 2441 | SStream *O, MCRegisterInfo *MRI) |
| 2442 | { |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2443 | #ifndef CAPSTONE_DIET |
| 2444 | uint8_t access; |
| 2445 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2446 | unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); |
| 2447 | unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0); |
| 2448 | unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_1); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2449 | |
| 2450 | #ifndef CAPSTONE_DIET |
| 2451 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
| 2452 | #endif |
| 2453 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2454 | SStream_concat0(O, "{"); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2455 | printRegName(MI->csh, O, Reg0); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2456 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2457 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2458 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2459 | #ifndef CAPSTONE_DIET |
| 2460 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2461 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2462 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2463 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2464 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2465 | printRegName(MI->csh, O, Reg1); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2466 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2467 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2468 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2469 | #ifndef CAPSTONE_DIET |
| 2470 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2471 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2472 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2473 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2474 | SStream_concat0(O, "}"); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2475 | |
| 2476 | #ifndef CAPSTONE_DIET |
| 2477 | MI->ac_idx++; |
| 2478 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2479 | } |
| 2480 | |
| 2481 | static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, |
| 2482 | SStream *O, MCRegisterInfo *MRI) |
| 2483 | { |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2484 | #ifndef CAPSTONE_DIET |
| 2485 | uint8_t access; |
| 2486 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2487 | unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); |
| 2488 | unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0); |
| 2489 | unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_2); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2490 | |
| 2491 | #ifndef CAPSTONE_DIET |
| 2492 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
| 2493 | #endif |
| 2494 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2495 | SStream_concat0(O, "{"); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2496 | printRegName(MI->csh, O, Reg0); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2497 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2498 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2499 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2500 | #ifndef CAPSTONE_DIET |
| 2501 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2502 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2503 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2504 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2505 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2506 | printRegName(MI->csh, O, Reg1); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2507 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2508 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2509 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2510 | #ifndef CAPSTONE_DIET |
| 2511 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2512 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2513 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2514 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2515 | SStream_concat0(O, "}"); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2516 | |
| 2517 | #ifndef CAPSTONE_DIET |
| 2518 | MI->ac_idx++; |
| 2519 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2520 | } |
| 2521 | |
| 2522 | static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O) |
| 2523 | { |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2524 | #ifndef CAPSTONE_DIET |
| 2525 | uint8_t access; |
| 2526 | |
| 2527 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
| 2528 | #endif |
| 2529 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2530 | // Normally, it's not safe to use register enum values directly with |
| 2531 | // addition to get the next register, but for VFP registers, the |
| 2532 | // sort order is guaranteed because they're all of the form D<n>. |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2533 | SStream_concat0(O, "{"); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2534 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2535 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2536 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2537 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2538 | #ifndef CAPSTONE_DIET |
| 2539 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2540 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2541 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2542 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2543 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2544 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2545 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2546 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2547 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2548 | #ifndef CAPSTONE_DIET |
| 2549 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2550 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2551 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2552 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2553 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2554 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2555 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2556 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2557 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2558 | #ifndef CAPSTONE_DIET |
| 2559 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2560 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2561 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2562 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2563 | SStream_concat0(O, "}"); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2564 | |
| 2565 | #ifndef CAPSTONE_DIET |
| 2566 | MI->ac_idx++; |
| 2567 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2568 | } |
| 2569 | |
| 2570 | static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O) |
| 2571 | { |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2572 | #ifndef CAPSTONE_DIET |
| 2573 | uint8_t access; |
| 2574 | |
| 2575 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
| 2576 | #endif |
| 2577 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2578 | // Normally, it's not safe to use register enum values directly with |
| 2579 | // addition to get the next register, but for VFP registers, the |
| 2580 | // sort order is guaranteed because they're all of the form D<n>. |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2581 | SStream_concat0(O, "{"); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2582 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2583 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2584 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2585 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2586 | #ifndef CAPSTONE_DIET |
| 2587 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2588 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2589 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2590 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2591 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2592 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2593 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2594 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2595 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2596 | #ifndef CAPSTONE_DIET |
| 2597 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2598 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2599 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2600 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2601 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2602 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2603 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2604 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2605 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2606 | #ifndef CAPSTONE_DIET |
| 2607 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2608 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2609 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2610 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2611 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2612 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2613 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2614 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2615 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2616 | #ifndef CAPSTONE_DIET |
| 2617 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2618 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2619 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2620 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2621 | SStream_concat0(O, "}"); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2622 | |
| 2623 | #ifndef CAPSTONE_DIET |
| 2624 | MI->ac_idx++; |
| 2625 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2626 | } |
| 2627 | |
| 2628 | static void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O) |
| 2629 | { |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2630 | #ifndef CAPSTONE_DIET |
| 2631 | uint8_t access; |
| 2632 | |
| 2633 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
| 2634 | #endif |
| 2635 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2636 | SStream_concat0(O, "{"); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2637 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2638 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2639 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2640 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2641 | #ifndef CAPSTONE_DIET |
| 2642 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2643 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2644 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2645 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2646 | SStream_concat0(O, "[]}"); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2647 | |
| 2648 | #ifndef CAPSTONE_DIET |
| 2649 | MI->ac_idx++; |
| 2650 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2651 | } |
| 2652 | |
| 2653 | static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, |
| 2654 | SStream *O, MCRegisterInfo *MRI) |
| 2655 | { |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2656 | #ifndef CAPSTONE_DIET |
| 2657 | uint8_t access; |
| 2658 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2659 | unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); |
| 2660 | unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0); |
| 2661 | unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_1); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2662 | |
| 2663 | #ifndef CAPSTONE_DIET |
| 2664 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
| 2665 | #endif |
| 2666 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2667 | SStream_concat0(O, "{"); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2668 | printRegName(MI->csh, O, Reg0); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2669 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2670 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2671 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2672 | #ifndef CAPSTONE_DIET |
| 2673 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2674 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2675 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2676 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2677 | SStream_concat0(O, "[], "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2678 | printRegName(MI->csh, O, Reg1); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2679 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2680 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2681 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2682 | #ifndef CAPSTONE_DIET |
| 2683 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2684 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2685 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2686 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2687 | SStream_concat0(O, "[]}"); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2688 | |
| 2689 | #ifndef CAPSTONE_DIET |
| 2690 | MI->ac_idx++; |
| 2691 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2692 | } |
| 2693 | |
| 2694 | static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O) |
| 2695 | { |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2696 | #ifndef CAPSTONE_DIET |
| 2697 | uint8_t access; |
| 2698 | |
| 2699 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
| 2700 | #endif |
| 2701 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2702 | // Normally, it's not safe to use register enum values directly with |
| 2703 | // addition to get the next register, but for VFP registers, the |
| 2704 | // sort order is guaranteed because they're all of the form D<n>. |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2705 | SStream_concat0(O, "{"); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2706 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2707 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2708 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2709 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2710 | #ifndef CAPSTONE_DIET |
| 2711 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2712 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2713 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2714 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2715 | SStream_concat0(O, "[], "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2716 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2717 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2718 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2719 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2720 | #ifndef CAPSTONE_DIET |
| 2721 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2722 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2723 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2724 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2725 | SStream_concat0(O, "[], "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2726 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2727 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2728 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2729 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2730 | #ifndef CAPSTONE_DIET |
| 2731 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2732 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2733 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2734 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2735 | SStream_concat0(O, "[]}"); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2736 | |
| 2737 | #ifndef CAPSTONE_DIET |
| 2738 | MI->ac_idx++; |
| 2739 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2740 | } |
| 2741 | |
| 2742 | static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O) |
| 2743 | { |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2744 | #ifndef CAPSTONE_DIET |
| 2745 | uint8_t access; |
| 2746 | |
| 2747 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
| 2748 | #endif |
| 2749 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2750 | // Normally, it's not safe to use register enum values directly with |
| 2751 | // addition to get the next register, but for VFP registers, the |
| 2752 | // sort order is guaranteed because they're all of the form D<n>. |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2753 | SStream_concat0(O, "{"); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2754 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2755 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2756 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2757 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2758 | #ifndef CAPSTONE_DIET |
| 2759 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2760 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2761 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2762 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2763 | SStream_concat0(O, "[], "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2764 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2765 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2766 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2767 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2768 | #ifndef CAPSTONE_DIET |
| 2769 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2770 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2771 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2772 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2773 | SStream_concat0(O, "[], "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2774 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2775 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2776 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2777 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2778 | #ifndef CAPSTONE_DIET |
| 2779 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2780 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2781 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2782 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2783 | SStream_concat0(O, "[], "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2784 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2785 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2786 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2787 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2788 | #ifndef CAPSTONE_DIET |
| 2789 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2790 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2791 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2792 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2793 | SStream_concat0(O, "[]}"); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2794 | |
| 2795 | #ifndef CAPSTONE_DIET |
| 2796 | MI->ac_idx++; |
| 2797 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2798 | } |
| 2799 | |
| 2800 | static void printVectorListTwoSpacedAllLanes(MCInst *MI, |
| 2801 | unsigned OpNum, SStream *O, MCRegisterInfo *MRI) |
| 2802 | { |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2803 | #ifndef CAPSTONE_DIET |
| 2804 | uint8_t access; |
| 2805 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2806 | unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); |
| 2807 | unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0); |
| 2808 | unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_2); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2809 | |
| 2810 | #ifndef CAPSTONE_DIET |
| 2811 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
| 2812 | #endif |
| 2813 | |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2814 | SStream_concat0(O, "{"); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2815 | printRegName(MI->csh, O, Reg0); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2816 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2817 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2818 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2819 | #ifndef CAPSTONE_DIET |
| 2820 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2821 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2822 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2823 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2824 | SStream_concat0(O, "[], "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2825 | printRegName(MI->csh, O, Reg1); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2826 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2827 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2828 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2829 | #ifndef CAPSTONE_DIET |
| 2830 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2831 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2832 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2833 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2834 | SStream_concat0(O, "[]}"); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2835 | |
| 2836 | #ifndef CAPSTONE_DIET |
| 2837 | MI->ac_idx++; |
| 2838 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2839 | } |
| 2840 | |
| 2841 | static void printVectorListThreeSpacedAllLanes(MCInst *MI, |
| 2842 | unsigned OpNum, SStream *O) |
| 2843 | { |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2844 | #ifndef CAPSTONE_DIET |
| 2845 | uint8_t access; |
| 2846 | |
| 2847 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
| 2848 | #endif |
| 2849 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2850 | // Normally, it's not safe to use register enum values directly with |
| 2851 | // addition to get the next register, but for VFP registers, the |
| 2852 | // sort order is guaranteed because they're all of the form D<n>. |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2853 | SStream_concat0(O, "{"); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2854 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2855 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2856 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2857 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2858 | #ifndef CAPSTONE_DIET |
| 2859 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2860 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2861 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2862 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2863 | SStream_concat0(O, "[], "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2864 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2865 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2866 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2867 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2868 | #ifndef CAPSTONE_DIET |
| 2869 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2870 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2871 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2872 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2873 | SStream_concat0(O, "[], "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2874 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2875 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2876 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2877 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2878 | #ifndef CAPSTONE_DIET |
| 2879 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2880 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2881 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2882 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2883 | SStream_concat0(O, "[]}"); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2884 | |
| 2885 | #ifndef CAPSTONE_DIET |
| 2886 | MI->ac_idx++; |
| 2887 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2888 | } |
| 2889 | |
| 2890 | static void printVectorListFourSpacedAllLanes(MCInst *MI, |
| 2891 | unsigned OpNum, SStream *O) |
| 2892 | { |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2893 | #ifndef CAPSTONE_DIET |
| 2894 | uint8_t access; |
| 2895 | |
| 2896 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
| 2897 | #endif |
| 2898 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2899 | // Normally, it's not safe to use register enum values directly with |
| 2900 | // addition to get the next register, but for VFP registers, the |
| 2901 | // sort order is guaranteed because they're all of the form D<n>. |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2902 | SStream_concat0(O, "{"); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2903 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2904 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2905 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2906 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2907 | #ifndef CAPSTONE_DIET |
| 2908 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2909 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2910 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2911 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2912 | SStream_concat0(O, "[], "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2913 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2914 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2915 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2916 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2917 | #ifndef CAPSTONE_DIET |
| 2918 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2919 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2920 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2921 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2922 | SStream_concat0(O, "[], "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2923 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2924 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2925 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2926 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2927 | #ifndef CAPSTONE_DIET |
| 2928 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2929 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2930 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2931 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2932 | SStream_concat0(O, "[], "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2933 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2934 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2935 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2936 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2937 | #ifndef CAPSTONE_DIET |
| 2938 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2939 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2940 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2941 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2942 | SStream_concat0(O, "[]}"); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2943 | |
| 2944 | #ifndef CAPSTONE_DIET |
| 2945 | MI->ac_idx++; |
| 2946 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2947 | } |
| 2948 | |
| 2949 | static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O) |
| 2950 | { |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2951 | #ifndef CAPSTONE_DIET |
| 2952 | uint8_t access; |
| 2953 | |
| 2954 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
| 2955 | #endif |
| 2956 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2957 | // Normally, it's not safe to use register enum values directly with |
| 2958 | // addition to get the next register, but for VFP registers, the |
| 2959 | // sort order is guaranteed because they're all of the form D<n>. |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2960 | SStream_concat0(O, "{"); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2961 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2962 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2963 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2964 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2965 | #ifndef CAPSTONE_DIET |
| 2966 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2967 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2968 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2969 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2970 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2971 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2972 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2973 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2974 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2975 | #ifndef CAPSTONE_DIET |
| 2976 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2977 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2978 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2979 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2980 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 2981 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 2982 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2983 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 2984 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2985 | #ifndef CAPSTONE_DIET |
| 2986 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 2987 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 2988 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 2989 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 2990 | SStream_concat0(O, "}"); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2991 | |
| 2992 | #ifndef CAPSTONE_DIET |
| 2993 | MI->ac_idx++; |
| 2994 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 2995 | } |
| 2996 | |
| 2997 | static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O) |
| 2998 | { |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 2999 | #ifndef CAPSTONE_DIET |
| 3000 | uint8_t access; |
| 3001 | |
| 3002 | access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); |
| 3003 | #endif |
| 3004 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 3005 | // Normally, it's not safe to use register enum values directly with |
| 3006 | // addition to get the next register, but for VFP registers, the |
| 3007 | // sort order is guaranteed because they're all of the form D<n>. |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 3008 | SStream_concat0(O, "{"); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 3009 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 3010 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 3011 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 3012 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 3013 | #ifndef CAPSTONE_DIET |
| 3014 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 3015 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 3016 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 3017 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 3018 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 3019 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 3020 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 3021 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 3022 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 3023 | #ifndef CAPSTONE_DIET |
| 3024 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 3025 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 3026 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 3027 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 3028 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 3029 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 3030 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 3031 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 3032 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 3033 | #ifndef CAPSTONE_DIET |
| 3034 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 3035 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 3036 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 3037 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 3038 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 2ff665a | 2014-03-11 00:18:50 +0800 | [diff] [blame] | 3039 | printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 3040 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 3041 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 3042 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6; |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 3043 | #ifndef CAPSTONE_DIET |
| 3044 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; |
| 3045 | #endif |
Nguyen Anh Quynh | 29fd0f6 | 2014-06-09 08:00:18 +0700 | [diff] [blame] | 3046 | MI->flat_insn->detail->arm.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 3047 | } |
Nguyen Anh Quynh | dd9225b | 2014-06-10 00:37:53 +0700 | [diff] [blame] | 3048 | SStream_concat0(O, "}"); |
Nguyen Anh Quynh | 29f777b | 2015-04-07 11:59:26 +0800 | [diff] [blame] | 3049 | |
| 3050 | #ifndef CAPSTONE_DIET |
| 3051 | MI->ac_idx++; |
| 3052 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 3053 | } |
Nguyen Anh Quynh | 8598a21 | 2014-05-14 11:26:41 +0800 | [diff] [blame] | 3054 | |
Nguyen Anh Quynh | 04d9f8e | 2014-09-01 23:27:24 +0800 | [diff] [blame] | 3055 | void ARM_addVectorDataType(MCInst *MI, arm_vectordata_type vd) |
| 3056 | { |
| 3057 | if (MI->csh->detail) { |
| 3058 | MI->flat_insn->detail->arm.vector_data = vd; |
| 3059 | } |
| 3060 | } |
| 3061 | |
| 3062 | void ARM_addVectorDataSize(MCInst *MI, int size) |
| 3063 | { |
| 3064 | if (MI->csh->detail) { |
| 3065 | MI->flat_insn->detail->arm.vector_size = size; |
| 3066 | } |
| 3067 | } |
| 3068 | |
| 3069 | void ARM_addReg(MCInst *MI, int reg) |
| 3070 | { |
| 3071 | if (MI->csh->detail) { |
| 3072 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; |
| 3073 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = reg; |
| 3074 | MI->flat_insn->detail->arm.op_count++; |
| 3075 | } |
| 3076 | } |
| 3077 | |
| 3078 | void ARM_addUserMode(MCInst *MI) |
| 3079 | { |
| 3080 | if (MI->csh->detail) { |
| 3081 | MI->flat_insn->detail->arm.usermode = true; |
| 3082 | } |
| 3083 | } |
| 3084 | |
| 3085 | void ARM_addSysReg(MCInst *MI, arm_sysreg reg) |
| 3086 | { |
| 3087 | if (MI->csh->detail) { |
| 3088 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SYSREG; |
| 3089 | MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = reg; |
| 3090 | MI->flat_insn->detail->arm.op_count++; |
| 3091 | } |
| 3092 | } |
| 3093 | |
Nguyen Anh Quynh | 8598a21 | 2014-05-14 11:26:41 +0800 | [diff] [blame] | 3094 | #endif |