Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 1 | //===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file includes code for rendering MCInst instances as AT&T-style |
| 11 | // assembly. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
Nguyen Anh Quynh | 8598a21 | 2014-05-14 11:26:41 +0800 | [diff] [blame] | 15 | /* Capstone Disassembly Engine */ |
| 16 | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ |
| 17 | |
Nguyen Anh Quynh | f785026 | 2014-05-14 22:03:06 +0800 | [diff] [blame] | 18 | // this code is only relevant when DIET mode is disable |
baguette | 86e8450 | 2014-08-17 20:59:05 +0200 | [diff] [blame] | 19 | #if defined(CAPSTONE_HAS_X86) && !defined(CAPSTONE_DIET) && !defined(CAPSTONE_X86_ATT_DISABLE) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 20 | |
reverser | bcf09f4 | 2015-04-09 18:28:19 +0100 | [diff] [blame] | 21 | #if !defined(CAPSTONE_HAS_OSXKERNEL) |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 22 | #include <ctype.h> |
reverser | bcf09f4 | 2015-04-09 18:28:19 +0100 | [diff] [blame] | 23 | #endif |
Cr4sh | 9d60607 | 2015-03-29 18:29:06 +0800 | [diff] [blame] | 24 | #include "../../myinttypes.h" |
reverser | bcf09f4 | 2015-04-09 18:28:19 +0100 | [diff] [blame] | 25 | #if defined(CAPSTONE_HAS_OSXKERNEL) |
| 26 | #include <libkern/libkern.h> |
| 27 | #else |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 28 | #include <stdio.h> |
| 29 | #include <stdlib.h> |
reverser | bcf09f4 | 2015-04-09 18:28:19 +0100 | [diff] [blame] | 30 | #endif |
| 31 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 32 | #include <string.h> |
| 33 | |
| 34 | #include "../../utils.h" |
| 35 | #include "../../MCInst.h" |
| 36 | #include "../../SStream.h" |
| 37 | #include "../../MCRegisterInfo.h" |
Nguyen Anh Quynh | f328f30 | 2014-01-20 09:47:21 +0800 | [diff] [blame] | 38 | #include "X86Mapping.h" |
Nguyen Anh Quynh | 0b69038 | 2014-08-13 13:01:50 +0800 | [diff] [blame] | 39 | #include "X86BaseInfo.h" |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 40 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 41 | |
Nguyen Anh Quynh | e93179b | 2014-04-25 11:18:40 +0800 | [diff] [blame] | 42 | #define GET_INSTRINFO_ENUM |
| 43 | #ifdef CAPSTONE_X86_REDUCE |
| 44 | #include "X86GenInstrInfo_reduce.inc" |
| 45 | #else |
| 46 | #include "X86GenInstrInfo.inc" |
| 47 | #endif |
| 48 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 49 | static void printMemReference(MCInst *MI, unsigned Op, SStream *O); |
Nguyen Anh Quynh | 13f40d2 | 2014-02-07 22:06:33 +0800 | [diff] [blame] | 50 | static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 51 | |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 52 | |
| 53 | static void set_mem_access(MCInst *MI, bool status) |
| 54 | { |
| 55 | if (MI->csh->detail != CS_OPT_ON) |
| 56 | return; |
| 57 | |
| 58 | MI->csh->doing_mem = status; |
Nguyen Anh Quynh | 14ba46b | 2014-06-24 14:32:01 +0800 | [diff] [blame] | 59 | if (!status) |
| 60 | // done, create the next operand slot |
| 61 | MI->flat_insn->detail->x86.op_count++; |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 62 | } |
| 63 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 64 | static void printopaquemem(MCInst *MI, unsigned OpNo, SStream *O) |
| 65 | { |
Nguyen Anh Quynh | e10b53f | 2015-02-10 00:21:00 +0800 | [diff] [blame] | 66 | switch(MI->csh->mode) { |
| 67 | case CS_MODE_16: |
| 68 | MI->x86opsize = 2; |
| 69 | break; |
| 70 | case CS_MODE_32: |
| 71 | MI->x86opsize = 4; |
| 72 | break; |
| 73 | case CS_MODE_64: |
| 74 | MI->x86opsize = 8; |
| 75 | break; |
| 76 | default: // never reach |
| 77 | break; |
| 78 | } |
| 79 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 80 | printMemReference(MI, OpNo, O); |
| 81 | } |
| 82 | |
| 83 | static void printi8mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 84 | { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 85 | MI->x86opsize = 1; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 86 | printMemReference(MI, OpNo, O); |
| 87 | } |
| 88 | |
| 89 | static void printi16mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 90 | { |
Nguyen Anh Quynh | d319c11 | 2014-12-26 16:49:10 +0800 | [diff] [blame] | 91 | MI->x86opsize = 2; |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 92 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 93 | printMemReference(MI, OpNo, O); |
| 94 | } |
| 95 | |
| 96 | static void printi32mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 97 | { |
Nguyen Anh Quynh | d319c11 | 2014-12-26 16:49:10 +0800 | [diff] [blame] | 98 | MI->x86opsize = 4; |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 99 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 100 | printMemReference(MI, OpNo, O); |
| 101 | } |
| 102 | |
| 103 | static void printi64mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 104 | { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 105 | MI->x86opsize = 8; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 106 | printMemReference(MI, OpNo, O); |
| 107 | } |
| 108 | |
| 109 | static void printi128mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 110 | { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 111 | MI->x86opsize = 16; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 112 | printMemReference(MI, OpNo, O); |
| 113 | } |
| 114 | |
Nguyen Anh Quynh | 59b5489 | 2014-03-27 10:54:44 +0800 | [diff] [blame] | 115 | #ifndef CAPSTONE_X86_REDUCE |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 116 | static void printi256mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 117 | { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 118 | MI->x86opsize = 32; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 119 | printMemReference(MI, OpNo, O); |
| 120 | } |
| 121 | |
| 122 | static void printi512mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 123 | { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 124 | MI->x86opsize = 64; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 125 | printMemReference(MI, OpNo, O); |
| 126 | } |
| 127 | |
| 128 | static void printf32mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 129 | { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 130 | MI->x86opsize = 4; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 131 | printMemReference(MI, OpNo, O); |
| 132 | } |
| 133 | |
| 134 | static void printf64mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 135 | { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 136 | MI->x86opsize = 8; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 137 | printMemReference(MI, OpNo, O); |
| 138 | } |
| 139 | |
| 140 | static void printf80mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 141 | { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 142 | MI->x86opsize = 10; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 143 | printMemReference(MI, OpNo, O); |
| 144 | } |
| 145 | |
| 146 | static void printf128mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 147 | { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 148 | MI->x86opsize = 16; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 149 | printMemReference(MI, OpNo, O); |
| 150 | } |
| 151 | |
| 152 | static void printf256mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 153 | { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 154 | MI->x86opsize = 32; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 155 | printMemReference(MI, OpNo, O); |
| 156 | } |
| 157 | |
| 158 | static void printf512mem(MCInst *MI, unsigned OpNo, SStream *O) |
| 159 | { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 160 | MI->x86opsize = 64; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 161 | printMemReference(MI, OpNo, O); |
| 162 | } |
| 163 | |
Nguyen Anh Quynh | 9518148 | 2014-03-25 23:20:41 +0800 | [diff] [blame] | 164 | static void printSSECC(MCInst *MI, unsigned Op, SStream *OS) |
| 165 | { |
Nguyen Anh Quynh | 9f694cc | 2014-12-26 17:54:11 +0800 | [diff] [blame] | 166 | int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 7; |
Nguyen Anh Quynh | 9518148 | 2014-03-25 23:20:41 +0800 | [diff] [blame] | 167 | switch (Imm) { |
| 168 | default: break; // never reach |
Nguyen Anh Quynh | 9f694cc | 2014-12-26 17:54:11 +0800 | [diff] [blame] | 169 | case 0: SStream_concat0(OS, "eq"); op_addSseCC(MI, X86_SSE_CC_EQ); break; |
| 170 | case 1: SStream_concat0(OS, "lt"); op_addSseCC(MI, X86_SSE_CC_LT); break; |
| 171 | case 2: SStream_concat0(OS, "le"); op_addSseCC(MI, X86_SSE_CC_LE); break; |
| 172 | case 3: SStream_concat0(OS, "unord"); op_addSseCC(MI, X86_SSE_CC_UNORD); break; |
| 173 | case 4: SStream_concat0(OS, "neq"); op_addSseCC(MI, X86_SSE_CC_NEQ); break; |
| 174 | case 5: SStream_concat0(OS, "nlt"); op_addSseCC(MI, X86_SSE_CC_NLT); break; |
| 175 | case 6: SStream_concat0(OS, "nle"); op_addSseCC(MI, X86_SSE_CC_NLE); break; |
| 176 | case 7: SStream_concat0(OS, "ord"); op_addSseCC(MI, X86_SSE_CC_ORD); break; |
| 177 | case 8: SStream_concat0(OS, "eq_uq"); op_addSseCC(MI, X86_SSE_CC_EQ_UQ); break; |
| 178 | case 9: SStream_concat0(OS, "nge"); op_addSseCC(MI, X86_SSE_CC_NGE); break; |
| 179 | case 0xa: SStream_concat0(OS, "ngt"); op_addSseCC(MI, X86_SSE_CC_NGT); break; |
| 180 | case 0xb: SStream_concat0(OS, "false"); op_addSseCC(MI, X86_SSE_CC_FALSE); break; |
| 181 | case 0xc: SStream_concat0(OS, "neq_oq"); op_addSseCC(MI, X86_SSE_CC_NEQ_OQ); break; |
| 182 | case 0xd: SStream_concat0(OS, "ge"); op_addSseCC(MI, X86_SSE_CC_GE); break; |
| 183 | case 0xe: SStream_concat0(OS, "gt"); op_addSseCC(MI, X86_SSE_CC_GT); break; |
| 184 | case 0xf: SStream_concat0(OS, "true"); op_addSseCC(MI, X86_SSE_CC_TRUE); break; |
Nguyen Anh Quynh | 9518148 | 2014-03-25 23:20:41 +0800 | [diff] [blame] | 185 | } |
| 186 | } |
| 187 | |
| 188 | static void printAVXCC(MCInst *MI, unsigned Op, SStream *O) |
| 189 | { |
| 190 | int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x1f; |
| 191 | switch (Imm) { |
| 192 | default: break;//printf("Invalid avxcc argument!\n"); break; |
Nguyen Anh Quynh | 9f694cc | 2014-12-26 17:54:11 +0800 | [diff] [blame] | 193 | case 0: SStream_concat0(O, "eq"); op_addAvxCC(MI, X86_AVX_CC_EQ); break; |
| 194 | case 1: SStream_concat0(O, "lt"); op_addAvxCC(MI, X86_AVX_CC_LT); break; |
| 195 | case 2: SStream_concat0(O, "le"); op_addAvxCC(MI, X86_AVX_CC_LE); break; |
| 196 | case 3: SStream_concat0(O, "unord"); op_addAvxCC(MI, X86_AVX_CC_UNORD); break; |
| 197 | case 4: SStream_concat0(O, "neq"); op_addAvxCC(MI, X86_AVX_CC_NEQ); break; |
| 198 | case 5: SStream_concat0(O, "nlt"); op_addAvxCC(MI, X86_AVX_CC_NLT); break; |
| 199 | case 6: SStream_concat0(O, "nle"); op_addAvxCC(MI, X86_AVX_CC_NLE); break; |
| 200 | case 7: SStream_concat0(O, "ord"); op_addAvxCC(MI, X86_AVX_CC_ORD); break; |
| 201 | case 8: SStream_concat0(O, "eq_uq"); op_addAvxCC(MI, X86_AVX_CC_EQ_UQ); break; |
| 202 | case 9: SStream_concat0(O, "nge"); op_addAvxCC(MI, X86_AVX_CC_NGE); break; |
| 203 | case 0xa: SStream_concat0(O, "ngt"); op_addAvxCC(MI, X86_AVX_CC_NGT); break; |
| 204 | case 0xb: SStream_concat0(O, "false"); op_addAvxCC(MI, X86_AVX_CC_FALSE); break; |
| 205 | case 0xc: SStream_concat0(O, "neq_oq"); op_addAvxCC(MI, X86_AVX_CC_NEQ_OQ); break; |
| 206 | case 0xd: SStream_concat0(O, "ge"); op_addAvxCC(MI, X86_AVX_CC_GE); break; |
| 207 | case 0xe: SStream_concat0(O, "gt"); op_addAvxCC(MI, X86_AVX_CC_GT); break; |
| 208 | case 0xf: SStream_concat0(O, "true"); op_addAvxCC(MI, X86_AVX_CC_TRUE); break; |
| 209 | case 0x10: SStream_concat0(O, "eq_os"); op_addAvxCC(MI, X86_AVX_CC_EQ_OS); break; |
| 210 | case 0x11: SStream_concat0(O, "lt_oq"); op_addAvxCC(MI, X86_AVX_CC_LT_OQ); break; |
| 211 | case 0x12: SStream_concat0(O, "le_oq"); op_addAvxCC(MI, X86_AVX_CC_LE_OQ); break; |
| 212 | case 0x13: SStream_concat0(O, "unord_s"); op_addAvxCC(MI, X86_AVX_CC_UNORD_S); break; |
| 213 | case 0x14: SStream_concat0(O, "neq_us"); op_addAvxCC(MI, X86_AVX_CC_NEQ_US); break; |
| 214 | case 0x15: SStream_concat0(O, "nlt_uq"); op_addAvxCC(MI, X86_AVX_CC_NLT_UQ); break; |
| 215 | case 0x16: SStream_concat0(O, "nle_uq"); op_addAvxCC(MI, X86_AVX_CC_NLE_UQ); break; |
| 216 | case 0x17: SStream_concat0(O, "ord_s"); op_addAvxCC(MI, X86_AVX_CC_ORD_S); break; |
| 217 | case 0x18: SStream_concat0(O, "eq_us"); op_addAvxCC(MI, X86_AVX_CC_EQ_US); break; |
| 218 | case 0x19: SStream_concat0(O, "nge_uq"); op_addAvxCC(MI, X86_AVX_CC_NGE_UQ); break; |
| 219 | case 0x1a: SStream_concat0(O, "ngt_uq"); op_addAvxCC(MI, X86_AVX_CC_NGT_UQ); break; |
| 220 | case 0x1b: SStream_concat0(O, "false_os"); op_addAvxCC(MI, X86_AVX_CC_FALSE_OS); break; |
| 221 | case 0x1c: SStream_concat0(O, "neq_os"); op_addAvxCC(MI, X86_AVX_CC_NEQ_OS); break; |
| 222 | case 0x1d: SStream_concat0(O, "ge_oq"); op_addAvxCC(MI, X86_AVX_CC_GE_OQ); break; |
| 223 | case 0x1e: SStream_concat0(O, "gt_oq"); op_addAvxCC(MI, X86_AVX_CC_GT_OQ); break; |
| 224 | case 0x1f: SStream_concat0(O, "true_us"); op_addAvxCC(MI, X86_AVX_CC_TRUE_US); break; |
Nguyen Anh Quynh | 9518148 | 2014-03-25 23:20:41 +0800 | [diff] [blame] | 225 | } |
| 226 | } |
| 227 | |
| 228 | static void printRoundingControl(MCInst *MI, unsigned Op, SStream *O) |
| 229 | { |
| 230 | int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x3; |
| 231 | switch (Imm) { |
Nguyen Anh Quynh | 1a66fec | 2014-06-26 12:09:15 +0800 | [diff] [blame] | 232 | case 0: SStream_concat0(O, "{rn-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RN); break; |
| 233 | case 1: SStream_concat0(O, "{rd-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RD); break; |
| 234 | case 2: SStream_concat0(O, "{ru-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RU); break; |
| 235 | case 3: SStream_concat0(O, "{rz-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RZ); break; |
Nguyen Anh Quynh | a62b9a0 | 2014-06-04 22:25:48 +0700 | [diff] [blame] | 236 | default: break; // nev0er reach |
Nguyen Anh Quynh | 9518148 | 2014-03-25 23:20:41 +0800 | [diff] [blame] | 237 | } |
| 238 | } |
| 239 | |
| 240 | #endif |
| 241 | |
Nguyen Anh Quynh | 14ba46b | 2014-06-24 14:32:01 +0800 | [diff] [blame] | 242 | static void printRegName(SStream *OS, unsigned RegNo); |
| 243 | |
| 244 | // local printOperand, without updating public operands |
| 245 | static void _printOperand(MCInst *MI, unsigned OpNo, SStream *O) |
| 246 | { |
| 247 | MCOperand *Op = MCInst_getOperand(MI, OpNo); |
| 248 | if (MCOperand_isReg(Op)) { |
| 249 | printRegName(O, MCOperand_getReg(Op)); |
| 250 | } else if (MCOperand_isImm(Op)) { |
| 251 | // Print X86 immediates as signed values. |
| 252 | int64_t imm = MCOperand_getImm(Op); |
| 253 | if (imm < 0) { |
| 254 | if (imm < -HEX_THRESHOLD) |
| 255 | SStream_concat(O, "$-0x%"PRIx64, -imm); |
| 256 | else |
| 257 | SStream_concat(O, "$-%"PRIu64, -imm); |
| 258 | } else { |
| 259 | if (imm > HEX_THRESHOLD) |
| 260 | SStream_concat(O, "$0x%"PRIx64, imm); |
| 261 | else |
| 262 | SStream_concat(O, "$%"PRIu64, imm); |
| 263 | } |
| 264 | } |
| 265 | } |
| 266 | |
Nguyen Anh Quynh | 13f40d2 | 2014-02-07 22:06:33 +0800 | [diff] [blame] | 267 | static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O) |
| 268 | { |
| 269 | MCOperand *SegReg; |
Nguyen Anh Quynh | 14ba46b | 2014-06-24 14:32:01 +0800 | [diff] [blame] | 270 | int reg; |
| 271 | |
| 272 | if (MI->csh->detail) { |
| 273 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; |
| 274 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; |
| 275 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; |
| 276 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID; |
| 277 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID; |
| 278 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; |
| 279 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; |
| 280 | } |
Nguyen Anh Quynh | 13f40d2 | 2014-02-07 22:06:33 +0800 | [diff] [blame] | 281 | |
| 282 | SegReg = MCInst_getOperand(MI, Op+1); |
Nguyen Anh Quynh | 14ba46b | 2014-06-24 14:32:01 +0800 | [diff] [blame] | 283 | reg = MCOperand_getReg(SegReg); |
Nguyen Anh Quynh | 13f40d2 | 2014-02-07 22:06:33 +0800 | [diff] [blame] | 284 | |
Nguyen Anh Quynh | 13f40d2 | 2014-02-07 22:06:33 +0800 | [diff] [blame] | 285 | // If this has a segment register, print it. |
Nguyen Anh Quynh | 14ba46b | 2014-06-24 14:32:01 +0800 | [diff] [blame] | 286 | if (reg) { |
| 287 | _printOperand(MI, Op+1, O); |
| 288 | if (MI->csh->detail) { |
| 289 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = reg; |
| 290 | } |
| 291 | |
Nguyen Anh Quynh | a62b9a0 | 2014-06-04 22:25:48 +0700 | [diff] [blame] | 292 | SStream_concat0(O, ":"); |
Nguyen Anh Quynh | 13f40d2 | 2014-02-07 22:06:33 +0800 | [diff] [blame] | 293 | } |
| 294 | |
Nguyen Anh Quynh | a62b9a0 | 2014-06-04 22:25:48 +0700 | [diff] [blame] | 295 | SStream_concat0(O, "("); |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 296 | set_mem_access(MI, true); |
Nguyen Anh Quynh | 13f40d2 | 2014-02-07 22:06:33 +0800 | [diff] [blame] | 297 | |
| 298 | printOperand(MI, Op, O); |
| 299 | |
Nguyen Anh Quynh | 1e688d4 | 2014-06-18 14:28:55 +0800 | [diff] [blame] | 300 | SStream_concat0(O, ")"); |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 301 | set_mem_access(MI, false); |
Nguyen Anh Quynh | 13f40d2 | 2014-02-07 22:06:33 +0800 | [diff] [blame] | 302 | } |
| 303 | |
| 304 | static void printDstIdx(MCInst *MI, unsigned Op, SStream *O) |
| 305 | { |
Nguyen Anh Quynh | 14ba46b | 2014-06-24 14:32:01 +0800 | [diff] [blame] | 306 | if (MI->csh->detail) { |
| 307 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; |
| 308 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; |
| 309 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; |
| 310 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID; |
| 311 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID; |
| 312 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; |
| 313 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; |
| 314 | } |
| 315 | |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 316 | // DI accesses are always ES-based on non-64bit mode |
Nguyen Anh Quynh | 14ba46b | 2014-06-24 14:32:01 +0800 | [diff] [blame] | 317 | if (MI->csh->mode != CS_MODE_64) { |
Nguyen Anh Quynh | 1e688d4 | 2014-06-18 14:28:55 +0800 | [diff] [blame] | 318 | SStream_concat0(O, "%es:("); |
Nguyen Anh Quynh | 14ba46b | 2014-06-24 14:32:01 +0800 | [diff] [blame] | 319 | if (MI->csh->detail) { |
| 320 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_ES; |
| 321 | } |
| 322 | } else |
Nguyen Anh Quynh | 1e688d4 | 2014-06-18 14:28:55 +0800 | [diff] [blame] | 323 | SStream_concat0(O, "("); |
Nguyen Anh Quynh | 14ba46b | 2014-06-24 14:32:01 +0800 | [diff] [blame] | 324 | |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 325 | set_mem_access(MI, true); |
| 326 | |
Nguyen Anh Quynh | 13f40d2 | 2014-02-07 22:06:33 +0800 | [diff] [blame] | 327 | printOperand(MI, Op, O); |
| 328 | |
Nguyen Anh Quynh | 1e688d4 | 2014-06-18 14:28:55 +0800 | [diff] [blame] | 329 | SStream_concat0(O, ")"); |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 330 | set_mem_access(MI, false); |
Nguyen Anh Quynh | 13f40d2 | 2014-02-07 22:06:33 +0800 | [diff] [blame] | 331 | } |
| 332 | |
| 333 | static void printSrcIdx8(MCInst *MI, unsigned OpNo, SStream *O) |
| 334 | { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 335 | MI->x86opsize = 1; |
Nguyen Anh Quynh | 13f40d2 | 2014-02-07 22:06:33 +0800 | [diff] [blame] | 336 | printSrcIdx(MI, OpNo, O); |
| 337 | } |
| 338 | |
| 339 | static void printSrcIdx16(MCInst *MI, unsigned OpNo, SStream *O) |
| 340 | { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 341 | MI->x86opsize = 2; |
Nguyen Anh Quynh | 13f40d2 | 2014-02-07 22:06:33 +0800 | [diff] [blame] | 342 | printSrcIdx(MI, OpNo, O); |
| 343 | } |
| 344 | |
| 345 | static void printSrcIdx32(MCInst *MI, unsigned OpNo, SStream *O) |
| 346 | { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 347 | MI->x86opsize = 4; |
Nguyen Anh Quynh | 13f40d2 | 2014-02-07 22:06:33 +0800 | [diff] [blame] | 348 | printSrcIdx(MI, OpNo, O); |
| 349 | } |
| 350 | |
| 351 | static void printSrcIdx64(MCInst *MI, unsigned OpNo, SStream *O) |
| 352 | { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 353 | MI->x86opsize = 8; |
Nguyen Anh Quynh | 13f40d2 | 2014-02-07 22:06:33 +0800 | [diff] [blame] | 354 | printSrcIdx(MI, OpNo, O); |
| 355 | } |
| 356 | |
| 357 | static void printDstIdx8(MCInst *MI, unsigned OpNo, SStream *O) |
| 358 | { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 359 | MI->x86opsize = 1; |
Nguyen Anh Quynh | 13f40d2 | 2014-02-07 22:06:33 +0800 | [diff] [blame] | 360 | printDstIdx(MI, OpNo, O); |
| 361 | } |
| 362 | |
| 363 | static void printDstIdx16(MCInst *MI, unsigned OpNo, SStream *O) |
| 364 | { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 365 | MI->x86opsize = 2; |
Nguyen Anh Quynh | 13f40d2 | 2014-02-07 22:06:33 +0800 | [diff] [blame] | 366 | printDstIdx(MI, OpNo, O); |
| 367 | } |
| 368 | |
| 369 | static void printDstIdx32(MCInst *MI, unsigned OpNo, SStream *O) |
| 370 | { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 371 | MI->x86opsize = 4; |
Nguyen Anh Quynh | 13f40d2 | 2014-02-07 22:06:33 +0800 | [diff] [blame] | 372 | printDstIdx(MI, OpNo, O); |
| 373 | } |
| 374 | |
| 375 | static void printDstIdx64(MCInst *MI, unsigned OpNo, SStream *O) |
| 376 | { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 377 | MI->x86opsize = 8; |
Nguyen Anh Quynh | 13f40d2 | 2014-02-07 22:06:33 +0800 | [diff] [blame] | 378 | printDstIdx(MI, OpNo, O); |
| 379 | } |
| 380 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 381 | static void printMemOffset(MCInst *MI, unsigned Op, SStream *O) |
| 382 | { |
| 383 | MCOperand *DispSpec = MCInst_getOperand(MI, Op); |
Nguyen Anh Quynh | 13f40d2 | 2014-02-07 22:06:33 +0800 | [diff] [blame] | 384 | MCOperand *SegReg = MCInst_getOperand(MI, Op+1); |
Nguyen Anh Quynh | 14ba46b | 2014-06-24 14:32:01 +0800 | [diff] [blame] | 385 | int reg; |
Nguyen Anh Quynh | 13f40d2 | 2014-02-07 22:06:33 +0800 | [diff] [blame] | 386 | |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 387 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 5329a6f | 2014-06-08 23:35:52 +0700 | [diff] [blame] | 388 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 389 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; |
Nguyen Anh Quynh | 14ba46b | 2014-06-24 14:32:01 +0800 | [diff] [blame] | 390 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; |
Nguyen Anh Quynh | 5329a6f | 2014-06-08 23:35:52 +0700 | [diff] [blame] | 391 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID; |
| 392 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID; |
| 393 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; |
| 394 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 395 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 396 | |
Nguyen Anh Quynh | 14ba46b | 2014-06-24 14:32:01 +0800 | [diff] [blame] | 397 | // If this has a segment register, print it. |
| 398 | reg = MCOperand_getReg(SegReg); |
| 399 | if (reg) { |
| 400 | _printOperand(MI, Op + 1, O); |
| 401 | SStream_concat0(O, ":"); |
| 402 | if (MI->csh->detail) { |
| 403 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = reg; |
| 404 | } |
| 405 | } |
| 406 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 407 | if (MCOperand_isImm(DispSpec)) { |
| 408 | int64_t imm = MCOperand_getImm(DispSpec); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 409 | if (MI->csh->detail) |
Nguyen Anh Quynh | 5329a6f | 2014-06-08 23:35:52 +0700 | [diff] [blame] | 410 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm; |
Nguyen Anh Quynh | 4fe4281 | 2013-12-13 12:26:26 +0800 | [diff] [blame] | 411 | if (imm < 0) { |
Nguyen Anh Quynh | 6d3d800 | 2014-03-29 17:26:51 +0800 | [diff] [blame] | 412 | SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & imm); |
Nguyen Anh Quynh | 4fe4281 | 2013-12-13 12:26:26 +0800 | [diff] [blame] | 413 | } else { |
Nguyen Anh Quynh | f22557b | 2013-12-13 09:37:52 +0800 | [diff] [blame] | 414 | if (imm > HEX_THRESHOLD) |
| 415 | SStream_concat(O, "0x%"PRIx64, imm); |
| 416 | else |
| 417 | SStream_concat(O, "%"PRIu64, imm); |
| 418 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 419 | } |
| 420 | |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 421 | if (MI->csh->detail) |
Nguyen Anh Quynh | 5329a6f | 2014-06-08 23:35:52 +0700 | [diff] [blame] | 422 | MI->flat_insn->detail->x86.op_count++; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 423 | } |
| 424 | |
| 425 | static void printMemOffs8(MCInst *MI, unsigned OpNo, SStream *O) |
| 426 | { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 427 | MI->x86opsize = 1; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 428 | printMemOffset(MI, OpNo, O); |
| 429 | } |
| 430 | |
| 431 | static void printMemOffs16(MCInst *MI, unsigned OpNo, SStream *O) |
| 432 | { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 433 | MI->x86opsize = 2; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 434 | printMemOffset(MI, OpNo, O); |
| 435 | } |
| 436 | |
| 437 | static void printMemOffs32(MCInst *MI, unsigned OpNo, SStream *O) |
| 438 | { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 439 | MI->x86opsize = 4; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 440 | printMemOffset(MI, OpNo, O); |
| 441 | } |
| 442 | |
| 443 | static void printMemOffs64(MCInst *MI, unsigned OpNo, SStream *O) |
| 444 | { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 445 | MI->x86opsize = 8; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 446 | printMemOffset(MI, OpNo, O); |
| 447 | } |
| 448 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 449 | /// printPCRelImm - This is used to print an immediate value that ends up |
| 450 | /// being encoded as a pc-relative value (e.g. for jumps and calls). These |
| 451 | /// print slightly differently than normal immediates. For example, a $ is not |
| 452 | /// emitted. |
| 453 | static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O) |
| 454 | { |
| 455 | MCOperand *Op = MCInst_getOperand(MI, OpNo); |
| 456 | if (MCOperand_isImm(Op)) { |
Nguyen Anh Quynh | 5329a6f | 2014-06-08 23:35:52 +0700 | [diff] [blame] | 457 | int64_t imm = MCOperand_getImm(Op) + MI->flat_insn->size + MI->address; |
Nguyen Anh Quynh | af806e0 | 2015-07-11 10:00:29 +0800 | [diff] [blame] | 458 | |
| 459 | // truncat imm for non-64bit |
| 460 | if (MI->csh->mode != CS_MODE_64) { |
| 461 | imm = imm & 0xffffffff; |
| 462 | } |
| 463 | |
Nguyen Anh Quynh | 4fe4281 | 2013-12-13 12:26:26 +0800 | [diff] [blame] | 464 | if (imm < 0) { |
Nguyen Anh Quynh | a90b047 | 2014-10-02 12:04:35 +0800 | [diff] [blame] | 465 | SStream_concat(O, "0x%"PRIx64, imm); |
Nguyen Anh Quynh | 4fe4281 | 2013-12-13 12:26:26 +0800 | [diff] [blame] | 466 | } else { |
Nguyen Anh Quynh | 2d34251 | 2014-05-11 15:33:11 +0800 | [diff] [blame] | 467 | // handle 16bit segment bound |
| 468 | if (MI->csh->mode == CS_MODE_16 && imm > 0x100000) |
| 469 | imm -= 0x10000; |
| 470 | |
Nguyen Anh Quynh | f22557b | 2013-12-13 09:37:52 +0800 | [diff] [blame] | 471 | if (imm > HEX_THRESHOLD) |
| 472 | SStream_concat(O, "0x%"PRIx64, imm); |
| 473 | else |
| 474 | SStream_concat(O, "%"PRIu64, imm); |
| 475 | } |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 476 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 5329a6f | 2014-06-08 23:35:52 +0700 | [diff] [blame] | 477 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; |
Nguyen Anh Quynh | ff7bba3 | 2014-11-03 16:32:06 +0800 | [diff] [blame] | 478 | MI->has_imm = true; |
Nguyen Anh Quynh | 5329a6f | 2014-06-08 23:35:52 +0700 | [diff] [blame] | 479 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm; |
| 480 | MI->flat_insn->detail->x86.op_count++; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 481 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 482 | } |
| 483 | } |
| 484 | |
| 485 | static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) |
| 486 | { |
Nguyen Anh Quynh | 3f00a72 | 2015-06-06 00:04:03 +0800 | [diff] [blame] | 487 | int opsize = 0; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 488 | MCOperand *Op = MCInst_getOperand(MI, OpNo); |
Nguyen Anh Quynh | 3f00a72 | 2015-06-06 00:04:03 +0800 | [diff] [blame] | 489 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 490 | if (MCOperand_isReg(Op)) { |
Nguyen Anh Quynh | ea3c089 | 2014-10-02 10:17:55 +0800 | [diff] [blame] | 491 | unsigned int reg = MCOperand_getReg(Op); |
| 492 | printRegName(O, reg); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 493 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 494 | if (MI->csh->doing_mem) { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 495 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = reg; |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 496 | } else { |
| 497 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG; |
| 498 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = reg; |
| 499 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->csh->regsize_map[reg]; |
| 500 | MI->flat_insn->detail->x86.op_count++; |
| 501 | } |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 502 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 503 | } else if (MCOperand_isImm(Op)) { |
| 504 | // Print X86 immediates as signed values. |
| 505 | int64_t imm = MCOperand_getImm(Op); |
Nguyen Anh Quynh | 9cc8787 | 2014-11-04 11:04:16 +0800 | [diff] [blame] | 506 | |
Nguyen Anh Quynh | 3f00a72 | 2015-06-06 00:04:03 +0800 | [diff] [blame] | 507 | switch(MCInst_getOpcode(MI)) { |
| 508 | default: |
| 509 | break; |
| 510 | |
| 511 | case X86_AAD8i8: |
| 512 | case X86_AAM8i8: |
| 513 | case X86_ADC8i8: |
| 514 | case X86_ADD8i8: |
| 515 | case X86_AND8i8: |
| 516 | case X86_CMP8i8: |
| 517 | case X86_OR8i8: |
| 518 | case X86_SBB8i8: |
| 519 | case X86_SUB8i8: |
| 520 | case X86_TEST8i8: |
| 521 | case X86_XOR8i8: |
| 522 | case X86_ROL8ri: |
| 523 | case X86_ADC8ri: |
| 524 | case X86_ADD8ri: |
| 525 | case X86_ADD8ri8: |
| 526 | case X86_AND8ri: |
| 527 | case X86_AND8ri8: |
| 528 | case X86_CMP8ri: |
| 529 | case X86_MOV8ri: |
| 530 | case X86_MOV8ri_alt: |
| 531 | case X86_OR8ri: |
| 532 | case X86_OR8ri8: |
| 533 | case X86_RCL8ri: |
| 534 | case X86_RCR8ri: |
| 535 | case X86_ROR8ri: |
| 536 | case X86_SAL8ri: |
| 537 | case X86_SAR8ri: |
| 538 | case X86_SBB8ri: |
| 539 | case X86_SHL8ri: |
| 540 | case X86_SHR8ri: |
| 541 | case X86_SUB8ri: |
| 542 | case X86_SUB8ri8: |
| 543 | case X86_TEST8ri: |
| 544 | case X86_TEST8ri_NOREX: |
| 545 | case X86_TEST8ri_alt: |
| 546 | case X86_XOR8ri: |
| 547 | case X86_XOR8ri8: |
| 548 | case X86_OUT8ir: |
| 549 | |
| 550 | case X86_ADC8mi: |
| 551 | case X86_ADD8mi: |
| 552 | case X86_AND8mi: |
| 553 | case X86_CMP8mi: |
| 554 | case X86_LOCK_ADD8mi: |
| 555 | case X86_LOCK_AND8mi: |
| 556 | case X86_LOCK_OR8mi: |
| 557 | case X86_LOCK_SUB8mi: |
| 558 | case X86_LOCK_XOR8mi: |
| 559 | case X86_MOV8mi: |
| 560 | case X86_OR8mi: |
| 561 | case X86_RCL8mi: |
| 562 | case X86_RCR8mi: |
| 563 | case X86_ROL8mi: |
| 564 | case X86_ROR8mi: |
| 565 | case X86_SAL8mi: |
| 566 | case X86_SAR8mi: |
| 567 | case X86_SBB8mi: |
| 568 | case X86_SHL8mi: |
| 569 | case X86_SHR8mi: |
| 570 | case X86_SUB8mi: |
| 571 | case X86_TEST8mi: |
| 572 | case X86_TEST8mi_alt: |
| 573 | case X86_XOR8mi: |
| 574 | case X86_PUSH64i8: |
| 575 | case X86_CMP32ri8: |
| 576 | case X86_CMP64ri8: |
| 577 | |
| 578 | imm = imm & 0xff; |
| 579 | opsize = 1; // immediate of 1 byte |
| 580 | break; |
| 581 | } |
| 582 | |
Nguyen Anh Quynh | 9cc8787 | 2014-11-04 11:04:16 +0800 | [diff] [blame] | 583 | switch(MI->flat_insn->id) { |
| 584 | default: |
| 585 | if (imm >= 0) { |
| 586 | if (imm > HEX_THRESHOLD) |
| 587 | SStream_concat(O, "$0x%"PRIx64, imm); |
| 588 | else |
| 589 | SStream_concat(O, "$%"PRIu64, imm); |
| 590 | } else { |
| 591 | if (imm < -HEX_THRESHOLD) |
| 592 | SStream_concat(O, "$-0x%"PRIx64, -imm); |
| 593 | else |
| 594 | SStream_concat(O, "$-%"PRIu64, -imm); |
| 595 | } |
| 596 | break; |
Nguyen Anh Quynh | 36d0594 | 2015-06-20 10:56:54 +0800 | [diff] [blame] | 597 | |
Nguyen Anh Quynh | 981c201 | 2015-08-13 21:36:27 +0800 | [diff] [blame^] | 598 | case X86_INS_INT: |
| 599 | // do not print number in negative form |
| 600 | imm = imm & 0xff; |
| 601 | if (imm >= 0 && imm <= HEX_THRESHOLD) |
| 602 | SStream_concat(O, "$%u", imm); |
| 603 | else { |
| 604 | SStream_concat(O, "$0x%x", imm); |
| 605 | } |
| 606 | break; |
| 607 | |
| 608 | case X86_INS_LCALL: |
| 609 | case X86_INS_LJMP: |
| 610 | // always print address in positive form |
| 611 | if (OpNo == 1) { // selector is ptr16 |
| 612 | imm = imm & 0xffff; |
| 613 | opsize = 2; |
| 614 | } |
| 615 | SStream_concat(O, "$0x%"PRIx64, imm); |
| 616 | break; |
| 617 | |
Nguyen Anh Quynh | 36d0594 | 2015-06-20 10:56:54 +0800 | [diff] [blame] | 618 | case X86_INS_AND: |
| 619 | case X86_INS_OR: |
| 620 | case X86_INS_XOR: |
| 621 | // do not print number in negative form |
| 622 | if (imm >= 0 && imm <= HEX_THRESHOLD) |
| 623 | SStream_concat(O, "$%u", imm); |
| 624 | else { |
| 625 | imm = arch_masks[MI->op1_size? MI->op1_size : MI->imm_size] & imm; |
| 626 | SStream_concat(O, "$0x%"PRIx64, imm); |
| 627 | } |
| 628 | break; |
| 629 | |
Nguyen Anh Quynh | 9cc8787 | 2014-11-04 11:04:16 +0800 | [diff] [blame] | 630 | case X86_INS_RET: |
| 631 | // RET imm16 |
| 632 | if (imm >= 0 && imm <= HEX_THRESHOLD) |
| 633 | SStream_concat(O, "$%u", imm); |
| 634 | else { |
| 635 | imm = 0xffff & imm; |
| 636 | SStream_concat(O, "$0x%x", imm); |
| 637 | } |
| 638 | break; |
Nguyen Anh Quynh | be90639 | 2013-12-13 15:37:57 +0800 | [diff] [blame] | 639 | } |
Nguyen Anh Quynh | 9cc8787 | 2014-11-04 11:04:16 +0800 | [diff] [blame] | 640 | |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 641 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 642 | if (MI->csh->doing_mem) { |
| 643 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 644 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm; |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 645 | } else { |
| 646 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; |
Nguyen Anh Quynh | ff7bba3 | 2014-11-03 16:32:06 +0800 | [diff] [blame] | 647 | MI->has_imm = true; |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 648 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm; |
Nguyen Anh Quynh | 36d0594 | 2015-06-20 10:56:54 +0800 | [diff] [blame] | 649 | |
Nguyen Anh Quynh | 3f00a72 | 2015-06-06 00:04:03 +0800 | [diff] [blame] | 650 | if (opsize > 0) |
| 651 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = opsize; |
| 652 | else if (MI->op1_size > 0) |
| 653 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->op1_size; |
| 654 | else |
| 655 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size; |
Nguyen Anh Quynh | 36d0594 | 2015-06-20 10:56:54 +0800 | [diff] [blame] | 656 | |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 657 | MI->flat_insn->detail->x86.op_count++; |
| 658 | } |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 659 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 660 | } |
| 661 | } |
| 662 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 663 | static void printMemReference(MCInst *MI, unsigned Op, SStream *O) |
| 664 | { |
Nguyen Anh Quynh | 0b69038 | 2014-08-13 13:01:50 +0800 | [diff] [blame] | 665 | MCOperand *BaseReg = MCInst_getOperand(MI, Op + X86_AddrBaseReg); |
| 666 | MCOperand *IndexReg = MCInst_getOperand(MI, Op + X86_AddrIndexReg); |
| 667 | MCOperand *DispSpec = MCInst_getOperand(MI, Op + X86_AddrDisp); |
| 668 | MCOperand *SegReg = MCInst_getOperand(MI, Op + X86_AddrSegmentReg); |
Nguyen Anh Quynh | bb0744d | 2014-05-12 13:41:49 +0800 | [diff] [blame] | 669 | uint64_t ScaleVal; |
Nguyen Anh Quynh | 14ba46b | 2014-06-24 14:32:01 +0800 | [diff] [blame] | 670 | int reg; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 671 | |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 672 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 5329a6f | 2014-06-08 23:35:52 +0700 | [diff] [blame] | 673 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; |
Nguyen Anh Quynh | 1085073 | 2014-06-18 12:16:24 +0800 | [diff] [blame] | 674 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; |
Nguyen Anh Quynh | 14ba46b | 2014-06-24 14:32:01 +0800 | [diff] [blame] | 675 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; |
Nguyen Anh Quynh | 5329a6f | 2014-06-08 23:35:52 +0700 | [diff] [blame] | 676 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = MCOperand_getReg(BaseReg); |
| 677 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = MCOperand_getReg(IndexReg); |
| 678 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; |
| 679 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; |
Nguyen Anh Quynh | a209e67 | 2013-12-14 00:23:41 +0800 | [diff] [blame] | 680 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 681 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 682 | // If this has a segment register, print it. |
Nguyen Anh Quynh | 14ba46b | 2014-06-24 14:32:01 +0800 | [diff] [blame] | 683 | reg = MCOperand_getReg(SegReg); |
| 684 | if (reg) { |
Nguyen Anh Quynh | 0b69038 | 2014-08-13 13:01:50 +0800 | [diff] [blame] | 685 | _printOperand(MI, Op + X86_AddrSegmentReg, O); |
Nguyen Anh Quynh | 14ba46b | 2014-06-24 14:32:01 +0800 | [diff] [blame] | 686 | if (MI->csh->detail) { |
| 687 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = reg; |
| 688 | } |
| 689 | |
Nguyen Anh Quynh | a62b9a0 | 2014-06-04 22:25:48 +0700 | [diff] [blame] | 690 | SStream_concat0(O, ":"); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 691 | } |
| 692 | |
| 693 | if (MCOperand_isImm(DispSpec)) { |
| 694 | int64_t DispVal = MCOperand_getImm(DispSpec); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 695 | if (MI->csh->detail) |
Nguyen Anh Quynh | 5329a6f | 2014-06-08 23:35:52 +0700 | [diff] [blame] | 696 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = DispVal; |
Nguyen Anh Quynh | b87f855 | 2014-11-02 23:38:35 +0800 | [diff] [blame] | 697 | if (DispVal) { |
| 698 | if (MCOperand_getReg(IndexReg) || MCOperand_getReg(BaseReg)) { |
| 699 | if (DispVal < 0) { |
| 700 | if (DispVal < -HEX_THRESHOLD) |
Nguyen Anh Quynh | 9cc8787 | 2014-11-04 11:04:16 +0800 | [diff] [blame] | 701 | SStream_concat(O, "-0x%"PRIx64, -DispVal); |
Nguyen Anh Quynh | b87f855 | 2014-11-02 23:38:35 +0800 | [diff] [blame] | 702 | else |
Nguyen Anh Quynh | 9cc8787 | 2014-11-04 11:04:16 +0800 | [diff] [blame] | 703 | SStream_concat(O, "-%"PRIu64, -DispVal); |
Nguyen Anh Quynh | b87f855 | 2014-11-02 23:38:35 +0800 | [diff] [blame] | 704 | } else { |
| 705 | if (DispVal > HEX_THRESHOLD) |
| 706 | SStream_concat(O, "0x%"PRIx64, DispVal); |
| 707 | else |
| 708 | SStream_concat(O, "%"PRIu64, DispVal); |
| 709 | } |
Nguyen Anh Quynh | 4fe4281 | 2013-12-13 12:26:26 +0800 | [diff] [blame] | 710 | } else { |
Nguyen Anh Quynh | b87f855 | 2014-11-02 23:38:35 +0800 | [diff] [blame] | 711 | // only immediate as address of memory |
| 712 | if (DispVal < 0) { |
| 713 | SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & DispVal); |
| 714 | } else { |
| 715 | if (DispVal > HEX_THRESHOLD) |
| 716 | SStream_concat(O, "0x%"PRIx64, DispVal); |
| 717 | else |
| 718 | SStream_concat(O, "%"PRIu64, DispVal); |
| 719 | } |
Nguyen Anh Quynh | f22557b | 2013-12-13 09:37:52 +0800 | [diff] [blame] | 720 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 721 | } |
| 722 | } |
| 723 | |
| 724 | if (MCOperand_getReg(IndexReg) || MCOperand_getReg(BaseReg)) { |
Nguyen Anh Quynh | a62b9a0 | 2014-06-04 22:25:48 +0700 | [diff] [blame] | 725 | SStream_concat0(O, "("); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 726 | |
| 727 | if (MCOperand_getReg(BaseReg)) |
Nguyen Anh Quynh | 0b69038 | 2014-08-13 13:01:50 +0800 | [diff] [blame] | 728 | _printOperand(MI, Op + X86_AddrBaseReg, O); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 729 | |
| 730 | if (MCOperand_getReg(IndexReg)) { |
Nguyen Anh Quynh | a62b9a0 | 2014-06-04 22:25:48 +0700 | [diff] [blame] | 731 | SStream_concat0(O, ", "); |
Nguyen Anh Quynh | 0b69038 | 2014-08-13 13:01:50 +0800 | [diff] [blame] | 732 | _printOperand(MI, Op + X86_AddrIndexReg, O); |
| 733 | ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op + X86_AddrScaleAmt)); |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 734 | if (MI->csh->detail) |
Nguyen Anh Quynh | 5329a6f | 2014-06-08 23:35:52 +0700 | [diff] [blame] | 735 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = (int)ScaleVal; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 736 | if (ScaleVal != 1) { |
Nguyen Anh Quynh | 1e688d4 | 2014-06-18 14:28:55 +0800 | [diff] [blame] | 737 | SStream_concat(O, ", %u", ScaleVal); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 738 | } |
| 739 | } |
Nguyen Anh Quynh | a62b9a0 | 2014-06-04 22:25:48 +0700 | [diff] [blame] | 740 | SStream_concat0(O, ")"); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 741 | } |
| 742 | |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 743 | if (MI->csh->detail) |
Nguyen Anh Quynh | 5329a6f | 2014-06-08 23:35:52 +0700 | [diff] [blame] | 744 | MI->flat_insn->detail->x86.op_count++; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 745 | } |
| 746 | |
| 747 | #include "X86InstPrinter.h" |
| 748 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 749 | #define GET_REGINFO_ENUM |
| 750 | #include "X86GenRegisterInfo.inc" |
| 751 | |
| 752 | // Include the auto-generated portion of the assembly writer. |
| 753 | #define PRINT_ALIAS_INSTR |
Nguyen Anh Quynh | 59b5489 | 2014-03-27 10:54:44 +0800 | [diff] [blame] | 754 | #ifdef CAPSTONE_X86_REDUCE |
| 755 | #include "X86GenAsmWriter_reduce.inc" |
Nguyen Anh Quynh | 9518148 | 2014-03-25 23:20:41 +0800 | [diff] [blame] | 756 | #else |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 757 | #include "X86GenAsmWriter.inc" |
Nguyen Anh Quynh | 9518148 | 2014-03-25 23:20:41 +0800 | [diff] [blame] | 758 | #endif |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 759 | |
| 760 | static void printRegName(SStream *OS, unsigned RegNo) |
| 761 | { |
Nguyen Anh Quynh | 1e688d4 | 2014-06-18 14:28:55 +0800 | [diff] [blame] | 762 | SStream_concat(OS, "%%%s", getRegisterName(RegNo)); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 763 | } |
| 764 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 765 | void X86_ATT_printInst(MCInst *MI, SStream *OS, void *info) |
| 766 | { |
Nguyen Anh Quynh | 27b9a96 | 2014-02-19 10:13:47 +0800 | [diff] [blame] | 767 | char *mnem; |
Nguyen Anh Quynh | 9578185 | 2014-12-12 11:25:12 +0800 | [diff] [blame] | 768 | x86_reg reg, reg2; |
Nguyen Anh Quynh | f1ec526 | 2014-06-25 22:03:18 +0800 | [diff] [blame] | 769 | int i; |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 770 | |
Nguyen Anh Quynh | 1f196d1 | 2014-09-09 23:59:38 +0800 | [diff] [blame] | 771 | // Output CALLpcrel32 as "callq" in 64-bit mode. |
| 772 | // In Intel annotation it's always emitted as "call". |
| 773 | // |
| 774 | // TODO: Probably this hack should be redesigned via InstAlias in |
| 775 | // InstrInfo.td as soon as Requires clause is supported properly |
| 776 | // for InstAlias. |
| 777 | if (MI->csh->mode == CS_MODE_64 && MCInst_getOpcode(MI) == X86_CALLpcrel32) { |
| 778 | SStream_concat0(OS, "callq\t"); |
| 779 | MCInst_setOpcodePub(MI, X86_INS_CALL); |
| 780 | printPCRelImm(MI, 0, OS); |
| 781 | return; |
| 782 | } |
| 783 | |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 784 | // Try to print any aliases first. |
Nguyen Anh Quynh | 0b69038 | 2014-08-13 13:01:50 +0800 | [diff] [blame] | 785 | mnem = printAliasInstr(MI, OS, info); |
Nguyen Anh Quynh | 27b9a96 | 2014-02-19 10:13:47 +0800 | [diff] [blame] | 786 | if (mnem) |
| 787 | cs_mem_free(mnem); |
| 788 | else |
Nguyen Anh Quynh | 0b69038 | 2014-08-13 13:01:50 +0800 | [diff] [blame] | 789 | printInstruction(MI, OS, info); |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 790 | |
Nguyen Anh Quynh | f1ec526 | 2014-06-25 22:03:18 +0800 | [diff] [blame] | 791 | if (MI->has_imm) { |
| 792 | // if op_count > 1, then this operand's size is taken from the destination op |
| 793 | if (MI->flat_insn->detail->x86.op_count > 1) { |
Nguyen Anh Quynh | 981c201 | 2015-08-13 21:36:27 +0800 | [diff] [blame^] | 794 | if (MI->flat_insn->id != X86_INS_LCALL && MI->flat_insn->id != X86_INS_LJMP) { |
| 795 | for (i = 0; i < MI->flat_insn->detail->x86.op_count; i++) { |
| 796 | if (MI->flat_insn->detail->x86.operands[i].type == X86_OP_IMM) |
| 797 | MI->flat_insn->detail->x86.operands[i].size = |
| 798 | MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count - 1].size; |
| 799 | } |
Nguyen Anh Quynh | f1ec526 | 2014-06-25 22:03:18 +0800 | [diff] [blame] | 800 | } |
| 801 | } else |
| 802 | MI->flat_insn->detail->x86.operands[0].size = MI->imm_size; |
| 803 | } |
| 804 | |
Nguyen Anh Quynh | 42c6b1a | 2013-12-30 00:15:25 +0800 | [diff] [blame] | 805 | if (MI->csh->detail) { |
Nguyen Anh Quynh | 27526f3 | 2015-05-08 14:23:08 +0800 | [diff] [blame] | 806 | // some instructions need to supply immediate 1 in the first op |
| 807 | switch(MCInst_getOpcode(MI)) { |
| 808 | default: |
| 809 | break; |
| 810 | case X86_SHL8r1: |
| 811 | case X86_SHL16r1: |
| 812 | case X86_SHL32r1: |
| 813 | case X86_SHL64r1: |
| 814 | case X86_SAL8r1: |
| 815 | case X86_SAL16r1: |
| 816 | case X86_SAL32r1: |
| 817 | case X86_SAL64r1: |
| 818 | case X86_SHR8r1: |
| 819 | case X86_SHR16r1: |
| 820 | case X86_SHR32r1: |
| 821 | case X86_SHR64r1: |
| 822 | case X86_SAR8r1: |
| 823 | case X86_SAR16r1: |
| 824 | case X86_SAR32r1: |
| 825 | case X86_SAR64r1: |
| 826 | case X86_RCL8r1: |
| 827 | case X86_RCL16r1: |
| 828 | case X86_RCL32r1: |
| 829 | case X86_RCL64r1: |
| 830 | case X86_RCR8r1: |
| 831 | case X86_RCR16r1: |
| 832 | case X86_RCR32r1: |
| 833 | case X86_RCR64r1: |
| 834 | case X86_ROL8r1: |
| 835 | case X86_ROL16r1: |
| 836 | case X86_ROL32r1: |
| 837 | case X86_ROL64r1: |
| 838 | case X86_ROR8r1: |
| 839 | case X86_ROR16r1: |
| 840 | case X86_ROR32r1: |
| 841 | case X86_ROR64r1: |
| 842 | case X86_SHL8m1: |
| 843 | case X86_SHL16m1: |
| 844 | case X86_SHL32m1: |
| 845 | case X86_SHL64m1: |
| 846 | case X86_SAL8m1: |
| 847 | case X86_SAL16m1: |
| 848 | case X86_SAL32m1: |
| 849 | case X86_SAL64m1: |
| 850 | case X86_SHR8m1: |
| 851 | case X86_SHR16m1: |
| 852 | case X86_SHR32m1: |
| 853 | case X86_SHR64m1: |
| 854 | case X86_SAR8m1: |
| 855 | case X86_SAR16m1: |
| 856 | case X86_SAR32m1: |
| 857 | case X86_SAR64m1: |
| 858 | case X86_RCL8m1: |
| 859 | case X86_RCL16m1: |
| 860 | case X86_RCL32m1: |
| 861 | case X86_RCL64m1: |
| 862 | case X86_RCR8m1: |
| 863 | case X86_RCR16m1: |
| 864 | case X86_RCR32m1: |
| 865 | case X86_RCR64m1: |
| 866 | case X86_ROL8m1: |
| 867 | case X86_ROL16m1: |
| 868 | case X86_ROL32m1: |
| 869 | case X86_ROL64m1: |
| 870 | case X86_ROR8m1: |
| 871 | case X86_ROR16m1: |
| 872 | case X86_ROR32m1: |
| 873 | case X86_ROR64m1: |
| 874 | // shift all the ops right to leave 1st slot for this new register op |
| 875 | memmove(&(MI->flat_insn->detail->x86.operands[1]), &(MI->flat_insn->detail->x86.operands[0]), |
| 876 | sizeof(MI->flat_insn->detail->x86.operands[0]) * (ARR_SIZE(MI->flat_insn->detail->x86.operands) - 1)); |
| 877 | MI->flat_insn->detail->x86.operands[0].type = X86_OP_IMM; |
| 878 | MI->flat_insn->detail->x86.operands[0].imm = 1; |
| 879 | MI->flat_insn->detail->x86.operands[0].size = 1; |
| 880 | MI->flat_insn->detail->x86.op_count++; |
| 881 | } |
| 882 | |
Nguyen Anh Quynh | 85cddef | 2014-02-18 11:59:36 +0800 | [diff] [blame] | 883 | // special instruction needs to supply register op |
Nguyen Anh Quynh | 14ba46b | 2014-06-24 14:32:01 +0800 | [diff] [blame] | 884 | // first op can be embedded in the asm by llvm. |
| 885 | // so we have to add the missing register as the first operand |
| 886 | reg = X86_insn_reg_att(MCInst_getOpcode(MI)); |
Nguyen Anh Quynh | 85cddef | 2014-02-18 11:59:36 +0800 | [diff] [blame] | 887 | if (reg) { |
Nguyen Anh Quynh | 14ba46b | 2014-06-24 14:32:01 +0800 | [diff] [blame] | 888 | // shift all the ops right to leave 1st slot for this new register op |
| 889 | memmove(&(MI->flat_insn->detail->x86.operands[1]), &(MI->flat_insn->detail->x86.operands[0]), |
| 890 | sizeof(MI->flat_insn->detail->x86.operands[0]) * (ARR_SIZE(MI->flat_insn->detail->x86.operands) - 1)); |
| 891 | MI->flat_insn->detail->x86.operands[0].type = X86_OP_REG; |
| 892 | MI->flat_insn->detail->x86.operands[0].reg = reg; |
| 893 | MI->flat_insn->detail->x86.operands[0].size = MI->csh->regsize_map[reg]; |
| 894 | MI->flat_insn->detail->x86.op_count++; |
Nguyen Anh Quynh | 9578185 | 2014-12-12 11:25:12 +0800 | [diff] [blame] | 895 | } else { |
| 896 | if (X86_insn_reg_att2(MCInst_getOpcode(MI), ®, ®2)) { |
| 897 | MI->flat_insn->detail->x86.operands[0].type = X86_OP_REG; |
| 898 | MI->flat_insn->detail->x86.operands[0].reg = reg; |
| 899 | MI->flat_insn->detail->x86.operands[0].size = MI->csh->regsize_map[reg]; |
| 900 | MI->flat_insn->detail->x86.operands[1].type = X86_OP_REG; |
| 901 | MI->flat_insn->detail->x86.operands[1].reg = reg2; |
| 902 | MI->flat_insn->detail->x86.operands[1].size = MI->csh->regsize_map[reg2]; |
| 903 | MI->flat_insn->detail->x86.op_count = 2; |
| 904 | } |
Nguyen Anh Quynh | 26ee41a | 2013-11-27 12:11:31 +0800 | [diff] [blame] | 905 | } |
| 906 | } |
| 907 | } |
| 908 | |
Nguyen Anh Quynh | 8598a21 | 2014-05-14 11:26:41 +0800 | [diff] [blame] | 909 | #endif |