Nguyen Anh Quynh | c80d840 | 2014-05-26 23:02:48 +0800 | [diff] [blame] | 1 | #ifndef CAPSTONE_XCORE_H |
| 2 | #define CAPSTONE_XCORE_H |
| 3 | |
| 4 | /* Capstone Disassembly Engine */ |
| 5 | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014 */ |
| 6 | |
| 7 | #ifdef __cplusplus |
| 8 | extern "C" { |
| 9 | #endif |
| 10 | |
| 11 | #include <stdint.h> |
| 12 | #include "platform.h" |
| 13 | |
| 14 | #ifdef _MSC_VER |
| 15 | #pragma warning(disable:4201) |
| 16 | #endif |
| 17 | |
| 18 | //> Operand type for instruction's operands |
| 19 | typedef enum xcore_op_type { |
Nguyen Anh Quynh | c58e704 | 2014-10-31 13:55:18 +0800 | [diff] [blame] | 20 | XCORE_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized). |
| 21 | XCORE_OP_REG, // = CS_OP_REG (Register operand). |
| 22 | XCORE_OP_IMM, // = CS_OP_IMM (Immediate operand). |
| 23 | XCORE_OP_MEM, // = CS_OP_MEM (Memory operand). |
Nguyen Anh Quynh | c80d840 | 2014-05-26 23:02:48 +0800 | [diff] [blame] | 24 | } xcore_op_type; |
| 25 | |
| 26 | // Instruction's operand referring to memory |
| 27 | // This is associated with XCORE_OP_MEM operand type above |
| 28 | typedef struct xcore_op_mem { |
| 29 | uint8_t base; // base register |
| 30 | uint8_t index; // index register |
| 31 | int32_t disp; // displacement/offset value |
| 32 | int direct; // +1: forward, -1: backward |
| 33 | } xcore_op_mem; |
| 34 | |
| 35 | // Instruction operand |
| 36 | typedef struct cs_xcore_op { |
| 37 | xcore_op_type type; // operand type |
| 38 | union { |
| 39 | unsigned int reg; // register value for REG operand |
| 40 | int32_t imm; // immediate value for IMM operand |
| 41 | xcore_op_mem mem; // base/disp value for MEM operand |
| 42 | }; |
| 43 | } cs_xcore_op; |
| 44 | |
| 45 | // Instruction structure |
| 46 | typedef struct cs_xcore { |
| 47 | // Number of operands of this instruction, |
| 48 | // or 0 when instruction has no operand. |
| 49 | uint8_t op_count; |
| 50 | cs_xcore_op operands[8]; // operands for this instruction. |
| 51 | } cs_xcore; |
| 52 | |
| 53 | //> XCore registers |
| 54 | typedef enum xcore_reg { |
| 55 | XCORE_REG_INVALID = 0, |
| 56 | |
| 57 | XCORE_REG_CP, |
| 58 | XCORE_REG_DP, |
| 59 | XCORE_REG_LR, |
| 60 | XCORE_REG_SP, |
| 61 | XCORE_REG_R0, |
| 62 | XCORE_REG_R1, |
| 63 | XCORE_REG_R2, |
| 64 | XCORE_REG_R3, |
| 65 | XCORE_REG_R4, |
| 66 | XCORE_REG_R5, |
| 67 | XCORE_REG_R6, |
| 68 | XCORE_REG_R7, |
| 69 | XCORE_REG_R8, |
| 70 | XCORE_REG_R9, |
| 71 | XCORE_REG_R10, |
| 72 | XCORE_REG_R11, |
| 73 | |
Nguyen Anh Quynh | be2b788 | 2014-05-27 23:34:03 +0800 | [diff] [blame] | 74 | //> pseudo registers |
| 75 | XCORE_REG_PC, // pc |
| 76 | |
| 77 | // internal thread registers |
| 78 | // see The-XMOS-XS1-Architecture(X7879A).pdf |
| 79 | XCORE_REG_SCP, // save pc |
| 80 | XCORE_REG_SSR, // save status |
| 81 | XCORE_REG_ET, // exception type |
| 82 | XCORE_REG_ED, // exception data |
| 83 | XCORE_REG_SED, // save exception data |
| 84 | XCORE_REG_KEP, // kernel entry pointer |
| 85 | XCORE_REG_KSP, // kernel stack pointer |
| 86 | XCORE_REG_ID, // thread ID |
| 87 | |
Nguyen Anh Quynh | d7e42b7 | 2014-09-29 17:15:25 +0800 | [diff] [blame] | 88 | XCORE_REG_ENDING, // <-- mark the end of the list of registers |
Nguyen Anh Quynh | c80d840 | 2014-05-26 23:02:48 +0800 | [diff] [blame] | 89 | } xcore_reg; |
| 90 | |
| 91 | //> XCore instruction |
| 92 | typedef enum xcore_insn { |
| 93 | XCORE_INS_INVALID = 0, |
| 94 | |
| 95 | XCORE_INS_ADD, |
| 96 | XCORE_INS_ANDNOT, |
| 97 | XCORE_INS_AND, |
| 98 | XCORE_INS_ASHR, |
| 99 | XCORE_INS_BAU, |
| 100 | XCORE_INS_BITREV, |
| 101 | XCORE_INS_BLA, |
| 102 | XCORE_INS_BLAT, |
| 103 | XCORE_INS_BL, |
| 104 | XCORE_INS_BF, |
| 105 | XCORE_INS_BT, |
| 106 | XCORE_INS_BU, |
| 107 | XCORE_INS_BRU, |
| 108 | XCORE_INS_BYTEREV, |
| 109 | XCORE_INS_CHKCT, |
| 110 | XCORE_INS_CLRE, |
| 111 | XCORE_INS_CLRPT, |
| 112 | XCORE_INS_CLRSR, |
| 113 | XCORE_INS_CLZ, |
| 114 | XCORE_INS_CRC8, |
| 115 | XCORE_INS_CRC32, |
| 116 | XCORE_INS_DCALL, |
| 117 | XCORE_INS_DENTSP, |
| 118 | XCORE_INS_DGETREG, |
| 119 | XCORE_INS_DIVS, |
| 120 | XCORE_INS_DIVU, |
| 121 | XCORE_INS_DRESTSP, |
| 122 | XCORE_INS_DRET, |
| 123 | XCORE_INS_ECALLF, |
| 124 | XCORE_INS_ECALLT, |
| 125 | XCORE_INS_EDU, |
| 126 | XCORE_INS_EEF, |
| 127 | XCORE_INS_EET, |
| 128 | XCORE_INS_EEU, |
| 129 | XCORE_INS_ENDIN, |
| 130 | XCORE_INS_ENTSP, |
| 131 | XCORE_INS_EQ, |
| 132 | XCORE_INS_EXTDP, |
| 133 | XCORE_INS_EXTSP, |
| 134 | XCORE_INS_FREER, |
| 135 | XCORE_INS_FREET, |
| 136 | XCORE_INS_GETD, |
| 137 | XCORE_INS_GET, |
| 138 | XCORE_INS_GETN, |
| 139 | XCORE_INS_GETR, |
| 140 | XCORE_INS_GETSR, |
| 141 | XCORE_INS_GETST, |
| 142 | XCORE_INS_GETTS, |
| 143 | XCORE_INS_INCT, |
| 144 | XCORE_INS_INIT, |
| 145 | XCORE_INS_INPW, |
| 146 | XCORE_INS_INSHR, |
| 147 | XCORE_INS_INT, |
| 148 | XCORE_INS_IN, |
| 149 | XCORE_INS_KCALL, |
| 150 | XCORE_INS_KENTSP, |
| 151 | XCORE_INS_KRESTSP, |
| 152 | XCORE_INS_KRET, |
| 153 | XCORE_INS_LADD, |
| 154 | XCORE_INS_LD16S, |
| 155 | XCORE_INS_LD8U, |
| 156 | XCORE_INS_LDA16, |
| 157 | XCORE_INS_LDAP, |
| 158 | XCORE_INS_LDAW, |
| 159 | XCORE_INS_LDC, |
| 160 | XCORE_INS_LDW, |
| 161 | XCORE_INS_LDIVU, |
| 162 | XCORE_INS_LMUL, |
| 163 | XCORE_INS_LSS, |
| 164 | XCORE_INS_LSUB, |
| 165 | XCORE_INS_LSU, |
| 166 | XCORE_INS_MACCS, |
| 167 | XCORE_INS_MACCU, |
| 168 | XCORE_INS_MJOIN, |
| 169 | XCORE_INS_MKMSK, |
| 170 | XCORE_INS_MSYNC, |
| 171 | XCORE_INS_MUL, |
| 172 | XCORE_INS_NEG, |
| 173 | XCORE_INS_NOT, |
| 174 | XCORE_INS_OR, |
| 175 | XCORE_INS_OUTCT, |
| 176 | XCORE_INS_OUTPW, |
| 177 | XCORE_INS_OUTSHR, |
| 178 | XCORE_INS_OUTT, |
| 179 | XCORE_INS_OUT, |
| 180 | XCORE_INS_PEEK, |
| 181 | XCORE_INS_REMS, |
| 182 | XCORE_INS_REMU, |
| 183 | XCORE_INS_RETSP, |
| 184 | XCORE_INS_SETCLK, |
| 185 | XCORE_INS_SET, |
| 186 | XCORE_INS_SETC, |
| 187 | XCORE_INS_SETD, |
| 188 | XCORE_INS_SETEV, |
| 189 | XCORE_INS_SETN, |
| 190 | XCORE_INS_SETPSC, |
| 191 | XCORE_INS_SETPT, |
| 192 | XCORE_INS_SETRDY, |
| 193 | XCORE_INS_SETSR, |
| 194 | XCORE_INS_SETTW, |
| 195 | XCORE_INS_SETV, |
| 196 | XCORE_INS_SEXT, |
| 197 | XCORE_INS_SHL, |
| 198 | XCORE_INS_SHR, |
| 199 | XCORE_INS_SSYNC, |
| 200 | XCORE_INS_ST16, |
| 201 | XCORE_INS_ST8, |
| 202 | XCORE_INS_STW, |
| 203 | XCORE_INS_SUB, |
| 204 | XCORE_INS_SYNCR, |
| 205 | XCORE_INS_TESTCT, |
| 206 | XCORE_INS_TESTLCL, |
| 207 | XCORE_INS_TESTWCT, |
| 208 | XCORE_INS_TSETMR, |
| 209 | XCORE_INS_START, |
| 210 | XCORE_INS_WAITEF, |
| 211 | XCORE_INS_WAITET, |
| 212 | XCORE_INS_WAITEU, |
| 213 | XCORE_INS_XOR, |
| 214 | XCORE_INS_ZEXT, |
| 215 | |
Nguyen Anh Quynh | d7e42b7 | 2014-09-29 17:15:25 +0800 | [diff] [blame] | 216 | XCORE_INS_ENDING, // <-- mark the end of the list of instructions |
Nguyen Anh Quynh | c80d840 | 2014-05-26 23:02:48 +0800 | [diff] [blame] | 217 | } xcore_insn; |
| 218 | |
| 219 | //> Group of XCore instructions |
| 220 | typedef enum xcore_insn_group { |
Nguyen Anh Quynh | 3ab5091 | 2014-10-31 14:40:45 +0800 | [diff] [blame] | 221 | XCORE_GRP_INVALID = 0, // = CS_GRP_INVALID |
Nguyen Anh Quynh | c80d840 | 2014-05-26 23:02:48 +0800 | [diff] [blame] | 222 | |
Nguyen Anh Quynh | 3ab5091 | 2014-10-31 14:40:45 +0800 | [diff] [blame] | 223 | //> Generic groups |
| 224 | // all jump instructions (conditional+direct+indirect jumps) |
| 225 | XCORE_GRP_JUMP, // = CS_GRP_JUMP |
Nguyen Anh Quynh | c80d840 | 2014-05-26 23:02:48 +0800 | [diff] [blame] | 226 | |
Nguyen Anh Quynh | d7e42b7 | 2014-09-29 17:15:25 +0800 | [diff] [blame] | 227 | XCORE_GRP_ENDING, // <-- mark the end of the list of groups |
Nguyen Anh Quynh | c80d840 | 2014-05-26 23:02:48 +0800 | [diff] [blame] | 228 | } xcore_insn_group; |
| 229 | |
| 230 | #ifdef __cplusplus |
| 231 | } |
| 232 | #endif |
| 233 | |
| 234 | #endif |