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Guillaume Chatelet439d3712018-02-01 10:03:09 +01001// Copyright 2017 Google Inc.
2//
3// Licensed under the Apache License, Version 2.0 (the "License");
4// you may not use this file except in compliance with the License.
5// You may obtain a copy of the License at
6//
7// http://www.apache.org/licenses/LICENSE-2.0
8//
9// Unless required by applicable law or agreed to in writing, software
10// distributed under the License is distributed on an "AS IS" BASIS,
11// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12// See the License for the specific language governing permissions and
13// limitations under the License.
14
Guillaume Chatelet8e58ef02018-02-01 10:38:48 +010015#ifndef CPU_FEATURES_INCLUDE_CPUINFO_X86_H_
16#define CPU_FEATURES_INCLUDE_CPUINFO_X86_H_
Guillaume Chatelet439d3712018-02-01 10:03:09 +010017
Artem Alekseev653d5812019-07-02 17:52:25 +030018#include "cpu_features_cache_info.h"
Guillaume Chatelet439d3712018-02-01 10:03:09 +010019#include "cpu_features_macros.h"
20
Guillaume Chatelete4195732018-02-12 16:15:15 +010021CPU_FEATURES_START_CPP_NAMESPACE
Guillaume Chatelet439d3712018-02-01 10:03:09 +010022
23// See https://en.wikipedia.org/wiki/CPUID for a list of x86 cpu features.
Guillaume Chateletd395dfa2019-01-22 13:19:42 +010024// The field names are based on the short name provided in the wikipedia tables.
Guillaume Chatelet439d3712018-02-01 10:03:09 +010025typedef struct {
Dr.-Ing. Patrick Siegl367bc422019-06-13 11:53:39 +020026 int fpu : 1;
27 int tsc : 1;
28 int cx8 : 1;
29 int clfsh : 1;
30 int mmx : 1;
Guillaume Chatelet439d3712018-02-01 10:03:09 +010031 int aes : 1;
32 int erms : 1;
33 int f16c : 1;
34 int fma3 : 1;
Dr.-Ing. Patrick Siegl367bc422019-06-13 11:53:39 +020035 int vaes : 1;
Guillaume Chatelet11e3e202018-02-09 08:55:11 +010036 int vpclmulqdq : 1;
Guillaume Chatelet439d3712018-02-01 10:03:09 +010037 int bmi1 : 1;
Dr.-Ing. Patrick Siegl367bc422019-06-13 11:53:39 +020038 int hle : 1;
Guillaume Chatelet439d3712018-02-01 10:03:09 +010039 int bmi2 : 1;
Dr.-Ing. Patrick Siegl367bc422019-06-13 11:53:39 +020040 int rtm : 1;
41 int rdseed : 1;
42 int clflushopt : 1;
43 int clwb : 1;
Guillaume Chatelet439d3712018-02-01 10:03:09 +010044
Dr.-Ing. Patrick Siegl367bc422019-06-13 11:53:39 +020045 int sse : 1;
46 int sse2 : 1;
47 int sse3 : 1;
Guillaume Chatelet439d3712018-02-01 10:03:09 +010048 int ssse3 : 1;
49 int sse4_1 : 1;
50 int sse4_2 : 1;
51
52 int avx : 1;
53 int avx2 : 1;
54
55 int avx512f : 1;
56 int avx512cd : 1;
57 int avx512er : 1;
58 int avx512pf : 1;
59 int avx512bw : 1;
60 int avx512dq : 1;
61 int avx512vl : 1;
62 int avx512ifma : 1;
63 int avx512vbmi : 1;
64 int avx512vbmi2 : 1;
65 int avx512vnni : 1;
66 int avx512bitalg : 1;
67 int avx512vpopcntdq : 1;
68 int avx512_4vnniw : 1;
69 int avx512_4vbmi2 : 1;
70
Dr.-Ing. Patrick Siegl367bc422019-06-13 11:53:39 +020071 int pclmulqdq : 1;
Patrik Fiedler3ee0d622018-02-13 11:14:32 +010072 int smx : 1;
73 int sgx : 1;
Guillaume Chatelet9b872ce2018-03-13 10:58:42 +010074 int cx16 : 1; // aka. CMPXCHG16B
Guillaume Chateletd395dfa2019-01-22 13:19:42 +010075 int sha : 1;
76 int popcnt : 1;
77 int movbe : 1;
78 int rdrnd : 1;
Patrik Fiedler3ee0d622018-02-13 11:14:32 +010079
Artem Alekseev3ee4a9e2019-06-19 16:06:05 +030080 int dca : 1;
81 int ss : 1;
Guillaume Chatelet439d3712018-02-01 10:03:09 +010082 // Make sure to update X86FeaturesEnum below if you add a field here.
83} X86Features;
84
85typedef struct {
86 X86Features features;
87 int family;
88 int model;
89 int stepping;
90 char vendor[13]; // 0 terminated string
91} X86Info;
92
93// Calls cpuid and returns an initialized X86info.
94// This function is guaranteed to be malloc, memset and memcpy free.
95X86Info GetX86Info(void);
96
Artem Alekseev653d5812019-07-02 17:52:25 +030097// Returns cache hierarchy informations.
98// Can call cpuid multiple times.
99// Only works on Intel CPU at the moment.
100// This function is guaranteed to be malloc, memset and memcpy free.
101CacheInfo GetX86CacheInfo(void);
102
Guillaume Chatelet439d3712018-02-01 10:03:09 +0100103typedef enum {
104 X86_UNKNOWN,
105 INTEL_CORE, // CORE
106 INTEL_PNR, // PENRYN
107 INTEL_NHM, // NEHALEM
108 INTEL_ATOM_BNL, // BONNELL
109 INTEL_WSM, // WESTMERE
110 INTEL_SNB, // SANDYBRIDGE
111 INTEL_IVB, // IVYBRIDGE
112 INTEL_ATOM_SMT, // SILVERMONT
113 INTEL_HSW, // HASWELL
114 INTEL_BDW, // BROADWELL
115 INTEL_SKL, // SKYLAKE
116 INTEL_ATOM_GMT, // GOLDMONT
117 INTEL_KBL, // KABY LAKE
118 INTEL_CFL, // COFFEE LAKE
Brandon Surmanskiefcc49a2018-02-07 11:07:00 -0800119 INTEL_CNL, // CANNON LAKE
Guillaume Chatelet439d3712018-02-01 10:03:09 +0100120 AMD_HAMMER, // K8
121 AMD_K10, // K10
122 AMD_BOBCAT, // K14
123 AMD_BULLDOZER, // K15
124 AMD_JAGUAR, // K16
125 AMD_ZEN, // K17
126} X86Microarchitecture;
127
128// Returns the underlying microarchitecture by looking at X86Info's vendor,
129// family and model.
130X86Microarchitecture GetX86Microarchitecture(const X86Info* info);
131
132// Calls cpuid and fills the brand_string.
133// - brand_string *must* be of size 49 (beware of array decaying).
134// - brand_string will be zero terminated.
135// - This function calls memcpy.
136void FillX86BrandString(char brand_string[49]);
137
138////////////////////////////////////////////////////////////////////////////////
139// Introspection functions
140
141typedef enum {
Dr.-Ing. Patrick Siegl367bc422019-06-13 11:53:39 +0200142 X86_FPU,
143 X86_TSC,
144 X86_CX8,
145 X86_CLFSH,
146 X86_MMX,
Guillaume Chatelet439d3712018-02-01 10:03:09 +0100147 X86_AES,
148 X86_ERMS,
149 X86_F16C,
150 X86_FMA3,
Dr.-Ing. Patrick Siegl367bc422019-06-13 11:53:39 +0200151 X86_VAES,
Guillaume Chatelet11e3e202018-02-09 08:55:11 +0100152 X86_VPCLMULQDQ,
Guillaume Chatelet439d3712018-02-01 10:03:09 +0100153 X86_BMI1,
Dr.-Ing. Patrick Siegl367bc422019-06-13 11:53:39 +0200154 X86_HLE,
Guillaume Chatelet439d3712018-02-01 10:03:09 +0100155 X86_BMI2,
Dr.-Ing. Patrick Siegl367bc422019-06-13 11:53:39 +0200156 X86_RTM,
157 X86_RDSEED,
158 X86_CLFLUSHOPT,
159 X86_CLWB,
160 X86_SSE,
161 X86_SSE2,
162 X86_SSE3,
Guillaume Chatelet439d3712018-02-01 10:03:09 +0100163 X86_SSSE3,
164 X86_SSE4_1,
165 X86_SSE4_2,
166 X86_AVX,
167 X86_AVX2,
168 X86_AVX512F,
169 X86_AVX512CD,
170 X86_AVX512ER,
171 X86_AVX512PF,
172 X86_AVX512BW,
173 X86_AVX512DQ,
174 X86_AVX512VL,
175 X86_AVX512IFMA,
176 X86_AVX512VBMI,
177 X86_AVX512VBMI2,
178 X86_AVX512VNNI,
179 X86_AVX512BITALG,
180 X86_AVX512VPOPCNTDQ,
181 X86_AVX512_4VNNIW,
182 X86_AVX512_4VBMI2,
Dr.-Ing. Patrick Siegl367bc422019-06-13 11:53:39 +0200183 X86_PCLMULQDQ,
Patrik Fiedler3ee0d622018-02-13 11:14:32 +0100184 X86_SMX,
185 X86_SGX,
Guillaume Chatelet9b872ce2018-03-13 10:58:42 +0100186 X86_CX16,
Guillaume Chateletd395dfa2019-01-22 13:19:42 +0100187 X86_SHA,
188 X86_POPCNT,
189 X86_MOVBE,
190 X86_RDRND,
Artem Alekseev3ee4a9e2019-06-19 16:06:05 +0300191 X86_DCA,
192 X86_SS,
Guillaume Chatelet439d3712018-02-01 10:03:09 +0100193 X86_LAST_,
194} X86FeaturesEnum;
195
196int GetX86FeaturesEnumValue(const X86Features* features, X86FeaturesEnum value);
197
198const char* GetX86FeaturesEnumName(X86FeaturesEnum);
199
200const char* GetX86MicroarchitectureName(X86Microarchitecture);
201
Guillaume Chatelete4195732018-02-12 16:15:15 +0100202CPU_FEATURES_END_CPP_NAMESPACE
Guillaume Chatelet439d3712018-02-01 10:03:09 +0100203
Guillaume Chatelet4155ee72019-01-18 13:38:22 +0100204#if !defined(CPU_FEATURES_ARCH_X86)
205#error "Including cpuinfo_x86.h from a non-x86 target."
206#endif
207
Guillaume Chatelet8e58ef02018-02-01 10:38:48 +0100208#endif // CPU_FEATURES_INCLUDE_CPUINFO_X86_H_