blob: f307a9576d9f9a3d2c5f3e8ce60630e7d664b482 [file] [log] [blame]
Marat Dukhan7be11402017-11-27 14:57:02 -08001#include <gtest/gtest.h>
2
3#include <cpuinfo.h>
4#include <cpuinfo-mock.h>
5
6
7TEST(PROCESSORS, count) {
8 ASSERT_EQ(8, cpuinfo_get_processors_count());
9}
10
11TEST(PROCESSORS, non_null) {
12 ASSERT_TRUE(cpuinfo_get_processors());
13}
14
15TEST(PROCESSORS, smt_id) {
16 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
17 ASSERT_EQ(0, cpuinfo_get_processor(i)->smt_id);
18 }
19}
20
21TEST(PROCESSORS, core) {
22 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
23 ASSERT_EQ(cpuinfo_get_core(i), cpuinfo_get_processor(i)->core);
24 }
25}
26
Marat Dukhan2b307932018-03-18 16:15:36 -070027TEST(PROCESSORS, cluster) {
28 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
29 switch (i) {
30 case 0:
31 case 1:
32 case 2:
33 case 3:
34 ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_processor(i)->cluster);
35 break;
36 case 4:
37 case 5:
38 case 6:
39 case 7:
40 ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_processor(i)->cluster);
41 break;
42 }
43 }
44}
45
Marat Dukhan7be11402017-11-27 14:57:02 -080046TEST(PROCESSORS, package) {
47 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
48 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_processor(i)->package);
49 }
50}
51
52TEST(PROCESSORS, linux_id) {
53 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
54 switch (i) {
55 case 0:
56 case 1:
57 case 2:
58 case 3:
59 ASSERT_EQ(i + 4, cpuinfo_get_processor(i)->linux_id);
60 break;
61 case 4:
62 case 5:
63 case 6:
64 case 7:
65 ASSERT_EQ(i - 4, cpuinfo_get_processor(i)->linux_id);
66 break;
67 }
68 }
69}
70
71TEST(PROCESSORS, l1i) {
72 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
73 ASSERT_EQ(cpuinfo_get_l1i_cache(i), cpuinfo_get_processor(i)->cache.l1i);
74 }
75}
76
77TEST(PROCESSORS, l1d) {
78 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
79 ASSERT_EQ(cpuinfo_get_l1d_cache(i), cpuinfo_get_processor(i)->cache.l1d);
80 }
81}
82
83TEST(PROCESSORS, l2) {
84 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
85 switch (i) {
86 case 0:
87 case 1:
88 case 2:
89 case 3:
90 ASSERT_EQ(cpuinfo_get_l2_cache(0), cpuinfo_get_processor(i)->cache.l2);
91 break;
92 case 4:
93 case 5:
94 case 6:
95 case 7:
96 ASSERT_EQ(cpuinfo_get_l2_cache(1), cpuinfo_get_processor(i)->cache.l2);
97 break;
98 }
99 }
100}
101
102TEST(PROCESSORS, l3) {
103 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
104 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l3);
105 }
106}
107
108TEST(PROCESSORS, l4) {
109 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
110 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l4);
111 }
112}
113
114TEST(CORES, count) {
115 ASSERT_EQ(8, cpuinfo_get_cores_count());
116}
117
118TEST(CORES, non_null) {
119 ASSERT_TRUE(cpuinfo_get_cores());
120}
121
122TEST(CORES, processor_start) {
123 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
124 ASSERT_EQ(i, cpuinfo_get_core(i)->processor_start);
125 }
126}
127
128TEST(CORES, processor_count) {
129 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
130 ASSERT_EQ(1, cpuinfo_get_core(i)->processor_count);
131 }
132}
133
134TEST(CORES, core_id) {
135 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
136 ASSERT_EQ(i, cpuinfo_get_core(i)->core_id);
137 }
138}
139
Marat Dukhan2b307932018-03-18 16:15:36 -0700140TEST(CORES, cluster) {
141 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
142 switch (i) {
143 case 0:
144 case 1:
145 case 2:
146 case 3:
147 ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_core(i)->cluster);
148 break;
149 case 4:
150 case 5:
151 case 6:
152 case 7:
153 ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_core(i)->cluster);
154 break;
155 }
156 }
157}
158
Marat Dukhan7be11402017-11-27 14:57:02 -0800159TEST(CORES, package) {
160 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
161 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_core(i)->package);
162 }
163}
164
165TEST(CORES, vendor) {
166 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
167 ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_core(i)->vendor);
168 }
169}
170
171TEST(CORES, uarch) {
172 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
173 switch (i) {
174 case 0:
175 case 1:
176 case 2:
177 case 3:
178 ASSERT_EQ(cpuinfo_uarch_cortex_a73, cpuinfo_get_core(i)->uarch);
179 break;
180 case 4:
181 case 5:
182 case 6:
183 case 7:
184 ASSERT_EQ(cpuinfo_uarch_cortex_a53, cpuinfo_get_core(i)->uarch);
185 break;
186 }
187 }
188}
189
190TEST(CORES, midr) {
191 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
192 switch (i) {
193 case 0:
194 case 1:
195 case 2:
196 case 3:
197 ASSERT_EQ(UINT32_C(0x410FD092), cpuinfo_get_core(i)->midr);
198 break;
199 case 4:
200 case 5:
201 case 6:
202 case 7:
203 ASSERT_EQ(UINT32_C(0x410FD034), cpuinfo_get_core(i)->midr);
204 break;
205 }
206 }
207}
208
Marat Dukhan575a6302018-03-10 14:38:49 -0800209TEST(CORES, DISABLED_frequency) {
210 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
211 switch (i) {
212 case 0:
213 case 1:
214 case 2:
215 case 3:
216 ASSERT_EQ(UINT64_C(2362000000), cpuinfo_get_core(i)->frequency);
217 break;
218 case 4:
219 case 5:
220 case 6:
221 case 7:
222 ASSERT_EQ(UINT64_C(1844000000), cpuinfo_get_core(i)->frequency);
223 break;
224 }
225 }
226}
227
Marat Dukhan7be11402017-11-27 14:57:02 -0800228TEST(PACKAGES, count) {
229 ASSERT_EQ(1, cpuinfo_get_packages_count());
230}
231
232TEST(PACKAGES, name) {
233 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
234 ASSERT_EQ("HiSilicon Kirin 970",
235 std::string(cpuinfo_get_package(i)->name,
236 strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX)));
237 }
238}
239
Marat Dukhanfd0f3ef2017-12-18 17:45:18 -0800240TEST(PACKAGES, gpu_name) {
241 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
242 ASSERT_EQ("ARM Mali-G72",
243 std::string(cpuinfo_get_package(i)->gpu_name,
244 strnlen(cpuinfo_get_package(i)->gpu_name, CPUINFO_GPU_NAME_MAX)));
245 }
246}
247
Marat Dukhan7be11402017-11-27 14:57:02 -0800248TEST(PACKAGES, processor_start) {
249 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
250 ASSERT_EQ(0, cpuinfo_get_package(i)->processor_start);
251 }
252}
253
254TEST(PACKAGES, processor_count) {
255 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
256 ASSERT_EQ(8, cpuinfo_get_package(i)->processor_count);
257 }
258}
259
260TEST(PACKAGES, core_start) {
261 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
262 ASSERT_EQ(0, cpuinfo_get_package(i)->core_start);
263 }
264}
265
266TEST(PACKAGES, core_count) {
267 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
268 ASSERT_EQ(8, cpuinfo_get_package(i)->core_count);
269 }
270}
271
Marat Dukhan2b307932018-03-18 16:15:36 -0700272TEST(PACKAGES, cluster_start) {
273 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
274 ASSERT_EQ(0, cpuinfo_get_package(i)->cluster_start);
275 }
276}
277
278TEST(PACKAGES, cluster_count) {
279 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
280 ASSERT_EQ(2, cpuinfo_get_package(i)->cluster_count);
281 }
282}
283
Marat Dukhan7be11402017-11-27 14:57:02 -0800284TEST(ISA, thumb) {
285 #if CPUINFO_ARCH_ARM
286 ASSERT_TRUE(cpuinfo_has_arm_thumb());
287 #elif CPUINFO_ARCH_ARM64
288 ASSERT_FALSE(cpuinfo_has_arm_thumb());
289 #endif
290}
291
292TEST(ISA, thumb2) {
293 #if CPUINFO_ARCH_ARM
294 ASSERT_TRUE(cpuinfo_has_arm_thumb2());
295 #elif CPUINFO_ARCH_ARM64
296 ASSERT_FALSE(cpuinfo_has_arm_thumb2());
297 #endif
298}
299
300TEST(ISA, armv5e) {
301 #if CPUINFO_ARCH_ARM
302 ASSERT_TRUE(cpuinfo_has_arm_v5e());
303 #elif CPUINFO_ARCH_ARM64
304 ASSERT_FALSE(cpuinfo_has_arm_v5e());
305 #endif
306}
307
308TEST(ISA, armv6) {
309 #if CPUINFO_ARCH_ARM
310 ASSERT_TRUE(cpuinfo_has_arm_v6());
311 #elif CPUINFO_ARCH_ARM64
312 ASSERT_FALSE(cpuinfo_has_arm_v6());
313 #endif
314}
315
316TEST(ISA, armv6k) {
317 #if CPUINFO_ARCH_ARM
318 ASSERT_TRUE(cpuinfo_has_arm_v6k());
319 #elif CPUINFO_ARCH_ARM64
320 ASSERT_FALSE(cpuinfo_has_arm_v6k());
321 #endif
322}
323
324TEST(ISA, armv7) {
325 #if CPUINFO_ARCH_ARM
326 ASSERT_TRUE(cpuinfo_has_arm_v7());
327 #elif CPUINFO_ARCH_ARM64
328 ASSERT_FALSE(cpuinfo_has_arm_v7());
329 #endif
330}
331
332TEST(ISA, armv7mp) {
333 #if CPUINFO_ARCH_ARM
334 ASSERT_TRUE(cpuinfo_has_arm_v7mp());
335 #elif CPUINFO_ARCH_ARM64
336 ASSERT_FALSE(cpuinfo_has_arm_v7mp());
337 #endif
338}
339
340TEST(ISA, idiv) {
341 ASSERT_TRUE(cpuinfo_has_arm_idiv());
342}
343
344TEST(ISA, vfpv2) {
345 ASSERT_FALSE(cpuinfo_has_arm_vfpv2());
346}
347
348TEST(ISA, vfpv3) {
349 ASSERT_TRUE(cpuinfo_has_arm_vfpv3());
350}
351
352TEST(ISA, vfpv3_d32) {
353 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_d32());
354}
355
356TEST(ISA, vfpv3_fp16) {
357 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16());
358}
359
360TEST(ISA, vfpv3_fp16_d32) {
361 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16_d32());
362}
363
364TEST(ISA, vfpv4) {
365 ASSERT_TRUE(cpuinfo_has_arm_vfpv4());
366}
367
368TEST(ISA, vfpv4_d32) {
369 ASSERT_TRUE(cpuinfo_has_arm_vfpv4_d32());
370}
371
372TEST(ISA, wmmx) {
373 ASSERT_FALSE(cpuinfo_has_arm_wmmx());
374}
375
376TEST(ISA, wmmx2) {
377 ASSERT_FALSE(cpuinfo_has_arm_wmmx2());
378}
379
380TEST(ISA, neon) {
381 ASSERT_TRUE(cpuinfo_has_arm_neon());
382}
383
384TEST(ISA, neon_fp16) {
385 ASSERT_TRUE(cpuinfo_has_arm_neon_fp16());
386}
387
388TEST(ISA, neon_fma) {
389 ASSERT_TRUE(cpuinfo_has_arm_neon_fma());
390}
391
392TEST(ISA, atomics) {
393 ASSERT_FALSE(cpuinfo_has_arm_atomics());
394}
395
396TEST(ISA, neon_rdm) {
397 ASSERT_FALSE(cpuinfo_has_arm_neon_rdm());
398}
399
400TEST(ISA, fp16_arith) {
401 ASSERT_FALSE(cpuinfo_has_arm_fp16_arith());
402}
403
404TEST(ISA, jscvt) {
405 ASSERT_FALSE(cpuinfo_has_arm_jscvt());
406}
407
408TEST(ISA, fcma) {
409 ASSERT_FALSE(cpuinfo_has_arm_fcma());
410}
411
412TEST(ISA, aes) {
413 ASSERT_TRUE(cpuinfo_has_arm_aes());
414}
415
416TEST(ISA, sha1) {
417 ASSERT_TRUE(cpuinfo_has_arm_sha1());
418}
419
420TEST(ISA, sha2) {
421 ASSERT_TRUE(cpuinfo_has_arm_sha2());
422}
423
424TEST(ISA, pmull) {
425 ASSERT_TRUE(cpuinfo_has_arm_pmull());
426}
427
428TEST(ISA, crc32) {
429 ASSERT_TRUE(cpuinfo_has_arm_crc32());
430}
431
432TEST(L1I, count) {
433 ASSERT_EQ(8, cpuinfo_get_l1i_caches_count());
434}
435
436TEST(L1I, non_null) {
437 ASSERT_TRUE(cpuinfo_get_l1i_caches());
438}
439
440TEST(L1I, size) {
441 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
442 switch (i) {
443 case 0:
444 case 1:
445 case 2:
446 case 3:
447 ASSERT_EQ(64 * 1024, cpuinfo_get_l1i_cache(i)->size);
448 break;
449 case 4:
450 case 5:
451 case 6:
452 case 7:
453 ASSERT_EQ(32 * 1024, cpuinfo_get_l1i_cache(i)->size);
454 break;
455 }
456 }
457}
458
459TEST(L1I, associativity) {
460 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
461 switch (i) {
462 case 0:
463 case 1:
464 case 2:
465 case 3:
466 ASSERT_EQ(4, cpuinfo_get_l1i_cache(i)->associativity);
467 break;
468 case 4:
469 case 5:
470 case 6:
471 case 7:
472 ASSERT_EQ(2, cpuinfo_get_l1i_cache(i)->associativity);
473 break;
474 }
475 }
476}
477
478TEST(L1I, sets) {
479 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
480 ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size,
481 cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity);
482 }
483}
484
485TEST(L1I, partitions) {
486 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
487 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->partitions);
488 }
489}
490
491TEST(L1I, line_size) {
492 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
493 ASSERT_EQ(64, cpuinfo_get_l1i_cache(i)->line_size);
494 }
495}
496
497TEST(L1I, flags) {
498 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
499 ASSERT_EQ(0, cpuinfo_get_l1i_cache(i)->flags);
500 }
501}
502
503TEST(L1I, processors) {
504 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
505 ASSERT_EQ(i, cpuinfo_get_l1i_cache(i)->processor_start);
506 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->processor_count);
507 }
508}
509
510TEST(L1D, count) {
511 ASSERT_EQ(8, cpuinfo_get_l1d_caches_count());
512}
513
514TEST(L1D, non_null) {
515 ASSERT_TRUE(cpuinfo_get_l1d_caches());
516}
517
518TEST(L1D, size) {
519 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
520 switch (i) {
521 case 0:
522 case 1:
523 case 2:
524 case 3:
525 ASSERT_EQ(64 * 1024, cpuinfo_get_l1d_cache(i)->size);
526 break;
527 case 4:
528 case 5:
529 case 6:
530 case 7:
531 ASSERT_EQ(32 * 1024, cpuinfo_get_l1d_cache(i)->size);
532 break;
533 }
534 }
535}
536
537TEST(L1D, associativity) {
538 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
539 switch (i) {
540 case 0:
541 case 1:
542 case 2:
543 case 3:
544 ASSERT_EQ(16, cpuinfo_get_l1d_cache(i)->associativity);
545 break;
546 case 4:
547 case 5:
548 case 6:
549 case 7:
550 ASSERT_EQ(4, cpuinfo_get_l1d_cache(i)->associativity);
551 break;
552 }
553 }
554}
555
556TEST(L1D, sets) {
557 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
558 ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size,
559 cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity);
560 }
561}
562
563TEST(L1D, partitions) {
564 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
565 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->partitions);
566 }
567}
568
569TEST(L1D, line_size) {
570 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
571 ASSERT_EQ(64, cpuinfo_get_l1d_cache(i)->line_size);
572 }
573}
574
575TEST(L1D, flags) {
576 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
577 ASSERT_EQ(0, cpuinfo_get_l1d_cache(i)->flags);
578 }
579}
580
581TEST(L1D, processors) {
582 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
583 ASSERT_EQ(i, cpuinfo_get_l1d_cache(i)->processor_start);
584 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->processor_count);
585 }
586}
587
588TEST(L2, count) {
589 ASSERT_EQ(2, cpuinfo_get_l2_caches_count());
590}
591
592TEST(L2, non_null) {
593 ASSERT_TRUE(cpuinfo_get_l2_caches());
594}
595
596TEST(L2, size) {
597 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
598 switch (i) {
599 case 0:
600 ASSERT_EQ(2 * 1024 * 1024, cpuinfo_get_l2_cache(i)->size);
601 break;
602 case 1:
603 ASSERT_EQ(1024 * 1024, cpuinfo_get_l2_cache(i)->size);
604 break;
605 }
606 }
607}
608
609TEST(L2, associativity) {
610 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
611 ASSERT_EQ(16, cpuinfo_get_l2_cache(i)->associativity);
612 }
613}
614
615TEST(L2, sets) {
616 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
617 ASSERT_EQ(cpuinfo_get_l2_cache(i)->size,
618 cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity);
619 }
620}
621
622TEST(L2, partitions) {
623 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
624 ASSERT_EQ(1, cpuinfo_get_l2_cache(i)->partitions);
625 }
626}
627
628TEST(L2, line_size) {
629 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
630 ASSERT_EQ(64, cpuinfo_get_l2_cache(i)->line_size);
631 }
632}
633
634TEST(L2, flags) {
635 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
636 switch (i) {
637 case 0:
638 ASSERT_EQ(CPUINFO_CACHE_INCLUSIVE, cpuinfo_get_l2_cache(i)->flags);
639 break;
640 case 1:
641 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->flags);
642 break;
643 }
644 }
645}
646
647TEST(L2, processors) {
648 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
649 switch (i) {
650 case 0:
651 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->processor_start);
652 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_count);
653 break;
654 case 1:
655 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_start);
656 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_count);
657 break;
658 }
659 }
660}
661
662TEST(L3, none) {
663 ASSERT_EQ(0, cpuinfo_get_l3_caches_count());
664 ASSERT_FALSE(cpuinfo_get_l3_caches());
665}
666
667TEST(L4, none) {
668 ASSERT_EQ(0, cpuinfo_get_l4_caches_count());
669 ASSERT_FALSE(cpuinfo_get_l4_caches());
670}
671
672#include <huawei-mate-10.h>
673
674int main(int argc, char* argv[]) {
Marat Dukhan63a7a6b2017-11-29 15:11:56 -0800675#if CPUINFO_ARCH_ARM
676 cpuinfo_set_hwcap(UINT32_C(0x0037B0D6));
677 cpuinfo_set_hwcap2(UINT32_C(0x0000001F));
678#elif CPUINFO_ARCH_ARM64
679 cpuinfo_set_hwcap(UINT32_C(0x000000FF));
680#endif
Marat Dukhan7be11402017-11-27 14:57:02 -0800681 cpuinfo_mock_filesystem(filesystem);
682#ifdef __ANDROID__
683 cpuinfo_mock_android_properties(properties);
Marat Dukhanfd0f3ef2017-12-18 17:45:18 -0800684 cpuinfo_mock_gl_renderer("Mali-G72");
Marat Dukhan7be11402017-11-27 14:57:02 -0800685#endif
686 cpuinfo_initialize();
687 ::testing::InitGoogleTest(&argc, argv);
688 return RUN_ALL_TESTS();
689}