blob: 897b7ace789c3e8e5417a174cb936e9c86001e7c [file] [log] [blame]
Marat Dukhane3ee90d2017-09-25 23:23:05 -07001#include <gtest/gtest.h>
2
3#include <cpuinfo.h>
4#include <cpuinfo-mock.h>
5
6
7TEST(PROCESSORS, count) {
Marat Dukhan30401972017-09-26 18:35:52 -07008 ASSERT_EQ(4, cpuinfo_get_processors_count());
Marat Dukhane3ee90d2017-09-25 23:23:05 -07009}
10
11TEST(PROCESSORS, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -070012 ASSERT_TRUE(cpuinfo_get_processors());
Marat Dukhane3ee90d2017-09-25 23:23:05 -070013}
14
15TEST(PROCESSORS, smt_id) {
Marat Dukhan30401972017-09-26 18:35:52 -070016 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
17 ASSERT_EQ(0, cpuinfo_get_processor(i)->smt_id);
Marat Dukhane3ee90d2017-09-25 23:23:05 -070018 }
19}
20
21TEST(PROCESSORS, core) {
Marat Dukhan30401972017-09-26 18:35:52 -070022 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
23 ASSERT_EQ(cpuinfo_get_core(i), cpuinfo_get_processor(i)->core);
Marat Dukhane3ee90d2017-09-25 23:23:05 -070024 }
25}
26
27TEST(PROCESSORS, package) {
Marat Dukhan30401972017-09-26 18:35:52 -070028 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
29 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_processor(i)->package);
Marat Dukhane3ee90d2017-09-25 23:23:05 -070030 }
31}
32
33TEST(PROCESSORS, linux_id) {
Marat Dukhan30401972017-09-26 18:35:52 -070034 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
35 ASSERT_EQ(i, cpuinfo_get_processor(i)->linux_id);
Marat Dukhane3ee90d2017-09-25 23:23:05 -070036 }
37}
38
39TEST(PROCESSORS, l1i) {
Marat Dukhan30401972017-09-26 18:35:52 -070040 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
41 ASSERT_EQ(cpuinfo_get_l1i_cache(i), cpuinfo_get_processor(i)->cache.l1i);
Marat Dukhane3ee90d2017-09-25 23:23:05 -070042 }
43}
44
45TEST(PROCESSORS, l1d) {
Marat Dukhan30401972017-09-26 18:35:52 -070046 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
47 ASSERT_EQ(cpuinfo_get_l1d_cache(i), cpuinfo_get_processor(i)->cache.l1d);
Marat Dukhane3ee90d2017-09-25 23:23:05 -070048 }
49}
50
51TEST(PROCESSORS, l2) {
Marat Dukhan30401972017-09-26 18:35:52 -070052 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
53 ASSERT_EQ(cpuinfo_get_l2_cache(i / 2), cpuinfo_get_processor(i)->cache.l2);
Marat Dukhane3ee90d2017-09-25 23:23:05 -070054 }
55}
56
57TEST(PROCESSORS, l3) {
Marat Dukhan30401972017-09-26 18:35:52 -070058 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
59 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l3);
Marat Dukhane3ee90d2017-09-25 23:23:05 -070060 }
61}
62
63TEST(PROCESSORS, l4) {
Marat Dukhan30401972017-09-26 18:35:52 -070064 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
65 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l4);
Marat Dukhane3ee90d2017-09-25 23:23:05 -070066 }
67}
68
69TEST(CORES, count) {
Marat Dukhan30401972017-09-26 18:35:52 -070070 ASSERT_EQ(4, cpuinfo_get_cores_count());
Marat Dukhane3ee90d2017-09-25 23:23:05 -070071}
72
73TEST(CORES, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -070074 ASSERT_TRUE(cpuinfo_get_cores());
Marat Dukhane3ee90d2017-09-25 23:23:05 -070075}
76
77TEST(CORES, processor_start) {
Marat Dukhan30401972017-09-26 18:35:52 -070078 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
79 ASSERT_EQ(i, cpuinfo_get_core(i)->processor_start);
Marat Dukhane3ee90d2017-09-25 23:23:05 -070080 }
81}
82
83TEST(CORES, processor_count) {
Marat Dukhan30401972017-09-26 18:35:52 -070084 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
85 ASSERT_EQ(1, cpuinfo_get_core(i)->processor_count);
Marat Dukhane3ee90d2017-09-25 23:23:05 -070086 }
87}
88
89TEST(CORES, core_id) {
Marat Dukhan30401972017-09-26 18:35:52 -070090 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
91 ASSERT_EQ(i, cpuinfo_get_core(i)->core_id);
Marat Dukhane3ee90d2017-09-25 23:23:05 -070092 }
93}
94
95TEST(CORES, package) {
Marat Dukhan30401972017-09-26 18:35:52 -070096 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
97 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_core(i)->package);
Marat Dukhane3ee90d2017-09-25 23:23:05 -070098 }
99}
100
101TEST(CORES, vendor) {
Marat Dukhan30401972017-09-26 18:35:52 -0700102 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
103 ASSERT_EQ(cpuinfo_vendor_intel, cpuinfo_get_core(i)->vendor);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700104 }
105}
106
107TEST(CORES, uarch) {
Marat Dukhan30401972017-09-26 18:35:52 -0700108 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
109 ASSERT_EQ(cpuinfo_uarch_silvermont, cpuinfo_get_core(i)->uarch);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700110 }
111}
112
113TEST(CORES, cpuid) {
Marat Dukhan30401972017-09-26 18:35:52 -0700114 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
115 ASSERT_EQ(UINT32_C(0x00030678), cpuinfo_get_core(i)->cpuid);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700116 }
117}
118
Marat Dukhan575a6302018-03-10 14:38:49 -0800119TEST(CORES, DISABLED_frequency) {
120 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
121 ASSERT_EQ(UINT64_C(1862000000), cpuinfo_get_core(i)->frequency);
122 }
123}
124
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700125TEST(PACKAGES, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700126 ASSERT_EQ(1, cpuinfo_get_packages_count());
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700127}
128
129TEST(PACKAGES, name) {
Marat Dukhan30401972017-09-26 18:35:52 -0700130 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
Marat Dukhanba208d12018-03-11 15:30:40 -0700131 ASSERT_EQ("Intel Atom Z3745",
Marat Dukhan30401972017-09-26 18:35:52 -0700132 std::string(cpuinfo_get_package(i)->name,
133 strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX)));
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700134 }
135}
136
Marat Dukhanfd0f3ef2017-12-18 17:45:18 -0800137TEST(PACKAGES, gpu_name) {
138 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
139 ASSERT_EQ("Intel Gen 7",
140 std::string(cpuinfo_get_package(i)->gpu_name,
141 strnlen(cpuinfo_get_package(i)->gpu_name, CPUINFO_GPU_NAME_MAX)));
142 }
143}
144
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700145TEST(PACKAGES, processor_start) {
Marat Dukhan30401972017-09-26 18:35:52 -0700146 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
147 ASSERT_EQ(0, cpuinfo_get_package(i)->processor_start);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700148 }
149}
150
151TEST(PACKAGES, processor_count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700152 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
153 ASSERT_EQ(4, cpuinfo_get_package(i)->processor_count);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700154 }
155}
156
157TEST(PACKAGES, core_start) {
Marat Dukhan30401972017-09-26 18:35:52 -0700158 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
159 ASSERT_EQ(0, cpuinfo_get_package(i)->core_start);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700160 }
161}
162
163TEST(PACKAGES, core_count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700164 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
165 ASSERT_EQ(4, cpuinfo_get_package(i)->core_count);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700166 }
167}
168
169TEST(ISA, rdtsc) {
Marat Dukhan640b91a2017-09-26 11:04:32 -0700170 ASSERT_TRUE(cpuinfo_has_x86_rdtsc());
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700171}
172
173TEST(ISA, rdtscp) {
Marat Dukhan640b91a2017-09-26 11:04:32 -0700174 ASSERT_TRUE(cpuinfo_has_x86_rdtscp());
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700175}
176
177TEST(ISA, rdpid) {
Marat Dukhan640b91a2017-09-26 11:04:32 -0700178 ASSERT_FALSE(cpuinfo_has_x86_rdpid());
179}
180
181TEST(ISA, clzero) {
182 ASSERT_FALSE(cpuinfo_has_x86_clzero());
183}
184
185TEST(ISA, mwait) {
186 ASSERT_TRUE(cpuinfo_has_x86_mwait());
187}
188
189TEST(ISA, mwaitx) {
190 ASSERT_FALSE(cpuinfo_has_x86_mwaitx());
191}
192
193TEST(ISA, fxsave) {
194 ASSERT_TRUE(cpuinfo_has_x86_fxsave());
195}
196
197TEST(ISA, xsave) {
198 ASSERT_FALSE(cpuinfo_has_x86_xsave());
199}
200
201TEST(ISA, fpu) {
202 ASSERT_TRUE(cpuinfo_has_x86_fpu());
203}
204
205TEST(ISA, mmx) {
206 ASSERT_TRUE(cpuinfo_has_x86_mmx());
207}
208
209TEST(ISA, mmx_plus) {
210 ASSERT_TRUE(cpuinfo_has_x86_mmx_plus());
211}
212
213TEST(ISA, three_d_now) {
214 ASSERT_FALSE(cpuinfo_has_x86_3dnow());
215}
216
217TEST(ISA, three_d_now_plus) {
218 ASSERT_FALSE(cpuinfo_has_x86_3dnow_plus());
219}
220
221TEST(ISA, three_d_now_geode) {
222 ASSERT_FALSE(cpuinfo_has_x86_3dnow_geode());
223}
224
225TEST(ISA, prefetch) {
226 ASSERT_FALSE(cpuinfo_has_x86_prefetch());
227}
228
229TEST(ISA, prefetchw) {
230 ASSERT_TRUE(cpuinfo_has_x86_prefetchw());
231}
232
233TEST(ISA, prefetchwt1) {
234 ASSERT_FALSE(cpuinfo_has_x86_prefetchwt1());
235}
236
237TEST(ISA, daz) {
238 ASSERT_TRUE(cpuinfo_has_x86_daz());
239}
240
241TEST(ISA, sse) {
242 ASSERT_TRUE(cpuinfo_has_x86_sse());
243}
244
245TEST(ISA, sse2) {
246 ASSERT_TRUE(cpuinfo_has_x86_sse2());
247}
248
249TEST(ISA, sse3) {
250 ASSERT_TRUE(cpuinfo_has_x86_sse3());
251}
252
253TEST(ISA, ssse3) {
254 ASSERT_TRUE(cpuinfo_has_x86_ssse3());
255}
256
257TEST(ISA, sse4_1) {
258 ASSERT_TRUE(cpuinfo_has_x86_sse4_1());
259}
260
261TEST(ISA, sse4_2) {
262 ASSERT_TRUE(cpuinfo_has_x86_sse4_2());
263}
264
265TEST(ISA, sse4a) {
266 ASSERT_FALSE(cpuinfo_has_x86_sse4a());
267}
268
269TEST(ISA, misaligned_sse) {
270 ASSERT_FALSE(cpuinfo_has_x86_misaligned_sse());
271}
272
273TEST(ISA, avx) {
274 ASSERT_FALSE(cpuinfo_has_x86_avx());
275}
276
277TEST(ISA, fma3) {
278 ASSERT_FALSE(cpuinfo_has_x86_fma3());
279}
280
281TEST(ISA, fma4) {
282 ASSERT_FALSE(cpuinfo_has_x86_fma4());
283}
284
285TEST(ISA, xop) {
286 ASSERT_FALSE(cpuinfo_has_x86_xop());
287}
288
289TEST(ISA, f16c) {
290 ASSERT_FALSE(cpuinfo_has_x86_f16c());
291}
292
293TEST(ISA, avx2) {
294 ASSERT_FALSE(cpuinfo_has_x86_avx2());
295}
296
297TEST(ISA, avx512f) {
298 ASSERT_FALSE(cpuinfo_has_x86_avx512f());
299}
300
301TEST(ISA, avx512pf) {
302 ASSERT_FALSE(cpuinfo_has_x86_avx512pf());
303}
304
305TEST(ISA, avx512er) {
306 ASSERT_FALSE(cpuinfo_has_x86_avx512er());
307}
308
309TEST(ISA, avx512cd) {
310 ASSERT_FALSE(cpuinfo_has_x86_avx512cd());
311}
312
313TEST(ISA, avx512dq) {
314 ASSERT_FALSE(cpuinfo_has_x86_avx512dq());
315}
316
317TEST(ISA, avx512bw) {
318 ASSERT_FALSE(cpuinfo_has_x86_avx512bw());
319}
320
321TEST(ISA, avx512vl) {
322 ASSERT_FALSE(cpuinfo_has_x86_avx512vl());
323}
324
325TEST(ISA, avx512ifma) {
326 ASSERT_FALSE(cpuinfo_has_x86_avx512ifma());
327}
328
329TEST(ISA, avx512vbmi) {
330 ASSERT_FALSE(cpuinfo_has_x86_avx512vbmi());
331}
332
333TEST(ISA, avx512vpopcntdq) {
334 ASSERT_FALSE(cpuinfo_has_x86_avx512vpopcntdq());
335}
336
337TEST(ISA, avx512_4vnniw) {
338 ASSERT_FALSE(cpuinfo_has_x86_avx512_4vnniw());
339}
340
341TEST(ISA, avx512_4fmaps) {
342 ASSERT_FALSE(cpuinfo_has_x86_avx512_4fmaps());
343}
344
345TEST(ISA, hle) {
346 ASSERT_FALSE(cpuinfo_has_x86_hle());
347}
348
349TEST(ISA, rtm) {
350 ASSERT_FALSE(cpuinfo_has_x86_rtm());
351}
352
353TEST(ISA, xtest) {
354 ASSERT_FALSE(cpuinfo_has_x86_xtest());
355}
356
357TEST(ISA, mpx) {
358 ASSERT_FALSE(cpuinfo_has_x86_mpx());
359}
360
361TEST(ISA, cmov) {
362 ASSERT_TRUE(cpuinfo_has_x86_cmov());
363}
364
365TEST(ISA, cmpxchg8b) {
366 ASSERT_TRUE(cpuinfo_has_x86_cmpxchg8b());
367}
368
369TEST(ISA, cmpxchg16b) {
370 ASSERT_FALSE(cpuinfo_has_x86_cmpxchg16b());
371}
372
373TEST(ISA, clwb) {
374 ASSERT_FALSE(cpuinfo_has_x86_clwb());
375}
376
377TEST(ISA, movbe) {
378 ASSERT_TRUE(cpuinfo_has_x86_movbe());
379}
380
Marat Dukhan30401972017-09-26 18:35:52 -0700381TEST(ISA, lahf_sahf) {
382 ASSERT_TRUE(cpuinfo_has_x86_lahf_sahf());
Marat Dukhan640b91a2017-09-26 11:04:32 -0700383}
384
385TEST(ISA, lzcnt) {
386 ASSERT_FALSE(cpuinfo_has_x86_lzcnt());
387}
388
389TEST(ISA, popcnt) {
390 ASSERT_TRUE(cpuinfo_has_x86_popcnt());
391}
392
393TEST(ISA, tbm) {
394 ASSERT_FALSE(cpuinfo_has_x86_tbm());
395}
396
397TEST(ISA, bmi) {
398 ASSERT_FALSE(cpuinfo_has_x86_bmi());
399}
400
401TEST(ISA, bmi2) {
402 ASSERT_FALSE(cpuinfo_has_x86_bmi2());
403}
404
405TEST(ISA, adx) {
406 ASSERT_FALSE(cpuinfo_has_x86_adx());
407}
408
409TEST(ISA, aes) {
410 ASSERT_TRUE(cpuinfo_has_x86_aes());
411}
412
413TEST(ISA, pclmulqdq) {
414 ASSERT_TRUE(cpuinfo_has_x86_pclmulqdq());
415}
416
417TEST(ISA, rdrand) {
418 ASSERT_TRUE(cpuinfo_has_x86_rdrand());
419}
420
421TEST(ISA, rdseed) {
422 ASSERT_FALSE(cpuinfo_has_x86_rdseed());
423}
424
425TEST(ISA, sha) {
426 ASSERT_FALSE(cpuinfo_has_x86_sha());
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700427}
428
429TEST(L1I, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700430 ASSERT_EQ(4, cpuinfo_get_l1i_caches_count());
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700431}
432
433TEST(L1I, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700434 ASSERT_TRUE(cpuinfo_get_l1i_caches());
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700435}
436
437TEST(L1I, size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700438 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
439 ASSERT_EQ(32 * 1024, cpuinfo_get_l1i_cache(i)->size);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700440 }
441}
442
443TEST(L1I, associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700444 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
445 ASSERT_EQ(8, cpuinfo_get_l1i_cache(i)->associativity);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700446 }
447}
448
449TEST(L1I, sets) {
Marat Dukhan30401972017-09-26 18:35:52 -0700450 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
451 ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size,
452 cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700453 }
454}
455
456TEST(L1I, partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700457 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
458 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->partitions);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700459 }
460}
461
462TEST(L1I, line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700463 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
464 ASSERT_EQ(64, cpuinfo_get_l1i_cache(i)->line_size);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700465 }
466}
467
468TEST(L1I, flags) {
Marat Dukhan30401972017-09-26 18:35:52 -0700469 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
470 ASSERT_EQ(0, cpuinfo_get_l1i_cache(i)->flags);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700471 }
472}
473
474TEST(L1I, processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700475 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
476 ASSERT_EQ(i, cpuinfo_get_l1i_cache(i)->processor_start);
477 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->processor_count);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700478 }
479}
480
481TEST(L1D, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700482 ASSERT_EQ(4, cpuinfo_get_l1d_caches_count());
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700483}
484
485TEST(L1D, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700486 ASSERT_TRUE(cpuinfo_get_l1d_caches());
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700487}
488
489TEST(L1D, size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700490 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
491 ASSERT_EQ(24 * 1024, cpuinfo_get_l1d_cache(i)->size);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700492 }
493}
494
495TEST(L1D, associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700496 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
497 ASSERT_EQ(6, cpuinfo_get_l1d_cache(i)->associativity);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700498 }
499}
500
501TEST(L1D, sets) {
Marat Dukhan30401972017-09-26 18:35:52 -0700502 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
503 ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size,
504 cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700505 }
506}
507
508TEST(L1D, partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700509 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
510 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->partitions);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700511 }
512}
513
514TEST(L1D, line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700515 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
516 ASSERT_EQ(64, cpuinfo_get_l1d_cache(i)->line_size);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700517 }
518}
519
520TEST(L1D, flags) {
Marat Dukhan30401972017-09-26 18:35:52 -0700521 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
522 ASSERT_EQ(0, cpuinfo_get_l1d_cache(i)->flags);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700523 }
524}
525
526TEST(L1D, processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700527 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
528 ASSERT_EQ(i, cpuinfo_get_l1d_cache(i)->processor_start);
529 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->processor_count);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700530 }
531}
532
533TEST(L2, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700534 ASSERT_EQ(2, cpuinfo_get_l2_caches_count());
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700535}
536
537TEST(L2, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700538 ASSERT_TRUE(cpuinfo_get_l2_caches());
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700539}
540
541TEST(L2, size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700542 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
543 ASSERT_EQ(1024 * 1024, cpuinfo_get_l2_cache(i)->size);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700544 }
545}
546
547TEST(L2, associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700548 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
549 ASSERT_EQ(16, cpuinfo_get_l2_cache(i)->associativity);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700550 }
551}
552
553TEST(L2, sets) {
Marat Dukhan30401972017-09-26 18:35:52 -0700554 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
555 ASSERT_EQ(cpuinfo_get_l2_cache(i)->size,
556 cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700557 }
558}
559
560TEST(L2, partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700561 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
562 ASSERT_EQ(1, cpuinfo_get_l2_cache(i)->partitions);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700563 }
564}
565
566TEST(L2, line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700567 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
568 ASSERT_EQ(64, cpuinfo_get_l2_cache(i)->line_size);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700569 }
570}
571
572TEST(L2, flags) {
Marat Dukhan30401972017-09-26 18:35:52 -0700573 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
574 ASSERT_EQ(CPUINFO_CACHE_UNIFIED, cpuinfo_get_l2_cache(i)->flags);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700575 }
576}
577
578TEST(L2, processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700579 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
580 ASSERT_EQ(i * 2, cpuinfo_get_l2_cache(i)->processor_start);
581 ASSERT_EQ(2, cpuinfo_get_l2_cache(i)->processor_count);
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700582 }
583}
584
585TEST(L3, none) {
Marat Dukhan30401972017-09-26 18:35:52 -0700586 ASSERT_EQ(0, cpuinfo_get_l3_caches_count());
587 ASSERT_FALSE(cpuinfo_get_l3_caches());
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700588}
589
590TEST(L4, none) {
Marat Dukhan30401972017-09-26 18:35:52 -0700591 ASSERT_EQ(0, cpuinfo_get_l4_caches_count());
592 ASSERT_FALSE(cpuinfo_get_l4_caches());
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700593}
594
595#include <memo-pad-7.h>
596
597int main(int argc, char* argv[]) {
598 cpuinfo_mock_filesystem(filesystem);
599 cpuinfo_mock_set_cpuid(cpuid_dump, sizeof(cpuid_dump) / sizeof(cpuinfo_mock_cpuid));
Marat Dukhanfd0f3ef2017-12-18 17:45:18 -0800600#ifdef __ANDROID__
601 cpuinfo_mock_gl_renderer("Intel(R) HD Graphics for BayTrail");
602#endif
Marat Dukhane3ee90d2017-09-25 23:23:05 -0700603 cpuinfo_initialize();
604 ::testing::InitGoogleTest(&argc, argv);
605 return RUN_ALL_TESTS();
Marat Dukhan30401972017-09-26 18:35:52 -0700606}