blob: f2c03b615788095e7a8ab6c356c3f199a3be6056 [file] [log] [blame]
Marat Dukhancf149942017-09-08 17:39:01 -07001#include <gtest/gtest.h>
2
3#include <cpuinfo.h>
4#include <cpuinfo-mock.h>
5
6
7TEST(PROCESSORS, count) {
Marat Dukhan30401972017-09-26 18:35:52 -07008 ASSERT_EQ(4, cpuinfo_get_processors_count());
Marat Dukhancf149942017-09-08 17:39:01 -07009}
10
11TEST(PROCESSORS, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -070012 ASSERT_TRUE(cpuinfo_get_processors());
Marat Dukhancf149942017-09-08 17:39:01 -070013}
14
Marat Dukhan2d37dc42017-09-25 01:32:37 -070015TEST(PROCESSORS, smt_id) {
Marat Dukhan30401972017-09-26 18:35:52 -070016 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
17 ASSERT_EQ(0, cpuinfo_get_processor(i)->smt_id);
Marat Dukhancf149942017-09-08 17:39:01 -070018 }
19}
20
Marat Dukhan2d37dc42017-09-25 01:32:37 -070021TEST(PROCESSORS, core) {
Marat Dukhan30401972017-09-26 18:35:52 -070022 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
23 ASSERT_EQ(cpuinfo_get_core(i), cpuinfo_get_processor(i)->core);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070024 }
25}
26
Marat Dukhan2b307932018-03-18 16:15:36 -070027TEST(PROCESSORS, cluster) {
28 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
29 switch (i) {
30 case 0:
31 case 1:
32 ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_processor(i)->cluster);
33 break;
34 case 2:
35 case 3:
36 ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_processor(i)->cluster);
37 break;
38 }
39 }
40}
41
Marat Dukhan2d37dc42017-09-25 01:32:37 -070042TEST(PROCESSORS, package) {
Marat Dukhan30401972017-09-26 18:35:52 -070043 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
44 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_processor(i)->package);
Marat Dukhancf149942017-09-08 17:39:01 -070045 }
46}
47
Marat Dukhan846c1782017-09-13 09:47:26 -070048TEST(PROCESSORS, linux_id) {
Marat Dukhan30401972017-09-26 18:35:52 -070049 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
Marat Dukhan846c1782017-09-13 09:47:26 -070050 switch (i) {
51 case 0:
52 case 1:
Marat Dukhan30401972017-09-26 18:35:52 -070053 ASSERT_EQ(i + 2, cpuinfo_get_processor(i)->linux_id);
Marat Dukhan846c1782017-09-13 09:47:26 -070054 break;
55 case 2:
56 case 3:
Marat Dukhan30401972017-09-26 18:35:52 -070057 ASSERT_EQ(i - 2, cpuinfo_get_processor(i)->linux_id);
Marat Dukhan846c1782017-09-13 09:47:26 -070058 break;
59 }
60 }
61}
62
Marat Dukhan2d37dc42017-09-25 01:32:37 -070063TEST(PROCESSORS, l1i) {
Marat Dukhan30401972017-09-26 18:35:52 -070064 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
65 ASSERT_EQ(cpuinfo_get_l1i_cache(i), cpuinfo_get_processor(i)->cache.l1i);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070066 }
67}
68
69TEST(PROCESSORS, l1d) {
Marat Dukhan30401972017-09-26 18:35:52 -070070 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
71 ASSERT_EQ(cpuinfo_get_l1d_cache(i), cpuinfo_get_processor(i)->cache.l1d);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070072 }
73}
74
75TEST(PROCESSORS, l2) {
Marat Dukhan30401972017-09-26 18:35:52 -070076 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
Marat Dukhan2d37dc42017-09-25 01:32:37 -070077 switch (i) {
78 case 0:
79 case 1:
Marat Dukhan30401972017-09-26 18:35:52 -070080 ASSERT_EQ(cpuinfo_get_l2_cache(0), cpuinfo_get_processor(i)->cache.l2);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070081 break;
82 case 2:
83 case 3:
Marat Dukhan30401972017-09-26 18:35:52 -070084 ASSERT_EQ(cpuinfo_get_l2_cache(1), cpuinfo_get_processor(i)->cache.l2);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070085 break;
86 }
87 }
88}
89
90TEST(PROCESSORS, l3) {
Marat Dukhan30401972017-09-26 18:35:52 -070091 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
92 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l3);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070093 }
94}
95
96TEST(PROCESSORS, l4) {
Marat Dukhan30401972017-09-26 18:35:52 -070097 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
98 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l4);
Marat Dukhan2d37dc42017-09-25 01:32:37 -070099 }
100}
101
Marat Dukhan7073e832017-09-24 22:23:55 -0700102TEST(CORES, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700103 ASSERT_EQ(4, cpuinfo_get_cores_count());
Marat Dukhan7073e832017-09-24 22:23:55 -0700104}
105
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700106TEST(CORES, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700107 ASSERT_TRUE(cpuinfo_get_cores());
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700108}
109
Marat Dukhan7073e832017-09-24 22:23:55 -0700110TEST(CORES, processor_start) {
Marat Dukhan30401972017-09-26 18:35:52 -0700111 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
112 ASSERT_EQ(i, cpuinfo_get_core(i)->processor_start);
Marat Dukhan7073e832017-09-24 22:23:55 -0700113 }
114}
115
116TEST(CORES, processor_count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700117 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
118 ASSERT_EQ(1, cpuinfo_get_core(i)->processor_count);
Marat Dukhan7073e832017-09-24 22:23:55 -0700119 }
120}
121
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700122TEST(CORES, core_id) {
Marat Dukhan30401972017-09-26 18:35:52 -0700123 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
124 ASSERT_EQ(i, cpuinfo_get_core(i)->core_id);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700125 }
126}
127
Marat Dukhan2b307932018-03-18 16:15:36 -0700128TEST(CORES, cluster) {
129 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
130 switch (i) {
131 case 0:
132 case 1:
133 ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_core(i)->cluster);
134 break;
135 case 2:
136 case 3:
137 ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_core(i)->cluster);
138 break;
139 }
140 }
141}
142
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700143TEST(CORES, package) {
Marat Dukhan30401972017-09-26 18:35:52 -0700144 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
145 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_core(i)->package);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700146 }
147}
148
149TEST(CORES, vendor) {
Marat Dukhan30401972017-09-26 18:35:52 -0700150 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
151 ASSERT_EQ(cpuinfo_vendor_qualcomm, cpuinfo_get_core(i)->vendor);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700152 }
153}
154
155TEST(CORES, uarch) {
Marat Dukhan30401972017-09-26 18:35:52 -0700156 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
157 ASSERT_EQ(cpuinfo_uarch_kryo, cpuinfo_get_core(i)->uarch);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700158 }
159}
160
161TEST(CORES, midr) {
Marat Dukhan30401972017-09-26 18:35:52 -0700162 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700163 switch (i) {
164 case 0:
165 case 1:
Marat Dukhan30401972017-09-26 18:35:52 -0700166 ASSERT_EQ(UINT32_C(0x512F2051), cpuinfo_get_core(i)->midr);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700167 break;
168 case 2:
169 case 3:
Marat Dukhan30401972017-09-26 18:35:52 -0700170 ASSERT_EQ(UINT32_C(0x512F2011), cpuinfo_get_core(i)->midr);
Marat Dukhan2d37dc42017-09-25 01:32:37 -0700171 break;
172 }
173 }
174}
175
Marat Dukhan575a6302018-03-10 14:38:49 -0800176TEST(CORES, DISABLED_frequency) {
177 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
178 switch (i) {
179 case 0:
180 case 1:
181 ASSERT_EQ(UINT64_C(2150400000), cpuinfo_get_core(i)->frequency);
182 break;
183 case 2:
184 case 3:
185 ASSERT_EQ(UINT64_C(1593600000), cpuinfo_get_core(i)->frequency);
186 break;
187 }
188 }
189}
190
Marat Dukhandbc78402018-03-18 22:49:35 -0700191TEST(CLUSTERS, count) {
192 ASSERT_EQ(2, cpuinfo_get_clusters_count());
193}
194
195TEST(CLUSTERS, non_null) {
196 ASSERT_TRUE(cpuinfo_get_clusters());
197}
198
199TEST(CLUSTERS, processor_start) {
200 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
201 switch (i) {
202 case 0:
203 ASSERT_EQ(0, cpuinfo_get_cluster(i)->processor_start);
204 break;
205 case 1:
206 ASSERT_EQ(2, cpuinfo_get_cluster(i)->processor_start);
207 break;
208 }
209 }
210}
211
212TEST(CLUSTERS, processor_count) {
213 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
214 ASSERT_EQ(2, cpuinfo_get_cluster(i)->processor_count);
215 }
216}
217
218TEST(CLUSTERS, core_start) {
219 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
220 switch (i) {
221 case 0:
222 ASSERT_EQ(0, cpuinfo_get_cluster(i)->core_start);
223 break;
224 case 1:
225 ASSERT_EQ(2, cpuinfo_get_cluster(i)->core_start);
226 break;
227 }
228 }
229}
230
231TEST(CLUSTERS, core_count) {
232 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
233 ASSERT_EQ(2, cpuinfo_get_cluster(i)->core_count);
234 }
235}
236
237TEST(CLUSTERS, cluster_id) {
238 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
239 ASSERT_EQ(i, cpuinfo_get_cluster(i)->cluster_id);
240 }
241}
242
243TEST(CLUSTERS, package) {
244 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
245 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_cluster(i)->package);
246 }
247}
248
249TEST(CLUSTERS, vendor) {
250 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
251 ASSERT_EQ(cpuinfo_vendor_qualcomm, cpuinfo_get_cluster(i)->vendor);
252 }
253}
254
255TEST(CLUSTERS, uarch) {
256 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
257 ASSERT_EQ(cpuinfo_uarch_kryo, cpuinfo_get_cluster(i)->uarch);
258 }
259}
260
261TEST(CLUSTERS, midr) {
262 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
263 switch (i) {
264 case 0:
265 ASSERT_EQ(UINT32_C(0x512F2051), cpuinfo_get_cluster(i)->midr);
266 break;
267 case 1:
268 ASSERT_EQ(UINT32_C(0x512F2011), cpuinfo_get_cluster(i)->midr);
269 break;
270 }
271 }
272}
273
274TEST(CLUSTERS, DISABLED_frequency) {
275 for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) {
276 switch (i) {
277 case 0:
278 ASSERT_EQ(UINT64_C(2150400000), cpuinfo_get_cluster(i)->frequency);
279 break;
280 case 1:
281 ASSERT_EQ(UINT64_C(1593600000), cpuinfo_get_cluster(i)->frequency);
282 break;
283 }
284 }
285}
286
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700287TEST(PACKAGES, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700288 ASSERT_EQ(1, cpuinfo_get_packages_count());
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700289}
290
291TEST(PACKAGES, name) {
Marat Dukhan30401972017-09-26 18:35:52 -0700292 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700293 ASSERT_EQ("Qualcomm MSM8996PRO-AB",
Marat Dukhan30401972017-09-26 18:35:52 -0700294 std::string(cpuinfo_get_package(i)->name,
295 strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX)));
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700296 }
297}
298
Marat Dukhanfd0f3ef2017-12-18 17:45:18 -0800299TEST(PACKAGES, gpu_name) {
300 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
301 ASSERT_EQ("Qualcomm Adreno 530",
302 std::string(cpuinfo_get_package(i)->gpu_name,
303 strnlen(cpuinfo_get_package(i)->gpu_name, CPUINFO_GPU_NAME_MAX)));
304 }
305}
306
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700307TEST(PACKAGES, processor_start) {
Marat Dukhan30401972017-09-26 18:35:52 -0700308 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
309 ASSERT_EQ(0, cpuinfo_get_package(i)->processor_start);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700310 }
311}
312
313TEST(PACKAGES, processor_count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700314 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
315 ASSERT_EQ(4, cpuinfo_get_package(i)->processor_count);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700316 }
317}
318
319TEST(PACKAGES, core_start) {
Marat Dukhan30401972017-09-26 18:35:52 -0700320 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
321 ASSERT_EQ(0, cpuinfo_get_package(i)->core_start);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700322 }
323}
324
325TEST(PACKAGES, core_count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700326 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
327 ASSERT_EQ(4, cpuinfo_get_package(i)->core_count);
Marat Dukhanfb4fbe02017-09-13 00:51:05 -0700328 }
329}
330
Marat Dukhan2b307932018-03-18 16:15:36 -0700331TEST(PACKAGES, cluster_start) {
332 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
333 ASSERT_EQ(0, cpuinfo_get_package(i)->cluster_start);
334 }
335}
336
337TEST(PACKAGES, cluster_count) {
338 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
339 ASSERT_EQ(2, cpuinfo_get_package(i)->cluster_count);
340 }
341}
342
Marat Dukhancf149942017-09-08 17:39:01 -0700343TEST(ISA, thumb) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700344 #if CPUINFO_ARCH_ARM
345 ASSERT_TRUE(cpuinfo_has_arm_thumb());
346 #elif CPUINFO_ARCH_ARM64
347 ASSERT_FALSE(cpuinfo_has_arm_thumb());
348 #endif
Marat Dukhancf149942017-09-08 17:39:01 -0700349}
350
351TEST(ISA, thumb2) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700352 #if CPUINFO_ARCH_ARM
353 ASSERT_TRUE(cpuinfo_has_arm_thumb2());
354 #elif CPUINFO_ARCH_ARM64
355 ASSERT_FALSE(cpuinfo_has_arm_thumb2());
356 #endif
Marat Dukhancf149942017-09-08 17:39:01 -0700357}
358
359TEST(ISA, armv5e) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700360 #if CPUINFO_ARCH_ARM
361 ASSERT_TRUE(cpuinfo_has_arm_v5e());
362 #elif CPUINFO_ARCH_ARM64
363 ASSERT_FALSE(cpuinfo_has_arm_v5e());
364 #endif
Marat Dukhancf149942017-09-08 17:39:01 -0700365}
366
367TEST(ISA, armv6) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700368 #if CPUINFO_ARCH_ARM
369 ASSERT_TRUE(cpuinfo_has_arm_v6());
370 #elif CPUINFO_ARCH_ARM64
371 ASSERT_FALSE(cpuinfo_has_arm_v6());
372 #endif
Marat Dukhancf149942017-09-08 17:39:01 -0700373}
374
375TEST(ISA, armv6k) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700376 #if CPUINFO_ARCH_ARM
377 ASSERT_TRUE(cpuinfo_has_arm_v6k());
378 #elif CPUINFO_ARCH_ARM64
379 ASSERT_FALSE(cpuinfo_has_arm_v6k());
380 #endif
Marat Dukhancf149942017-09-08 17:39:01 -0700381}
382
383TEST(ISA, armv7) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700384 #if CPUINFO_ARCH_ARM
385 ASSERT_TRUE(cpuinfo_has_arm_v7());
386 #elif CPUINFO_ARCH_ARM64
387 ASSERT_FALSE(cpuinfo_has_arm_v7());
388 #endif
Marat Dukhancf149942017-09-08 17:39:01 -0700389}
390
391TEST(ISA, armv7mp) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700392 #if CPUINFO_ARCH_ARM
393 ASSERT_TRUE(cpuinfo_has_arm_v7mp());
394 #elif CPUINFO_ARCH_ARM64
395 ASSERT_FALSE(cpuinfo_has_arm_v7mp());
396 #endif
Marat Dukhancf149942017-09-08 17:39:01 -0700397}
398
399TEST(ISA, idiv) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700400 ASSERT_TRUE(cpuinfo_has_arm_idiv());
Marat Dukhancf149942017-09-08 17:39:01 -0700401}
402
403TEST(ISA, vfpv2) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700404 ASSERT_FALSE(cpuinfo_has_arm_vfpv2());
Marat Dukhancf149942017-09-08 17:39:01 -0700405}
406
407TEST(ISA, vfpv3) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700408 ASSERT_TRUE(cpuinfo_has_arm_vfpv3());
Marat Dukhancf149942017-09-08 17:39:01 -0700409}
410
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700411TEST(ISA, vfpv3_d32) {
412 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_d32());
Marat Dukhancf149942017-09-08 17:39:01 -0700413}
414
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700415TEST(ISA, vfpv3_fp16) {
416 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16());
Marat Dukhancf149942017-09-08 17:39:01 -0700417}
418
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700419TEST(ISA, vfpv3_fp16_d32) {
420 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16_d32());
421}
422
423TEST(ISA, vfpv4) {
424 ASSERT_TRUE(cpuinfo_has_arm_vfpv4());
425}
426
427TEST(ISA, vfpv4_d32) {
428 ASSERT_TRUE(cpuinfo_has_arm_vfpv4_d32());
Marat Dukhancf149942017-09-08 17:39:01 -0700429}
430
431TEST(ISA, wmmx) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700432 ASSERT_FALSE(cpuinfo_has_arm_wmmx());
Marat Dukhancf149942017-09-08 17:39:01 -0700433}
434
435TEST(ISA, wmmx2) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700436 ASSERT_FALSE(cpuinfo_has_arm_wmmx2());
Marat Dukhancf149942017-09-08 17:39:01 -0700437}
438
439TEST(ISA, neon) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700440 ASSERT_TRUE(cpuinfo_has_arm_neon());
Marat Dukhancf149942017-09-08 17:39:01 -0700441}
442
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700443TEST(ISA, neon_fp16) {
444 ASSERT_TRUE(cpuinfo_has_arm_neon_fp16());
Marat Dukhancf149942017-09-08 17:39:01 -0700445}
446
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700447TEST(ISA, neon_fma) {
448 ASSERT_TRUE(cpuinfo_has_arm_neon_fma());
Marat Dukhancf149942017-09-08 17:39:01 -0700449}
450
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700451TEST(ISA, atomics) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700452 ASSERT_FALSE(cpuinfo_has_arm_atomics());
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700453}
454
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700455TEST(ISA, neon_rdm) {
456 ASSERT_FALSE(cpuinfo_has_arm_neon_rdm());
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700457}
458
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700459TEST(ISA, fp16_arith) {
460 ASSERT_FALSE(cpuinfo_has_arm_fp16_arith());
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700461}
462
463TEST(ISA, jscvt) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700464 ASSERT_FALSE(cpuinfo_has_arm_jscvt());
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700465}
466
467TEST(ISA, fcma) {
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700468 ASSERT_FALSE(cpuinfo_has_arm_fcma());
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700469}
Marat Dukhaneb3025f2017-09-26 12:57:41 -0700470
471TEST(ISA, aes) {
472 ASSERT_TRUE(cpuinfo_has_arm_aes());
473}
474
475TEST(ISA, sha1) {
476 ASSERT_TRUE(cpuinfo_has_arm_sha1());
477}
478
479TEST(ISA, sha2) {
480 ASSERT_TRUE(cpuinfo_has_arm_sha2());
481}
482
483TEST(ISA, pmull) {
484 ASSERT_TRUE(cpuinfo_has_arm_pmull());
485}
486
487TEST(ISA, crc32) {
488 ASSERT_TRUE(cpuinfo_has_arm_crc32());
489}
Marat Dukhan3e8e1c72017-09-13 12:15:35 -0700490
Marat Dukhancf149942017-09-08 17:39:01 -0700491TEST(L1I, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700492 ASSERT_EQ(4, cpuinfo_get_l1i_caches_count());
Marat Dukhancf149942017-09-08 17:39:01 -0700493}
494
495TEST(L1I, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700496 ASSERT_TRUE(cpuinfo_get_l1i_caches());
Marat Dukhancf149942017-09-08 17:39:01 -0700497}
498
499TEST(L1I, size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700500 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
501 ASSERT_EQ(32 * 1024, cpuinfo_get_l1i_cache(i)->size);
Marat Dukhancf149942017-09-08 17:39:01 -0700502 }
503}
504
505TEST(L1I, associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700506 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
507 ASSERT_EQ(4, cpuinfo_get_l1i_cache(i)->associativity);
Marat Dukhancf149942017-09-08 17:39:01 -0700508 }
509}
510
511TEST(L1I, sets) {
Marat Dukhan30401972017-09-26 18:35:52 -0700512 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
513 ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size,
514 cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity);
Marat Dukhancf149942017-09-08 17:39:01 -0700515 }
516}
517
518TEST(L1I, partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700519 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
520 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->partitions);
Marat Dukhancf149942017-09-08 17:39:01 -0700521 }
522}
523
524TEST(L1I, line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700525 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
526 ASSERT_EQ(64, cpuinfo_get_l1i_cache(i)->line_size);
Marat Dukhancf149942017-09-08 17:39:01 -0700527 }
528}
529
530TEST(L1I, flags) {
Marat Dukhan30401972017-09-26 18:35:52 -0700531 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
532 ASSERT_EQ(0, cpuinfo_get_l1i_cache(i)->flags);
Marat Dukhancf149942017-09-08 17:39:01 -0700533 }
534}
535
536TEST(L1I, processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700537 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
538 ASSERT_EQ(i, cpuinfo_get_l1i_cache(i)->processor_start);
539 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->processor_count);
Marat Dukhancf149942017-09-08 17:39:01 -0700540 }
541}
542
543TEST(L1D, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700544 ASSERT_EQ(4, cpuinfo_get_l1d_caches_count());
Marat Dukhancf149942017-09-08 17:39:01 -0700545}
546
547TEST(L1D, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700548 ASSERT_TRUE(cpuinfo_get_l1d_caches());
Marat Dukhancf149942017-09-08 17:39:01 -0700549}
550
551TEST(L1D, size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700552 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
553 ASSERT_EQ(24 * 1024, cpuinfo_get_l1d_cache(i)->size);
Marat Dukhancf149942017-09-08 17:39:01 -0700554 }
555}
556
557TEST(L1D, associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700558 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
559 ASSERT_EQ(3, cpuinfo_get_l1d_cache(i)->associativity);
Marat Dukhancf149942017-09-08 17:39:01 -0700560 }
561}
562
563TEST(L1D, sets) {
Marat Dukhan30401972017-09-26 18:35:52 -0700564 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
565 ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size,
566 cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity);
Marat Dukhancf149942017-09-08 17:39:01 -0700567 }
568}
569
570TEST(L1D, partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700571 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
572 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->partitions);
Marat Dukhancf149942017-09-08 17:39:01 -0700573 }
574}
575
576TEST(L1D, line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700577 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
578 ASSERT_EQ(64, cpuinfo_get_l1d_cache(i)->line_size);
Marat Dukhancf149942017-09-08 17:39:01 -0700579 }
580}
581
582TEST(L1D, flags) {
Marat Dukhan30401972017-09-26 18:35:52 -0700583 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
584 ASSERT_EQ(0, cpuinfo_get_l1d_cache(i)->flags);
Marat Dukhancf149942017-09-08 17:39:01 -0700585 }
586}
587
588TEST(L1D, processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700589 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
590 ASSERT_EQ(i, cpuinfo_get_l1d_cache(i)->processor_start);
591 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->processor_count);
Marat Dukhancf149942017-09-08 17:39:01 -0700592 }
593}
594
595TEST(L2, count) {
Marat Dukhan30401972017-09-26 18:35:52 -0700596 ASSERT_EQ(2, cpuinfo_get_l2_caches_count());
Marat Dukhancf149942017-09-08 17:39:01 -0700597}
598
599TEST(L2, non_null) {
Marat Dukhan30401972017-09-26 18:35:52 -0700600 ASSERT_TRUE(cpuinfo_get_l2_caches());
Marat Dukhancf149942017-09-08 17:39:01 -0700601}
602
603TEST(L2, size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700604 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
605 switch (i) {
Marat Dukhancf149942017-09-08 17:39:01 -0700606 case 0:
Marat Dukhan30401972017-09-26 18:35:52 -0700607 ASSERT_EQ(1 * 1024 * 1024, cpuinfo_get_l2_cache(i)->size);
Marat Dukhancf149942017-09-08 17:39:01 -0700608 break;
609 case 1:
Marat Dukhan30401972017-09-26 18:35:52 -0700610 ASSERT_EQ(512 * 1024, cpuinfo_get_l2_cache(i)->size);
Marat Dukhancf149942017-09-08 17:39:01 -0700611 break;
612 }
613 }
614}
615
616TEST(L2, associativity) {
Marat Dukhan30401972017-09-26 18:35:52 -0700617 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
618 ASSERT_EQ(8, cpuinfo_get_l2_cache(i)->associativity);
Marat Dukhancf149942017-09-08 17:39:01 -0700619 }
620}
621
622TEST(L2, sets) {
Marat Dukhan30401972017-09-26 18:35:52 -0700623 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
624 ASSERT_EQ(cpuinfo_get_l2_cache(i)->size,
625 cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity);
Marat Dukhancf149942017-09-08 17:39:01 -0700626 }
627}
628
629TEST(L2, partitions) {
Marat Dukhan30401972017-09-26 18:35:52 -0700630 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
631 ASSERT_EQ(1, cpuinfo_get_l2_cache(i)->partitions);
Marat Dukhancf149942017-09-08 17:39:01 -0700632 }
633}
634
635TEST(L2, line_size) {
Marat Dukhan30401972017-09-26 18:35:52 -0700636 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
637 ASSERT_EQ(128, cpuinfo_get_l2_cache(i)->line_size);
Marat Dukhancf149942017-09-08 17:39:01 -0700638 }
639}
640
641TEST(L2, flags) {
Marat Dukhan30401972017-09-26 18:35:52 -0700642 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
643 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->flags);
Marat Dukhancf149942017-09-08 17:39:01 -0700644 }
645}
646
647TEST(L2, processors) {
Marat Dukhan30401972017-09-26 18:35:52 -0700648 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
649 switch (i) {
Marat Dukhancf149942017-09-08 17:39:01 -0700650 case 0:
Marat Dukhan30401972017-09-26 18:35:52 -0700651 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->processor_start);
652 ASSERT_EQ(2, cpuinfo_get_l2_cache(i)->processor_count);
Marat Dukhancf149942017-09-08 17:39:01 -0700653 break;
654 case 1:
Marat Dukhan30401972017-09-26 18:35:52 -0700655 ASSERT_EQ(2, cpuinfo_get_l2_cache(i)->processor_start);
656 ASSERT_EQ(2, cpuinfo_get_l2_cache(i)->processor_count);
Marat Dukhancf149942017-09-08 17:39:01 -0700657 break;
658 }
659 }
660}
661
662TEST(L3, none) {
Marat Dukhan30401972017-09-26 18:35:52 -0700663 ASSERT_EQ(0, cpuinfo_get_l3_caches_count());
664 ASSERT_FALSE(cpuinfo_get_l3_caches());
Marat Dukhancf149942017-09-08 17:39:01 -0700665}
666
667TEST(L4, none) {
Marat Dukhan30401972017-09-26 18:35:52 -0700668 ASSERT_EQ(0, cpuinfo_get_l4_caches_count());
669 ASSERT_FALSE(cpuinfo_get_l4_caches());
Marat Dukhancf149942017-09-08 17:39:01 -0700670}
671
672#include <pixel.h>
673
674int main(int argc, char* argv[]) {
Marat Dukhan63a7a6b2017-11-29 15:11:56 -0800675#if CPUINFO_ARCH_ARM
676 cpuinfo_set_hwcap(UINT32_C(0x0037B0D6));
677 cpuinfo_set_hwcap2(UINT32_C(0x0000001F));
678#elif CPUINFO_ARCH_ARM64
679 cpuinfo_set_hwcap(UINT32_C(0x000000FF));
680#endif
Marat Dukhancf149942017-09-08 17:39:01 -0700681 cpuinfo_mock_filesystem(filesystem);
Marat Dukhan5659d292017-09-12 23:21:03 -0700682#ifdef __ANDROID__
683 cpuinfo_mock_android_properties(properties);
Marat Dukhanfd0f3ef2017-12-18 17:45:18 -0800684 cpuinfo_mock_gl_renderer("Adreno (TM) 530");
Marat Dukhan5659d292017-09-12 23:21:03 -0700685#endif
Marat Dukhancf149942017-09-08 17:39:01 -0700686 cpuinfo_initialize();
687 ::testing::InitGoogleTest(&argc, argv);
688 return RUN_ALL_TESTS();
Marat Dukhan30401972017-09-26 18:35:52 -0700689}