blob: cad4b483ae0fa52073125c70b22be76c361cb77d [file] [log] [blame]
Marat Dukhana5fda232017-12-04 16:08:25 -08001#include <gtest/gtest.h>
2
3#include <cpuinfo.h>
4#include <cpuinfo-mock.h>
5
6
7TEST(PROCESSORS, count) {
8 ASSERT_EQ(8, cpuinfo_get_processors_count());
9}
10
11TEST(PROCESSORS, non_null) {
12 ASSERT_TRUE(cpuinfo_get_processors());
13}
14
15TEST(PROCESSORS, smt_id) {
16 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
17 ASSERT_EQ(0, cpuinfo_get_processor(i)->smt_id);
18 }
19}
20
21TEST(PROCESSORS, core) {
22 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
23 ASSERT_EQ(cpuinfo_get_core(i), cpuinfo_get_processor(i)->core);
24 }
25}
26
27TEST(PROCESSORS, package) {
28 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
29 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_processor(i)->package);
30 }
31}
32
33TEST(PROCESSORS, linux_id) {
34 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
35 switch (i) {
36 case 0:
37 case 1:
38 case 2:
39 case 3:
40 ASSERT_EQ(i + 4, cpuinfo_get_processor(i)->linux_id);
41 break;
42 case 4:
43 case 5:
44 case 6:
45 case 7:
46 ASSERT_EQ(i - 4, cpuinfo_get_processor(i)->linux_id);
47 break;
48 }
49 }
50}
51
52TEST(PROCESSORS, l1i) {
53 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
54 ASSERT_EQ(cpuinfo_get_l1i_cache(i), cpuinfo_get_processor(i)->cache.l1i);
55 }
56}
57
58TEST(PROCESSORS, l1d) {
59 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
60 ASSERT_EQ(cpuinfo_get_l1d_cache(i), cpuinfo_get_processor(i)->cache.l1d);
61 }
62}
63
64TEST(PROCESSORS, l2) {
65 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
66 switch (i) {
67 case 0:
68 case 1:
69 case 2:
70 case 3:
71 ASSERT_EQ(cpuinfo_get_l2_cache(0), cpuinfo_get_processor(i)->cache.l2);
72 break;
73 case 4:
74 case 5:
75 case 6:
76 case 7:
77 ASSERT_EQ(cpuinfo_get_l2_cache(1), cpuinfo_get_processor(i)->cache.l2);
78 break;
79 }
80 }
81}
82
83TEST(PROCESSORS, l3) {
84 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
85 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l3);
86 }
87}
88
89TEST(PROCESSORS, l4) {
90 for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) {
91 ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l4);
92 }
93}
94
95TEST(CORES, count) {
96 ASSERT_EQ(8, cpuinfo_get_cores_count());
97}
98
99TEST(CORES, non_null) {
100 ASSERT_TRUE(cpuinfo_get_cores());
101}
102
103TEST(CORES, processor_start) {
104 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
105 ASSERT_EQ(i, cpuinfo_get_core(i)->processor_start);
106 }
107}
108
109TEST(CORES, processor_count) {
110 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
111 ASSERT_EQ(1, cpuinfo_get_core(i)->processor_count);
112 }
113}
114
115TEST(CORES, core_id) {
116 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
117 ASSERT_EQ(i, cpuinfo_get_core(i)->core_id);
118 }
119}
120
121TEST(CORES, package) {
122 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
123 ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_core(i)->package);
124 }
125}
126
127TEST(CORES, vendor) {
128 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
129 ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_core(i)->vendor);
130 }
131}
132
133TEST(CORES, uarch) {
134 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
135 ASSERT_EQ(cpuinfo_uarch_cortex_a53, cpuinfo_get_core(i)->uarch);
136 }
137}
138
139TEST(CORES, midr) {
140 for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) {
141 ASSERT_EQ(UINT32_C(0x410FD034), cpuinfo_get_core(i)->midr);
142 }
143}
144
145TEST(PACKAGES, count) {
146 ASSERT_EQ(1, cpuinfo_get_packages_count());
147}
148
149TEST(PACKAGES, name) {
150 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
151 ASSERT_EQ("Qualcomm MSM8953",
152 std::string(cpuinfo_get_package(i)->name,
153 strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX)));
154 }
155}
156
Marat Dukhanfd0f3ef2017-12-18 17:45:18 -0800157TEST(PACKAGES, gpu_name) {
158 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
159 ASSERT_EQ("Qualcomm Adreno 506",
160 std::string(cpuinfo_get_package(i)->gpu_name,
161 strnlen(cpuinfo_get_package(i)->gpu_name, CPUINFO_GPU_NAME_MAX)));
162 }
163}
164
Marat Dukhana5fda232017-12-04 16:08:25 -0800165TEST(PACKAGES, processor_start) {
166 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
167 ASSERT_EQ(0, cpuinfo_get_package(i)->processor_start);
168 }
169}
170
171TEST(PACKAGES, processor_count) {
172 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
173 ASSERT_EQ(8, cpuinfo_get_package(i)->processor_count);
174 }
175}
176
177TEST(PACKAGES, core_start) {
178 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
179 ASSERT_EQ(0, cpuinfo_get_package(i)->core_start);
180 }
181}
182
183TEST(PACKAGES, core_count) {
184 for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) {
185 ASSERT_EQ(8, cpuinfo_get_package(i)->core_count);
186 }
187}
188
189TEST(ISA, thumb) {
190 #if CPUINFO_ARCH_ARM
191 ASSERT_TRUE(cpuinfo_has_arm_thumb());
192 #elif CPUINFO_ARCH_ARM64
193 ASSERT_FALSE(cpuinfo_has_arm_thumb());
194 #endif
195}
196
197TEST(ISA, thumb2) {
198 #if CPUINFO_ARCH_ARM
199 ASSERT_TRUE(cpuinfo_has_arm_thumb2());
200 #elif CPUINFO_ARCH_ARM64
201 ASSERT_FALSE(cpuinfo_has_arm_thumb2());
202 #endif
203}
204
205TEST(ISA, armv5e) {
206 #if CPUINFO_ARCH_ARM
207 ASSERT_TRUE(cpuinfo_has_arm_v5e());
208 #elif CPUINFO_ARCH_ARM64
209 ASSERT_FALSE(cpuinfo_has_arm_v5e());
210 #endif
211}
212
213TEST(ISA, armv6) {
214 #if CPUINFO_ARCH_ARM
215 ASSERT_TRUE(cpuinfo_has_arm_v6());
216 #elif CPUINFO_ARCH_ARM64
217 ASSERT_FALSE(cpuinfo_has_arm_v6());
218 #endif
219}
220
221TEST(ISA, armv6k) {
222 #if CPUINFO_ARCH_ARM
223 ASSERT_TRUE(cpuinfo_has_arm_v6k());
224 #elif CPUINFO_ARCH_ARM64
225 ASSERT_FALSE(cpuinfo_has_arm_v6k());
226 #endif
227}
228
229TEST(ISA, armv7) {
230 #if CPUINFO_ARCH_ARM
231 ASSERT_TRUE(cpuinfo_has_arm_v7());
232 #elif CPUINFO_ARCH_ARM64
233 ASSERT_FALSE(cpuinfo_has_arm_v7());
234 #endif
235}
236
237TEST(ISA, armv7mp) {
238 #if CPUINFO_ARCH_ARM
239 ASSERT_TRUE(cpuinfo_has_arm_v7mp());
240 #elif CPUINFO_ARCH_ARM64
241 ASSERT_FALSE(cpuinfo_has_arm_v7mp());
242 #endif
243}
244
245TEST(ISA, idiv) {
246 ASSERT_TRUE(cpuinfo_has_arm_idiv());
247}
248
249TEST(ISA, vfpv2) {
250 ASSERT_FALSE(cpuinfo_has_arm_vfpv2());
251}
252
253TEST(ISA, vfpv3) {
254 ASSERT_TRUE(cpuinfo_has_arm_vfpv3());
255}
256
257TEST(ISA, vfpv3_d32) {
258 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_d32());
259}
260
261TEST(ISA, vfpv3_fp16) {
262 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16());
263}
264
265TEST(ISA, vfpv3_fp16_d32) {
266 ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16_d32());
267}
268
269TEST(ISA, vfpv4) {
270 ASSERT_TRUE(cpuinfo_has_arm_vfpv4());
271}
272
273TEST(ISA, vfpv4_d32) {
274 ASSERT_TRUE(cpuinfo_has_arm_vfpv4_d32());
275}
276
277TEST(ISA, wmmx) {
278 ASSERT_FALSE(cpuinfo_has_arm_wmmx());
279}
280
281TEST(ISA, wmmx2) {
282 ASSERT_FALSE(cpuinfo_has_arm_wmmx2());
283}
284
285TEST(ISA, neon) {
286 ASSERT_TRUE(cpuinfo_has_arm_neon());
287}
288
289TEST(ISA, neon_fp16) {
290 ASSERT_TRUE(cpuinfo_has_arm_neon_fp16());
291}
292
293TEST(ISA, neon_fma) {
294 ASSERT_TRUE(cpuinfo_has_arm_neon_fma());
295}
296
297TEST(ISA, atomics) {
298 ASSERT_FALSE(cpuinfo_has_arm_atomics());
299}
300
301TEST(ISA, neon_rdm) {
302 ASSERT_FALSE(cpuinfo_has_arm_neon_rdm());
303}
304
305TEST(ISA, fp16_arith) {
306 ASSERT_FALSE(cpuinfo_has_arm_fp16_arith());
307}
308
309TEST(ISA, jscvt) {
310 ASSERT_FALSE(cpuinfo_has_arm_jscvt());
311}
312
313TEST(ISA, fcma) {
314 ASSERT_FALSE(cpuinfo_has_arm_fcma());
315}
316
317TEST(ISA, aes) {
318 ASSERT_TRUE(cpuinfo_has_arm_aes());
319}
320
321TEST(ISA, sha1) {
322 ASSERT_TRUE(cpuinfo_has_arm_sha1());
323}
324
325TEST(ISA, sha2) {
326 ASSERT_TRUE(cpuinfo_has_arm_sha2());
327}
328
329TEST(ISA, pmull) {
330 ASSERT_TRUE(cpuinfo_has_arm_pmull());
331}
332
333TEST(ISA, crc32) {
334 ASSERT_TRUE(cpuinfo_has_arm_crc32());
335}
336
337TEST(L1I, count) {
338 ASSERT_EQ(8, cpuinfo_get_l1i_caches_count());
339}
340
341TEST(L1I, non_null) {
342 ASSERT_TRUE(cpuinfo_get_l1i_caches());
343}
344
345TEST(L1I, size) {
346 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
347 ASSERT_EQ(32 * 1024, cpuinfo_get_l1i_cache(i)->size);
348 }
349}
350
351TEST(L1I, associativity) {
352 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
353 ASSERT_EQ(2, cpuinfo_get_l1i_cache(i)->associativity);
354 }
355}
356
357TEST(L1I, sets) {
358 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
359 ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size,
360 cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity);
361 }
362}
363
364TEST(L1I, partitions) {
365 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
366 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->partitions);
367 }
368}
369
370TEST(L1I, line_size) {
371 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
372 ASSERT_EQ(64, cpuinfo_get_l1i_cache(i)->line_size);
373 }
374}
375
376TEST(L1I, flags) {
377 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
378 ASSERT_EQ(0, cpuinfo_get_l1i_cache(i)->flags);
379 }
380}
381
382TEST(L1I, processors) {
383 for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) {
384 ASSERT_EQ(i, cpuinfo_get_l1i_cache(i)->processor_start);
385 ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->processor_count);
386 }
387}
388
389TEST(L1D, count) {
390 ASSERT_EQ(8, cpuinfo_get_l1d_caches_count());
391}
392
393TEST(L1D, non_null) {
394 ASSERT_TRUE(cpuinfo_get_l1d_caches());
395}
396
397TEST(L1D, size) {
398 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
399 ASSERT_EQ(32 * 1024, cpuinfo_get_l1d_cache(i)->size);
400 }
401}
402
403TEST(L1D, associativity) {
404 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
405 ASSERT_EQ(4, cpuinfo_get_l1d_cache(i)->associativity);
406 }
407}
408
409TEST(L1D, sets) {
410 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
411 ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size,
412 cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity);
413 }
414}
415
416TEST(L1D, partitions) {
417 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
418 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->partitions);
419 }
420}
421
422TEST(L1D, line_size) {
423 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
424 ASSERT_EQ(64, cpuinfo_get_l1d_cache(i)->line_size);
425 }
426}
427
428TEST(L1D, flags) {
429 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
430 ASSERT_EQ(0, cpuinfo_get_l1d_cache(i)->flags);
431 }
432}
433
434TEST(L1D, processors) {
435 for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) {
436 ASSERT_EQ(i, cpuinfo_get_l1d_cache(i)->processor_start);
437 ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->processor_count);
438 }
439}
440
441TEST(L2, count) {
442 ASSERT_EQ(2, cpuinfo_get_l2_caches_count());
443}
444
445TEST(L2, non_null) {
446 ASSERT_TRUE(cpuinfo_get_l2_caches());
447}
448
449TEST(L2, size) {
450 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
451 switch (i) {
452 case 0:
453 ASSERT_EQ(1024 * 1024, cpuinfo_get_l2_cache(i)->size);
454 break;
455 case 1:
456 ASSERT_EQ(512 * 1024, cpuinfo_get_l2_cache(i)->size);
457 break;
458 }
459 }
460}
461
462TEST(L2, associativity) {
463 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
464 ASSERT_EQ(16, cpuinfo_get_l2_cache(i)->associativity);
465 }
466}
467
468TEST(L2, sets) {
469 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
470 ASSERT_EQ(cpuinfo_get_l2_cache(i)->size,
471 cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity);
472 }
473}
474
475TEST(L2, partitions) {
476 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
477 ASSERT_EQ(1, cpuinfo_get_l2_cache(i)->partitions);
478 }
479}
480
481TEST(L2, line_size) {
482 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
483 ASSERT_EQ(64, cpuinfo_get_l2_cache(i)->line_size);
484 }
485}
486
487TEST(L2, flags) {
488 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
489 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->flags);
490 }
491}
492
493TEST(L2, processors) {
494 for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) {
495 switch (i) {
496 case 0:
497 ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->processor_start);
498 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_count);
499 break;
500 case 1:
501 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_start);
502 ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->processor_count);
503 break;
504 }
505 }
506}
507
508TEST(L3, none) {
509 ASSERT_EQ(0, cpuinfo_get_l3_caches_count());
510 ASSERT_FALSE(cpuinfo_get_l3_caches());
511}
512
513TEST(L4, none) {
514 ASSERT_EQ(0, cpuinfo_get_l4_caches_count());
515 ASSERT_FALSE(cpuinfo_get_l4_caches());
516}
517
518#include <xiaomi-redmi-note-4.h>
519
520int main(int argc, char* argv[]) {
521#if CPUINFO_ARCH_ARM
522 cpuinfo_set_hwcap(UINT32_C(0x0037B0D6));
523 cpuinfo_set_hwcap2(UINT32_C(0x0000001F));
524#elif CPUINFO_ARCH_ARM64
525 cpuinfo_set_hwcap(UINT32_C(0x000000FF));
526#endif
527 cpuinfo_mock_filesystem(filesystem);
528#ifdef __ANDROID__
529 cpuinfo_mock_android_properties(properties);
Marat Dukhanfd0f3ef2017-12-18 17:45:18 -0800530 cpuinfo_mock_gl_renderer("Adreno (TM) 506");
Marat Dukhana5fda232017-12-04 16:08:25 -0800531#endif
532 cpuinfo_initialize();
533 ::testing::InitGoogleTest(&argc, argv);
534 return RUN_ALL_TESTS();
535}