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gerrit-public.fairphone.software / platform / external / elfutils / ee67b64540a734fec61a103e17e48d24f52ad2a3 / . / libcpu / defs / i386
blob: f32aac9a49804ed7298dd413cace76d6cfad9a76 [file] [log] [blame]
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]1%mask {s} 1
2%mask {w} 1
3%mask {w1} 1
4dnl floating point reg suffix
5%mask {D} 1
6%mask {imm8} 8
7%mask {imms8} 8
8%mask {imm16} 16
9%mask {reg} 3
10%mask {reg16} 3
11%mask {tttn} 4
12%mask {gg} 2
13%mask {mod} 2
14%mask {moda} 2
15%mask {MOD} 2
16%mask {r_m} 3
17dnl like {r_m} but referencing byte register
18%mask {8r_m} 3
19dnl like {r_m} but referencing 16-bit register
20%mask {16r_m} 3
21%mask {disp8} 8
22dnl imm really is 8/16/32 bit depending on the situation.
23%mask {imm} 8
24%mask {imms} 8
25%mask {rel} 32
26%mask {abs} 32
27%mask {absval} 32
28%mask {sel} 16
29%mask {imm32} 32
30%mask {ccc} 3
31%mask {ddd} 3
32%mask {sreg3} 3
33%mask {sreg2} 2
34%mask {mmxreg} 3
35%mask {mmxreg2} 3
36%mask {R_M} 3
37%mask {0g} 2
38%mask {GG} 2
39%mask {gG} 2
40%mask {Mod} 2
41%mask {xmmreg} 3
42%mask {R_m} 3
43%mask {mmreg} 3
44%mask {xmmreg1} 3
45%mask {xmmreg2} 3
46%mask {predpd} 8
47%mask {predps} 8
48%mask {predsd} 8
49%mask {predss} 8
50%mask {freg} 3
51%mask {fmod} 2
52%mask {fr_m} 3
53%prefix {R}
54%prefix {RE}
55%suffix {W}
56%suffix {w0}
57%synonym {xmmreg1} {xmmreg}
58%synonym {xmmreg2} {xmmreg}
59
60%%
61ifdef(`i386',
62`00110111:aaa
6311010101,00001010:aad
6411010100,00001010:aam
6500111111:aas
66')dnl
670001010{w},{imm}:adc {imm}{w},{ax}{w}
681000000{w},{mod}010{r_m},{imm}:adc{w} {imm}{w},{mod}{r_m}{w}
691000001{w},{mod}010{r_m},{imms8}:adc{w} {imms8},{mod}{r_m}
700001000{w},{mod}{reg}{r_m}:adc {reg}{w},{mod}{r_m}
710001001{w},{mod}{reg}{r_m}:adc {mod}{r_m},{reg}{w}
720000010{w},{imm}:add {imm}{w},{ax}{w}
731000000{w},{mod}000{r_m},{imm}:add{w} {imm}{w},{mod}{r_m}{w}
7410000011,{mod}000{r_m},{imms8}:add{w0} {imms8},{mod}{r_m}
750000000{w},{mod}{reg}{r_m}:add {reg}{w},{mod}{r_m}
760000001{w},{mod}{reg}{r_m}:add {mod}{r_m},{reg}{w}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]7701100110,00001111,11010000,{Mod}{xmmreg}{R_m}:addsubpd {Mod}{R_m},{xmmreg}
7811110010,00001111,11010000,{Mod}{xmmreg}{R_m}:addsubps {Mod}{R_m},{xmmreg}
790010010{w},{imm}:and {imm}{w},{ax}{w}
801000000{w},{mod}100{r_m},{imm}:and{w} {imm}{w},{mod}{r_m}{w}
811000001{w},{mod}100{r_m},{imms}:and{w} {imms},{mod}{r_m}
820010000{w},{mod}{reg}{r_m}:and {reg}{w},{mod}{r_m}{w}
830010001{w},{mod}{reg}{r_m}:and {mod}{r_m}{w},{reg}{w}
8401100110,00001111,01010100,{Mod}{xmmreg}{R_m}:andpd {Mod}{R_m},{xmmreg}
8500001111,01010100,{Mod}{xmmreg}{R_m}:andps {Mod}{R_m},{xmmreg}
8601100110,00001111,01010101,{Mod}{xmmreg}{R_m}:andnpd {Mod}{R_m},{xmmreg}
8700001111,01010101,{Mod}{xmmreg}{R_m}:andnps {Mod}{R_m},{xmmreg}
88ifdef(`i386',
89`01100011,{mod}{reg16}{r_m}:arpl {reg16},{mod}{r_m}
9001100010,{moda}{reg}{r_m}:bound {reg},{moda}{r_m}
91')dnl
9200001111,10111100,{mod}{reg}{r_m}:bsf {reg},{mod}{r_m}
9300001111,10111101,{mod}{reg}{r_m}:bsr {reg},{mod}{r_m}
9400001111,11001{reg}:bswap {reg}
9500001111,10100011,{mod}{reg}{r_m}:bt {reg},{mod}{r_m}
9600001111,10111010,{mod}100{r_m},{imm8}:bt {imm8},{mod}{r_m}
9700001111,10111011,{mod}{reg}{r_m}:btc {reg},{mod}{r_m}
9800001111,10111010,{mod}111{r_m},{imm8}:btc {imm8},{mod}{r_m}
9900001111,10110011,{mod}{reg}{r_m}:btr {reg},{mod}{r_m}
10000001111,10111010,{mod}110{r_m},{imm8}:btr {imm8},{mod}{r_m}
10100001111,10101011,{mod}{reg}{r_m}:bts {reg},{mod}{r_m}
10200001111,10111010,{mod}101{r_m},{imm8}:bts {imm8},{mod}{r_m}
10311101000,{rel}:call {rel}
10411111111,{mod}010{r_m}:call *{mod}{r_m}
105ifdef(`i386',
106`10011010,{absval},{sel}:lcall {sel},{absval}
107')dnl
10811111111,{mod}011{r_m}:lcall *{mod}{r_m}
109# SPECIAL 10011000:[{rex.w}?cltq:{dpfx}?cbtw:cwtl]
11010011000:INVALID
111# SPECIAL 10011001:[{rew.w}?cqto:{dpfx}?cltd:cwtd]
11210011001:INVALID
11311111000:clc
11411111100:cld
11500001111,10101110,{mod}111{r_m}:clflush {mod}{r_m}
11611111010:cli
11700001111,00000101:syscall
11800001111,00000110:clts
11900001111,00000111:sysret
12000001111,00110100:sysenter
12100001111,00110101:sysexit
12211110101:cmc
12300001111,0100{tttn},{mod}{reg}{r_m}:cmov{tttn} {mod}{r_m},{reg}
1240011110{w},{imm}:cmp {imm}{w},{ax}{w}
1251000000{w},{mod}111{r_m},{imm}:cmp{w} {imm}{w},{mod}{r_m}{w}
12610000011,{mod}111{r_m},{imms8}:cmp{w0} {imms8},{mod}{r_m}
1270011100{w},{mod}{reg}{r_m}:cmp {reg}{w},{mod}{r_m}{w}
1280011101{w},{mod}{reg}{r_m}:cmp {mod}{r_m}{w},{reg}{w}
12901100110,00001111,11000010,{Mod}{xmmreg}{R_m},{predpd}:cmpl{predpd} {Mod}{R_m},{xmmreg}
130ifdef(`ASSEMBLER',
131`01100110,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmppd {imm8},{Mod}{R_m},{xmmreg
132}')dnl
13300001111,11000010,{Mod}{xmmreg}{R_m},{predps}:cmpl{predps} {Mod}{R_m},{xmmreg}
134ifdef(`ASSEMBLER',
135`00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpps {imm8},{Mod}{R_m},{xmmreg}
136')dnl
1371010011{w}:{RE}cmps{w} {es_di},{ds_si}
13811110010,00001111,11000010,{Mod}{xmmreg}{R_m},{predsd}:cmpl{predsd} {Mod}{R_m},{xmmreg}
139ifdef(`ASSEMBLER',
140`11110010,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpsd {imm8},{Mod}{R_m},{xmmreg}
141')dnl
14211110011,00001111,11000010,{Mod}{xmmreg}{R_m},{predss}:cmpl{predss} {Mod}{R_m},{xmmreg}
143ifdef(`ASSEMBLER',
144`11110011,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpss {imm8},{Mod}{R_m},{xmmreg}
145')dnl
14600001111,1011000{w},{mod}{reg}{r_m}:cmpxchg{w} {reg},{mod}{r_m}
147# SPECIAL 00001111,11000111,{mod}001{r_m}:[{rex.w}?cmpxchg16b:cmpxchg8b] {reg},{mod}{r_m}
14800001111,10100010:cpuid
14911110011,00001111,11100110,{Mod}{xmmreg}{R_m}:cvtdq2pd {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]15011110010,00001111,11100110,{Mod}{xmmreg}{R_m}:cvtpd2dq {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]15101100110,00001111,11100110,{Mod}{xmmreg}{R_m}:cvttpd2dq {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]152ifdef(`i386',
153`00100111:daa
15400101111:das
155')dnl
1561111111{w},{mod}001{r_m}:dec{w} {mod}{r_m}{w}
157ifdef(`i386',
158`01001{reg}:dec {reg}
159')dnl
1601111011{w},{mod}110{r_m}:div{w} {mod}{r_m}{w}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]16100001111,01110111:emms
16211001000,{imm16},{imm8}:enter {imm16},{imm8}
16311011001,11010000:fnop
16411011001,11100000:fchs
16511011001,11100001:fabs
16611011001,11100100:ftst
16711011001,11100101:fxam
16811011001,11101000:fld1
16911011001,11101001:fldl2t
17011011001,11101010:fldl2e
17111011001,11101011:fldpi
17211011001,11101100:fldlg2
17311011001,11101101:fldln2
17411011001,11101110:fldz
17511011001,11110000:f2xm1
17611011001,11110001:fyl2x
17711011001,11110010:fptan
17811011001,11110011:fpatan
17911011001,11110100:fxtract
18011011001,11110101:fprem1
18111011001,11110110:fdecstp
18211011001,11110111:fincstp
18311011001,11111000:fprem
18411011001,11111001:fyl2xp1
18511011001,11111010:fsqrt
18611011001,11111011:fsincos
18711011001,11111100:frndint
18811011001,11111101:fscale
18911011001,11111110:fsin
19011011001,11111111:fcos
191# ORDER
19211011000,11000{freg}:fadd {freg},%st
19311011100,11000{freg}:fadd %st,{freg}
19411011{D}00,{mod}000{r_m}:fadd{D} {mod}{r_m}
195# ORDER END
196# ORDER
19711011000,11001{freg}:fmul {freg},%st
19811011100,11001{freg}:fmul %st,{freg}
19911011{D}00,{mod}001{r_m}:fmul{D} {mod}{r_m}
200# ORDER END
201# ORDER
20211011000,11100{freg}:fsub {freg},%st
20311011100,11100{freg}:fsub %st,{freg}
20411011{D}00,{mod}100{r_m}:fsub{D} {mod}{r_m}
205# ORDER END
206# ORDER
20711011000,11101{freg}:fsubr {freg},%st
20811011100,11101{freg}:fsubr %st,{freg}
20911011{D}00,{mod}101{r_m}:fsubr{D} {mod}{r_m}
210# ORDER END
211# ORDER
21211011101,11010{freg}:fst {freg}
21311011{D}01,{mod}010{r_m}:fst{D} {mod}{r_m}
214# ORDER END
215# ORDER
21611011101,11011{freg}:fstp {freg}
21711011{D}01,{mod}011{r_m}:fstp{D} {mod}{r_m}
218# ORDER END
21911011001,{mod}100{r_m}:fldenv {mod}{r_m}
22011011001,{mod}101{r_m}:fldcw {mod}{r_m}
22111011001,{mod}110{r_m}:fnstenv {mod}{r_m}
22211011001,{mod}111{r_m}:fnstcw {mod}{r_m}
22311011001,11001{freg}:fxch {freg}
224# ORDER
22511011110,11000{freg}:faddp %st,{freg}
226ifdef(`ASSEMBLER',
227`11011110,11000001:faddp
228')dnl
229# ORDER
23011011010,11000{freg}:fcmovb {freg},%st
23111011{w1}10,{mod}000{r_m}:fiadd{w1} {mod}{r_m}
232# ORDER END
233# ORDER
23411011010,11001{freg}:fcmove {freg},%st
23511011110,11001{freg}:fmulp %st,{freg}
23611011{w1}10,{mod}001{r_m}:fimul{w1} {mod}{r_m}
237# ORDER END
238# ORDER
23911011110,11100{freg}:fsubp %st,{freg}
24011011{w1}10,{mod}100{r_m}:fisub{w1} {mod}{r_m}
241# ORDER END
242# ORDER
24311011110,11101{freg}:fsubrp %st,{freg}
24411011{w1}10,{mod}101{r_m}:fisubr{w1} {mod}{r_m}
245# ORDER END
246# ORDER
24711011111,11100000:fnstsw %ax
24811011111,{mod}100{r_m}:fbld {mod}{r_m}
249# ORDER END
250# ORDER
25111011111,11110{freg}:fcomip {freg},%st
25211011111,{mod}110{r_m}:fbstp {mod}{r_m}
253# ORDER END
25411011001,11100000:fchs
255# ORDER
25610011011,11011011,11100010:fclex
25710011011,11011011,11100011:finit
25810011011:fwait
259# END ORDER
26011011011,11100010:fnclex
26111011010,11000{freg}:fcmovb {freg},%st
26211011010,11001{freg}:fcmove {freg},%st
26311011010,11010{freg}:fcmovbe {freg},%st
26411011010,11011{freg}:fcmovu {freg},%st
26511011011,11000{freg}:fcmovnb {freg},%st
26611011011,11001{freg}:fcmovne {freg},%st
26711011011,11010{freg}:fcmovnbe {freg},%st
26811011011,11011{freg}:fcmovnu {freg},%st
269# ORDER
27011011000,11010{freg}:fcom {freg}
271ifdef(`ASSEMBLER',
272`11011000,11010001:fcom
273')dnl
27411011{D}00,{mod}010{r_m}:fcom{D} {mod}{r_m}
275# END ORDER
276# ORDER
27711011000,11011{freg}:fcomp {freg}
278ifdef(`ASSEMBLER',
279`11011000,11011001:fcomp
280')dnl
28111011{D}00,{mod}011{r_m}:fcomp{D} {mod}{r_m}
282# END ORDER
28311011110,11011001:fcompp
28411011011,11110{freg}:fcomi {freg},%st
28511011111,11110{freg}:fcomip {freg},%st
28611011011,11101{freg}:fucomi {freg},%st
28711011111,11101{freg}:fucomip {freg},%st
28811011001,11111111:fcos
28911011001,11110110:fdecstp
290# ORDER
29111011000,11110{freg}:fdiv {freg},%st
29211011100,11110{freg}:fdiv %st,{freg}
29311011{D}00,{mod}110{r_m}:fdiv{D} {mod}{r_m}
294# END ORDER
29511011010,{mod}110{r_m}:fidivl {mod}{r_m}
296# ORDER
29711011110,11110{freg}:fdivp %st,{freg}
29811011110,{mod}110{r_m}:fidiv {mod}{r_m}
299# END ORDER
30011011110,11111{freg}:fdivrp %st,{freg}
301ifdef(`ASSEMBLER',
302`11011110,11111001:fdivp
303')dnl
304# ORDER
30511011000,11111{freg}:fdivr {freg},%st
30611011100,11111{freg}:fdivr %st,{freg}
30711011{D}00,{mod}111{r_m}:fdivr{D} {mod}{r_m}
308# END ORDER
30911011010,{mod}111{r_m}:fidivrl {mod}{r_m}
31011011110,{mod}111{r_m}:fidivr {mod}{r_m}
31111011110,11110{freg}:fdivrp %st,{freg}
312ifdef(`ASSEMBLER',
313`11011110,11110001:fdivrp
314')dnl
31511011101,11000{freg}:ffree {freg}
31611011010,11010{freg}:fcmovbe {freg}
31711011{w1}10,{mod}010{r_m}:ficom{w1} {mod}{r_m}
31811011010,11011{freg}:fcmovu {freg}
31911011{w1}10,{mod}011{r_m}:ficomp{w1} {mod}{r_m}
32011011111,{mod}000{r_m}:fild {mod}{r_m}
32111011011,{mod}000{r_m}:fildl {mod}{r_m}
32211011111,{mod}101{r_m}:fildll {mod}{r_m}
32311011001,11110111:fincstp
32411011011,11100011:fninit
32511011{w1}11,{mod}010{r_m}:fist{w1} {mod}{r_m}
32611011{w1}11,{mod}011{r_m}:fistp{w1} {mod}{r_m}
32711011111,{mod}111{r_m}:fistpll {mod}{r_m}
32811011{w1}11,{mod}001{r_m}:fisttp{w1} {mod}{r_m}
32911011101,{mod}001{r_m}:fisttpll {mod}{r_m}
33011011011,{mod}101{r_m}:fldt {mod}{r_m}
33111011011,{mod}111{r_m}:fstpt {mod}{r_m}
332# ORDER
33311011001,11000{freg}:fld {freg}
33411011{D}01,{mod}000{r_m}:fld{D} {mod}{r_m}
335# ORDER END
336# ORDER
33711011101,11100{freg}:fucom {freg}
33811011101,{mod}100{r_m}:frstor {mod}{r_m}
339# ORDER END
34011011101,11101{freg}:fucomp {freg}
34111011101,{mod}110{r_m}:fnsave {mod}{r_m}
34211011101,{mod}111{r_m}:fnstsw {mod}{r_m}
343#
344#
345#
34611110100:hlt
3471111011{w},{mod}111{r_m}:idiv{w} {mod}{r_m}{w}
3481111011{w},{mod}101{r_m}:imul{w} {mod}{r_m}{w}
34900001111,10101111,{mod}{reg}{r_m}:imul {reg},{mod}{r_m}
350011010{s}1,{mod}{reg}{r_m},{imm}:imul {imm}{s},{mod}{r_m},{reg}
3511110010{w},{imm8}:in {imm8},{ax}{w}
3521110110{w}:in {dx},{ax}{w}
3531111111{w},{mod}000{r_m}:inc{w} {mod}{r_m}{w}
35401000{reg}:inc {reg}
3550110110{w}:{R}ins{w} {dx},{es_di}
35611001101,{imm8}:int {imm8}
35711001100:int3
35811001110:into
35900001111,00001000:invd
360# ORDER
36100001111,00000001,11111000:swapgs
36200001111,00000001,{mod}111{r_m}:invlpg {mod}{r_m}
363# ORDER END
36411001111:iret{W}
3650111{tttn},{disp8}:j{tttn} {disp8}
36600001111,1000{tttn},{rel}:j{tttn} {rel}
36700001111,1001{tttn},{mod}000{8r_m}:set{tttn} {mod}{8r_m}
368# SPECIAL 11100011,{disp8}:[{dpfx}?jcxz:jecxz] {disp8}
36911100011,{disp8}:INVALID {disp8}
37011101011,{disp8}:jmp {disp8}
37111101001,{rel}:jmp {rel}
37211111111,{mod}100{r_m}:jmp *{mod}{r_m}
37311101010,{absval},{sel}:ljmp {sel},{absval}
37411111111,{mod}101{r_m}:ljmp *{mod}{r_m}
37510011111:lahf
37600001111,00000010,{mod}{reg}{16r_m}:lar {mod}{16r_m},{reg}
37711000101,{mod}{reg}{r_m}:lds {mod}{r_m},{reg}
37810001101,{mod}{reg}{r_m}:lea {mod}{r_m},{reg}
37911001001:leave
38011000100,{mod}{reg}{r_m}:les {mod}{r_m},{reg}
38100001111,10110100,{mod}{reg}{r_m}:lfs {mod}{r_m},{reg}
38200001111,00000001,{mod}010{r_m}:lgdt{w0} {mod}{r_m}
38300001111,10110101,{mod}{reg}{r_m}:lgs {mod}{r_m},{reg}
38400001111,00000001,{mod}011{r_m}:lidt{w0} {mod}{r_m}
38500001111,00000000,{mod}010{16r_m}:lldt {mod}{16r_m}
38600001111,00000001,{mod}110{16r_m}:lmsw {mod}{16r_m}
38711110000:lock
3881010110{w}:{R}lods {ds_si},{ax}{w}
38911100010,{disp8}:loop {disp8}
39011100001,{disp8}:loope {disp8}
39111100000,{disp8}:loopne {disp8}
39200001111,00000011,{mod}{reg}{16r_m}:lsl {mod}{16r_m},{reg}
39300001111,10110010,{mod}{reg}{r_m}:lss {mod}{r_m},{reg}
39400001111,00000000,{mod}011{16r_m}:ltr {mod}{16r_m}
3951000100{w},{mod}{reg}{r_m}:mov {reg}{w},{mod}{r_m}{w}
3961000101{w},{mod}{reg}{r_m}:mov {mod}{r_m}{w},{reg}{w}
3971100011{w},{mod}000{r_m},{imm}:mov{w} {imm}{w},{mod}{r_m}{w}
3981011{w}{reg},{imm}:mov {imm}{w},{reg}{w}
3991010000{w},{abs}:mov {abs},{ax}{w}
4001010001{w},{abs}:mov {ax}{w},{abs}
40100001111,00100000,11{ccc}{reg}:mov {ccc},{reg}
40200001111,00100010,11{ccc}{reg}:mov {reg},{ccc}
40300001111,00100001,11{ddd}{reg}:mov {ddd},{reg}
40400001111,00100011,11{ddd}{reg}:mov {reg},{ddd}
40510001100,{mod}{sreg3}{r_m}:mov {sreg3},{mod}{r_m}
40610001110,{mod}{sreg3}{r_m}:mov {mod}{r_m},{sreg3}
4071010010{w}:{R}movs{w} {ds_si},{es_di}
40800001111,1011111{w},{mod}{reg}{r_m}:movsx{w} {mod}{r_m},{reg}
40900001111,1011011{w},{mod}{reg}{r_m}:movzx{w} {mod}{r_m},{reg}
4101111011{w},{mod}100{r_m}:mul{w} {mod}{r_m}{w}
4111111011{w},{mod}011{r_m}:neg{w} {mod}{r_m}{w}
412ifdef(`ASSEMBLER',
413`10010000:nop
41411110011,10010000:pause
415',
416`10010000:{R}INVALID
417')dnl
4181111011{w},{mod}010{r_m}:not{w} {mod}{r_m}{w}
4190000100{w},{mod}{reg}{r_m}:or {reg}{w},{mod}{r_m}{w}
4200000101{w},{mod}{reg}{r_m}:or {mod}{r_m}{w},{reg}{w}
4211000000{w},{mod}001{r_m},{imm}:or{w} {imm}{w},{mod}{r_m}{w}
422100000{s}{w},{mod}001{r_m},{imm}:or{w} {imm}{s},{mod}{r_m}{w}
4230000110{w},{imm}:or {imm}{w},{ax}{w}
4241110011{w},{imm8}:out {ax}{w},{imm8}
4251110111{w}:out {ax}{w},{dx}
4260110111{w}:{R}outs{w} {ds_si},{dx}
42710001111,{mod}000{r_m}:pop{w} {mod}{r_m}
42801011{reg}:pop {reg}
42900001111,10{sreg3}001:pop {sreg3}
43001100001:popa{W}
43110011101:popf{W}
43211111111,{mod}110{r_m}:push{w} {mod}{r_m}
43301010{reg}:push {reg}
434011010{s}0,{imm}:push {imm}{s}
435000{sreg2}110:push {sreg2}
43600001111,10{sreg3}000:push {sreg3}
43701100000:pusha{W}
43810011100:pushf{W}
4391101000{w},{mod}010{r_m}:rcl{w} {mod}{r_m}{w}
4401101001{w},{mod}010{r_m}:rcl{w} %cl,{mod}{r_m}{w}
4411100000{w},{mod}010{r_m},{imm8}:rcl{w} {imm8},{mod}{r_m}{w}
4421101000{w},{mod}011{r_m}:rcr{w} {mod}{r_m}{w}
4431101001{w},{mod}011{r_m}:rcr{w} %cl,{mod}{r_m}{w}
4441100000{w},{mod}011{r_m},{imm8}:rcr{w} {imm8},{mod}{r_m}{w}
44500001111,00110010:rdmsr
44600001111,00110011:rdpmc
44700001111,00110001:rdtsc
44811000011:ret
44911000010,{imm16}:ret {imm16}
45011001011:lret
45111001010,{imm16}:lret {imm16}
4521101000{w},{mod}000{r_m}:rol{w} {mod}{r_m}{w}
4531101001{w},{mod}000{r_m}:rol{w} %cl,{mod}{r_m}{w}
4541100000{w},{mod}000{r_m},{imm8}:rol{w} {imm8},{mod}{r_m}{w}
4551101000{w},{mod}001{r_m}:ror{w} {mod}{r_m}{w}
4561101001{w},{mod}001{r_m}:ror{w} %cl,{mod}{r_m}{w}
4571100000{w},{mod}001{r_m},{imm8}:ror{w} {imm8},{mod}{r_m}{w}
45800001111,10101010:rsm
45910011110:sahf
4601101000{w},{mod}111{r_m}:sar{w} {mod}{r_m}{w}
4611101001{w},{mod}111{r_m}:sar{w} %cl,{mod}{r_m}{w}
4621100000{w},{mod}111{r_m},{imm8}:sar{w} {imm8},{mod}{r_m}{w}
4630001100{w},{mod}{reg}{r_m}:sbb {reg}{w},{mod}{r_m}{w}
4640001101{w},{mod}{reg}{r_m}:sbb {mod}{r_m}{w},{reg}{w}
4650001110{w},{imm}:sbb {imm}{w},{ax}{w}
4661000000{w},{mod}011{r_m},{imm}:sbb{w} {imm}{w},{mod}{r_m}{w}
4671000001{w},{mod}011{r_m},{imms}:sbb{w} {imms},{mod}{r_m}
4681010111{w}:{RE}scas {es_di},{ax}{w}
46900001111,1001{tttn},{mod}000{r_m}:set{tttn} {mod}{r_m}
4701101000{w},{mod}100{r_m}:shl{w} {mod}{r_m}{w}
4711101001{w},{mod}100{r_m}:shl{w} %cl,{mod}{r_m}{w}
4721100000{w},{mod}100{r_m},{imm8}:shl{w} {imm8},{mod}{r_m}{w}
4731101000{w},{mod}101{r_m}:shr{w} {mod}{r_m}{w}
47400001111,10100100,{mod}{reg}{r_m},{imm8}:shld {imm8},{reg},{mod}{r_m}
47500001111,10100101,{mod}{reg}{r_m}:shld %cl,{reg},{mod}{r_m}
4761101001{w},{mod}101{r_m}:shr{w} %cl,{mod}{r_m}{w}
4771100000{w},{mod}101{r_m},{imm8}:shr{w} {imm8},{mod}{r_m}{w}
47800001111,10101100,{mod}{reg}{r_m},{imm8}:shrd {imm8},{reg},{mod}{r_m}
47900001111,10101101,{mod}{reg}{r_m}:shrd %cl,{reg},{mod}{r_m}
480# ORDER
48100001111,00000001,11000001:vmcall
48200001111,00000001,11000010:vmlaunch
48300001111,00000001,11000011:vmresume
48400001111,00000001,11000100:vmxoff
48500001111,00000001,{mod}000{r_m}:sgdtl {mod}{r_m}
486# ORDER END
487# ORDER
48800001111,00000001,11001000:monitor %eax,%ecx,%edx
48900001111,00000001,11001001:mwait %eax,%ecx
49000001111,00000001,{mod}001{r_m}:sidtl {mod}{r_m}
491# ORDER END
49200001111,00000000,{mod}000{r_m}:sldt {mod}{r_m}
49300001111,00000001,{mod}100{r_m}:smsw {mod}{r_m}
49411111001:stc
49511111101:std
49611111011:sti
4971010101{w}:{R}stos {ax}{w},{es_di}
49800001111,00000000,{mod}001{r_m}:str {mod}{r_m}
4990010100{w},{mod}{reg}{r_m}:sub {reg}{w},{mod}{r_m}{w}
5000010101{w},{mod}{reg}{r_m}:sub {mod}{r_m}{w},{reg}{w}
5010010110{w},{imm}:sub {imm}{w},{ax}{w}
5021000000{w},{mod}101{r_m},{imm}:sub{w} {imm}{w},{mod}{r_m}{w}
5031000001{w},{mod}101{r_m},{imms}:sub{w} {imms},{mod}{r_m}
5041000010{w},{mod}{reg}{r_m}:test {reg}{w},{mod}{r_m}{w}
5051010100{w},{imm}:test {imm}{w},{ax}{w}
5061111011{w},{mod}000{r_m},{imm}:test{w} {imm}{w},{mod}{r_m}{w}
50700001111,00001011:ud2a
50800001111,00000000,{mod}100{16r_m}:verr {mod}{16r_m}
50900001111,00000000,{mod}101{16r_m}:verw {mod}{16r_m}
51000001111,00001001:wbinvd
51100001111,00001101,{mod}000{8r_m}:prefetch {mod}{8r_m}
51200001111,00001101,{mod}001{8r_m}:prefetchw {mod}{8r_m}
51300001111,00011000,{mod}000{r_m}:prefetchnta {mod}{r_m}
51400001111,00011000,{mod}001{r_m}:prefetcht0 {mod}{r_m}
51500001111,00011000,{mod}010{r_m}:prefetcht1 {mod}{r_m}
51600001111,00011000,{mod}011{r_m}:prefetcht2 {mod}{r_m}
51700001111,00011111,{mod}{reg}{r_m}:nop{w} {mod}{r_m}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]51800001111,00110000:wrmsr
51900001111,1100000{w},{mod}{reg}{r_m}:xadd{w} {reg},{mod}{r_m}
5201000011{w},{mod}{reg}{r_m}:xchg {reg}{w},{mod}{r_m}{w}
52110010{reg}:xchg {ax},{reg}
52211010111:xlat {ds_bx}
5230011000{w},{mod}{reg}{r_m}:xor {reg}{w},{mod}{r_m}{w}
5240011001{w},{mod}{reg}{r_m}:xor {mod}{r_m}{w},{reg}{w}
5250011010{w},{imm}:xor {imm}{w},{ax}{w}
5261000000{w},{mod}110{r_m},{imm}:xor{w} {imm}{w},{mod}{r_m}{w}
5271000001{w},{mod}110{r_m},{imms}:xor{w} {imms},{mod}{r_m}
52800001111,01110111:emms
52900001111,01101110,{mod}{mmxreg}{r_m}:movd {mod}{r_m},{mmxreg}
53000001111,01111110,{mod}{mmxreg}{r_m}:movd {mmxreg},{mod}{r_m}
53100001111,01101111,{MOD}{mmxreg}{R_M}:movq {MOD}{R_M},{mmxreg}
53200001111,01111111,{MOD}{mmxreg}{R_M}:movq {mmxreg},{MOD}{R_M}
53300001111,01101011,{MOD}{mmxreg}{R_M}:packssdw {MOD}{R_M},{mmxreg}
53400001111,01100011,{MOD}{mmxreg}{R_M}:packsswb {MOD}{R_M},{mmxreg}
53500001111,01100111,{MOD}{mmxreg}{R_M}:packuswb {MOD}{R_M},{mmxreg}
53600001111,111111{gg},{MOD}{mmxreg}{R_M}:padd{gg} {MOD}{R_M},{mmxreg}
53700001111,111111{0g},{MOD}{mmxreg}{R_M}:padds{0g} {MOD}{R_M},{mmxreg}
53800001111,110111{0g},{MOD}{mmxreg}{R_M}:paddus{0g} {MOD}{R_M},{mmxreg}
53900001111,11011011,{MOD}{mmxreg}{R_M}:pand {MOD}{R_M},{mmxreg}
54000001111,11011111,{MOD}{mmxreg}{R_M}:pandn {MOD}{R_M},{mmxreg}
54100001111,011101{gg},{MOD}{mmxreg}{R_M}:pcmpeq{gg} {MOD}{R_M},{mmxreg}
54200001111,011001{gg},{MOD}{mmxreg}{R_M}:pcmpgt{gg} {MOD}{R_M},{mmxreg}
54300001111,11110101,{MOD}{mmxreg}{R_M}:pmaddwd {MOD}{R_M},{mmxreg}
54400001111,11100101,{MOD}{mmxreg}{R_M}:pmulhw {MOD}{R_M},{mmxreg}
54500001111,11010101,{MOD}{mmxreg}{R_M}:pmullw {MOD}{R_M},{mmxreg}
54600001111,11101011,{MOD}{mmxreg}{R_M}:por {MOD}{R_M},{mmxreg}
54700001111,111100{GG},{MOD}{mmxreg}{R_M}:psll{GG} {MOD}{R_M},{mmxreg}
54800001111,011100{GG},11110{mmxreg},{imm8}:psll{GG} {imm8},{mmxreg}
54900001111,111000{gG},{MOD}{mmxreg}{R_M}:psra{gG} {MOD}{R_M},{mmxreg}
55000001111,011100{gG},11100{mmxreg},{imm8}:psra{gG} {imm8},{mmxreg}
55100001111,110100{GG},{MOD}{mmxreg}{R_M}:psrl{GG} {MOD}{R_M},{mmxreg}
55200001111,011100{GG},11010{mmxreg},{imm8}:psrl{GG} {imm8},{mmxreg}
55300001111,111110{gg},{MOD}{mmxreg}{R_M}:psub{gg} {MOD}{R_M},{mmxreg}
55400001111,111010{0g},{MOD}{mmxreg}{R_M}:psubs{0g} {MOD}{R_M},{mmxreg}
55500001111,110110{0g},{MOD}{mmxreg}{R_M}:psubus{0g} {MOD}{R_M},{mmxreg}
55600001111,011010{gg},{MOD}{mmxreg}{R_M}:punpckh{gg} {MOD}{R_M},{mmxreg}
55700001111,011000{gg},{MOD}{mmxreg}{R_M}:punpckl{gg} {MOD}{R_M},{mmxreg}
55800001111,11101111,{MOD}{mmxreg}{R_M}:pxor {MOD}{R_M},{mmxreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]55900001111,01010101,{Mod}{xmmreg}{R_m}:andnps {Mod}{R_m},{xmmreg}
56000001111,01010100,{Mod}{xmmreg}{R_m}:andps {Mod}{R_m},{xmmreg}
56100001111,11000010,{Mod}{xmmreg}{R_m},00000000:cmpeqps {Mod}{R_m},{xmmreg}
56200001111,11000010,{Mod}{xmmreg}{R_m},00000001:cmpltps {Mod}{R_m},{xmmreg}
56300001111,11000010,{Mod}{xmmreg}{R_m},00000010:cmpleps {Mod}{R_m},{xmmreg}
56400001111,11000010,{Mod}{xmmreg}{R_m},00000011:cmpunordps {Mod}{R_m},{xmmreg}
56500001111,11000010,{Mod}{xmmreg}{R_m},00000100:cmpneqps {Mod}{R_m},{xmmreg}
56600001111,11000010,{Mod}{xmmreg}{R_m},00000101:cmpnltps {Mod}{R_m},{xmmreg}
56700001111,11000010,{Mod}{xmmreg}{R_m},00000110:cmpnleps {Mod}{R_m},{xmmreg}
56800001111,11000010,{Mod}{xmmreg}{R_m},00000111:cmpordps {Mod}{R_m},{xmmreg}
56911110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000000:cmpeqss {Mod}{R_m},{xmmreg}
57011110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000001:cmpltss {Mod}{R_m},{xmmreg}
57111110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000010:cmpless {Mod}{R_m},{xmmreg}
57211110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000011:cmpunordss {Mod}{R_m},{xmmreg}
57311110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000100:cmpneqss {Mod}{R_m},{xmmreg}
57411110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000101:cmpnltss {Mod}{R_m},{xmmreg}
57511110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000110:cmpnless {Mod}{R_m},{xmmreg}
57611110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000111:cmpordss {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]57700001111,10101110,{mod}001{r_m}:fxrstor {mod}{r_m}
57800001111,10101110,{mod}000{r_m}:fxsave {mod}{r_m}
57900001111,10101110,{mod}010{r_m}:ldmxcsr {mod}{r_m}
Ulrich Drepper515d8d72008-01-03 07:41:03 +0000[diff] [blame]58011110010,00001111,00010000,{Mod}{xmmreg}{R_m}:movsd {Mod}{R_m},{xmmreg}
58111110011,00001111,00010000,{Mod}{xmmreg}{R_m}:movss {Mod}{R_m},{xmmreg}
58201100110,00001111,00010000,{Mod}{xmmreg}{R_m}:movupd {Mod}{R_m},{xmmreg}
58300001111,00010000,{Mod}{xmmreg}{R_m}:movups {Mod}{R_m},{xmmreg}
58411110010,00001111,00010001,{Mod}{xmmreg}{R_m}:movsd {xmmreg},{Mod}{R_m}
58511110011,00001111,00010001,{Mod}{xmmreg}{R_m}:movss {xmmreg},{Mod}{R_m}
58601100110,00001111,00010001,{Mod}{xmmreg}{R_m}:movupd {xmmreg},{Mod}{R_m}
58700001111,00010001,{Mod}{xmmreg}{R_m}:movups {xmmreg},{Mod}{R_m}
58811110010,00001111,00010010,{Mod}{xmmreg}{R_m}:movddup {Mod}{R_m},{xmmreg}
58911110011,00001111,00010010,{Mod}{xmmreg}{R_m}:movsldup {Mod}{R_m},{xmmreg}
59001100110,00001111,00010010,{Mod}{xmmreg}{R_m}:movlpd {Mod}{R_m},{xmmreg}
59100001111,00010010,11{xmmreg1}{xmmreg2}:movhlps {xmmreg2},{xmmreg1}
59200001111,00010010,{Mod}{xmmreg}{R_m}:movlps {Mod}{R_m},{xmmreg}
59301100110,00001111,00010011,11{xmmreg1}{xmmreg2}:movhlpd {xmmreg1},{xmmreg2}
59400001111,00010011,11{xmmreg1}{xmmreg2}:movhlps {xmmreg1},{xmmreg2}
59501100110,00001111,00010011,{Mod}{xmmreg}{R_m}:movlpd {xmmreg},{Mod}{R_m}
59600001111,00010011,{Mod}{xmmreg}{R_m}:movlps {xmmreg},{Mod}{R_m}
59701100110,00001111,00010100,{Mod}{xmmreg}{R_m}:unpcklpd {Mod}{R_m},{xmmreg}
59800001111,00010100,{Mod}{xmmreg}{R_m}:unpcklps {Mod}{R_m},{xmmreg}
59901100110,00001111,00010101,{Mod}{xmmreg}{R_m}:unpckhpd {Mod}{R_m},{xmmreg}
60000001111,00010101,{Mod}{xmmreg}{R_m}:unpckhps {Mod}{R_m},{xmmreg}
60111110011,00001111,00010110,{Mod}{xmmreg}{R_m}:movshdup {Mod}{R_m},{xmmreg}
60201100110,00001111,00010110,{Mod}{xmmreg}{R_m}:movhpd {Mod}{R_m},{xmmreg}
60300001111,00010110,11{xmmreg1}{xmmreg2}:movlhps {xmmreg2},{xmmreg1}
60400001111,00010110,{Mod}{xmmreg}{R_m}:movhps {Mod}{R_m},{xmmreg}
60501100110,00001111,00010111,11{xmmreg1}{xmmreg2}:movlhpd {xmmreg1},{xmmreg2}
60600001111,00010111,11{xmmreg1}{xmmreg2}:movlhps {xmmreg1},{xmmreg2}
60701100110,00001111,00010111,{Mod}{xmmreg}{R_m}:movhpd {xmmreg},{Mod}{R_m}
60800001111,00010111,{Mod}{xmmreg}{R_m}:movhps {xmmreg},{Mod}{R_m}
60901100110,00001111,00101000,{Mod}{xmmreg}{R_m}:movapd {Mod}{R_m},{xmmreg}
61000001111,00101000,{Mod}{xmmreg}{R_m}:movaps {Mod}{R_m},{xmmreg}
61101100110,00001111,00101001,{Mod}{xmmreg}{R_m}:movapd {xmmreg},{Mod}{R_m}
61200001111,00101001,{Mod}{xmmreg}{R_m}:movaps {xmmreg},{Mod}{R_m}
61311110010,00001111,00101010,{mod}{xmmreg}{r_m}:cvtsi2sd {mod}{r_m},{xmmreg}
61411110011,00001111,00101010,{mod}{xmmreg}{r_m}:cvtsi2ss {mod}{r_m},{xmmreg}
61501100110,00001111,00101010,{MOD}{xmmreg}{R_M}:cvtpi2pd {MOD}{R_M},{xmmreg}
61600001111,00101010,{MOD}{xmmreg}{R_M}:cvtpi2ps {MOD}{R_M},{xmmreg}
61701100110,00001111,00101011,{mod}{xmmreg}{r_m}:movntpd {xmmreg},{mod}{r_m}
61800001111,00101011,{mod}{xmmreg}{r_m}:movntps {xmmreg},{mod}{r_m}
61911110010,00001111,00101100,{Mod}{reg}{R_m}:cvttsd2si {Mod}{R_m},{reg}
62011110011,00001111,00101100,{Mod}{reg}{R_m}:cvttss2si {Mod}{R_m},{reg}
62101100110,00001111,00101100,{Mod}{mmxreg}{R_m}:cvttpd2pi {Mod}{R_m},{mmxreg}
62200001111,00101100,{Mod}{mmxreg}{R_m}:cvttps2pi {Mod}{R_m},{mmxreg}
62301100110,00001111,00101101,{Mod}{mmxreg}{R_m}:cvtpd2pi {Mod}{R_m},{mmxreg}
62411110010,00001111,00101101,{Mod}{reg}{R_m}:cvtsd2si {Mod}{R_m},{reg}
62511110011,00001111,00101101,{Mod}{reg}{R_m}:cvtss2si {Mod}{R_m},{reg}
62600001111,00101101,{Mod}{mmxreg}{R_m}:cvtps2pi {Mod}{R_m},{mmxreg}
62701100110,00001111,00101110,{Mod}{xmmreg}{R_m}:ucomisd {Mod}{R_m},{xmmreg}
62800001111,00101110,{Mod}{xmmreg}{R_m}:ucomiss {Mod}{R_m},{xmmreg}
62901100110,00001111,00101111,{Mod}{xmmreg}{R_m}:comisd {Mod}{R_m},{xmmreg}
63000001111,00101111,{Mod}{xmmreg}{R_m}:comiss {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]63100001111,00110111:getsec
Ulrich Drepper515d8d72008-01-03 07:41:03 +0000[diff] [blame]63201100110,00001111,01010000,11{reg}{xmmreg}:movmskpd {xmmreg},{reg}
63300001111,01010000,11{reg}{xmmreg}:movmskps {xmmreg},{reg}
63401100110,00001111,01010001,{Mod}{xmmreg}{R_m}:sqrtpd {Mod}{R_m},{xmmreg}
63511110010,00001111,01010001,{Mod}{xmmreg}{R_m}:sqrtsd {Mod}{R_m},{xmmreg}
63611110011,00001111,01010001,{Mod}{xmmreg}{R_m}:sqrtss {Mod}{R_m},{xmmreg}
63700001111,01010001,{Mod}{xmmreg}{R_m}:sqrtps {Mod}{R_m},{xmmreg}
63811110011,00001111,01010010,{Mod}{xmmreg}{R_m}:rsqrtss {Mod}{R_m},{xmmreg}
63900001111,01010010,{Mod}{xmmreg}{R_m}:rsqrtps {Mod}{R_m},{xmmreg}
64011110011,00001111,01010011,{Mod}{xmmreg}{R_m}:rcpss {Mod}{R_m},{xmmreg}
64100001111,01010011,{Mod}{xmmreg}{R_m}:rcpps {Mod}{R_m},{xmmreg}
Ulrich Drepperee67b642008-01-03 08:45:10 +0000[diff] [blame^]64201100110,00001111,01010100,{Mod}{xmmreg}{R_m}:andpd {Mod}{R_m},{xmmreg}
64300001111,01010100,{Mod}{xmmreg}{R_m}:andps {Mod}{R_m},{xmmreg}
64401100110,00001111,01010101,{Mod}{xmmreg}{R_m}:andnpd {Mod}{R_m},{xmmreg}
64500001111,01010101,{Mod}{xmmreg}{R_m}:andnps {Mod}{R_m},{xmmreg}
64601100110,00001111,01010110,{Mod}{xmmreg}{R_m}:orpd {Mod}{R_m},{xmmreg}
64700001111,01010110,{Mod}{xmmreg}{R_m}:orps {Mod}{R_m},{xmmreg}
64801100110,00001111,01010111,{Mod}{xmmreg}{R_m}:xorpd {Mod}{R_m},{xmmreg}
64900001111,01010111,{Mod}{xmmreg}{R_m}:xorps {Mod}{R_m},{xmmreg}
65011110010,00001111,01011000,{Mod}{xmmreg}{R_m}:addsd {Mod}{R_m},{xmmreg}
65111110011,00001111,01011000,{Mod}{xmmreg}{R_m}:addss {Mod}{R_m},{xmmreg}
65201100110,00001111,01011000,{Mod}{xmmreg}{R_m}:addpd {Mod}{R_m},{xmmreg}
65300001111,01011000,{Mod}{xmmreg}{R_m}:addps {Mod}{R_m},{xmmreg}
65411110010,00001111,01011001,{Mod}{xmmreg}{R_m}:mulsd {Mod}{R_m},{xmmreg}
65511110011,00001111,01011001,{Mod}{xmmreg}{R_m}:mulss {Mod}{R_m},{xmmreg}
65601100110,00001111,01011001,{Mod}{xmmreg}{R_m}:mulpd {Mod}{R_m},{xmmreg}
65700001111,01011001,{Mod}{xmmreg}{R_m}:mulps {Mod}{R_m},{xmmreg}
65811110010,00001111,01011010,{Mod}{xmmreg}{R_m}:cvtsd2ss {Mod}{R_m},{xmmreg}
65911110011,00001111,01011010,{Mod}{xmmreg}{R_m}:cvtss2sd {Mod}{R_m},{xmmreg}
66001100110,00001111,01011010,{Mod}{xmmreg}{R_m}:cvtpd2ps {Mod}{R_m},{xmmreg}
66100001111,01011010,{Mod}{xmmreg}{R_m}:cvtps2pd {Mod}{R_m},{xmmreg}
66201100110,00001111,01011011,{Mod}{xmmreg}{R_m}:cvtps2dq {Mod}{R_m},{xmmreg}
66311110011,00001111,01011011,{Mod}{xmmreg}{R_m}:cvttps2dq {Mod}{R_m},{xmmreg}
66400001111,01011011,{Mod}{xmmreg}{R_m}:cvtdq2ps {Mod}{R_m},{xmmreg}
66511110010,00001111,01011100,{Mod}{xmmreg}{R_m}:subsd {Mod}{R_m},{xmmreg}
66611110011,00001111,01011100,{Mod}{xmmreg}{R_m}:subss {Mod}{R_m},{xmmreg}
66701100110,00001111,01011100,{Mod}{xmmreg}{R_m}:subpd {Mod}{R_m},{xmmreg}
66800001111,01011100,{Mod}{xmmreg}{R_m}:subps {Mod}{R_m},{xmmreg}
66911110010,00001111,01011101,{Mod}{xmmreg}{R_m}:minsd {Mod}{R_m},{xmmreg}
67011110011,00001111,01011101,{Mod}{xmmreg}{R_m}:minss {Mod}{R_m},{xmmreg}
67101100110,00001111,01011101,{Mod}{xmmreg}{R_m}:minpd {Mod}{R_m},{xmmreg}
67200001111,01011101,{Mod}{xmmreg}{R_m}:minps {Mod}{R_m},{xmmreg}
67311110010,00001111,01011110,{Mod}{xmmreg}{R_m}:divsd {Mod}{R_m},{xmmreg}
67411110011,00001111,01011110,{Mod}{xmmreg}{R_m}:divss {Mod}{R_m},{xmmreg}
67501100110,00001111,01011110,{Mod}{xmmreg}{R_m}:divpd {Mod}{R_m},{xmmreg}
67600001111,01011110,{Mod}{xmmreg}{R_m}:divps {Mod}{R_m},{xmmreg}
67711110010,00001111,01011111,{Mod}{xmmreg}{R_m}:maxsd {Mod}{R_m},{xmmreg}
67811110011,00001111,01011111,{Mod}{xmmreg}{R_m}:maxss {Mod}{R_m},{xmmreg}
67901100110,00001111,01011111,{Mod}{xmmreg}{R_m}:maxpd {Mod}{R_m},{xmmreg}
68000001111,01011111,{Mod}{xmmreg}{R_m}:maxps {Mod}{R_m},{xmmreg}
Ulrich Drepper3cbdd382008-01-02 17:44:39 +0000[diff] [blame]681# ORDER:
682dnl Many previous entries depend on this being last.
683000{sreg2}111:pop {sreg2}
684# ORDER END: