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gerrit-public.fairphone.software / platform / external / ethtool / c1eaddf7add88f82a531b8211db5d2b55ddcddd4 / . / e1000.c
blob: afeb7f82ec0fe96d92e9899671facf46d0181fc1 [file] [log] [blame]
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]1/* Copyright (c) 2002 Intel Corporation */
2#include <stdio.h>
Ben Hutchings5ba70c02011-11-01 16:48:31 +0000[diff] [blame]3#include "internal.h"
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]4
5/* Register Bit Masks */
6/* Device Control */
7#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
8#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
9#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
10#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
11#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
12#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
13#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
14#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
15#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
16#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
17#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
18#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
19#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
20#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
21#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
22#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
23#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
24#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
25#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
26#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
27#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
28#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
29#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
30#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
31#define E1000_CTRL_RST 0x04000000 /* Global reset */
32#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
33#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
34#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
35#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
36#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
37
38/* Device Status */
39#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
40#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
41#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
42#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
43#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
44#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
45#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
46#define E1000_STATUS_SPEED_MASK 0x000000C0
47#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
48#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
49#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
50#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
51#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
52#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
53#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
54#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
55#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
56
57/* Constants used to intrepret the masked PCI-X bus speed. */
58#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
59#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
60#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
61
62/* Receive Control */
63#define E1000_RCTL_RST 0x00000001 /* Software reset */
64#define E1000_RCTL_EN 0x00000002 /* enable */
65#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
66#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
67#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
68#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
69#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
70#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
71#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
72#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
73#define E1000_RCTL_RDMTS 0x00000300 /* rx desc min threshold size */
74#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
75#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
76#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
77#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
78#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
79#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
80#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
81#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
82#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
83#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
84#define E1000_RCTL_SZ 0x00030000 /* rx buffer size */
85/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
86#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
87#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
88#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
89#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
90/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
91#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
92#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
93#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
94#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
95#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
96#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
97#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
98#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
99#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
100
101/* Transmit Control */
102#define E1000_TCTL_RST 0x00000001 /* software reset */
103#define E1000_TCTL_EN 0x00000002 /* enable tx */
104#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
105#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
106#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
107#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
108#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
109#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
110#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
111#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
112
Anthony DeRobertis94edb322010-03-19 00:32:29 -0400[diff] [blame]113/* M88E1000 PHY Specific Status Register */
114#define M88_PSSR_JABBER 0x0001 /* 1=Jabber */
115#define M88_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
116#define M88_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
117#define M88_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
118#define M88_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
119 * 3=110-140M;4=>140M */
120#define M88_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
121#define M88_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
122#define M88_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
123#define M88_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
124#define M88_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
125#define M88_PSSR_10MBS 0x0000 /* 00=10Mbs */
126#define M88_PSSR_100MBS 0x4000 /* 01=100Mbs */
127#define M88_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
128
129#define M88_PSSR_CL_0_50 (0<<7)
130#define M88_PSSR_CL_50_80 (1<<7)
131#define M88_PSSR_CL_80_110 (2<<7)
132#define M88_PSSR_CL_110_140 (3<<7)
133#define M88_PSSR_CL_140_PLUS (4<<7)
134
135/* M88E1000 PHY Specific Control Register */
136#define M88_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
137#define M88_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
138#define M88_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
139#define M88_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
140 * 0=CLK125 toggling
141 */
142#define M88_PSCR_MDI_MASK 0x0060
143#define M88_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
144 /* Manual MDI configuration */
145#define M88_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
146#define M88_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
147 * 100BASE-TX/10BASE-T:
148 * MDI Mode
149 */
150#define M88_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
151 * all speeds.
152 */
153#define M88_PSCR_10BT_EXT_DIST_ENABLE 0x0080
154 /* 1=Enable Extended 10BASE-T distance
155 * (Lower 10BASE-T RX Threshold)
156 * 0=Normal 10BASE-T RX Threshold */
157#define M88_PSCR_MII_5BIT_ENABLE 0x0100
158 /* 1=5-Bit interface in 100BASE-TX
159 * 0=MII interface in 100BASE-TX */
160#define M88_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
161#define M88_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
162#define M88_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
163
164#define M88_PSCR_POLARITY_REVERSAL_SHIFT 1
165#define M88_PSCR_AUTO_X_MODE_SHIFT 5
166#define M88_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
167
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]168/* PCI Device IDs */
Auke Kok96144b82007-01-19 14:49:57 -0800[diff] [blame]169#define E1000_DEV_ID_82542 0x1000
170#define E1000_DEV_ID_82543GC_FIBER 0x1001
171#define E1000_DEV_ID_82543GC_COPPER 0x1004
172#define E1000_DEV_ID_82544EI_COPPER 0x1008
173#define E1000_DEV_ID_82544EI_FIBER 0x1009
174#define E1000_DEV_ID_82544GC_COPPER 0x100C
175#define E1000_DEV_ID_82544GC_LOM 0x100D
176#define E1000_DEV_ID_82540EM 0x100E
177#define E1000_DEV_ID_82540EM_LOM 0x1015
178#define E1000_DEV_ID_82540EP_LOM 0x1016
179#define E1000_DEV_ID_82540EP 0x1017
180#define E1000_DEV_ID_82540EP_LP 0x101E
181#define E1000_DEV_ID_82545EM_COPPER 0x100F
182#define E1000_DEV_ID_82545EM_FIBER 0x1011
183#define E1000_DEV_ID_82545GM_COPPER 0x1026
184#define E1000_DEV_ID_82545GM_FIBER 0x1027
185#define E1000_DEV_ID_82545GM_SERDES 0x1028
186#define E1000_DEV_ID_82546EB_COPPER 0x1010
187#define E1000_DEV_ID_82546EB_FIBER 0x1012
188#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
189#define E1000_DEV_ID_82546GB_COPPER 0x1079
190#define E1000_DEV_ID_82546GB_FIBER 0x107A
191#define E1000_DEV_ID_82546GB_SERDES 0x107B
192#define E1000_DEV_ID_82546GB_PCIE 0x108A
193#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
194#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
195#define E1000_DEV_ID_82541EI 0x1013
196#define E1000_DEV_ID_82541EI_MOBILE 0x1018
197#define E1000_DEV_ID_82541ER_LOM 0x1014
198#define E1000_DEV_ID_82541ER 0x1078
199#define E1000_DEV_ID_82541GI 0x1076
200#define E1000_DEV_ID_82541GI_LF 0x107C
201#define E1000_DEV_ID_82541GI_MOBILE 0x1077
202#define E1000_DEV_ID_82547EI 0x1019
203#define E1000_DEV_ID_82547EI_MOBILE 0x101A
204#define E1000_DEV_ID_82547GI 0x1075
205#define E1000_DEV_ID_82571EB_COPPER 0x105E
206#define E1000_DEV_ID_82571EB_FIBER 0x105F
207#define E1000_DEV_ID_82571EB_SERDES 0x1060
208#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
209#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
210#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
211#define E1000_DEV_ID_82572EI_COPPER 0x107D
212#define E1000_DEV_ID_82572EI_FIBER 0x107E
213#define E1000_DEV_ID_82572EI_SERDES 0x107F
214#define E1000_DEV_ID_82572EI 0x10B9
215#define E1000_DEV_ID_82573E 0x108B
216#define E1000_DEV_ID_82573E_IAMT 0x108C
217#define E1000_DEV_ID_82573L 0x109A
218#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
219#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
220#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
221#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
222#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
223#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
224#define E1000_DEV_ID_ICH8_IGP_C 0x104B
225#define E1000_DEV_ID_ICH8_IFE 0x104C
226#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
227#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
228#define E1000_DEV_ID_ICH8_IGP_M 0x104D
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]229
230#define E1000_82542_2_0_REV_ID 2
231#define E1000_82542_2_1_REV_ID 3
232
233/* Enumerated types specific to the e1000 hardware */
234/* Media Access Controlers */
235enum e1000_mac_type {
236 e1000_undefined = 0,
Auke Kok96144b82007-01-19 14:49:57 -0800[diff] [blame]237 e1000_82542,
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]238 e1000_82543,
239 e1000_82544,
240 e1000_82540,
241 e1000_82545,
242 e1000_82545_rev_3,
243 e1000_82546,
244 e1000_82546_rev_3,
245 e1000_82541,
246 e1000_82541_rev_2,
247 e1000_82547,
248 e1000_82547_rev_2,
Auke Kok96144b82007-01-19 14:49:57 -0800[diff] [blame]249 e1000_82571,
250 e1000_82572,
Jesse Brandeburg26e7b972005-05-10 08:40:32 -0700[diff] [blame]251 e1000_82573,
Auke Kok96144b82007-01-19 14:49:57 -0800[diff] [blame]252 e1000_80003es2lan,
253 e1000_ich8lan,
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]254 e1000_num_macs
255};
256
257static enum e1000_mac_type
258e1000_get_mac_type(u16 device_id, u8 revision_id)
259{
260 enum e1000_mac_type mac_type = e1000_undefined;
261
262 switch (device_id) {
263 case E1000_DEV_ID_82542:
Auke Kok96144b82007-01-19 14:49:57 -0800[diff] [blame]264 mac_type = e1000_82542;
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]265 break;
266 case E1000_DEV_ID_82543GC_FIBER:
267 case E1000_DEV_ID_82543GC_COPPER:
268 mac_type = e1000_82543;
269 break;
270 case E1000_DEV_ID_82544EI_COPPER:
271 case E1000_DEV_ID_82544EI_FIBER:
272 case E1000_DEV_ID_82544GC_COPPER:
273 case E1000_DEV_ID_82544GC_LOM:
274 mac_type = e1000_82544;
275 break;
276 case E1000_DEV_ID_82540EM:
277 case E1000_DEV_ID_82540EM_LOM:
278 case E1000_DEV_ID_82540EP:
279 case E1000_DEV_ID_82540EP_LOM:
280 case E1000_DEV_ID_82540EP_LP:
281 mac_type = e1000_82540;
282 break;
283 case E1000_DEV_ID_82545EM_COPPER:
284 case E1000_DEV_ID_82545EM_FIBER:
285 mac_type = e1000_82545;
286 break;
287 case E1000_DEV_ID_82545GM_COPPER:
288 case E1000_DEV_ID_82545GM_FIBER:
289 case E1000_DEV_ID_82545GM_SERDES:
290 mac_type = e1000_82545_rev_3;
291 break;
292 case E1000_DEV_ID_82546EB_COPPER:
293 case E1000_DEV_ID_82546EB_FIBER:
294 case E1000_DEV_ID_82546EB_QUAD_COPPER:
295 mac_type = e1000_82546;
296 break;
297 case E1000_DEV_ID_82546GB_COPPER:
298 case E1000_DEV_ID_82546GB_FIBER:
299 case E1000_DEV_ID_82546GB_SERDES:
Jesse Brandeburg26e7b972005-05-10 08:40:32 -0700[diff] [blame]300 case E1000_DEV_ID_82546GB_PCIE:
301 case E1000_DEV_ID_82546GB_QUAD_COPPER:
Auke Kok96144b82007-01-19 14:49:57 -0800[diff] [blame]302 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]303 mac_type = e1000_82546_rev_3;
304 break;
305 case E1000_DEV_ID_82541EI:
306 case E1000_DEV_ID_82541EI_MOBILE:
Auke Kok96144b82007-01-19 14:49:57 -0800[diff] [blame]307 case E1000_DEV_ID_82541ER_LOM:
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]308 mac_type = e1000_82541;
309 break;
310 case E1000_DEV_ID_82541ER:
311 case E1000_DEV_ID_82541GI:
Jesse Brandeburg26e7b972005-05-10 08:40:32 -0700[diff] [blame]312 case E1000_DEV_ID_82541GI_LF:
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]313 case E1000_DEV_ID_82541GI_MOBILE:
314 mac_type = e1000_82541_rev_2;
315 break;
316 case E1000_DEV_ID_82547EI:
Auke Kok96144b82007-01-19 14:49:57 -0800[diff] [blame]317 case E1000_DEV_ID_82547EI_MOBILE:
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]318 mac_type = e1000_82547;
319 break;
320 case E1000_DEV_ID_82547GI:
321 mac_type = e1000_82547_rev_2;
322 break;
Auke Kok96144b82007-01-19 14:49:57 -0800[diff] [blame]323 case E1000_DEV_ID_82571EB_COPPER:
324 case E1000_DEV_ID_82571EB_FIBER:
325 case E1000_DEV_ID_82571EB_SERDES:
326 case E1000_DEV_ID_82571EB_QUAD_COPPER:
327 case E1000_DEV_ID_82571EB_QUAD_FIBER:
328 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
329 mac_type = e1000_82571;
330 break;
331 case E1000_DEV_ID_82572EI:
332 case E1000_DEV_ID_82572EI_COPPER:
333 case E1000_DEV_ID_82572EI_FIBER:
334 case E1000_DEV_ID_82572EI_SERDES:
335 mac_type = e1000_82572;
336 break;
Jesse Brandeburg26e7b972005-05-10 08:40:32 -0700[diff] [blame]337 case E1000_DEV_ID_82573E:
338 case E1000_DEV_ID_82573E_IAMT:
Auke Kok96144b82007-01-19 14:49:57 -0800[diff] [blame]339 case E1000_DEV_ID_82573L:
Jesse Brandeburg26e7b972005-05-10 08:40:32 -0700[diff] [blame]340 mac_type = e1000_82573;
341 break;
Auke Kok96144b82007-01-19 14:49:57 -0800[diff] [blame]342 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
343 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
344 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
345 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
346 mac_type = e1000_80003es2lan;
347 break;
348 case E1000_DEV_ID_ICH8_IFE:
349 case E1000_DEV_ID_ICH8_IFE_GT:
350 case E1000_DEV_ID_ICH8_IFE_G:
351 case E1000_DEV_ID_ICH8_IGP_M:
352 case E1000_DEV_ID_ICH8_IGP_M_AMT:
353 case E1000_DEV_ID_ICH8_IGP_AMT:
354 case E1000_DEV_ID_ICH8_IGP_C:
355 mac_type = e1000_ich8lan;
356 break;
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]357 default:
Auke Kok96144b82007-01-19 14:49:57 -0800[diff] [blame]358 /* assume old nic and attempt so user can get limited
359 * functionality */
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]360 mac_type = e1000_82543;
361 break;
362 }
363
364 return mac_type;
365}
366
367int
368e1000_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs)
369{
370 u32 *regs_buff = (u32 *)regs->data;
371 u16 hw_device_id = (u16)regs->version;
372 u8 hw_revision_id = (u8)(regs->version >> 16);
373 u8 version = (u8)(regs->version >> 24);
374 enum e1000_mac_type mac_type;
375 u32 reg;
376
Mark Einonfd215652013-01-22 21:04:50 +0000[diff] [blame]377 if (version != 1)
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]378 return -1;
379
380 mac_type = e1000_get_mac_type(hw_device_id, hw_revision_id);
381
382 if(mac_type == e1000_undefined)
383 return -1;
384
385 fprintf(stdout, "MAC Registers\n");
386 fprintf(stdout, "-------------\n");
387
388 /* Device control register */
389 reg = regs_buff[0];
390 fprintf(stdout,
391 "0x00000: CTRL (Device control register) 0x%08X\n"
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]392 " Endian mode (buffers): %s\n"
393 " Link reset: %s\n"
394 " Set link up: %s\n"
395 " Invert Loss-Of-Signal: %s\n"
396 " Receive flow control: %s\n"
397 " Transmit flow control: %s\n"
398 " VLAN mode: %s\n",
399 reg,
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]400 reg & E1000_CTRL_BEM ? "big" : "little",
401 reg & E1000_CTRL_LRST ? "reset" : "normal",
402 reg & E1000_CTRL_SLU ? "1" : "0",
403 reg & E1000_CTRL_ILOS ? "yes" : "no",
404 reg & E1000_CTRL_RFCE ? "enabled" : "disabled",
405 reg & E1000_CTRL_TFCE ? "enabled" : "disabled",
406 reg & E1000_CTRL_VME ? "enabled" : "disabled");
407 if(mac_type >= e1000_82543) {
408 fprintf(stdout,
409 " Auto speed detect: %s\n"
410 " Speed select: %s\n"
411 " Force speed: %s\n"
412 " Force duplex: %s\n",
413 reg & E1000_CTRL_ASDE ? "enabled" : "disabled",
414 (reg & E1000_CTRL_SPD_SEL) == E1000_CTRL_SPD_10 ? "10Mb/s" :
415 (reg & E1000_CTRL_SPD_SEL) == E1000_CTRL_SPD_100 ? "100Mb/s" :
416 (reg & E1000_CTRL_SPD_SEL) == E1000_CTRL_SPD_1000 ? "1000Mb/s" :
417 "not used",
418 reg & E1000_CTRL_FRCSPD ? "yes" : "no",
419 reg & E1000_CTRL_FRCDPX ? "yes" : "no");
420 }
421
422 /* Device status register */
423 reg = regs_buff[1];
424 fprintf(stdout,
425 "0x00008: STATUS (Device status register) 0x%08X\n"
426 " Duplex: %s\n"
427 " Link up: %s\n",
428 reg,
429 reg & E1000_STATUS_FD ? "full" : "half",
430 reg & E1000_STATUS_LU ? "link config" : "no link config");
Auke Kok96144b82007-01-19 14:49:57 -0800[diff] [blame]431 if (mac_type >= e1000_82571) {
Jesse Brandeburg26e7b972005-05-10 08:40:32 -0700[diff] [blame]432 fprintf(stdout,
433 " TBI mode: %s\n"
434 " Link speed: %s\n"
435 " Bus type: %s\n"
436 " Port number: %s\n",
437 reg & E1000_STATUS_TBIMODE ? "enabled" : "disabled",
438 (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_10 ?
439 "10Mb/s" :
440 (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_100 ?
441 "100Mb/s" :
442 (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_1000 ?
443 "1000Mb/s" : "not used",
444 "PCI Express",
445 (reg & E1000_STATUS_FUNC_MASK) == 0 ? "0" : "1");
446 }
Auke Kok96144b82007-01-19 14:49:57 -0800[diff] [blame]447 else if (mac_type >= e1000_82543) {
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]448 fprintf(stdout,
449 " TBI mode: %s\n"
450 " Link speed: %s\n"
451 " Bus type: %s\n"
452 " Bus speed: %s\n"
453 " Bus width: %s\n",
454 reg & E1000_STATUS_TBIMODE ? "enabled" : "disabled",
455 (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_10 ?
456 "10Mb/s" :
457 (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_100 ?
458 "100Mb/s" :
459 (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_1000 ?
460 "1000Mb/s" : "not used",
461 (reg & E1000_STATUS_PCIX_MODE) ? "PCI-X" : "PCI",
462 (reg & E1000_STATUS_PCIX_MODE) ?
463 ((reg & E1000_STATUS_PCIX_SPEED_133) ? "133MHz" :
464 (reg & E1000_STATUS_PCIX_SPEED_100) ? "100MHz" :
465 "66MHz") :
466 ((reg & E1000_STATUS_PCI66) ? "66MHz" : "33MHz"),
467 (reg & E1000_STATUS_BUS64) ? "64-bit" : "32-bit");
468 }
469
470 /* Receive control register */
471 reg = regs_buff[2];
472 fprintf(stdout,
473 "0x00100: RCTL (Receive control register) 0x%08X\n"
474 " Receiver: %s\n"
475 " Store bad packets: %s\n"
476 " Unicast promiscuous: %s\n"
477 " Multicast promiscuous: %s\n"
478 " Long packet: %s\n"
479 " Descriptor minimum threshold size: %s\n"
480 " Broadcast accept mode: %s\n"
481 " VLAN filter: %s\n"
Auke Kok9fecbca2006-09-08 16:13:30 -0700[diff] [blame]482 " Canonical form indicator: %s\n"
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]483 " Discard pause frames: %s\n"
484 " Pass MAC control frames: %s\n",
485 reg,
486 reg & E1000_RCTL_EN ? "enabled" : "disabled",
487 reg & E1000_RCTL_SBP ? "enabled" : "disabled",
488 reg & E1000_RCTL_UPE ? "enabled" : "disabled",
489 reg & E1000_RCTL_MPE ? "enabled" : "disabled",
490 reg & E1000_RCTL_LPE ? "enabled" : "disabled",
491 (reg & E1000_RCTL_RDMTS) == E1000_RCTL_RDMTS_HALF ? "1/2" :
492 (reg & E1000_RCTL_RDMTS) == E1000_RCTL_RDMTS_QUAT ? "1/4" :
493 (reg & E1000_RCTL_RDMTS) == E1000_RCTL_RDMTS_EIGTH ? "1/8" :
494 "reserved",
495 reg & E1000_RCTL_BAM ? "accept" : "ignore",
496 reg & E1000_RCTL_VFE ? "enabled" : "disabled",
497 reg & E1000_RCTL_CFIEN ? "enabled" : "disabled",
498 reg & E1000_RCTL_DPF ? "ignored" : "filtered",
499 reg & E1000_RCTL_PMCF ? "pass" : "don't pass");
500 if(mac_type >= e1000_82543) {
501 fprintf(stdout,
502 " Receive buffer size: %s\n",
503 reg & E1000_RCTL_BSEX ?
504 ((reg & E1000_RCTL_SZ)==E1000_RCTL_SZ_16384 ? "16384" :
505 (reg & E1000_RCTL_SZ)==E1000_RCTL_SZ_8192 ? "8192" :
506 (reg & E1000_RCTL_SZ)==E1000_RCTL_SZ_4096 ? "4096" :
507 "reserved") :
508 ((reg & E1000_RCTL_SZ)==E1000_RCTL_SZ_2048 ? "2048" :
509 (reg & E1000_RCTL_SZ)==E1000_RCTL_SZ_1024 ? "1024" :
510 (reg & E1000_RCTL_SZ)==E1000_RCTL_SZ_512 ? "512" :
511 "256"));
512 } else {
513 fprintf(stdout,
514 " Receive buffer size: %s\n",
515 (reg & E1000_RCTL_SZ) == E1000_RCTL_SZ_2048 ? "2048" :
516 (reg & E1000_RCTL_SZ) == E1000_RCTL_SZ_1024 ? "1024" :
517 (reg & E1000_RCTL_SZ) == E1000_RCTL_SZ_512 ? "512" :
518 "256");
519 }
520
521 /* Receive descriptor registers */
522 fprintf(stdout,
523 "0x02808: RDLEN (Receive desc length) 0x%08X\n",
524 regs_buff[3]);
525 fprintf(stdout,
526 "0x02810: RDH (Receive desc head) 0x%08X\n",
527 regs_buff[4]);
528 fprintf(stdout,
529 "0x02818: RDT (Receive desc tail) 0x%08X\n",
530 regs_buff[5]);
531 fprintf(stdout,
532 "0x02820: RDTR (Receive delay timer) 0x%08X\n",
533 regs_buff[6]);
534
535 /* Transmit control register */
536 reg = regs_buff[7];
537 fprintf(stdout,
538 "0x00400: TCTL (Transmit ctrl register) 0x%08X\n"
539 " Transmitter: %s\n"
540 " Pad short packets: %s\n"
541 " Software XOFF Transmission: %s\n",
542 reg,
543 reg & E1000_TCTL_EN ? "enabled" : "disabled",
544 reg & E1000_TCTL_PSP ? "enabled" : "disabled",
545 reg & E1000_TCTL_SWXOFF ? "enabled" : "disabled");
546 if(mac_type >= e1000_82543) {
547 fprintf(stdout,
548 " Re-transmit on late collision: %s\n",
549 reg & E1000_TCTL_RTLC ? "enabled" : "disabled");
550 }
551
552 /* Transmit descriptor registers */
553 fprintf(stdout,
554 "0x03808: TDLEN (Transmit desc length) 0x%08X\n",
555 regs_buff[8]);
556 fprintf(stdout,
557 "0x03810: TDH (Transmit desc head) 0x%08X\n",
558 regs_buff[9]);
559 fprintf(stdout,
560 "0x03818: TDT (Transmit desc tail) 0x%08X\n",
561 regs_buff[10]);
562 fprintf(stdout,
563 "0x03820: TIDV (Transmit delay timer) 0x%08X\n",
564 regs_buff[11]);
565
566 /* PHY type */
567 fprintf(stdout,
568 "PHY type: %s\n",
Jesse Brandeburg26e7b972005-05-10 08:40:32 -0700[diff] [blame]569 regs_buff[12] == 0 ? "M88" :
570 regs_buff[12] == 1 ? "IGP" :
571 regs_buff[12] == 2 ? "IGP2" : "unknown" );
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]572
Anthony DeRobertis94edb322010-03-19 00:32:29 -0400[diff] [blame]573 if (0 == regs_buff[12]) {
574 reg = regs_buff[13];
575 fprintf(stdout,
576 "M88 PHY STATUS REGISTER: 0x%08X\n"
577 " Jabber: %s\n"
578 " Polarity: %s\n"
579 " Downshifted: %s\n"
580 " MDI/MDIX: %s\n"
581 " Cable Length Estimate: %s meters\n"
582 " Link State: %s\n"
583 " Speed & Duplex Resolved: %s\n"
584 " Page Received: %s\n"
585 " Duplex: %s\n"
586 " Speed: %s mbps\n",
587 reg,
588 reg & M88_PSSR_JABBER ? "yes" : "no",
589 reg & M88_PSSR_REV_POLARITY ? "reverse" : "normal",
590 reg & M88_PSSR_DOWNSHIFT ? "yes" : "no",
591 reg & M88_PSSR_MDIX ? "MDIX" : "MDI",
592 ((reg & M88_PSSR_CABLE_LENGTH)==M88_PSSR_CL_0_50 ? "0-50"
593 : (reg & M88_PSSR_CABLE_LENGTH)==M88_PSSR_CL_50_80 ? "50-80"
594 : (reg & M88_PSSR_CABLE_LENGTH)==M88_PSSR_CL_80_110 ? "80-110"
595 : (reg & M88_PSSR_CABLE_LENGTH)==M88_PSSR_CL_110_140? "110-140"
596 : (reg & M88_PSSR_CABLE_LENGTH)==M88_PSSR_CL_140_PLUS ? "140+"
597 : "unknown"),
598 reg & M88_PSSR_LINK ? "Up" : "Down",
599 reg & M88_PSSR_SPD_DPLX_RESOLVED ? "Yes" : "No",
600 reg & M88_PSSR_PAGE_RCVD ? "Yes" : "No",
601 reg & M88_PSSR_DPLX ? "Full" : "Half",
602 ((reg & M88_PSSR_SPEED)==M88_PSSR_10MBS ? "10"
603 : (reg & M88_PSSR_SPEED)==M88_PSSR_100MBS ? "100"
604 : (reg & M88_PSSR_SPEED)==M88_PSSR_1000MBS ? "1000"
605 : "unknown")
606 );
607
608 reg = regs_buff[17];
609 fprintf(stdout,
610 "M88 PHY CONTROL REGISTER: 0x%08X\n"
Ville Skyttä500a9f42013-12-15 14:19:31 +0200[diff] [blame]611 " Jabber function: %s\n"
Anthony DeRobertis94edb322010-03-19 00:32:29 -0400[diff] [blame]612 " Auto-polarity: %s\n"
613 " SQE Test: %s\n"
614 " CLK125: %s\n"
615 " Auto-MDIX: %s\n"
616 " Extended 10Base-T Distance: %s\n"
617 " 100Base-TX Interface: %s\n"
618 " Scrambler: %s\n"
619 " Force Link Good: %s\n"
620 " Assert CRS on Transmit: %s\n",
621 reg,
622 reg & M88_PSCR_JABBER_DISABLE ? "disabled" : "enabled",
623 reg & M88_PSCR_POLARITY_REVERSAL ? "enabled" : "disabled",
624 reg & M88_PSCR_SQE_TEST ? "enabled" : "disabled",
625 reg & M88_PSCR_CLK125_DISABLE ? "disabled" : "enabled",
626 ((reg & M88_PSCR_MDI_MASK)==M88_PSCR_MDI_MANUAL_MODE ? "force MDI"
627 : (reg & M88_PSCR_MDI_MASK)==M88_PSCR_MDIX_MANUAL_MODE ? "force MDIX"
628 : (reg & M88_PSCR_MDI_MASK)==M88_PSCR_AUTO_X_1000T ? "1000 auto, 10/100 MDI"
629 : (reg & M88_PSCR_MDI_MASK)==M88_PSCR_AUTO_X_MODE ? "auto"
630 : "wtf"),
631 reg & M88_PSCR_10BT_EXT_DIST_ENABLE ? "enabled" : "disabled",
632 reg & M88_PSCR_MII_5BIT_ENABLE ? "5-bit" : "MII",
633 reg & M88_PSCR_SCRAMBLER_DISABLE ? "disabled" : "enabled",
634 reg & M88_PSCR_FORCE_LINK_GOOD ? "forced" : "disabled",
635 reg & M88_PSCR_ASSERT_CRS_ON_TX ? "enabled" : "disabled"
636 );
637 }
638
Jeff Garzik32c80372005-10-25 01:56:48 -0400[diff] [blame]639 return 0;
640}
641