blob: fc8af4421512082b3856b28f5045b322ecbb2cbe [file] [log] [blame]
Wu Fengguang9e9c9f22009-11-06 11:06:22 +08001/*
2 * Copyright © 2009 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Zhenyu Wang <zhenyu.z.wang@intel.com>
25 * Wu Fengguang <fengguang.wu@intel.com>
26 *
27 */
28
Wu Fengguang020abdb2010-04-19 13:13:06 +080029#define _GNU_SOURCE
Wu Fengguang9e9c9f22009-11-06 11:06:22 +080030#include <unistd.h>
Wu Fengguang020abdb2010-04-19 13:13:06 +080031#include <stdlib.h>
32#include <stdio.h>
33#include <string.h>
34#include <err.h>
Wu Fengguang9e9c9f22009-11-06 11:06:22 +080035#include <arpa/inet.h>
36#include "intel_gpu_tools.h"
37
Wu Fengguang020abdb2010-04-19 13:13:06 +080038static uint32_t devid;
39
40
41#define BITSTO(n) (n >= sizeof(long) * 8 ? ~0 : (1UL << (n)) - 1)
42#define BITMASK(high, low) (BITSTO(high+1) & ~BITSTO(low))
43#define BITS(reg, high, low) (((reg) & (BITMASK(high, low))) >> (low))
44#define BIT(reg, n) BITS(reg, n, n)
45
46#define min_t(type, x, y) ({ \
47 type __min1 = (x); \
48 type __min2 = (y); \
49 __min1 < __min2 ? __min1: __min2; })
50
51#define OPNAME(names, index) \
52 names[min_t(unsigned int, index, ARRAY_SIZE(names) - 1)]
53
54#define dump_reg(reg, desc) \
55 do { \
56 dword = INREG(reg); \
57 printf("%-21s 0x%08x %s\n", # reg, dword, desc); \
58 } while (0)
59
60
61static char *pixel_clock[] = {
62 [0] = "25.2 / 1.001 MHz",
63 [1] = "25.2 MHz",
64 [2] = "27 MHz",
65 [3] = "27 * 1.001 MHz",
66 [4] = "54 MHz",
67 [5] = "54 * 1.001 MHz",
68 [6] = "74.25 / 1.001 MHz",
69 [7] = "74.25 MHz",
70 [8] = "148.5 / 1.001 MHz",
71 [9] = "148.5 MHz",
72 [10] = "Reserved",
73};
74
75static char *power_state[] = {
76 [0] = "D0",
77 [1] = "D1",
78 [2] = "D2",
79 [3] = "D3",
80};
81
82static char *stream_type[] = {
83 [0] = "default samples",
84 [1] = "one bit stream",
85 [2] = "DST stream",
86 [3] = "MLP stream",
87 [4] = "Reserved",
88};
89
90static char *dip_port[] = {
91 [0] = "Reserved",
92 [1] = "Digital Port B",
93 [2] = "Digital Port C",
94 [3] = "Digital Port D",
95};
96
97static char *dip_index[] = {
98 [0] = "Audio DIP",
99 [1] = "ACP DIP",
100 [2] = "ISRC1 DIP",
101 [3] = "ISRC2 DIP",
102 [4] = "Reserved",
103};
104
105static char *dip_trans[] = {
106 [0] = "disabled",
107 [1] = "reserved",
108 [2] = "send once",
109 [3] = "best effort",
110};
111
112static char *video_dip_index[] = {
113 [0] = "AVI DIP",
114 [1] = "Vendor-specific DIP",
115 [2] = "Reserved",
116 [3] = "Source Product Description DIP",
117};
118
119static char *video_dip_trans[] = {
120 [0] = "send once",
121 [1] = "send every vsync",
122 [2] = "send at least every other vsync",
123 [3] = "reserved",
124};
125
126static char *trans_to_port_sel[] = {
127 [0] = "no port",
128 [1] = "Digital Port B",
129 [2] = "Digital Port B",
130 [3] = "Digital Port B",
131 [4] = "Digital Port B",
132 [5 ... 7] = "reserved",
133};
134
135static char *transcoder_select[] = {
136 [0] = "Transcoder A",
137 [1] = "Transcoder B",
138 [2] = "Transcoder C",
139 [3] = "reserved",
140};
141
142static char *dp_port_width[] = {
143 [0] = "x1 mode",
144 [1] = "x2 mode",
145 [2] = "x4 mode",
146 [3] = "reserved",
147};
148
149static void do_self_tests(void)
150{
151 if (BIT(1, 0) != 1)
152 exit(1);
153 if (BIT(0x80000000, 31) != 1)
154 exit(2);
155 if (BITS(0xc0000000, 31, 30) != 3)
156 exit(3);
157}
158
159/*
160 * EagleLake registers
161 */
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800162#define AUD_CONFIG 0x62000
163#define AUD_DEBUG 0x62010
164#define AUD_VID_DID 0x62020
165#define AUD_RID 0x62024
166#define AUD_SUBN_CNT 0x62028
167#define AUD_FUNC_GRP 0x62040
168#define AUD_SUBN_CNT2 0x62044
169#define AUD_GRP_CAP 0x62048
170#define AUD_PWRST 0x6204c
171#define AUD_SUPPWR 0x62050
172#define AUD_SID 0x62054
173#define AUD_OUT_CWCAP 0x62070
174#define AUD_OUT_PCMSIZE 0x62074
175#define AUD_OUT_STR 0x62078
176#define AUD_OUT_DIG_CNVT 0x6207c
177#define AUD_OUT_CH_STR 0x62080
178#define AUD_OUT_STR_DESC 0x62084
179#define AUD_PINW_CAP 0x620a0
180#define AUD_PIN_CAP 0x620a4
181#define AUD_PINW_CONNLNG 0x620a8
182#define AUD_PINW_CONNLST 0x620ac
183#define AUD_PINW_CNTR 0x620b0
184#define AUD_PINW_UNSOLRESP 0x620b8
185#define AUD_CNTL_ST 0x620b4
186#define AUD_PINW_CONFIG 0x620bc
187#define AUD_HDMIW_STATUS 0x620d4
188#define AUD_HDMIW_HDMIEDID 0x6210c
189#define AUD_HDMIW_INFOFR 0x62118
190#define AUD_CONV_CHCNT 0x62120
191#define AUD_CTS_ENABLE 0x62128
192
193#define VIDEO_DIP_CTL 0x61170
194#define VIDEO_DIP_ENABLE (1<<31)
195#define VIDEO_DIP_ENABLE_AVI (1<<21)
196#define VIDEO_DIP_ENABLE_VENDOR (1<<22)
197#define VIDEO_DIP_ENABLE_SPD (1<<24)
198#define VIDEO_DIP_BUF_AVI (0<<19)
199#define VIDEO_DIP_BUF_VENDOR (1<<19)
200#define VIDEO_DIP_BUF_SPD (3<<19)
201#define VIDEO_DIP_TRANS_ONCE (0<<16)
202#define VIDEO_DIP_TRANS_1 (1<<16)
203#define VIDEO_DIP_TRANS_2 (2<<16)
204
205#define AUDIO_HOTPLUG_EN (1<<24)
206
207
Wu Fengguang020abdb2010-04-19 13:13:06 +0800208static void dump_eaglelake(void)
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800209{
210 uint32_t dword;
211 int i;
212
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800213 /* printf("%-18s %8s %s\n\n", "register name", "raw value", "description"); */
214
215 dump_reg(VIDEO_DIP_CTL, "Video DIP Control");
216 dump_reg(SDVOB, "Digital Display Port B Control Register");
217 dump_reg(SDVOC, "Digital Display Port C Control Register");
218 dump_reg(PORT_HOTPLUG_EN, "Hot Plug Detect Enable");
219
220 dump_reg(AUD_CONFIG, "Audio Configuration");
221 dump_reg(AUD_DEBUG, "Audio Debug");
222 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
223 dump_reg(AUD_RID, "Audio Revision ID");
224 dump_reg(AUD_SUBN_CNT, "Audio Subordinate Node Count");
225 dump_reg(AUD_FUNC_GRP, "Audio Function Group Type");
226 dump_reg(AUD_SUBN_CNT2, "Audio Subordinate Node Count");
227 dump_reg(AUD_GRP_CAP, "Audio Function Group Capabilities");
228 dump_reg(AUD_PWRST, "Audio Power State");
229 dump_reg(AUD_SUPPWR, "Audio Supported Power States");
230 dump_reg(AUD_SID, "Audio Root Node Subsystem ID");
231 dump_reg(AUD_OUT_CWCAP, "Audio Output Converter Widget Capabilities");
232 dump_reg(AUD_OUT_PCMSIZE, "Audio PCM Size and Rates");
233 dump_reg(AUD_OUT_STR, "Audio Stream Formats");
234 dump_reg(AUD_OUT_DIG_CNVT, "Audio Digital Converter");
235 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
236 dump_reg(AUD_OUT_STR_DESC, "Audio Stream Descriptor Format");
237 dump_reg(AUD_PINW_CAP, "Audio Pin Complex Widget Capabilities");
238 dump_reg(AUD_PIN_CAP, "Audio Pin Capabilities");
239 dump_reg(AUD_PINW_CONNLNG, "Audio Connection List Length");
240 dump_reg(AUD_PINW_CONNLST, "Audio Connection List Entry");
241 dump_reg(AUD_PINW_CNTR, "Audio Pin Widget Control");
242 dump_reg(AUD_PINW_UNSOLRESP,"Audio Unsolicited Response Enable");
243 dump_reg(AUD_CNTL_ST, "Audio Control State Register");
244 dump_reg(AUD_PINW_CONFIG, "Audio Configuration Default");
245 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
246 dump_reg(AUD_HDMIW_HDMIEDID,"Audio HDMI Data EDID Block");
247 dump_reg(AUD_HDMIW_INFOFR, "Audio HDMI Widget Data Island Packet");
248 dump_reg(AUD_CONV_CHCNT, "Audio Converter Channel Count");
249 dump_reg(AUD_CTS_ENABLE, "Audio CTS Programming Enable");
250
251 printf("\nDetails:\n\n");
252
253 dword = INREG(AUD_VID_DID);
254 printf("AUD_VID_DID vendor id\t\t\t0x%x\n", dword >> 16);
255 printf("AUD_VID_DID device id\t\t\t0x%x\n", dword & 0xffff);
256
257 dword = INREG(AUD_RID);
258 printf("AUD_RID major revision\t\t\t0x%lx\n", BITS(dword, 23, 20));
259 printf("AUD_RID minor revision\t\t\t0x%lx\n", BITS(dword, 19, 16));
260 printf("AUD_RID revision id\t\t\t0x%lx\n", BITS(dword, 15, 8));
261 printf("AUD_RID stepping id\t\t\t0x%lx\n", BITS(dword, 7, 0));
262
263 dword = INREG(SDVOB);
264 printf("SDVOB enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
265 printf("SDVOB HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
266 printf("SDVOB SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
267 printf("SDVOB null packets\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
268 printf("SDVOB audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
269
270 dword = INREG(SDVOC);
271 printf("SDVOC enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
272 printf("SDVOC HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
273 printf("SDVOC SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
274 printf("SDVOC null packets\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
275 printf("SDVOC audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
276
277 dword = INREG(PORT_HOTPLUG_EN);
278 printf("PORT_HOTPLUG_EN DisplayPort/HDMI port B\t%ld\n", BIT(dword, 29)),
279 printf("PORT_HOTPLUG_EN DisplayPort/HDMI port C\t%ld\n", BIT(dword, 28)),
280 printf("PORT_HOTPLUG_EN DisplayPort port D\t%ld\n", BIT(dword, 27)),
281 printf("PORT_HOTPLUG_EN SDVOB\t\t\t%ld\n", BIT(dword, 26)),
282 printf("PORT_HOTPLUG_EN SDVOC\t\t\t%ld\n", BIT(dword, 25)),
283 printf("PORT_HOTPLUG_EN audio\t\t\t%ld\n", BIT(dword, 24)),
284 printf("PORT_HOTPLUG_EN TV\t\t\t%ld\n", BIT(dword, 23)),
285 printf("PORT_HOTPLUG_EN CRT\t\t\t%ld\n", BIT(dword, 9)),
286
287 dword = INREG(VIDEO_DIP_CTL);
288 printf("VIDEO_DIP_CTL enable graphics DIP\t%ld\n", BIT(dword, 31)),
289 printf("VIDEO_DIP_CTL port select\t\t[0x%lx] %s\n",
290 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
291 printf("VIDEO_DIP_CTL DIP buffer trans active\t%lu\n", BIT(dword, 28));
292 printf("VIDEO_DIP_CTL AVI DIP enabled\t\t%lu\n", BIT(dword, 21));
293 printf("VIDEO_DIP_CTL vendor DIP enabled\t%lu\n", BIT(dword, 22));
294 printf("VIDEO_DIP_CTL SPD DIP enabled\t\t%lu\n", BIT(dword, 24));
295 printf("VIDEO_DIP_CTL DIP buffer index\t\t[0x%lx] %s\n",
296 BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
297 printf("VIDEO_DIP_CTL DIP trans freq\t\t[0x%lx] %s\n",
298 BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
299 printf("VIDEO_DIP_CTL DIP buffer size\t\t%lu\n", BITS(dword, 11, 8));
300 printf("VIDEO_DIP_CTL DIP address\t\t%lu\n", BITS(dword, 3, 0));
301
302 dword = INREG(AUD_CONFIG);
303 printf("AUD_CONFIG pixel clock\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
304 OPNAME(pixel_clock, BITS(dword, 19, 16)));
305 printf("AUD_CONFIG fabrication enabled\t\t%lu\n", BITS(dword, 2, 2));
306 printf("AUD_CONFIG professional use allowed\t%lu\n", BIT(dword, 1));
307 printf("AUD_CONFIG fuse enabled\t\t\t%lu\n", BIT(dword, 0));
308
309 dword = INREG(AUD_DEBUG);
310 printf("AUD_DEBUG function reset\t\t%lu\n", BIT(dword, 0));
311
312 dword = INREG(AUD_SUBN_CNT);
313 printf("AUD_SUBN_CNT starting node number\t0x%lx\n", BITS(dword, 23, 16));
314 printf("AUD_SUBN_CNT total number of nodes\t0x%lx\n", BITS(dword, 7, 0));
315
316 dword = INREG(AUD_SUBN_CNT2);
317 printf("AUD_SUBN_CNT2 starting node number\t0x%lx\n", BITS(dword, 24, 16));
318 printf("AUD_SUBN_CNT2 total number of nodes\t0x%lx\n", BITS(dword, 7, 0));
319
320 dword = INREG(AUD_FUNC_GRP);
321 printf("AUD_FUNC_GRP unsol capable\t\t%lu\n", BIT(dword, 8));
322 printf("AUD_FUNC_GRP node type\t\t\t0x%lx\n", BITS(dword, 7, 0));
323
324 dword = INREG(AUD_GRP_CAP);
325 printf("AUD_GRP_CAP beep 0\t\t\t%lu\n", BIT(dword, 16));
326 printf("AUD_GRP_CAP input delay\t\t\t%lu\n", BITS(dword, 11, 8));
327 printf("AUD_GRP_CAP output delay\t\t%lu\n", BITS(dword, 3, 0));
328
329 dword = INREG(AUD_PWRST);
330 printf("AUD_PWRST device power state\t\t%s\n",
331 power_state[BITS(dword, 5, 4)]);
332 printf("AUD_PWRST device power state setting\t%s\n",
333 power_state[BITS(dword, 1, 0)]);
334
335 dword = INREG(AUD_SUPPWR);
336 printf("AUD_SUPPWR support D0\t\t\t%lu\n", BIT(dword, 0));
337 printf("AUD_SUPPWR support D1\t\t\t%lu\n", BIT(dword, 1));
338 printf("AUD_SUPPWR support D2\t\t\t%lu\n", BIT(dword, 2));
339 printf("AUD_SUPPWR support D3\t\t\t%lu\n", BIT(dword, 3));
340
341 dword = INREG(AUD_OUT_CWCAP);
342 printf("AUD_OUT_CWCAP widget type\t\t0x%lx\n", BITS(dword, 23, 20));
343 printf("AUD_OUT_CWCAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16));
344 printf("AUD_OUT_CWCAP channel count\t\t%lu\n",
345 BITS(dword, 15, 13) * 2 + BIT(dword, 0) + 1);
346 printf("AUD_OUT_CWCAP L-R swap\t\t\t%lu\n", BIT(dword, 11));
347 printf("AUD_OUT_CWCAP power control\t\t%lu\n", BIT(dword, 10));
348 printf("AUD_OUT_CWCAP digital\t\t\t%lu\n", BIT(dword, 9));
349 printf("AUD_OUT_CWCAP conn list\t\t\t%lu\n", BIT(dword, 8));
350 printf("AUD_OUT_CWCAP unsol\t\t\t%lu\n", BIT(dword, 7));
351 printf("AUD_OUT_CWCAP mute\t\t\t%lu\n", BIT(dword, 5));
352 printf("AUD_OUT_CWCAP format override\t\t%lu\n", BIT(dword, 4));
353 printf("AUD_OUT_CWCAP amp param override\t%lu\n", BIT(dword, 3));
354 printf("AUD_OUT_CWCAP out amp present\t\t%lu\n", BIT(dword, 2));
355 printf("AUD_OUT_CWCAP in amp present\t\t%lu\n", BIT(dword, 1));
356
357 dword = INREG(AUD_OUT_DIG_CNVT);
358 printf("AUD_OUT_DIG_CNVT SPDIF category\t\t0x%lx\n", BITS(dword, 14, 8));
359 printf("AUD_OUT_DIG_CNVT SPDIF level\t\t%lu\n", BIT(dword, 7));
360 printf("AUD_OUT_DIG_CNVT professional\t\t%lu\n", BIT(dword, 6));
361 printf("AUD_OUT_DIG_CNVT non PCM\t\t%lu\n", BIT(dword, 5));
362 printf("AUD_OUT_DIG_CNVT copyright asserted\t%lu\n", BIT(dword, 4));
363 printf("AUD_OUT_DIG_CNVT filter preemphasis\t%lu\n", BIT(dword, 3));
364 printf("AUD_OUT_DIG_CNVT validity config\t%lu\n", BIT(dword, 2));
365 printf("AUD_OUT_DIG_CNVT validity flag\t\t%lu\n", BIT(dword, 1));
366 printf("AUD_OUT_DIG_CNVT digital enable\t\t%lu\n", BIT(dword, 0));
367
368 dword = INREG(AUD_OUT_CH_STR);
369 printf("AUD_OUT_CH_STR stream id\t\t0x%lx\n", BITS(dword, 7, 4));
370 printf("AUD_OUT_CH_STR lowest channel\t\t0x%lx\n", BITS(dword, 3, 0));
371
372 dword = INREG(AUD_OUT_STR_DESC);
373 printf("AUD_OUT_STR_DESC stream channels\t0x%lx\n", BITS(dword, 3, 0));
374
375 dword = INREG(AUD_PINW_CAP);
376 printf("AUD_PINW_CAP widget type\t\t0x%lx\n", BITS(dword, 23, 20));
377 printf("AUD_PINW_CAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16));
378 printf("AUD_PINW_CAP channel count\t\t0x%lx\n",
379 BITS(dword, 15, 13) * 2 + BIT(dword, 0));
380 printf("AUD_PINW_CAP HDCP\t\t\t%lu\n", BIT(dword, 12));
381 printf("AUD_PINW_CAP L-R swap\t\t\t%lu\n", BIT(dword, 11));
382 printf("AUD_PINW_CAP power control\t\t%lu\n", BIT(dword, 10));
383 printf("AUD_PINW_CAP digital\t\t\t%lu\n", BIT(dword, 9));
384 printf("AUD_PINW_CAP conn list\t\t\t%lu\n", BIT(dword, 8));
385 printf("AUD_PINW_CAP unsol\t\t\t%lu\n", BIT(dword, 7));
386 printf("AUD_PINW_CAP mute\t\t\t%lu\n", BIT(dword, 5));
387 printf("AUD_PINW_CAP format override\t\t%lu\n", BIT(dword, 4));
388 printf("AUD_PINW_CAP amp param override\t\t%lu\n", BIT(dword, 3));
389 printf("AUD_PINW_CAP out amp present\t\t%lu\n", BIT(dword, 2));
390 printf("AUD_PINW_CAP in amp present\t\t%lu\n", BIT(dword, 1));
391
392
393 dword = INREG(AUD_PIN_CAP);
394 printf("AUD_PIN_CAP EAPD\t\t\t%lu\n", BIT(dword, 16));
395 printf("AUD_PIN_CAP HDMI\t\t\t%lu\n", BIT(dword, 7));
396 printf("AUD_PIN_CAP output\t\t\t%lu\n", BIT(dword, 4));
397 printf("AUD_PIN_CAP presence detect\t\t%lu\n", BIT(dword, 2));
398
399 dword = INREG(AUD_PINW_CNTR);
400 printf("AUD_PINW_CNTR mute status\t\t%lu\n", BIT(dword, 8));
401 printf("AUD_PINW_CNTR out enable\t\t%lu\n", BIT(dword, 6));
402 printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8));
403 printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8));
404 printf("AUD_PINW_CNTR stream type\t\t[0x%lx] %s\n",
405 BITS(dword, 2, 0),
406 OPNAME(stream_type, BITS(dword, 2, 0)));
407
408 dword = INREG(AUD_PINW_UNSOLRESP);
409 printf("AUD_PINW_UNSOLRESP enable unsol resp\t%lu\n", BIT(dword, 31));
410
411 dword = INREG(AUD_CNTL_ST);
412 printf("AUD_CNTL_ST DIP audio enabled\t\t%lu\n", BIT(dword, 21));
413 printf("AUD_CNTL_ST DIP ACP enabled\t\t%lu\n", BIT(dword, 22));
414 printf("AUD_CNTL_ST DIP ISRCx enabled\t\t%lu\n", BIT(dword, 23));
415 printf("AUD_CNTL_ST DIP port select\t\t[0x%lx] %s\n",
416 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
417 printf("AUD_CNTL_ST DIP buffer index\t\t[0x%lx] %s\n",
418 BITS(dword, 20, 18), OPNAME(dip_index, BITS(dword, 20, 18)));
419 printf("AUD_CNTL_ST DIP trans freq\t\t[0x%lx] %s\n",
420 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
421 printf("AUD_CNTL_ST DIP address\t\t\t%lu\n", BITS(dword, 3, 0));
422 printf("AUD_CNTL_ST CP ready\t\t\t%lu\n", BIT(dword, 15));
423 printf("AUD_CNTL_ST ELD valid\t\t\t%lu\n", BIT(dword, 14));
424 printf("AUD_CNTL_ST ELD ack\t\t\t%lu\n", BIT(dword, 4));
425 printf("AUD_CNTL_ST ELD bufsize\t\t\t%lu\n", BITS(dword, 13, 9));
426 printf("AUD_CNTL_ST ELD address\t\t\t%lu\n", BITS(dword, 8, 5));
427
428 dword = INREG(AUD_HDMIW_STATUS);
429 printf("AUD_HDMIW_STATUS CDCLK/DOTCLK underrun\t%lu\n", BIT(dword, 31));
430 printf("AUD_HDMIW_STATUS CDCLK/DOTCLK overrun\t%lu\n", BIT(dword, 30));
431 printf("AUD_HDMIW_STATUS BCLK/CDCLK underrun\t%lu\n", BIT(dword, 29));
432 printf("AUD_HDMIW_STATUS BCLK/CDCLK overrun\t%lu\n", BIT(dword, 28));
433
434 dword = INREG(AUD_CONV_CHCNT);
435 printf("AUD_CONV_CHCNT HDMI HBR enabled\t\t%lu\n", BITS(dword, 15, 14));
436 printf("AUD_CONV_CHCNT HDMI channel count\t%lu\n", BITS(dword, 11, 8) + 1);
437
438 printf("AUD_CONV_CHCNT HDMI channel mapping:\n");
439 for (i = 0; i < 8; i++) {
440 OUTREG(AUD_CONV_CHCNT, i);
441 dword = INREG(AUD_CONV_CHCNT);
442 printf("\t\t\t\t\t[0x%x] %u => %lu \n", dword, i, BITS(dword, 7, 4));
443 }
444
445 printf("AUD_HDMIW_INFOFR HDMI audio Infoframe:\n\t");
446 dword = INREG(AUD_CNTL_ST);
447 dword &= ~BITMASK(20, 18);
448 dword &= ~BITMASK(3, 0);
449 OUTREG(AUD_CNTL_ST, dword);
450 for (i = 0; i < 8; i++)
451 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR)));
452 printf("\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800453}
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800454
Wu Fengguang020abdb2010-04-19 13:13:06 +0800455#undef AUD_RID
456#undef AUD_VID_DID
457#undef AUD_PWRST
458#undef AUD_OUT_CH_STR
459#undef AUD_HDMIW_STATUS
460
461/*
462 * IronLake registers
463 */
464#define AUD_CONFIG_A 0xE2000
465#define AUD_CONFIG_B 0xE2100
466#define AUD_CTS_ENABLE_A 0xE2028
467#define AUD_CTS_ENABLE_B 0xE2128
468#define AUD_MISC_CTRL_A 0xE2010
469#define AUD_MISC_CTRL_B 0xE2110
470#define AUD_VID_DID 0xE2020
471#define AUD_RID 0xE2024
472#define AUD_PWRST 0xE204C
473#define AUD_PORT_EN_HD_CFG 0xE207C
474#define AUD_OUT_DIG_CNVT_A 0xE2080
475#define AUD_OUT_DIG_CNVT_B 0xE2180
476#define AUD_OUT_CH_STR 0xE2088
477#define AUD_OUT_STR_DESC_A 0xE2084
478#define AUD_OUT_STR_DESC_B 0xE2184
479#define AUD_PINW_CONNLNG_LIST 0xE20A8
480#define AUD_PINW_CONNLNG_SEL 0xE20AC
481#define AUD_CNTL_ST_A 0xE20B4
482#define AUD_CNTL_ST_B 0xE21B4
483#define AUD_CNTL_ST2 0xE20C0
484#define AUD_HDMIW_STATUS 0xE20D4
485#define AUD_HDMIW_HDMIEDID_A 0xE2050
486#define AUD_HDMIW_HDMIEDID_B 0xE2150
487#define AUD_HDMIW_INFOFR_A 0xE2054
488#define AUD_HDMIW_INFOFR_B 0xE2154
489
490static void dump_ironlake(void)
491{
492 uint32_t dword;
493 int i;
494
495 dump_reg(HDMIB, "sDVO/HDMI Port B Control");
496 dump_reg(HDMIC, "HDMI Port C Control");
497 dump_reg(HDMID, "HDMI Port D Control");
498 dump_reg(AUD_CONFIG_A, "Audio Configuration ­ Transcoder A");
499 dump_reg(AUD_CONFIG_B, "Audio Configuration ­ Transcoder B");
500 dump_reg(AUD_CTS_ENABLE_A, "Audio CTS Programming Enable ­ Transcoder A");
501 dump_reg(AUD_CTS_ENABLE_B, "Audio CTS Programming Enable ­ Transcoder B");
502 dump_reg(AUD_MISC_CTRL_A, "Audio MISC Control for Transcoder A");
503 dump_reg(AUD_MISC_CTRL_B, "Audio MISC Control for Transcoder B");
504 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
505 dump_reg(AUD_RID, "Audio Revision ID");
506 dump_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)");
507 dump_reg(AUD_PORT_EN_HD_CFG, "Audio Port Enable HDAudio Config");
508 dump_reg(AUD_OUT_DIG_CNVT_A, "Audio Digital Converter ­ Conv A");
509 dump_reg(AUD_OUT_DIG_CNVT_B, "Audio Digital Converter ­ Conv B");
510 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
511 dump_reg(AUD_OUT_STR_DESC_A, "Audio Stream Descriptor Format ­ Conv A");
512 dump_reg(AUD_OUT_STR_DESC_B, "Audio Stream Descriptor Format ­ Conv B");
513 dump_reg(AUD_PINW_CONNLNG_LIST, "Audio Connection List");
514 dump_reg(AUD_PINW_CONNLNG_SEL, "Audio Connection Select");
515 dump_reg(AUD_CNTL_ST_A, "Audio Control State Register ­ Transcoder A");
516 dump_reg(AUD_CNTL_ST_B, "Audio Control State Register ­ Transcoder B");
517 dump_reg(AUD_CNTL_ST2, "Audio Control State 2");
518 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
519 dump_reg(AUD_HDMIW_HDMIEDID_A, "HDMI Data EDID Block ­ Transcoder A");
520 dump_reg(AUD_HDMIW_HDMIEDID_B, "HDMI Data EDID Block ­ Transcoder B");
521 dump_reg(AUD_HDMIW_INFOFR_A, "Audio Widget Data Island Packet ­ Transcoder A");
522 dump_reg(AUD_HDMIW_INFOFR_B, "Audio Widget Data Island Packet ­ Transcoder B");
523
524 printf("\nDetails:\n\n");
525
526 dword = INREG(AUD_VID_DID);
527 printf("AUD_VID_DID vendor id\t\t\t\t\t0x%x\n", dword >> 16);
528 printf("AUD_VID_DID device id\t\t\t\t\t0x%x\n", dword & 0xffff);
529
530 dword = INREG(AUD_RID);
531 printf("AUD_RID Major_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 23, 20));
532 printf("AUD_RID Minor_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 19, 16));
533 printf("AUD_RID Revision_Id\t\t\t\t\t0x%lx\n", BITS(dword, 15, 8));
534 printf("AUD_RID Stepping_Id\t\t\t\t\t0x%lx\n", BITS(dword, 7, 0));
535
536 dword = INREG(HDMIB);
537 printf("HDMIB HDMIB_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
538 printf("HDMIB Transcoder_Select\t\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
539 printf("HDMIB HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
540 printf("HDMIB Digital_Port_D_Detected\t\t\t\t%lu\n", BIT(dword, 2));
541 printf("HDMIB Null_packets_enabled_during_Vsync\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
542 printf("HDMIB Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
543
544 dword = INREG(HDMIC);
545 printf("HDMIC HDMIC_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
546 printf("HDMIC Transcoder_Select\t\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
547 printf("HDMIC HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
548 printf("HDMIC Digital_Port_D_Detected\t\t\t\t%lu\n", BIT(dword, 2));
549 printf("HDMIC Null_packets_enabled_during_Vsync\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
550 printf("HDMIC Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
551
552 dword = INREG(HDMID);
553 printf("HDMID HDMID_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
554 printf("HDMID Transcoder_Select\t\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
555 printf("HDMID HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
556 printf("HDMID Digital_Port_D_Detected\t\t\t\t%lu\n", BIT(dword, 2));
557 printf("HDMID Null_packets_enabled_during_Vsync\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
558 printf("HDMID Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
559
560 dword = INREG(AUD_CONFIG_A);
561 printf("AUD_CONFIG_A Pixel_Clock\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
562 OPNAME(pixel_clock, BITS(dword, 19, 16)));
563 dword = INREG(AUD_CONFIG_B);
564 printf("AUD_CONFIG_B Pixel_Clock\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
565 OPNAME(pixel_clock, BITS(dword, 19, 16)));
566
567 dword = INREG(AUD_CTS_ENABLE_A);
568 printf("AUD_CTS_ENABLE_A Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
569 printf("AUD_CTS_ENABLE_A CTS/M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
570 printf("AUD_CTS_ENABLE_A CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
571 dword = INREG(AUD_CTS_ENABLE_B);
572 printf("AUD_CTS_ENABLE_B Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
573 printf("AUD_CTS_ENABLE_B CTS/M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
574 printf("AUD_CTS_ENABLE_B CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
575
576 dword = INREG(AUD_MISC_CTRL_A);
577 printf("AUD_MISC_CTRL_A Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
578 printf("AUD_MISC_CTRL_A Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
579 printf("AUD_MISC_CTRL_A Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
580 printf("AUD_MISC_CTRL_A Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
581 dword = INREG(AUD_MISC_CTRL_B);
582 printf("AUD_MISC_CTRL_B Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
583 printf("AUD_MISC_CTRL_B Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
584 printf("AUD_MISC_CTRL_B Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
585 printf("AUD_MISC_CTRL_B Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
586
587 dword = INREG(AUD_PWRST);
588 printf("AUD_PWRST Function_Group_Device_Power_State_Current\t%s\n", power_state[BITS(dword, 23, 22)]);
589 printf("AUD_PWRST Function_Group_Device_Power_State_Set \t%s\n", power_state[BITS(dword, 21, 20)]);
590 printf("AUD_PWRST ConvertorB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 19, 18)]);
591 printf("AUD_PWRST ConvertorB_Widget_Power_State_Requested \t%s\n", power_state[BITS(dword, 17, 16)]);
592 printf("AUD_PWRST ConvertorA_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 15, 14)]);
593 printf("AUD_PWRST ConvertorA_Widget_Power_State_Requsted \t%s\n", power_state[BITS(dword, 13, 12)]);
594 printf("AUD_PWRST PinD_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 11, 10)]);
595 printf("AUD_PWRST PinD_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 9, 8)]);
596 printf("AUD_PWRST PinC_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 7, 6)]);
597 printf("AUD_PWRST PinC_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 5, 4)]);
598 printf("AUD_PWRST PinB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 3, 2)]);
599 printf("AUD_PWRST PinB_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 1, 0)]);
600
601 dword = INREG(AUD_PORT_EN_HD_CFG);
602 printf("AUD_PORT_EN_HD_CFG Convertor_A_Digen\t\t\t%lu\n", BIT(dword, 0));
603 printf("AUD_PORT_EN_HD_CFG Convertor_B_Digen\t\t\t%lu\n", BIT(dword, 1));
604 printf("AUD_PORT_EN_HD_CFG ConvertorA_Stream_ID\t\t%lu\n", BITS(dword, 7, 4));
605 printf("AUD_PORT_EN_HD_CFG ConvertorB_Stream_ID\t\t%lu\n", BITS(dword, 11, 8));
606 printf("AUD_PORT_EN_HD_CFG Port_B_Out_Enable\t\t\t%lu\n", BIT(dword, 12));
607 printf("AUD_PORT_EN_HD_CFG Port_C_Out_Enable\t\t\t%lu\n", BIT(dword, 13));
608 printf("AUD_PORT_EN_HD_CFG Port_D_Out_Enable\t\t\t%lu\n", BIT(dword, 14));
609 printf("AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status\t\t%lu\n", BIT(dword, 16));
610 printf("AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status\t\t%lu\n", BIT(dword, 17));
611 printf("AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status\t\t%lu\n", BIT(dword, 18));
612
613 dword = INREG(AUD_OUT_DIG_CNVT_A);
614 printf("AUD_OUT_DIG_CNVT_A V\t\t\t\t\t%lu\n", BIT(dword, 1));
615 printf("AUD_OUT_DIG_CNVT_A VCFG\t\t\t\t%lu\n", BIT(dword, 2));
616 printf("AUD_OUT_DIG_CNVT_A PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
617 printf("AUD_OUT_DIG_CNVT_A Copy\t\t\t\t%lu\n", BIT(dword, 4));
618 printf("AUD_OUT_DIG_CNVT_A Non-Audio\t\t\t\t0x%lx\n", BIT(dword, 5));
619 printf("AUD_OUT_DIG_CNVT_A PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
620 printf("AUD_OUT_DIG_CNVT_A Level\t\t\t\t%lu\n", BIT(dword, 7));
621 printf("AUD_OUT_DIG_CNVT_A Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
622 printf("AUD_OUT_DIG_CNVT_A Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
623 printf("AUD_OUT_DIG_CNVT_A Stream_ID\t\t\t\t\t\t%lu\n", BITS(dword, 23, 20));
624
625 dword = INREG(AUD_OUT_DIG_CNVT_B);
626 printf("AUD_OUT_DIG_CNVT_B V\t\t\t\t\t%lu\n", BIT(dword, 1));
627 printf("AUD_OUT_DIG_CNVT_B VCFG\t\t\t\t%lu\n", BIT(dword, 2));
628 printf("AUD_OUT_DIG_CNVT_B PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
629 printf("AUD_OUT_DIG_CNVT_B Copy\t\t\t\t%lu\n", BIT(dword, 4));
630 printf("AUD_OUT_DIG_CNVT_B Non-Audio\t\t\t\t0x%lx\n", BIT(dword, 5));
631 printf("AUD_OUT_DIG_CNVT_B PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
632 printf("AUD_OUT_DIG_CNVT_B Level\t\t\t\t%lu\n", BIT(dword, 7));
633 printf("AUD_OUT_DIG_CNVT_B Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
634 printf("AUD_OUT_DIG_CNVT_B Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
635 printf("AUD_OUT_DIG_CNVT_B Stream_ID\t\t\t%lu\n", BITS(dword, 23, 20));
636
637 printf("AUD_OUT_CH_STR Converter_Channel_MAP PORTB PORTC PORTD\n");
638 for (i = 0; i < 8; i++) {
639 OUTREG(AUD_OUT_CH_STR, i | (i << 8) | (i << 16));
640 dword = INREG(AUD_OUT_CH_STR);
641 printf("\t\t\t\t%lu\t%lu\t%lu\t%lu\n",
642 1 + BITS(dword, 3, 0),
643 1 + BITS(dword, 7, 4),
644 1 + BITS(dword, 15, 12),
645 1 + BITS(dword, 23, 20));
646 }
647
648 dword = INREG(AUD_OUT_STR_DESC_A);
649 printf("AUD_OUT_STR_DESC_A HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
650 printf("AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16));
651 printf("AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t%lu\n", BITS(dword, 6, 4));
652 printf("AUD_OUT_STR_DESC_A Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
653
654 dword = INREG(AUD_OUT_STR_DESC_B);
655 printf("AUD_OUT_STR_DESC_B HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
656 printf("AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16));
657 printf("AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t%lu\n", BITS(dword, 6, 4));
658 printf("AUD_OUT_STR_DESC_B Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
659
660 dword = INREG(AUD_PINW_CONNLNG_SEL);
661 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_B\t%lu\n", BITS(dword, 7, 0));
662 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_C\t%lu\n", BITS(dword, 15, 8));
663 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_D\t%lu\n", BITS(dword, 23, 16));
664
665 dword = INREG(AUD_CNTL_ST_A);
666 printf("AUD_CNTL_ST_A DIP_Port_Select\t\t\t\t[%#lx] %s\n",
667 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
668 printf("AUD_CNTL_ST_A DIP_type_enable_status Audio DIP\t\t%lu\n", BIT(dword, 21));
669 printf("AUD_CNTL_ST_A DIP_type_enable_status Generic 1 ACP DIP\t%lu\n", BIT(dword, 22));
670 printf("AUD_CNTL_ST_A DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
671 printf("AUD_CNTL_ST_A DIP_transmission_frequency\t\t[0x%lx] %s\n",
672 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
673 printf("AUD_CNTL_ST_A ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
674 printf("AUD_CNTL_ST_A ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
675
676 dword = INREG(AUD_CNTL_ST_B);
677 printf("AUD_CNTL_ST_B DIP_Port_Select\t\t\t\t[%#lx] %s\n",
678 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
679 printf("AUD_CNTL_ST_B DIP_type_enable_status Audio DIP\t\t%lu\n", BIT(dword, 21));
680 printf("AUD_CNTL_ST_B DIP_type_enable_status Generic 1 ACP DIP\t%lu\n", BIT(dword, 22));
681 printf("AUD_CNTL_ST_B DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
682 printf("AUD_CNTL_ST_B DIP_transmission_frequency\t\t[0x%lx] %s\n",
683 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
684 printf("AUD_CNTL_ST_B ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
685 printf("AUD_CNTL_ST_B ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
686
687 dword = INREG(AUD_CNTL_ST2);
688 printf("AUD_CNTL_ST2 CP_ReadyB\t\t\t\t\t%lu\n", BIT(dword, 1));
689 printf("AUD_CNTL_ST2 ELD_validB\t\t\t\t%lu\n", BIT(dword, 0));
690 printf("AUD_CNTL_ST2 CP_ReadyC\t\t\t\t\t%lu\n", BIT(dword, 5));
691 printf("AUD_CNTL_ST2 ELD_validC\t\t\t\t%lu\n", BIT(dword, 4));
692 printf("AUD_CNTL_ST2 CP_ReadyD\t\t\t\t\t%lu\n", BIT(dword, 9));
693 printf("AUD_CNTL_ST2 ELD_validD\t\t\t\t%lu\n", BIT(dword, 8));
694
695 dword = INREG(AUD_HDMIW_STATUS);
696 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 31));
697 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 30));
698 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 29));
699 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 28));
700 printf("AUD_HDMIW_STATUS BCLK/CDCLK_FIFO_Overrun\t\t%lu\n", BIT(dword, 25));
701 printf("AUD_HDMIW_STATUS Function_Reset\t\t\t%lu\n", BIT(dword, 29));
702
703 printf("AUD_HDMIW_HDMIEDID_A HDMI ELD:\n\t");
704 dword = INREG(AUD_CNTL_ST_A);
705 dword &= ~BITMASK(9, 5);
706 OUTREG(AUD_CNTL_ST_A, dword);
707 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
708 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_A)));
709 printf("\n");
710
711 printf("AUD_HDMIW_HDMIEDID_B HDMI ELD:\n\t");
712 dword = INREG(AUD_CNTL_ST_B);
713 dword &= ~BITMASK(9, 5);
714 OUTREG(AUD_CNTL_ST_B, dword);
715 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
716 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_B)));
717 printf("\n");
718
719 printf("AUD_HDMIW_INFOFR_A HDMI audio Infoframe:\n\t");
720 dword = INREG(AUD_CNTL_ST_A);
721 dword &= ~BITMASK(20, 18);
722 dword &= ~BITMASK(3, 0);
723 OUTREG(AUD_CNTL_ST_A, dword);
724 for (i = 0; i < 8; i++)
725 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_A)));
726 printf("\n");
727
728 printf("AUD_HDMIW_INFOFR_B HDMI audio Infoframe:\n\t");
729 dword = INREG(AUD_CNTL_ST_B);
730 dword &= ~BITMASK(20, 18);
731 dword &= ~BITMASK(3, 0);
732 OUTREG(AUD_CNTL_ST_B, dword);
733 for (i = 0; i < 8; i++)
734 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_B)));
735 printf("\n");
736
737}
738
739
740#undef AUD_CONFIG_A
741#undef AUD_MISC_CTRL_A
742#undef AUD_VID_DID
743#undef AUD_RID
744#undef AUD_CTS_ENABLE_A
745#undef AUD_PWRST
746#undef AUD_HDMIW_HDMIEDID_A
747#undef AUD_HDMIW_INFOFR_A
748#undef AUD_PORT_EN_HD_CFG
749#undef AUD_OUT_DIG_CNVT_A
750#undef AUD_OUT_STR_DESC_A
751#undef AUD_OUT_CH_STR
752#undef AUD_PINW_CONNLNG_LIST
753#undef AUD_CNTL_ST_A
754#undef AUD_HDMIW_STATUS
755#undef AUD_CONFIG_B
756#undef AUD_MISC_CTRL_B
757#undef AUD_CTS_ENABLE_B
758#undef AUD_HDMIW_HDMIEDID_B
759#undef AUD_HDMIW_INFOFR_B
760#undef AUD_OUT_DIG_CNVT_B
761#undef AUD_OUT_STR_DESC_B
762#undef AUD_CNTL_ST_B
763
764/*
765 * CougarPoint registers
766 */
767#define DP_CTL_C 0xE4200
768#define DP_AUX_CTL_C 0xE4210
769#define DP_AUX_TST_C 0xE4228
770#define SPORT_DDI_CRC_C 0xE4250
771#define SPORT_DDI_CRC_R 0xE4264
772#define DP_CTL_D 0xE4300
773#define DP_AUX_CTL_D 0xE4310
774#define DP_AUX_TST_D 0xE4328
775#define SPORT_DDI_CRC_CTL_D 0xE4350
776#define AUD_CONFIG_A 0xE5000
777#define AUD_MISC_CTRL_A 0xE5010
778#define AUD_VID_DID 0xE5020
779#define AUD_RID 0xE5024
780#define AUD_CTS_ENABLE_A 0xE5028
781#define AUD_PWRST 0xE504C
782#define AUD_HDMIW_HDMIEDID_A 0xE5050
783#define AUD_HDMIW_INFOFR_A 0xE5054
784#define AUD_PORT_EN_HD_CFG 0xE507C
785#define AUD_OUT_DIG_CNVT_A 0xE5080
786#define AUD_OUT_STR_DESC_A 0xE5084
787#define AUD_OUT_CH_STR 0xE5088
788#define AUD_PINW_CONNLNG_LIST 0xE50A8
789#define AUD_PINW_CONNLNG_SELA 0xE50AC
790#define AUD_CNTL_ST_A 0xE50B4
791#define AUD_CNTRL_ST2 0xE50C0
792#define AUD_CNTRL_ST3 0xE50C4
793#define AUD_HDMIW_STATUS 0xE50D4
794#define AUD_CONFIG_B 0xE5100
795#define AUD_MISC_CTRL_B 0xE5110
796#define AUD_CTS_ENABLE_B 0xE5128
797#define AUD_HDMIW_HDMIEDID_B 0xE5150
798#define AUD_HDMIW_INFOFR_B 0xE5154
799#define AUD_OUT_DIG_CNVT_B 0xE5180
800#define AUD_OUT_STR_DESC_B 0xE5184
801#define AUD_CNTL_ST_B 0xE51B4
802#define AUD_CONFIG_C 0xE5200
803#define AUD_MISC_CTRL_C 0xE5210
804#define AUD_CTS_ENABLE_C 0xE5228
805#define AUD_HDMIW_HDMIEDID_C 0xE5250
806#define AUD_HDMIW_INFOFR_C 0xE5254
807#define AUD_OUT_DIG_CNVT_C 0xE5280
808#define AUD_OUT_STR_DESC_C 0xE5284
809#define AUD_CNTL_ST_C 0xE52B4
810#define AUD_CONFIG_D 0xE5300
811#define AUD_MISC_CTRL_D 0xE5310
812#define AUD_CTS_ENABLE_D 0xE5328
813#define AUD_HDMIW_HDMIEDID_D 0xE5350
814#define AUD_HDMIW_INFOFR_D 0xE5354
815#define AUD_OUT_DIG_CNVT_D 0xE5380
816#define AUD_OUT_STR_DESC_D 0xE5384
817#define AUD_CNTL_ST_D 0xE53B4
818
819
820static void dump_cpt(void)
821{
822 uint32_t dword;
823 int i;
824
825 dump_reg(HDMIB, "sDVO/HDMI Port B Control");
826 dump_reg(HDMIC, "HDMI Port C Control");
827 dump_reg(HDMID, "HDMI Port D Control");
828 dump_reg(AUD_CONFIG_A, "Audio Configuration ­ Transcoder A");
829 dump_reg(AUD_CONFIG_B, "Audio Configuration ­ Transcoder B");
830 dump_reg(AUD_CONFIG_C, "Audio Configuration ­ Transcoder C");
831 dump_reg(AUD_CTS_ENABLE_A, "Audio CTS Programming Enable ­ Transcoder A");
832 dump_reg(AUD_CTS_ENABLE_B, "Audio CTS Programming Enable ­ Transcoder B");
833 dump_reg(AUD_CTS_ENABLE_C, "Audio CTS Programming Enable ­ Transcoder C");
834 dump_reg(AUD_MISC_CTRL_A, "Audio MISC Control for Transcoder A");
835 dump_reg(AUD_MISC_CTRL_B, "Audio MISC Control for Transcoder B");
836 dump_reg(AUD_MISC_CTRL_C, "Audio MISC Control for Transcoder C");
837 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
838 dump_reg(AUD_RID, "Audio Revision ID");
839 dump_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)");
840 dump_reg(AUD_PORT_EN_HD_CFG, "Audio Port Enable HDAudio Config");
841 dump_reg(AUD_OUT_DIG_CNVT_A, "Audio Digital Converter ­ Conv A");
842 dump_reg(AUD_OUT_DIG_CNVT_B, "Audio Digital Converter ­ Conv B");
843 dump_reg(AUD_OUT_DIG_CNVT_C, "Audio Digital Converter ­ Conv C");
844 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
845 dump_reg(AUD_OUT_STR_DESC_A, "Audio Stream Descriptor Format ­ Conv A");
846 dump_reg(AUD_OUT_STR_DESC_B, "Audio Stream Descriptor Format ­ Conv B");
847 dump_reg(AUD_OUT_STR_DESC_C, "Audio Stream Descriptor Format ­ Conv C");
848 dump_reg(AUD_PINW_CONNLNG_LIST, "Audio Connection List");
849 dump_reg(AUD_PINW_CONNLNG_SEL, "Audio Connection Select");
850 dump_reg(AUD_CNTL_ST_A, "Audio Control State Register ­ Transcoder A");
851 dump_reg(AUD_CNTL_ST_B, "Audio Control State Register ­ Transcoder B");
852 dump_reg(AUD_CNTL_ST_C, "Audio Control State Register ­ Transcoder C");
853 dump_reg(AUD_CNTRL_ST2, "Audio Control State 2");
854 dump_reg(AUD_CNTRL_ST3, "Audio Control State 3");
855 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
856 dump_reg(AUD_HDMIW_HDMIEDID_A, "HDMI Data EDID Block ­ Transcoder A");
857 dump_reg(AUD_HDMIW_HDMIEDID_B, "HDMI Data EDID Block ­ Transcoder B");
858 dump_reg(AUD_HDMIW_HDMIEDID_C, "HDMI Data EDID Block ­ Transcoder C");
859 dump_reg(AUD_HDMIW_INFOFR_A, "Audio Widget Data Island Packet ­ Transcoder A");
860 dump_reg(AUD_HDMIW_INFOFR_B, "Audio Widget Data Island Packet ­ Transcoder B");
861 dump_reg(AUD_HDMIW_INFOFR_C, "Audio Widget Data Island Packet ­ Transcoder C");
862
863 printf("\nDetails:\n\n");
864
865 dword = INREG(AUD_VID_DID);
866 printf("AUD_VID_DID vendor id\t\t\t\t\t0x%x\n", dword >> 16);
867 printf("AUD_VID_DID device id\t\t\t\t\t0x%x\n", dword & 0xffff);
868
869 dword = INREG(AUD_RID);
870 printf("AUD_RID Major_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 23, 20));
871 printf("AUD_RID Minor_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 19, 16));
872 printf("AUD_RID Revision_Id\t\t\t\t\t0x%lx\n", BITS(dword, 15, 8));
873 printf("AUD_RID Stepping_Id\t\t\t\t\t0x%lx\n", BITS(dword, 7, 0));
874
875 dword = INREG(HDMIB);
876 printf("HDMIB Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
877 printf("HDMIB Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
878 BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]);
879 printf("HDMIB sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7));
880 printf("HDMIB HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
881 printf("HDMIB Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
882 printf("HDMIB HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI");
883 printf("HDMIB Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
884
885 dword = INREG(HDMIC);
886 printf("HDMIC Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
887 printf("HDMIC Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
888 BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]);
889 printf("HDMIC sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7));
890 printf("HDMIC HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
891 printf("HDMIC Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
892 printf("HDMIC HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI");
893 printf("HDMIC Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
894
895 dword = INREG(HDMID);
896 printf("HDMID Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
897 printf("HDMID Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
898 BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]);
899 printf("HDMID sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7));
900 printf("HDMID HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
901 printf("HDMID Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
902 printf("HDMID HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI");
903 printf("HDMID Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
904
905 dword = INREG(TRANS_DP_CTL_A);
906 printf("TRANS_DP_CTL_A DisplayPort_Enable\t\t\t%lu\n", BIT(dword, 31));
907 printf("TRANS_DP_CTL_A Port_Width_Selection\t\t\t[0x%lx] %s\n",
908 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
909 printf("TRANS_DP_CTL_A Port_Detected\t\t\t\t%lu\n", BIT(dword, 2));
910 printf("TRANS_DP_CTL_A HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
911 printf("TRANS_DP_CTL_A Audio_Output_Enable\t\t\t%lu\n", BIT(dword, 6));
912
913 dword = INREG(TRANS_DP_CTL_B);
914 printf("TRANS_DP_CTL_B DisplayPort_Enable\t\t\t%lu\n", BIT(dword, 31));
915 printf("TRANS_DP_CTL_B Port_Width_Selection\t\t\t[0x%lx] %s\n",
916 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
917 printf("TRANS_DP_CTL_B Port_Detected\t\t\t\t%lu\n", BIT(dword, 2));
918 printf("TRANS_DP_CTL_B HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
919 printf("TRANS_DP_CTL_B Audio_Output_Enable\t\t\t%lu\n", BIT(dword, 6));
920
921 dword = INREG(TRANS_DP_CTL_C);
922 printf("TRANS_DP_CTL_C DisplayPort_Enable\t\t\t%lu\n", BIT(dword, 31));
923 printf("TRANS_DP_CTL_C Port_Width_Selection\t\t\t[0x%lx] %s\n",
924 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
925 printf("TRANS_DP_CTL_C Port_Detected\t\t\t\t%lu\n", BIT(dword, 2));
926 printf("TRANS_DP_CTL_C HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
927 printf("TRANS_DP_CTL_C Audio_Output_Enable\t\t\t%lu\n", BIT(dword, 6));
928
929 dword = INREG(AUD_CONFIG_A);
930 printf("AUD_CONFIG_A Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
931 OPNAME(pixel_clock, BITS(dword, 19, 16)));
932 dword = INREG(AUD_CONFIG_B);
933 printf("AUD_CONFIG_B Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
934 OPNAME(pixel_clock, BITS(dword, 19, 16)));
935 dword = INREG(AUD_CONFIG_C);
936 printf("AUD_CONFIG_C Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
937 OPNAME(pixel_clock, BITS(dword, 19, 16)));
938
939 dword = INREG(AUD_CTS_ENABLE_A);
940 printf("AUD_CTS_ENABLE_A Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
941 printf("AUD_CTS_ENABLE_A CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
942 printf("AUD_CTS_ENABLE_A CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
943 dword = INREG(AUD_CTS_ENABLE_B);
944 printf("AUD_CTS_ENABLE_B Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
945 printf("AUD_CTS_ENABLE_B CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
946 printf("AUD_CTS_ENABLE_B CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
947 dword = INREG(AUD_CTS_ENABLE_C);
948 printf("AUD_CTS_ENABLE_C Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
949 printf("AUD_CTS_ENABLE_C CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
950 printf("AUD_CTS_ENABLE_C CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
951
952 dword = INREG(AUD_MISC_CTRL_A);
953 printf("AUD_MISC_CTRL_A Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
954 printf("AUD_MISC_CTRL_A Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
955 printf("AUD_MISC_CTRL_A Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
956 printf("AUD_MISC_CTRL_A Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
957 dword = INREG(AUD_MISC_CTRL_B);
958 printf("AUD_MISC_CTRL_B Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
959 printf("AUD_MISC_CTRL_B Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
960 printf("AUD_MISC_CTRL_B Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
961 printf("AUD_MISC_CTRL_B Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
962 dword = INREG(AUD_MISC_CTRL_C);
963 printf("AUD_MISC_CTRL_C Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
964 printf("AUD_MISC_CTRL_C Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
965 printf("AUD_MISC_CTRL_C Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
966 printf("AUD_MISC_CTRL_C Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
967
968 dword = INREG(AUD_PWRST);
969 printf("AUD_PWRST Func_Grp_Dev_PwrSt_Curr \t%s\n", power_state[BITS(dword, 27, 26)]);
970 printf("AUD_PWRST Func_Grp_Dev_PwrSt_Set \t%s\n", power_state[BITS(dword, 25, 24)]);
971 printf("AUD_PWRST ConvertorA_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 15, 14)]);
972 printf("AUD_PWRST ConvertorA_Widget_Power_State_Requsted \t%s\n", power_state[BITS(dword, 13, 12)]);
973 printf("AUD_PWRST ConvertorB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 19, 18)]);
974 printf("AUD_PWRST ConvertorB_Widget_Power_State_Requested \t%s\n", power_state[BITS(dword, 17, 16)]);
975 printf("AUD_PWRST ConvC_Widget_PwrSt_Curr \t%s\n", power_state[BITS(dword, 23, 22)]);
976 printf("AUD_PWRST ConvC_Widget_PwrSt_Req \t%s\n", power_state[BITS(dword, 21, 20)]);
977 printf("AUD_PWRST PinB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 3, 2)]);
978 printf("AUD_PWRST PinB_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 1, 0)]);
979 printf("AUD_PWRST PinC_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 7, 6)]);
980 printf("AUD_PWRST PinC_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 5, 4)]);
981 printf("AUD_PWRST PinD_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 11, 10)]);
982 printf("AUD_PWRST PinD_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 9, 8)]);
983
984 dword = INREG(AUD_PORT_EN_HD_CFG);
985 printf("AUD_PORT_EN_HD_CFG Convertor_A_Digen\t\t\t%lu\n", BIT(dword, 0));
986 printf("AUD_PORT_EN_HD_CFG Convertor_B_Digen\t\t\t%lu\n", BIT(dword, 1));
987 printf("AUD_PORT_EN_HD_CFG Convertor_C_Digen\t\t\t%lu\n", BIT(dword, 2));
988 printf("AUD_PORT_EN_HD_CFG ConvertorA_Stream_ID\t\t%lu\n", BITS(dword, 7, 4));
989 printf("AUD_PORT_EN_HD_CFG ConvertorB_Stream_ID\t\t%lu\n", BITS(dword, 11, 8));
990 printf("AUD_PORT_EN_HD_CFG ConvertorC_Stream_ID\t\t%lu\n", BITS(dword, 15, 12));
991 printf("AUD_PORT_EN_HD_CFG Port_B_Out_Enable\t\t\t%lu\n", BIT(dword, 16));
992 printf("AUD_PORT_EN_HD_CFG Port_C_Out_Enable\t\t\t%lu\n", BIT(dword, 17));
993 printf("AUD_PORT_EN_HD_CFG Port_D_Out_Enable\t\t\t%lu\n", BIT(dword, 18));
994 printf("AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status\t\t%lu\n", BIT(dword, 20));
995 printf("AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status\t\t%lu\n", BIT(dword, 21));
996 printf("AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status\t\t%lu\n", BIT(dword, 22));
997
998 dword = INREG(AUD_OUT_DIG_CNVT_A);
999 printf("AUD_OUT_DIG_CNVT_A V\t\t\t\t\t%lu\n", BIT(dword, 1));
1000 printf("AUD_OUT_DIG_CNVT_A VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1001 printf("AUD_OUT_DIG_CNVT_A PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1002 printf("AUD_OUT_DIG_CNVT_A Copy\t\t\t\t%lu\n", BIT(dword, 4));
1003 printf("AUD_OUT_DIG_CNVT_A NonAudio\t\t\t\t0x%lx\n", BIT(dword, 5));
1004 printf("AUD_OUT_DIG_CNVT_A PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1005 printf("AUD_OUT_DIG_CNVT_A Level\t\t\t\t%lu\n", BIT(dword, 7));
1006 printf("AUD_OUT_DIG_CNVT_A Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1007 printf("AUD_OUT_DIG_CNVT_A Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
1008 printf("AUD_OUT_DIG_CNVT_A Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
1009
1010 dword = INREG(AUD_OUT_DIG_CNVT_B);
1011 printf("AUD_OUT_DIG_CNVT_B V\t\t\t\t\t%lu\n", BIT(dword, 1));
1012 printf("AUD_OUT_DIG_CNVT_B VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1013 printf("AUD_OUT_DIG_CNVT_B PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1014 printf("AUD_OUT_DIG_CNVT_B Copy\t\t\t\t%lu\n", BIT(dword, 4));
1015 printf("AUD_OUT_DIG_CNVT_B NonAudio\t\t\t\t0x%lx\n", BIT(dword, 5));
1016 printf("AUD_OUT_DIG_CNVT_B PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1017 printf("AUD_OUT_DIG_CNVT_B Level\t\t\t\t%lu\n", BIT(dword, 7));
1018 printf("AUD_OUT_DIG_CNVT_B Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1019 printf("AUD_OUT_DIG_CNVT_B Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
1020 printf("AUD_OUT_DIG_CNVT_B Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
1021
1022 dword = INREG(AUD_OUT_DIG_CNVT_C);
1023 printf("AUD_OUT_DIG_CNVT_C V\t\t\t\t\t%lu\n", BIT(dword, 1));
1024 printf("AUD_OUT_DIG_CNVT_C VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1025 printf("AUD_OUT_DIG_CNVT_C PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1026 printf("AUD_OUT_DIG_CNVT_C Copy\t\t\t\t%lu\n", BIT(dword, 4));
1027 printf("AUD_OUT_DIG_CNVT_C NonAudio\t\t\t\t0x%lx\n", BIT(dword, 5));
1028 printf("AUD_OUT_DIG_CNVT_C PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1029 printf("AUD_OUT_DIG_CNVT_C Level\t\t\t\t%lu\n", BIT(dword, 7));
1030 printf("AUD_OUT_DIG_CNVT_C Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1031 printf("AUD_OUT_DIG_CNVT_C Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
1032 printf("AUD_OUT_DIG_CNVT_C Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
1033
1034 printf("AUD_OUT_CH_STR Converter_Channel_MAP PORTB PORTC PORTD\n");
1035 for (i = 0; i < 8; i++) {
1036 OUTREG(AUD_OUT_CH_STR, i | (i << 8) | (i << 16));
1037 dword = INREG(AUD_OUT_CH_STR);
1038 printf("\t\t\t\t%lu\t%lu\t%lu\t%lu\n",
1039 1 + BITS(dword, 3, 0),
1040 1 + BITS(dword, 7, 4),
1041 1 + BITS(dword, 15, 12),
1042 1 + BITS(dword, 23, 20));
1043 }
1044
1045 dword = INREG(AUD_OUT_STR_DESC_A);
1046 printf("AUD_OUT_STR_DESC_A HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
1047 printf("AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16));
1048 printf("AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t%lu\n", BITS(dword, 6, 4));
1049 printf("AUD_OUT_STR_DESC_A Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
1050
1051 dword = INREG(AUD_OUT_STR_DESC_B);
1052 printf("AUD_OUT_STR_DESC_B HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
1053 printf("AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16));
1054 printf("AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t%lu\n", BITS(dword, 6, 4));
1055 printf("AUD_OUT_STR_DESC_B Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
1056
1057 dword = INREG(AUD_OUT_STR_DESC_C);
1058 printf("AUD_OUT_STR_DESC_C HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
1059 printf("AUD_OUT_STR_DESC_C Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16));
1060 printf("AUD_OUT_STR_DESC_C Bits_per_Sample\t\t\t%lu\n", BITS(dword, 6, 4));
1061 printf("AUD_OUT_STR_DESC_C Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
1062
1063 dword = INREG(AUD_PINW_CONNLNG_SEL);
1064 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_B\t%lu\n", BITS(dword, 7, 0));
1065 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_C\t%lu\n", BITS(dword, 15, 8));
1066 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_D\t%lu\n", BITS(dword, 23, 16));
1067
1068 dword = INREG(AUD_CNTL_ST_A);
1069 printf("AUD_CNTL_ST_A DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1070 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
1071 printf("AUD_CNTL_ST_A DIP_type_enable_status Audio DIP\t\t%lu\n", BIT(dword, 21));
1072 printf("AUD_CNTL_ST_A DIP_type_enable_status Generic 1 ACP DIP\t%lu\n", BIT(dword, 22));
1073 printf("AUD_CNTL_ST_A DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
1074 printf("AUD_CNTL_ST_A DIP_transmission_frequency\t\t[0x%lx] %s\n",
1075 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1076 printf("AUD_CNTL_ST_A ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
1077 printf("AUD_CNTL_ST_A ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
1078
1079 dword = INREG(AUD_CNTL_ST_B);
1080 printf("AUD_CNTL_ST_B DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1081 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
1082 printf("AUD_CNTL_ST_B DIP_type_enable_status Audio DIP\t\t%lu\n", BIT(dword, 21));
1083 printf("AUD_CNTL_ST_B DIP_type_enable_status Generic 1 ACP DIP\t%lu\n", BIT(dword, 22));
1084 printf("AUD_CNTL_ST_B DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
1085 printf("AUD_CNTL_ST_B DIP_transmission_frequency\t\t[0x%lx] %s\n",
1086 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1087 printf("AUD_CNTL_ST_B ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
1088 printf("AUD_CNTL_ST_B ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
1089
1090 dword = INREG(AUD_CNTL_ST_C);
1091 printf("AUD_CNTL_ST_C DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1092 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
1093 printf("AUD_CNTL_ST_C DIP_type_enable_status Audio DIP\t\t%lu\n", BIT(dword, 21));
1094 printf("AUD_CNTL_ST_C DIP_type_enable_status Generic 1 ACP DIP\t%lu\n", BIT(dword, 22));
1095 printf("AUD_CNTL_ST_C DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
1096 printf("AUD_CNTL_ST_C DIP_transmission_frequency\t\t[0x%lx] %s\n",
1097 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1098 printf("AUD_CNTL_ST_C ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
1099 printf("AUD_CNTL_ST_C ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
1100
1101 dword = INREG(AUD_CNTRL_ST2);
1102 printf("AUD_CNTRL_ST2 CP_ReadyB\t\t\t\t%lu\n", BIT(dword, 1));
1103 printf("AUD_CNTRL_ST2 ELD_validB\t\t\t\t%lu\n", BIT(dword, 0));
1104 printf("AUD_CNTRL_ST2 CP_ReadyC\t\t\t\t%lu\n", BIT(dword, 5));
1105 printf("AUD_CNTRL_ST2 ELD_validC\t\t\t\t%lu\n", BIT(dword, 4));
1106 printf("AUD_CNTRL_ST2 CP_ReadyD\t\t\t\t%lu\n", BIT(dword, 9));
1107 printf("AUD_CNTRL_ST2 ELD_validD\t\t\t\t%lu\n", BIT(dword, 8));
1108
1109 dword = INREG(AUD_CNTRL_ST3);
1110 printf("AUD_CNTRL_ST3 TransA_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 3));
1111 printf("AUD_CNTRL_ST3 TransA_to_Port_Sel\t\t\t[%#lx] %s\n",
1112 BITS(dword, 2, 0), trans_to_port_sel[BITS(dword, 2, 0)]);
1113 printf("AUD_CNTRL_ST3 TransB_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 7));
1114 printf("AUD_CNTRL_ST3 TransB_to_Port_Sel\t\t\t[%#lx] %s\n",
1115 BITS(dword, 6, 4), trans_to_port_sel[BITS(dword, 6, 4)]);
1116 printf("AUD_CNTRL_ST3 TransC_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 11));
1117 printf("AUD_CNTRL_ST3 TransC_to_Port_Sel\t\t\t[%#lx] %s\n",
1118 BITS(dword, 10, 8), trans_to_port_sel[BITS(dword, 10, 8)]);
1119
1120 dword = INREG(AUD_HDMIW_STATUS);
1121 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 27));
1122 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 26));
1123 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 29));
1124 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 28));
1125 printf("AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 31));
1126 printf("AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 30));
1127 printf("AUD_HDMIW_STATUS BCLK/CDCLK_FIFO_Overrun\t\t%lu\n", BIT(dword, 25));
1128 printf("AUD_HDMIW_STATUS Function_Reset\t\t\t%lu\n", BIT(dword, 24));
1129
1130 printf("AUD_HDMIW_HDMIEDID_A HDMI ELD:\n\t");
1131 dword = INREG(AUD_CNTL_ST_A);
1132 dword &= ~BITMASK(9, 5);
1133 OUTREG(AUD_CNTL_ST_A, dword);
1134 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1135 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_A)));
1136 printf("\n");
1137
1138 printf("AUD_HDMIW_HDMIEDID_B HDMI ELD:\n\t");
1139 dword = INREG(AUD_CNTL_ST_B);
1140 dword &= ~BITMASK(9, 5);
1141 OUTREG(AUD_CNTL_ST_B, dword);
1142 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1143 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_B)));
1144 printf("\n");
1145
1146 printf("AUD_HDMIW_HDMIEDID_C HDMI ELD:\n\t");
1147 dword = INREG(AUD_CNTL_ST_C);
1148 dword &= ~BITMASK(9, 5);
1149 OUTREG(AUD_CNTL_ST_C, dword);
1150 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1151 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_C)));
1152 printf("\n");
1153
1154 printf("AUD_HDMIW_INFOFR_A HDMI audio Infoframe:\n\t");
1155 dword = INREG(AUD_CNTL_ST_A);
1156 dword &= ~BITMASK(20, 18);
1157 dword &= ~BITMASK(3, 0);
1158 OUTREG(AUD_CNTL_ST_A, dword);
1159 for (i = 0; i < 8; i++)
1160 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_A)));
1161 printf("\n");
1162
1163 printf("AUD_HDMIW_INFOFR_B HDMI audio Infoframe:\n\t");
1164 dword = INREG(AUD_CNTL_ST_B);
1165 dword &= ~BITMASK(20, 18);
1166 dword &= ~BITMASK(3, 0);
1167 OUTREG(AUD_CNTL_ST_B, dword);
1168 for (i = 0; i < 8; i++)
1169 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_B)));
1170 printf("\n");
1171
1172 printf("AUD_HDMIW_INFOFR_C HDMI audio Infoframe:\n\t");
1173 dword = INREG(AUD_CNTL_ST_C);
1174 dword &= ~BITMASK(20, 18);
1175 dword &= ~BITMASK(3, 0);
1176 OUTREG(AUD_CNTL_ST_C, dword);
1177 for (i = 0; i < 8; i++)
1178 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_C)));
1179 printf("\n");
1180
1181}
1182
1183int main(int argc, char **argv)
1184{
1185 struct pci_device *pci_dev;
1186
1187 pci_dev = intel_get_pci_device();
1188 devid = pci_dev->device_id; /* XXX not true when mapping! */
1189
1190 do_self_tests();
1191
1192 if (argc == 2)
1193 intel_map_file(argv[1]);
1194 else
1195 intel_get_mmio(pci_dev);
1196
1197 if (HAS_PCH_SPLIT(devid) || getenv("HAS_PCH_SPLIT")) {
1198 intel_check_pch();
1199 dump_cpt();
1200 } else if (IS_IRONLAKE(devid))
1201 dump_ironlake();
1202 else
1203 dump_eaglelake();
1204
1205 return 0;
Wu Fengguang9e9c9f22009-11-06 11:06:22 +08001206}