Chris Wilson | eb7d60e | 2015-06-17 18:29:49 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2015 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | */ |
| 24 | |
| 25 | /* |
| 26 | * Testcase: Test that only specific ioctl report a wedged GPU. |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #include <stdlib.h> |
| 31 | #include <stdio.h> |
| 32 | #include <string.h> |
| 33 | #include <unistd.h> |
| 34 | #include <fcntl.h> |
| 35 | #include <inttypes.h> |
| 36 | #include <errno.h> |
| 37 | #include <sys/ioctl.h> |
| 38 | |
| 39 | #include <drm.h> |
| 40 | |
Chris Wilson | 639d640 | 2017-09-08 13:45:21 +0100 | [diff] [blame^] | 41 | #include "igt.h" |
| 42 | #include "igt_sysfs.h" |
Chris Wilson | 92e457d | 2017-09-08 11:33:15 +0100 | [diff] [blame] | 43 | #include "sw_sync.h" |
Chris Wilson | eb7d60e | 2015-06-17 18:29:49 +0100 | [diff] [blame] | 44 | |
| 45 | IGT_TEST_DESCRIPTION("Test that specific ioctls report a wedged GPU (EIO)."); |
| 46 | |
| 47 | static bool i915_reset_control(bool enable) |
| 48 | { |
| 49 | const char *path = "/sys/module/i915/parameters/reset"; |
| 50 | int fd, ret; |
| 51 | |
| 52 | igt_debug("%s GPU reset\n", enable ? "Enabling" : "Disabling"); |
| 53 | |
| 54 | fd = open(path, O_RDWR); |
| 55 | igt_require(fd >= 0); |
| 56 | |
Chris Wilson | 6b2dddd | 2017-07-25 17:11:16 +0100 | [diff] [blame] | 57 | ret = write(fd, &"01"[enable], 1) == 1; |
Chris Wilson | eb7d60e | 2015-06-17 18:29:49 +0100 | [diff] [blame] | 58 | close(fd); |
| 59 | |
| 60 | return ret; |
| 61 | } |
| 62 | |
Chris Wilson | eb7d60e | 2015-06-17 18:29:49 +0100 | [diff] [blame] | 63 | static void trigger_reset(int fd) |
| 64 | { |
Chris Wilson | 83884e9 | 2017-03-21 17:16:03 +0000 | [diff] [blame] | 65 | igt_force_gpu_reset(fd); |
Chris Wilson | eb7d60e | 2015-06-17 18:29:49 +0100 | [diff] [blame] | 66 | |
| 67 | /* And just check the gpu is indeed running again */ |
| 68 | igt_debug("Checking that the GPU recovered\n"); |
| 69 | gem_quiescent_gpu(fd); |
| 70 | } |
| 71 | |
| 72 | static void wedge_gpu(int fd) |
| 73 | { |
| 74 | /* First idle the GPU then disable GPU resets before injecting a hang */ |
| 75 | gem_quiescent_gpu(fd); |
| 76 | |
| 77 | igt_require(i915_reset_control(false)); |
| 78 | |
| 79 | igt_debug("Wedging GPU by injecting hang\n"); |
| 80 | igt_post_hang_ring(fd, igt_hang_ring(fd, I915_EXEC_DEFAULT)); |
| 81 | |
| 82 | igt_assert(i915_reset_control(true)); |
| 83 | } |
| 84 | |
| 85 | static int __gem_throttle(int fd) |
| 86 | { |
| 87 | int err = 0; |
| 88 | if (drmIoctl(fd, DRM_IOCTL_I915_GEM_THROTTLE, NULL)) |
| 89 | err = -errno; |
| 90 | return err; |
| 91 | } |
| 92 | |
| 93 | static void test_throttle(int fd) |
| 94 | { |
| 95 | wedge_gpu(fd); |
| 96 | |
| 97 | igt_assert_eq(__gem_throttle(fd), -EIO); |
| 98 | |
| 99 | trigger_reset(fd); |
| 100 | } |
| 101 | |
Chris Wilson | eb7d60e | 2015-06-17 18:29:49 +0100 | [diff] [blame] | 102 | static void test_execbuf(int fd) |
| 103 | { |
| 104 | struct drm_i915_gem_execbuffer2 execbuf; |
| 105 | struct drm_i915_gem_exec_object2 exec; |
| 106 | uint32_t tmp[] = { MI_BATCH_BUFFER_END }; |
| 107 | |
| 108 | memset(&exec, 0, sizeof(exec)); |
| 109 | memset(&execbuf, 0, sizeof(execbuf)); |
| 110 | |
| 111 | exec.handle = gem_create(fd, 4096); |
| 112 | gem_write(fd, exec.handle, 0, tmp, sizeof(tmp)); |
| 113 | |
Chris Wilson | 4de67b2 | 2017-01-02 11:05:21 +0000 | [diff] [blame] | 114 | execbuf.buffers_ptr = to_user_pointer(&exec); |
Chris Wilson | eb7d60e | 2015-06-17 18:29:49 +0100 | [diff] [blame] | 115 | execbuf.buffer_count = 1; |
| 116 | |
| 117 | wedge_gpu(fd); |
| 118 | |
| 119 | igt_assert_eq(__gem_execbuf(fd, &execbuf), -EIO); |
| 120 | gem_close(fd, exec.handle); |
| 121 | |
| 122 | trigger_reset(fd); |
| 123 | } |
| 124 | |
Chris Wilson | 32c8988 | 2015-07-15 16:18:10 +0100 | [diff] [blame] | 125 | static int __gem_wait(int fd, uint32_t handle, int64_t timeout) |
| 126 | { |
| 127 | struct drm_i915_gem_wait wait; |
| 128 | int err = 0; |
| 129 | |
| 130 | memset(&wait, 0, sizeof(wait)); |
| 131 | wait.bo_handle = handle; |
| 132 | wait.timeout_ns = timeout; |
| 133 | if (drmIoctl(fd, DRM_IOCTL_I915_GEM_WAIT, &wait)) |
| 134 | err = -errno; |
| 135 | |
| 136 | return err; |
| 137 | } |
| 138 | |
| 139 | static void test_wait(int fd) |
| 140 | { |
Chris Wilson | 0a1fc45 | 2016-09-13 11:13:14 +0100 | [diff] [blame] | 141 | igt_hang_t hang; |
Chris Wilson | 32c8988 | 2015-07-15 16:18:10 +0100 | [diff] [blame] | 142 | |
Daniel Vetter | 40798ef | 2015-12-16 13:13:58 +0000 | [diff] [blame] | 143 | /* If the request we wait on completes due to a hang (even for |
| 144 | * that request), the user expects the return value to 0 (success). |
| 145 | */ |
Chris Wilson | 32c8988 | 2015-07-15 16:18:10 +0100 | [diff] [blame] | 146 | hang = igt_hang_ring(fd, I915_EXEC_DEFAULT); |
Daniel Vetter | 40798ef | 2015-12-16 13:13:58 +0000 | [diff] [blame] | 147 | igt_assert_eq(__gem_wait(fd, hang.handle, -1), 0); |
Chris Wilson | 32c8988 | 2015-07-15 16:18:10 +0100 | [diff] [blame] | 148 | igt_post_hang_ring(fd, hang); |
| 149 | |
Daniel Vetter | 40798ef | 2015-12-16 13:13:58 +0000 | [diff] [blame] | 150 | /* If the GPU is wedged during the wait, again we expect the return |
| 151 | * value to be 0 (success). |
| 152 | */ |
| 153 | igt_require(i915_reset_control(false)); |
| 154 | hang = igt_hang_ring(fd, I915_EXEC_DEFAULT); |
| 155 | igt_assert_eq(__gem_wait(fd, hang.handle, -1), 0); |
| 156 | igt_post_hang_ring(fd, hang); |
| 157 | igt_require(i915_reset_control(true)); |
| 158 | |
Chris Wilson | 32c8988 | 2015-07-15 16:18:10 +0100 | [diff] [blame] | 159 | trigger_reset(fd); |
| 160 | } |
| 161 | |
Chris Wilson | 92e457d | 2017-09-08 11:33:15 +0100 | [diff] [blame] | 162 | static void test_inflight_external(int fd) |
Chris Wilson | 9bbf642 | 2016-11-18 08:50:33 +0000 | [diff] [blame] | 163 | { |
| 164 | struct drm_i915_gem_execbuffer2 execbuf; |
Chris Wilson | 92e457d | 2017-09-08 11:33:15 +0100 | [diff] [blame] | 165 | struct drm_i915_gem_exec_object2 obj; |
Chris Wilson | 9bbf642 | 2016-11-18 08:50:33 +0000 | [diff] [blame] | 166 | uint32_t bbe = MI_BATCH_BUFFER_END; |
| 167 | igt_hang_t hang; |
Chris Wilson | 92e457d | 2017-09-08 11:33:15 +0100 | [diff] [blame] | 168 | int timeline, fence; |
| 169 | |
| 170 | igt_require_sw_sync(); |
| 171 | igt_require(gem_has_exec_fence(fd)); |
| 172 | |
| 173 | timeline = sw_sync_timeline_create(); |
| 174 | fence = sw_sync_timeline_create_fence(timeline, 1); |
Chris Wilson | 9bbf642 | 2016-11-18 08:50:33 +0000 | [diff] [blame] | 175 | |
| 176 | igt_require(i915_reset_control(false)); |
| 177 | hang = igt_hang_ring(fd, I915_EXEC_DEFAULT); |
| 178 | |
Chris Wilson | 92e457d | 2017-09-08 11:33:15 +0100 | [diff] [blame] | 179 | memset(&obj, 0, sizeof(obj)); |
| 180 | obj.handle = gem_create(fd, 4096); |
| 181 | gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe)); |
Chris Wilson | 9bbf642 | 2016-11-18 08:50:33 +0000 | [diff] [blame] | 182 | |
| 183 | memset(&execbuf, 0, sizeof(execbuf)); |
Chris Wilson | 92e457d | 2017-09-08 11:33:15 +0100 | [diff] [blame] | 184 | execbuf.buffers_ptr = to_user_pointer(&obj); |
| 185 | execbuf.buffer_count = 1; |
| 186 | execbuf.flags = I915_EXEC_FENCE_IN | I915_EXEC_FENCE_OUT; |
| 187 | execbuf.rsvd2 = (uint32_t)fence; |
Chris Wilson | 9bbf642 | 2016-11-18 08:50:33 +0000 | [diff] [blame] | 188 | |
Chris Wilson | 92e457d | 2017-09-08 11:33:15 +0100 | [diff] [blame] | 189 | gem_execbuf_wr(fd, &execbuf); |
| 190 | close(fence); |
Chris Wilson | 9bbf642 | 2016-11-18 08:50:33 +0000 | [diff] [blame] | 191 | |
Chris Wilson | 92e457d | 2017-09-08 11:33:15 +0100 | [diff] [blame] | 192 | fence = execbuf.rsvd2 >> 32; |
| 193 | igt_assert(fence != -1); |
Chris Wilson | 9bbf642 | 2016-11-18 08:50:33 +0000 | [diff] [blame] | 194 | |
Chris Wilson | 92e457d | 2017-09-08 11:33:15 +0100 | [diff] [blame] | 195 | igt_post_hang_ring(fd, hang); /* wedged, with an unready batch */ |
| 196 | sw_sync_timeline_inc(timeline, 1); /* only now submit our batches */ |
| 197 | |
| 198 | igt_assert_eq(__gem_wait(fd, obj.handle, -1), 0); |
| 199 | igt_assert_eq(sync_fence_status(fence), -EIO); |
| 200 | close(fence); |
| 201 | |
| 202 | igt_assert(i915_reset_control(true)); |
Chris Wilson | 9bbf642 | 2016-11-18 08:50:33 +0000 | [diff] [blame] | 203 | trigger_reset(fd); |
Chris Wilson | 92e457d | 2017-09-08 11:33:15 +0100 | [diff] [blame] | 204 | close(timeline); |
Chris Wilson | 9bbf642 | 2016-11-18 08:50:33 +0000 | [diff] [blame] | 205 | } |
| 206 | |
Chris Wilson | 639d640 | 2017-09-08 13:45:21 +0100 | [diff] [blame^] | 207 | static void test_inflight_internal(int fd) |
| 208 | { |
| 209 | struct drm_i915_gem_execbuffer2 execbuf; |
| 210 | struct drm_i915_gem_exec_object2 obj[2]; |
| 211 | uint32_t bbe = MI_BATCH_BUFFER_END; |
| 212 | unsigned engine, nfence = 0; |
| 213 | int fences[16]; |
| 214 | igt_hang_t hang; |
| 215 | |
| 216 | igt_require(gem_has_exec_fence(fd)); |
| 217 | |
| 218 | igt_require(i915_reset_control(false)); |
| 219 | hang = igt_hang_ring(fd, I915_EXEC_DEFAULT); |
| 220 | |
| 221 | memset(obj, 0, sizeof(obj)); |
| 222 | obj[0].handle = hang.handle; |
| 223 | obj[0].flags = EXEC_OBJECT_WRITE; |
| 224 | obj[1].handle = gem_create(fd, 4096); |
| 225 | gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe)); |
| 226 | |
| 227 | memset(&execbuf, 0, sizeof(execbuf)); |
| 228 | execbuf.buffers_ptr = to_user_pointer(obj); |
| 229 | execbuf.buffer_count = 2; |
| 230 | for_each_engine(fd, engine) { |
| 231 | execbuf.flags = engine | I915_EXEC_FENCE_OUT; |
| 232 | |
| 233 | gem_execbuf_wr(fd, &execbuf); |
| 234 | |
| 235 | fences[nfence] = execbuf.rsvd2 >> 32; |
| 236 | igt_assert(fences[nfence] != -1); |
| 237 | nfence++; |
| 238 | } |
| 239 | |
| 240 | igt_post_hang_ring(fd, hang); /* wedged, with an unready batch */ |
| 241 | |
| 242 | igt_assert_eq(__gem_wait(fd, obj[1].handle, -1), 0); |
| 243 | while (nfence--) { |
| 244 | igt_assert_eq(sync_fence_status(fences[nfence]), -EIO); |
| 245 | close(fences[nfence]); |
| 246 | } |
| 247 | |
| 248 | igt_assert(i915_reset_control(true)); |
| 249 | trigger_reset(fd); |
| 250 | } |
| 251 | |
| 252 | #define HAVE_EXECLISTS 0x1 |
| 253 | #define HAVE_GUC 0x2 |
| 254 | #define HAVE_SEMAPHORES 0x4 |
| 255 | |
| 256 | static unsigned print_welcome(int fd) |
| 257 | { |
| 258 | unsigned flags = 0; |
| 259 | bool active; |
| 260 | int dir; |
| 261 | |
| 262 | dir = igt_sysfs_open_parameters(fd); |
| 263 | if (dir < 0) |
| 264 | return 0; |
| 265 | |
| 266 | active = igt_sysfs_get_boolean(dir, "enable_guc_submission"); |
| 267 | if (active) { |
| 268 | igt_info("Using GuC submission\n"); |
| 269 | flags |= HAVE_GUC | HAVE_EXECLISTS; |
| 270 | goto out; |
| 271 | } |
| 272 | |
| 273 | active = igt_sysfs_get_boolean(dir, "enable_execlists"); |
| 274 | if (active) { |
| 275 | igt_info("Using Execlists submission\n"); |
| 276 | flags |= HAVE_EXECLISTS; |
| 277 | goto out; |
| 278 | } |
| 279 | |
| 280 | active = igt_sysfs_get_boolean(dir, "semaphores"); |
| 281 | if (active) |
| 282 | flags |= HAVE_SEMAPHORES; |
| 283 | igt_info("Using Legacy submission%s\n", |
| 284 | active ? ", with semaphores" : ""); |
| 285 | |
| 286 | out: |
| 287 | close(dir); |
| 288 | return flags; |
| 289 | } |
| 290 | |
Chris Wilson | 4f082c3 | 2017-09-08 13:48:05 +0100 | [diff] [blame] | 291 | static int fd = -1; |
| 292 | |
| 293 | static void |
| 294 | exit_handler(int sig) |
| 295 | { |
| 296 | i915_reset_control(true); |
| 297 | igt_force_gpu_reset(fd); |
| 298 | } |
| 299 | |
Chris Wilson | eb7d60e | 2015-06-17 18:29:49 +0100 | [diff] [blame] | 300 | igt_main |
| 301 | { |
Chris Wilson | 639d640 | 2017-09-08 13:45:21 +0100 | [diff] [blame^] | 302 | unsigned int caps = 0; |
Chris Wilson | eb7d60e | 2015-06-17 18:29:49 +0100 | [diff] [blame] | 303 | |
| 304 | igt_skip_on_simulation(); |
| 305 | |
| 306 | igt_fixture { |
Micah Fedke | c81d293 | 2015-07-22 21:54:02 +0000 | [diff] [blame] | 307 | fd = drm_open_driver(DRIVER_INTEL); |
Chris Wilson | 4f082c3 | 2017-09-08 13:48:05 +0100 | [diff] [blame] | 308 | |
| 309 | igt_require(i915_reset_control(true)); |
| 310 | igt_force_gpu_reset(fd); |
| 311 | igt_install_exit_handler(exit_handler); |
| 312 | |
Chris Wilson | 639d640 | 2017-09-08 13:45:21 +0100 | [diff] [blame^] | 313 | caps = print_welcome(fd); |
Chris Wilson | 28a2f14 | 2017-03-08 12:22:13 +0000 | [diff] [blame] | 314 | igt_require_gem(fd); |
Chris Wilson | 92caf13 | 2015-12-16 09:23:56 +0000 | [diff] [blame] | 315 | igt_require_hang_ring(fd, I915_EXEC_DEFAULT); |
Chris Wilson | eb7d60e | 2015-06-17 18:29:49 +0100 | [diff] [blame] | 316 | } |
| 317 | |
| 318 | igt_subtest("throttle") |
| 319 | test_throttle(fd); |
| 320 | |
| 321 | igt_subtest("execbuf") |
| 322 | test_execbuf(fd); |
| 323 | |
Chris Wilson | 32c8988 | 2015-07-15 16:18:10 +0100 | [diff] [blame] | 324 | igt_subtest("wait") |
| 325 | test_wait(fd); |
| 326 | |
Chris Wilson | 92e457d | 2017-09-08 11:33:15 +0100 | [diff] [blame] | 327 | igt_subtest("in-flight-external") |
| 328 | test_inflight_external(fd); |
Chris Wilson | 639d640 | 2017-09-08 13:45:21 +0100 | [diff] [blame^] | 329 | |
| 330 | igt_subtest("in-flight-internal") { |
| 331 | igt_skip_on(caps & HAVE_SEMAPHORES); |
| 332 | test_inflight_internal(fd); |
| 333 | } |
Chris Wilson | eb7d60e | 2015-06-17 18:29:49 +0100 | [diff] [blame] | 334 | } |