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gerrit-public.fairphone.software / platform / external / igt-gpu-tools / 70254d180b13a6bd1c6ae3f425a9cd2642da8392 / . / assembler / brw_structs.h
blob: 8c2d2b9fc02f69fa437684e08e676044928ead43 [file] [log] [blame]
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1/*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]5
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]13
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]17
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]25
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]31
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]32
33#ifndef BRW_STRUCTS_H
34#define BRW_STRUCTS_H
35
Damien Lespiaue75faa32013-01-31 14:25:42 +0000[diff] [blame]36#include <stdint.h>
37
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]38/* These seem to be passed around as function args, so it works out
39 * better to keep them as #defines:
40 */
41#define BRW_FLUSH_READ_CACHE 0x1
42#define BRW_FLUSH_STATE_CACHE 0x2
43#define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4
44#define BRW_FLUSH_SNAPSHOT_COUNTERS 0x8
45
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]46struct brw_urb_fence
47{
48 struct
49 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]50 unsigned length:8;
51 unsigned vs_realloc:1;
52 unsigned gs_realloc:1;
53 unsigned clp_realloc:1;
54 unsigned sf_realloc:1;
55 unsigned vfe_realloc:1;
56 unsigned cs_realloc:1;
57 unsigned pad:2;
58 unsigned opcode:16;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]59 } header;
60
61 struct
62 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]63 unsigned vs_fence:10;
64 unsigned gs_fence:10;
65 unsigned clp_fence:10;
66 unsigned pad:2;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]67 } bits0;
68
69 struct
70 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]71 unsigned sf_fence:10;
72 unsigned vf_fence:10;
73 unsigned cs_fence:11;
74 unsigned pad:1;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]75 } bits1;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]76};
77
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]78/* State structs for the various fixed function units:
79 */
80
81
82struct thread0
83{
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]84 unsigned pad0:1;
85 unsigned grf_reg_count:3;
86 unsigned pad1:2;
87 unsigned kernel_start_pointer:26; /* Offset from GENERAL_STATE_BASE */
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]88};
89
90struct thread1
91{
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]92 unsigned ext_halt_exception_enable:1;
93 unsigned sw_exception_enable:1;
94 unsigned mask_stack_exception_enable:1;
95 unsigned timeout_exception_enable:1;
96 unsigned illegal_op_exception_enable:1;
97 unsigned pad0:3;
98 unsigned depth_coef_urb_read_offset:6; /* WM only */
99 unsigned pad1:2;
100 unsigned floating_point_mode:1;
101 unsigned thread_priority:1;
102 unsigned binding_table_entry_count:8;
103 unsigned pad3:5;
104 unsigned single_program_flow:1;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]105};
106
107struct thread2
108{
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]109 unsigned per_thread_scratch_space:4;
110 unsigned pad0:6;
111 unsigned scratch_space_base_pointer:22;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]112};
113
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]114
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]115struct thread3
116{
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]117 unsigned dispatch_grf_start_reg:4;
118 unsigned urb_entry_read_offset:6;
119 unsigned pad0:1;
120 unsigned urb_entry_read_length:6;
121 unsigned pad1:1;
122 unsigned const_urb_entry_read_offset:6;
123 unsigned pad2:1;
124 unsigned const_urb_entry_read_length:6;
125 unsigned pad3:1;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]126};
127
128
129
130struct brw_clip_unit_state
131{
132 struct thread0 thread0;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]133 struct
134 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]135 unsigned pad0:7;
136 unsigned sw_exception_enable:1;
137 unsigned pad1:3;
138 unsigned mask_stack_exception_enable:1;
139 unsigned pad2:1;
140 unsigned illegal_op_exception_enable:1;
141 unsigned pad3:2;
142 unsigned floating_point_mode:1;
143 unsigned thread_priority:1;
144 unsigned binding_table_entry_count:8;
145 unsigned pad4:5;
146 unsigned single_program_flow:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]147 } thread1;
148
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]149 struct thread2 thread2;
150 struct thread3 thread3;
151
152 struct
153 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]154 unsigned pad0:9;
155 unsigned gs_output_stats:1; /* not always */
156 unsigned stats_enable:1;
157 unsigned nr_urb_entries:7;
158 unsigned pad1:1;
159 unsigned urb_entry_allocation_size:5;
160 unsigned pad2:1;
161 unsigned max_threads:5; /* may be less */
162 unsigned pad3:2;
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]163 } thread4;
164
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]165 struct
166 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]167 unsigned pad0:13;
168 unsigned clip_mode:3;
169 unsigned userclip_enable_flags:8;
170 unsigned userclip_must_clip:1;
171 unsigned negative_w_clip_test:1;
172 unsigned guard_band_enable:1;
173 unsigned viewport_z_clip_enable:1;
174 unsigned viewport_xy_clip_enable:1;
175 unsigned vertex_position_space:1;
176 unsigned api_mode:1;
177 unsigned pad2:1;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]178 } clip5;
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]179
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]180 struct
181 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]182 unsigned pad0:5;
183 unsigned clipper_viewport_state_ptr:27;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]184 } clip6;
185
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]186
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]187 float viewport_xmin;
188 float viewport_xmax;
189 float viewport_ymin;
190 float viewport_ymax;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]191};
192
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]193struct gen6_blend_state
194{
195 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]196 unsigned dest_blend_factor:5;
197 unsigned source_blend_factor:5;
198 unsigned pad3:1;
199 unsigned blend_func:3;
200 unsigned pad2:1;
201 unsigned ia_dest_blend_factor:5;
202 unsigned ia_source_blend_factor:5;
203 unsigned pad1:1;
204 unsigned ia_blend_func:3;
205 unsigned pad0:1;
206 unsigned ia_blend_enable:1;
207 unsigned blend_enable:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]208 } blend0;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]209
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]210 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]211 unsigned post_blend_clamp_enable:1;
212 unsigned pre_blend_clamp_enable:1;
213 unsigned clamp_range:2;
214 unsigned pad0:4;
215 unsigned x_dither_offset:2;
216 unsigned y_dither_offset:2;
217 unsigned dither_enable:1;
218 unsigned alpha_test_func:3;
219 unsigned alpha_test_enable:1;
220 unsigned pad1:1;
221 unsigned logic_op_func:4;
222 unsigned logic_op_enable:1;
223 unsigned pad2:1;
224 unsigned write_disable_b:1;
225 unsigned write_disable_g:1;
226 unsigned write_disable_r:1;
227 unsigned write_disable_a:1;
228 unsigned pad3:1;
229 unsigned alpha_to_coverage_dither:1;
230 unsigned alpha_to_one:1;
231 unsigned alpha_to_coverage:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]232 } blend1;
233};
234
235struct gen6_color_calc_state
236{
237 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]238 unsigned alpha_test_format:1;
239 unsigned pad0:14;
240 unsigned round_disable:1;
241 unsigned bf_stencil_ref:8;
242 unsigned stencil_ref:8;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]243 } cc0;
244
245 union {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]246 float alpha_ref_f;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]247 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]248 unsigned ui:8;
249 unsigned pad0:24;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]250 } alpha_ref_fi;
251 } cc1;
252
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]253 float constant_r;
254 float constant_g;
255 float constant_b;
256 float constant_a;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]257};
258
259struct gen6_depth_stencil_state
260{
261 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]262 unsigned pad0:3;
263 unsigned bf_stencil_pass_depth_pass_op:3;
264 unsigned bf_stencil_pass_depth_fail_op:3;
265 unsigned bf_stencil_fail_op:3;
266 unsigned bf_stencil_func:3;
267 unsigned bf_stencil_enable:1;
268 unsigned pad1:2;
269 unsigned stencil_write_enable:1;
270 unsigned stencil_pass_depth_pass_op:3;
271 unsigned stencil_pass_depth_fail_op:3;
272 unsigned stencil_fail_op:3;
273 unsigned stencil_func:3;
274 unsigned stencil_enable:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]275 } ds0;
276
277 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]278 unsigned bf_stencil_write_mask:8;
279 unsigned bf_stencil_test_mask:8;
280 unsigned stencil_write_mask:8;
281 unsigned stencil_test_mask:8;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]282 } ds1;
283
284 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]285 unsigned pad0:26;
286 unsigned depth_write_enable:1;
287 unsigned depth_test_func:3;
288 unsigned pad1:1;
289 unsigned depth_test_enable:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]290 } ds2;
291};
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]292
293struct brw_cc_unit_state
294{
295 struct
296 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]297 unsigned pad0:3;
298 unsigned bf_stencil_pass_depth_pass_op:3;
299 unsigned bf_stencil_pass_depth_fail_op:3;
300 unsigned bf_stencil_fail_op:3;
301 unsigned bf_stencil_func:3;
302 unsigned bf_stencil_enable:1;
303 unsigned pad1:2;
304 unsigned stencil_write_enable:1;
305 unsigned stencil_pass_depth_pass_op:3;
306 unsigned stencil_pass_depth_fail_op:3;
307 unsigned stencil_fail_op:3;
308 unsigned stencil_func:3;
309 unsigned stencil_enable:1;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]310 } cc0;
311
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]312
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]313 struct
314 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]315 unsigned bf_stencil_ref:8;
316 unsigned stencil_write_mask:8;
317 unsigned stencil_test_mask:8;
318 unsigned stencil_ref:8;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]319 } cc1;
320
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]321
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]322 struct
323 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]324 unsigned logicop_enable:1;
325 unsigned pad0:10;
326 unsigned depth_write_enable:1;
327 unsigned depth_test_function:3;
328 unsigned depth_test:1;
329 unsigned bf_stencil_write_mask:8;
330 unsigned bf_stencil_test_mask:8;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]331 } cc2;
332
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]333
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]334 struct
335 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]336 unsigned pad0:8;
337 unsigned alpha_test_func:3;
338 unsigned alpha_test:1;
339 unsigned blend_enable:1;
340 unsigned ia_blend_enable:1;
341 unsigned pad1:1;
342 unsigned alpha_test_format:1;
343 unsigned pad2:16;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]344 } cc3;
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]345
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]346 struct
347 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]348 unsigned pad0:5;
349 unsigned cc_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]350 } cc4;
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]351
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]352 struct
353 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]354 unsigned pad0:2;
355 unsigned ia_dest_blend_factor:5;
356 unsigned ia_src_blend_factor:5;
357 unsigned ia_blend_function:3;
358 unsigned statistics_enable:1;
359 unsigned logicop_func:4;
360 unsigned pad1:11;
361 unsigned dither_enable:1;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]362 } cc5;
363
364 struct
365 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]366 unsigned clamp_post_alpha_blend:1;
367 unsigned clamp_pre_alpha_blend:1;
368 unsigned clamp_range:2;
369 unsigned pad0:11;
370 unsigned y_dither_offset:2;
371 unsigned x_dither_offset:2;
372 unsigned dest_blend_factor:5;
373 unsigned src_blend_factor:5;
374 unsigned blend_function:3;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]375 } cc6;
376
377 struct {
378 union {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]379 float f;
380 uint8_t ub[4];
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]381 } alpha_ref;
382 } cc7;
383};
384
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]385struct brw_sf_unit_state
386{
387 struct thread0 thread0;
388 struct thread1 thread1;
389 struct thread2 thread2;
390 struct thread3 thread3;
391
392 struct
393 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]394 unsigned pad0:10;
395 unsigned stats_enable:1;
396 unsigned nr_urb_entries:7;
397 unsigned pad1:1;
398 unsigned urb_entry_allocation_size:5;
399 unsigned pad2:1;
400 unsigned max_threads:6;
401 unsigned pad3:1;
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]402 } thread4;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]403
404 struct
405 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]406 unsigned front_winding:1;
407 unsigned viewport_transform:1;
408 unsigned pad0:3;
409 unsigned sf_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]410 } sf5;
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]411
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]412 struct
413 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]414 unsigned pad0:9;
415 unsigned dest_org_vbias:4;
416 unsigned dest_org_hbias:4;
417 unsigned scissor:1;
418 unsigned disable_2x2_trifilter:1;
419 unsigned disable_zero_pix_trifilter:1;
420 unsigned point_rast_rule:2;
421 unsigned line_endcap_aa_region_width:2;
422 unsigned line_width:4;
423 unsigned fast_scissor_disable:1;
424 unsigned cull_mode:2;
425 unsigned aa_enable:1;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]426 } sf6;
427
428 struct
429 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]430 unsigned point_size:11;
431 unsigned use_point_size_state:1;
432 unsigned subpixel_precision:1;
433 unsigned sprite_point:1;
434 unsigned pad0:10;
435 unsigned aa_line_distance_mode:1;
436 unsigned trifan_pv:2;
437 unsigned linestrip_pv:2;
438 unsigned tristrip_pv:2;
439 unsigned line_last_pixel_enable:1;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]440 } sf7;
441
442};
443
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]444struct gen6_scissor_rect
445{
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]446 unsigned xmin:16;
447 unsigned ymin:16;
448 unsigned xmax:16;
449 unsigned ymax:16;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]450};
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]451
452struct brw_gs_unit_state
453{
454 struct thread0 thread0;
455 struct thread1 thread1;
456 struct thread2 thread2;
457 struct thread3 thread3;
458
459 struct
460 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]461 unsigned pad0:8;
462 unsigned rendering_enable:1; /* for Ironlake */
463 unsigned pad4:1;
464 unsigned stats_enable:1;
465 unsigned nr_urb_entries:7;
466 unsigned pad1:1;
467 unsigned urb_entry_allocation_size:5;
468 unsigned pad2:1;
469 unsigned max_threads:5;
470 unsigned pad3:2;
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]471 } thread4;
472
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]473 struct
474 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]475 unsigned sampler_count:3;
476 unsigned pad0:2;
477 unsigned sampler_state_pointer:27;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]478 } gs5;
479
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]480
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]481 struct
482 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]483 unsigned max_vp_index:4;
484 unsigned pad0:12;
485 unsigned svbi_post_inc_value:10;
486 unsigned pad1:1;
487 unsigned svbi_post_inc_enable:1;
488 unsigned svbi_payload:1;
489 unsigned discard_adjaceny:1;
490 unsigned reorder_enable:1;
491 unsigned pad2:1;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]492 } gs6;
493};
494
495
496struct brw_vs_unit_state
497{
498 struct thread0 thread0;
499 struct thread1 thread1;
500 struct thread2 thread2;
501 struct thread3 thread3;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]502
503 struct
504 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]505 unsigned pad0:10;
506 unsigned stats_enable:1;
507 unsigned nr_urb_entries:7;
508 unsigned pad1:1;
509 unsigned urb_entry_allocation_size:5;
510 unsigned pad2:1;
511 unsigned max_threads:6;
512 unsigned pad3:1;
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]513 } thread4;
514
515 struct
516 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]517 unsigned sampler_count:3;
518 unsigned pad0:2;
519 unsigned sampler_state_pointer:27;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]520 } vs5;
521
522 struct
523 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]524 unsigned vs_enable:1;
525 unsigned vert_cache_disable:1;
526 unsigned pad0:30;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]527 } vs6;
528};
529
530
531struct brw_wm_unit_state
532{
533 struct thread0 thread0;
534 struct thread1 thread1;
535 struct thread2 thread2;
536 struct thread3 thread3;
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]537
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]538 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]539 unsigned stats_enable:1;
540 unsigned depth_buffer_clear:1;
541 unsigned sampler_count:3;
542 unsigned sampler_state_pointer:27;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]543 } wm4;
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]544
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]545 struct
546 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]547 unsigned enable_8_pix:1;
548 unsigned enable_16_pix:1;
549 unsigned enable_32_pix:1;
550 unsigned enable_con_32_pix:1;
551 unsigned enable_con_64_pix:1;
552 unsigned pad0:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]553
554 /* These next four bits are for Ironlake+ */
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]555 unsigned fast_span_coverage_enable:1;
556 unsigned depth_buffer_clear:1;
557 unsigned depth_buffer_resolve_enable:1;
558 unsigned hierarchical_depth_buffer_resolve_enable:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]559
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]560 unsigned legacy_global_depth_bias:1;
561 unsigned line_stipple:1;
562 unsigned depth_offset:1;
563 unsigned polygon_stipple:1;
564 unsigned line_aa_region_width:2;
565 unsigned line_endcap_aa_region_width:2;
566 unsigned early_depth_test:1;
567 unsigned thread_dispatch_enable:1;
568 unsigned program_uses_depth:1;
569 unsigned program_computes_depth:1;
570 unsigned program_uses_killpixel:1;
571 unsigned legacy_line_rast: 1;
572 unsigned transposed_urb_read_enable:1;
573 unsigned max_threads:7;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]574 } wm5;
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]575
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]576 float global_depth_offset_constant;
577 float global_depth_offset_scale;
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]578
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]579 /* for Ironlake only */
580 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]581 unsigned pad0:1;
582 unsigned grf_reg_count_1:3;
583 unsigned pad1:2;
584 unsigned kernel_start_pointer_1:26;
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]585 } wm8;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]586
587 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]588 unsigned pad0:1;
589 unsigned grf_reg_count_2:3;
590 unsigned pad1:2;
591 unsigned kernel_start_pointer_2:26;
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]592 } wm9;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]593
594 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]595 unsigned pad0:1;
596 unsigned grf_reg_count_3:3;
597 unsigned pad1:2;
598 unsigned kernel_start_pointer_3:26;
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]599 } wm10;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]600};
601
602struct brw_sampler_default_color {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]603 float color[4];
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]604};
605
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]606struct gen5_sampler_default_color {
607 uint8_t ub[4];
608 float f[4];
609 uint16_t hf[4];
610 uint16_t us[4];
611 int16_t s[4];
612 uint8_t b[4];
613};
614
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]615struct brw_sampler_state
616{
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]617
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]618 struct
619 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]620 unsigned shadow_function:3;
621 unsigned lod_bias:11;
622 unsigned min_filter:3;
623 unsigned mag_filter:3;
624 unsigned mip_filter:2;
625 unsigned base_level:5;
626 unsigned min_mag_neq:1;
627 unsigned lod_preclamp:1;
628 unsigned default_color_mode:1;
629 unsigned pad0:1;
630 unsigned disable:1;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]631 } ss0;
632
633 struct
634 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]635 unsigned r_wrap_mode:3;
636 unsigned t_wrap_mode:3;
637 unsigned s_wrap_mode:3;
638 unsigned cube_control_mode:1;
639 unsigned pad:2;
640 unsigned max_lod:10;
641 unsigned min_lod:10;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]642 } ss1;
643
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]644
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]645 struct
646 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]647 unsigned pad:5;
648 unsigned default_color_pointer:27;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]649 } ss2;
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]650
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]651 struct
652 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]653 unsigned non_normalized_coord:1;
654 unsigned pad:12;
655 unsigned address_round:6;
656 unsigned max_aniso:3;
657 unsigned chroma_key_mode:1;
658 unsigned chroma_key_index:2;
659 unsigned chroma_key_enable:1;
660 unsigned monochrome_filter_width:3;
661 unsigned monochrome_filter_height:3;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]662 } ss3;
663};
664
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]665struct gen7_sampler_state
666{
667 struct
668 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]669 unsigned aniso_algorithm:1;
670 unsigned lod_bias:13;
671 unsigned min_filter:3;
672 unsigned mag_filter:3;
673 unsigned mip_filter:2;
674 unsigned base_level:5;
675 unsigned pad1:1;
676 unsigned lod_preclamp:1;
677 unsigned default_color_mode:1;
678 unsigned pad0:1;
679 unsigned disable:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]680 } ss0;
681
682 struct
683 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]684 unsigned cube_control_mode:1;
685 unsigned shadow_function:3;
686 unsigned pad:4;
687 unsigned max_lod:12;
688 unsigned min_lod:12;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]689 } ss1;
690
691 struct
692 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]693 unsigned pad:5;
694 unsigned default_color_pointer:27;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]695 } ss2;
696
697 struct
698 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]699 unsigned r_wrap_mode:3;
700 unsigned t_wrap_mode:3;
701 unsigned s_wrap_mode:3;
702 unsigned pad:1;
703 unsigned non_normalized_coord:1;
704 unsigned trilinear_quality:2;
705 unsigned address_round:6;
706 unsigned max_aniso:3;
707 unsigned chroma_key_mode:1;
708 unsigned chroma_key_index:2;
709 unsigned chroma_key_enable:1;
710 unsigned pad0:6;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]711 } ss3;
712};
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]713
714struct brw_clipper_viewport
715{
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]716 float xmin;
717 float xmax;
718 float ymin;
719 float ymax;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]720};
721
722struct brw_cc_viewport
723{
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]724 float min_depth;
725 float max_depth;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]726};
727
728struct brw_sf_viewport
729{
730 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]731 float m00;
732 float m11;
733 float m22;
734 float m30;
735 float m31;
736 float m32;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]737 } viewport;
738
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]739 /* scissor coordinates are inclusive */
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]740 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]741 int16_t xmin;
742 int16_t ymin;
743 int16_t xmax;
744 int16_t ymax;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]745 } scissor;
746};
747
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]748struct gen6_sf_viewport {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]749 float m00;
750 float m11;
751 float m22;
752 float m30;
753 float m31;
754 float m32;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]755};
756
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]757struct gen7_sf_clip_viewport {
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]758 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]759 float m00;
760 float m11;
761 float m22;
762 float m30;
763 float m31;
764 float m32;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]765 } viewport;
766
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]767 unsigned pad0[2];
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]768
769 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]770 float xmin;
771 float xmax;
772 float ymin;
773 float ymax;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]774 } guardband;
775
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]776 float pad1[4];
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]777};
778
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]779struct brw_vertex_element_state
780{
781 struct
782 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]783 unsigned src_offset:11;
784 unsigned pad:5;
785 unsigned src_format:9;
786 unsigned pad0:1;
787 unsigned valid:1;
788 unsigned vertex_buffer_index:5;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]789 } ve0;
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]790
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]791 struct
792 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]793 unsigned dst_offset:8;
794 unsigned pad:8;
795 unsigned vfcomponent3:4;
796 unsigned vfcomponent2:4;
797 unsigned vfcomponent1:4;
798 unsigned vfcomponent0:4;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]799 } ve1;
800};
801
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]802struct brw_urb_immediate {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]803 unsigned opcode:4;
804 unsigned offset:6;
805 unsigned swizzle_control:2;
806 unsigned pad:1;
807 unsigned allocate:1;
808 unsigned used:1;
809 unsigned complete:1;
810 unsigned response_length:4;
811 unsigned msg_length:4;
812 unsigned msg_target:4;
813 unsigned pad1:3;
814 unsigned end_of_thread:1;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]815};
816
817/* Instruction format for the execution units:
818 */
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]819
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]820struct brw_instruction
821{
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]822 struct
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]823 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]824 unsigned opcode:7;
825 unsigned pad:1;
826 unsigned access_mode:1;
827 unsigned mask_control:1;
828 unsigned dependency_control:2;
829 unsigned compression_control:2; /* gen6: quater control */
830 unsigned thread_control:2;
831 unsigned predicate_control:4;
832 unsigned predicate_inverse:1;
833 unsigned execution_size:3;
Damien Lespiaue71f1d22013-01-14 19:13:19 +0000[diff] [blame]834 /**
835 * Conditional Modifier for most instructions. On Gen6+, this is also
836 * used for the SEND instruction's Message Target/SFID.
837 */
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]838 unsigned destreg__conditionalmod:4;
839 unsigned acc_wr_control:1;
840 unsigned cmpt_control:1;
841 unsigned debug_control:1;
842 unsigned saturate:1;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]843 } header;
844
845 union {
846 struct
847 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]848 unsigned dest_reg_file:2;
849 unsigned dest_reg_type:3;
850 unsigned src0_reg_file:2;
851 unsigned src0_reg_type:3;
852 unsigned src1_reg_file:2;
853 unsigned src1_reg_type:3;
854 unsigned pad:1;
855 unsigned dest_subreg_nr:5;
856 unsigned dest_reg_nr:8;
857 unsigned dest_horiz_stride:2;
858 unsigned dest_address_mode:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]859 } da1;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]860
861 struct
862 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]863 unsigned dest_reg_file:2;
864 unsigned dest_reg_type:3;
865 unsigned src0_reg_file:2;
866 unsigned src0_reg_type:3;
867 unsigned src1_reg_file:2; /* 0x00000c00 */
868 unsigned src1_reg_type:3; /* 0x00007000 */
869 unsigned pad:1;
870 int dest_indirect_offset:10; /* offset against the deref'd address reg */
871 unsigned dest_subreg_nr:3; /* subnr for the address reg a0.x */
872 unsigned dest_horiz_stride:2;
873 unsigned dest_address_mode:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]874 } ia1;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]875
876 struct
877 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]878 unsigned dest_reg_file:2;
879 unsigned dest_reg_type:3;
880 unsigned src0_reg_file:2;
881 unsigned src0_reg_type:3;
882 unsigned src1_reg_file:2;
883 unsigned src1_reg_type:3;
884 unsigned pad:1;
885 unsigned dest_writemask:4;
886 unsigned dest_subreg_nr:1;
887 unsigned dest_reg_nr:8;
888 unsigned dest_horiz_stride:2;
889 unsigned dest_address_mode:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]890 } da16;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]891
892 struct
893 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]894 unsigned dest_reg_file:2;
895 unsigned dest_reg_type:3;
896 unsigned src0_reg_file:2;
897 unsigned src0_reg_type:3;
898 unsigned pad0:6;
899 unsigned dest_writemask:4;
900 int dest_indirect_offset:6;
901 unsigned dest_subreg_nr:3;
902 unsigned dest_horiz_stride:2;
903 unsigned dest_address_mode:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]904 } ia16;
Homer Hsing0d3f8492012-09-07 09:53:17 +0800[diff] [blame]905
Damien Lespiaucb425d62013-01-16 01:19:29 +0000[diff] [blame]906 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]907 unsigned dest_reg_file:2;
908 unsigned dest_reg_type:3;
909 unsigned src0_reg_file:2;
910 unsigned src0_reg_type:3;
911 unsigned src1_reg_file:2;
912 unsigned src1_reg_type:3;
913 unsigned pad:1;
Damien Lespiaucb425d62013-01-16 01:19:29 +0000[diff] [blame]914
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]915 int jump_count:16;
Damien Lespiaucb425d62013-01-16 01:19:29 +0000[diff] [blame]916 } branch_gen6;
917
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]918 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]919 unsigned dest_reg_file:1;
920 unsigned flag_subreg_nr:1;
921 unsigned flag_reg_nr:1;
922 unsigned pad0:1;
923 unsigned src0_abs:1;
924 unsigned src0_negate:1;
925 unsigned src1_abs:1;
926 unsigned src1_negate:1;
927 unsigned src2_abs:1;
928 unsigned src2_negate:1;
929 unsigned src_reg_type:2;
930 unsigned dest_reg_type:2;
931 unsigned pad1:1;
932 unsigned nib_ctrl:1;
933 unsigned pad2:1;
934 unsigned dest_writemask:4;
935 unsigned dest_subreg_nr:3;
936 unsigned dest_reg_nr:8;
Damien Lespiau31259c52013-01-15 14:05:23 +0000[diff] [blame]937 } da3src;
Homer Hsingc91bd8c2012-09-27 16:20:39 +0800[diff] [blame]938
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]939 uint32_t ud;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]940 } bits1;
941
942
943 union {
944 struct
945 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]946 unsigned src0_subreg_nr:5;
947 unsigned src0_reg_nr:8;
948 unsigned src0_abs:1;
949 unsigned src0_negate:1;
950 unsigned src0_address_mode:1;
951 unsigned src0_horiz_stride:2;
952 unsigned src0_width:3;
953 unsigned src0_vert_stride:4;
954 unsigned flag_subreg_nr:1;
955 unsigned flag_reg_nr:1;
956 unsigned pad:5;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]957 } da1;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]958
959 struct
960 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]961 int src0_indirect_offset:10;
962 unsigned src0_subreg_nr:3;
963 unsigned src0_abs:1;
964 unsigned src0_negate:1;
965 unsigned src0_address_mode:1;
966 unsigned src0_horiz_stride:2;
967 unsigned src0_width:3;
968 unsigned src0_vert_stride:4;
969 unsigned flag_subreg_nr:1;
970 unsigned flag_reg_nr:1;
971 unsigned pad:5;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]972 } ia1;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]973
974 struct
975 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]976 unsigned src0_swz_x:2;
977 unsigned src0_swz_y:2;
978 unsigned src0_subreg_nr:1;
979 unsigned src0_reg_nr:8;
980 unsigned src0_abs:1;
981 unsigned src0_negate:1;
982 unsigned src0_address_mode:1;
983 unsigned src0_swz_z:2;
984 unsigned src0_swz_w:2;
985 unsigned pad0:1;
986 unsigned src0_vert_stride:4;
987 unsigned flag_subreg_nr:1;
988 unsigned flag_reg_nr:1;
989 unsigned pad1:5;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]990 } da16;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]991
992 struct
993 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]994 unsigned src0_swz_x:2;
995 unsigned src0_swz_y:2;
996 int src0_indirect_offset:6;
997 unsigned src0_subreg_nr:3;
998 unsigned src0_abs:1;
999 unsigned src0_negate:1;
1000 unsigned src0_address_mode:1;
1001 unsigned src0_swz_z:2;
1002 unsigned src0_swz_w:2;
1003 unsigned pad0:1;
1004 unsigned src0_vert_stride:4;
1005 unsigned flag_subreg_nr:1;
1006 unsigned flag_reg_nr:1;
1007 unsigned pad1:5;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1008 } ia16;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]1009
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1010 /* Extended Message Descriptor for Ironlake (Gen5) SEND instruction.
1011 *
1012 * Does not apply to Gen6+. The SFID/message target moved to bits
1013 * 27:24 of the header (destreg__conditionalmod); EOT is in bits3.
1014 */
Damien Lespiau64e84282013-01-16 15:11:05 +0000[diff] [blame]1015 struct
Xiang Haihao549b7512009-06-30 10:02:33 +0800[diff] [blame]1016 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1017 unsigned pad:26;
1018 unsigned end_of_thread:1;
1019 unsigned pad1:1;
1020 unsigned sfid:4;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1021 } send_gen5; /* for Ironlake only */
1022
1023 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1024 unsigned src0_rep_ctrl:1;
1025 unsigned src0_swizzle:8;
1026 unsigned src0_subreg_nr:3;
1027 unsigned src0_reg_nr:8;
1028 unsigned pad0:1;
1029 unsigned src1_rep_ctrl:1;
1030 unsigned src1_swizzle:8;
1031 unsigned src1_subreg_nr_low:2;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1032 } da3src;
1033
1034 uint32_t ud;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]1035 } bits2;
1036
1037 union
1038 {
1039 struct
1040 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1041 unsigned src1_subreg_nr:5;
1042 unsigned src1_reg_nr:8;
1043 unsigned src1_abs:1;
1044 unsigned src1_negate:1;
1045 unsigned src1_address_mode:1;
1046 unsigned src1_horiz_stride:2;
1047 unsigned src1_width:3;
1048 unsigned src1_vert_stride:4;
1049 unsigned pad0:7;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1050 } da1;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]1051
1052 struct
1053 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1054 unsigned src1_swz_x:2;
1055 unsigned src1_swz_y:2;
1056 unsigned src1_subreg_nr:1;
1057 unsigned src1_reg_nr:8;
1058 unsigned src1_abs:1;
1059 unsigned src1_negate:1;
1060 unsigned src1_address_mode:1;
1061 unsigned src1_swz_z:2;
1062 unsigned src1_swz_w:2;
1063 unsigned pad1:1;
1064 unsigned src1_vert_stride:4;
1065 unsigned pad2:7;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1066 } da16;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]1067
1068 struct
1069 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1070 int src1_indirect_offset:10;
1071 unsigned src1_subreg_nr:3;
1072 unsigned src1_abs:1;
1073 unsigned src1_negate:1;
1074 unsigned src1_address_mode:1;
1075 unsigned src1_horiz_stride:2;
1076 unsigned src1_width:3;
1077 unsigned src1_vert_stride:4;
1078 unsigned pad1:7;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1079 } ia1;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]1080
1081 struct
1082 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1083 unsigned src1_swz_x:2;
1084 unsigned src1_swz_y:2;
1085 int src1_indirect_offset:6;
1086 unsigned src1_subreg_nr:3;
1087 unsigned src1_abs:1;
1088 unsigned src1_negate:1;
1089 unsigned src1_address_mode:1;
1090 unsigned src1_swz_z:2;
1091 unsigned src1_swz_w:2;
1092 unsigned pad1:1;
1093 unsigned src1_vert_stride:4;
1094 unsigned pad2:7;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1095 } ia16;
1096
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]1097
Homer Hsing0d3f8492012-09-07 09:53:17 +0800[diff] [blame]1098 struct
1099 {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1100 int jump_count:16; /* note: signed */
1101 unsigned pop_count:4;
1102 unsigned pad0:12;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1103 } if_else;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]1104
Damien Lespiauc7dac842013-01-16 01:44:41 +0000[diff] [blame]1105 /* This is also used for gen7 IF/ELSE instructions */
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]1106 struct
1107 {
Damien Lespiauc7dac842013-01-16 01:44:41 +0000[diff] [blame]1108 /* Signed jump distance to the ip to jump to if all channels
1109 * are disabled after the break or continue. It should point
1110 * to the end of the innermost control flow block, as that's
1111 * where some channel could get re-enabled.
1112 */
1113 int jip:16;
1114
1115 /* Signed jump distance to the location to resume execution
1116 * of this channel if it's enabled for the break or continue.
1117 */
1118 int uip:16;
1119 } break_cont;
Homer Hsing741008e2012-09-20 13:09:15 +0800[diff] [blame]1120
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1121 int JIP; /* used by Gen6 CALL instructions; Gen7 JMPI */
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]1122
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1123 /**
1124 * \defgroup SEND instructions / Message Descriptors
1125 *
1126 * @{
1127 */
1128
1129 /**
1130 * Generic Message Descriptor for Gen4 SEND instructions. The structs
1131 * below expand function_control to something specific for their
1132 * message. Due to struct packing issues, they duplicate these bits.
1133 *
1134 * See the G45 PRM, Volume 4, Table 14-15.
1135 */
1136 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1137 unsigned function_control:16;
1138 unsigned response_length:4;
1139 unsigned msg_length:4;
1140 unsigned msg_target:4;
1141 unsigned pad1:3;
1142 unsigned end_of_thread:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1143 } generic;
1144
1145 /**
1146 * Generic Message Descriptor for Gen5-7 SEND instructions.
1147 *
1148 * See the Sandybridge PRM, Volume 2 Part 2, Table 8-15. (Sadly, most
1149 * of the information on the SEND instruction is missing from the public
1150 * Ironlake PRM.)
1151 *
1152 * The table claims that bit 31 is reserved/MBZ on Gen6+, but it lies.
1153 * According to the SEND instruction description:
1154 * "The MSb of the message description, the EOT field, always comes from
1155 * bit 127 of the instruction word"...which is bit 31 of this field.
1156 */
1157 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1158 unsigned function_control:19;
1159 unsigned header_present:1;
1160 unsigned response_length:5;
1161 unsigned msg_length:4;
1162 unsigned pad1:2;
1163 unsigned end_of_thread:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1164 } generic_gen5;
1165
1166 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1167 unsigned opcode:1;
1168 unsigned requester_type:1;
1169 unsigned pad:2;
1170 unsigned resource_select:1;
1171 unsigned pad1:11;
1172 unsigned response_length:4;
1173 unsigned msg_length:4;
1174 unsigned msg_target:4;
1175 unsigned pad2:3;
1176 unsigned end_of_thread:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1177 } thread_spawner;
1178
1179 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1180 unsigned opcode:1;
1181 unsigned requester_type:1;
1182 unsigned pad0:2;
1183 unsigned resource_select:1;
1184 unsigned pad1:14;
1185 unsigned header_present:1;
1186 unsigned response_length:5;
1187 unsigned msg_length:4;
1188 unsigned pad2:2;
1189 unsigned end_of_thread:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1190 } thread_spawner_gen5;
1191
1192 /** G45 PRM, Volume 4, Section 6.1.1.1 */
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]1193 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1194 unsigned function:4;
1195 unsigned int_type:1;
1196 unsigned precision:1;
1197 unsigned saturate:1;
1198 unsigned data_type:1;
1199 unsigned pad0:8;
1200 unsigned response_length:4;
1201 unsigned msg_length:4;
1202 unsigned msg_target:4;
1203 unsigned pad1:3;
1204 unsigned end_of_thread:1;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]1205 } math;
1206
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1207 /** Ironlake PRM, Volume 4 Part 1, Section 6.1.1.1 */
1208 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1209 unsigned function:4;
1210 unsigned int_type:1;
1211 unsigned precision:1;
1212 unsigned saturate:1;
1213 unsigned data_type:1;
1214 unsigned snapshot:1;
1215 unsigned pad0:10;
1216 unsigned header_present:1;
1217 unsigned response_length:5;
1218 unsigned msg_length:4;
1219 unsigned pad1:2;
1220 unsigned end_of_thread:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1221 } math_gen5;
1222
1223 /** G45 PRM, Volume 4, Section 4.8.1.1.1 [DevBW] and [DevCL] */
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]1224 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1225 unsigned binding_table_index:8;
1226 unsigned sampler:4;
1227 unsigned return_format:2;
1228 unsigned msg_type:2;
1229 unsigned response_length:4;
1230 unsigned msg_length:4;
1231 unsigned msg_target:4;
1232 unsigned pad1:3;
1233 unsigned end_of_thread:1;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]1234 } sampler;
1235
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1236 /** G45 PRM, Volume 4, Section 4.8.1.1.2 [DevCTG] */
1237 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1238 unsigned binding_table_index:8;
1239 unsigned sampler:4;
1240 unsigned msg_type:4;
1241 unsigned response_length:4;
1242 unsigned msg_length:4;
1243 unsigned msg_target:4;
1244 unsigned pad1:3;
1245 unsigned end_of_thread:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1246 } sampler_g4x;
1247
1248 /** Ironlake PRM, Volume 4 Part 1, Section 4.11.1.1.3 */
1249 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1250 unsigned binding_table_index:8;
1251 unsigned sampler:4;
1252 unsigned msg_type:4;
1253 unsigned simd_mode:2;
1254 unsigned pad0:1;
1255 unsigned header_present:1;
1256 unsigned response_length:5;
1257 unsigned msg_length:4;
1258 unsigned pad1:2;
1259 unsigned end_of_thread:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1260 } sampler_gen5;
1261
1262 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1263 unsigned binding_table_index:8;
1264 unsigned sampler:4;
1265 unsigned msg_type:5;
1266 unsigned simd_mode:2;
1267 unsigned header_present:1;
1268 unsigned response_length:5;
1269 unsigned msg_length:4;
1270 unsigned pad1:2;
1271 unsigned end_of_thread:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1272 } sampler_gen7;
1273
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]1274 struct brw_urb_immediate urb;
1275
1276 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1277 unsigned opcode:4;
1278 unsigned offset:6;
1279 unsigned swizzle_control:2;
1280 unsigned pad:1;
1281 unsigned allocate:1;
1282 unsigned used:1;
1283 unsigned complete:1;
1284 unsigned pad0:3;
1285 unsigned header_present:1;
1286 unsigned response_length:5;
1287 unsigned msg_length:4;
1288 unsigned pad1:2;
1289 unsigned end_of_thread:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1290 } urb_gen5;
1291
1292 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1293 unsigned opcode:3;
1294 unsigned offset:11;
1295 unsigned swizzle_control:1;
1296 unsigned complete:1;
1297 unsigned per_slot_offset:1;
1298 unsigned pad0:2;
1299 unsigned header_present:1;
1300 unsigned response_length:5;
1301 unsigned msg_length:4;
1302 unsigned pad1:2;
1303 unsigned end_of_thread:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1304 } urb_gen7;
1305
1306 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1307 unsigned binding_table_index:8;
1308 unsigned search_path_index:3;
1309 unsigned lut_subindex:2;
1310 unsigned message_type:2;
1311 unsigned pad0:4;
1312 unsigned header_present:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1313 } vme_gen6;
1314
1315 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1316 unsigned binding_table_index:8;
1317 unsigned pad0:5;
1318 unsigned message_type:2;
1319 unsigned pad1:4;
1320 unsigned header_present:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1321 } cre_gen75;
1322
1323 /** 965 PRM, Volume 4, Section 5.10.1.1: Message Descriptor */
1324 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1325 unsigned binding_table_index:8;
1326 unsigned msg_control:4;
1327 unsigned msg_type:2;
1328 unsigned target_cache:2;
1329 unsigned response_length:4;
1330 unsigned msg_length:4;
1331 unsigned msg_target:4;
1332 unsigned pad1:3;
1333 unsigned end_of_thread:1;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]1334 } dp_read;
1335
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1336 /** G45 PRM, Volume 4, Section 5.10.1.1.2 */
1337 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1338 unsigned binding_table_index:8;
1339 unsigned msg_control:3;
1340 unsigned msg_type:3;
1341 unsigned target_cache:2;
1342 unsigned response_length:4;
1343 unsigned msg_length:4;
1344 unsigned msg_target:4;
1345 unsigned pad1:3;
1346 unsigned end_of_thread:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1347 } dp_read_g4x;
1348
1349 /** Ironlake PRM, Volume 4 Part 1, Section 5.10.2.1.2. */
1350 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1351 unsigned binding_table_index:8;
1352 unsigned msg_control:4;
1353 unsigned msg_type:2;
1354 unsigned target_cache:2;
1355 unsigned pad0:3;
1356 unsigned header_present:1;
1357 unsigned response_length:5;
1358 unsigned msg_length:4;
1359 unsigned pad1:2;
1360 unsigned end_of_thread:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1361 } dp_read_gen5;
1362
1363 /** G45 PRM, Volume 4, Section 5.10.1.1.2. For both Gen4 and G45. */
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]1364 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1365 unsigned binding_table_index:8;
1366 unsigned msg_control:3;
1367 unsigned last_render_target:1;
1368 unsigned msg_type:3;
1369 unsigned send_commit_msg:1;
1370 unsigned response_length:4;
1371 unsigned msg_length:4;
1372 unsigned msg_target:4;
1373 unsigned pad1:3;
1374 unsigned end_of_thread:1;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]1375 } dp_write;
1376
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1377 /** Ironlake PRM, Volume 4 Part 1, Section 5.10.2.1.2. */
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]1378 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1379 unsigned binding_table_index:8;
1380 unsigned msg_control:3;
1381 unsigned last_render_target:1;
1382 unsigned msg_type:3;
1383 unsigned send_commit_msg:1;
1384 unsigned pad0:3;
1385 unsigned header_present:1;
1386 unsigned response_length:5;
1387 unsigned msg_length:4;
1388 unsigned pad1:2;
1389 unsigned end_of_thread:1;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1390 } dp_write_gen5;
Xiang Haihao549b7512009-06-30 10:02:33 +0800[diff] [blame]1391
Damien Lespiau668e0df2013-01-15 16:40:06 +0000[diff] [blame]1392 /**
1393 * Message for the Sandybridge Sampler Cache or Constant Cache Data Port.
1394 *
1395 * See the Sandybridge PRM, Volume 4 Part 1, Section 3.9.2.1.1.
1396 **/
1397 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1398 unsigned binding_table_index:8;
1399 unsigned msg_control:5;
1400 unsigned msg_type:3;
1401 unsigned pad0:3;
1402 unsigned header_present:1;
1403 unsigned response_length:5;
1404 unsigned msg_length:4;
1405 unsigned pad1:2;
1406 unsigned end_of_thread:1;
Damien Lespiau668e0df2013-01-15 16:40:06 +0000[diff] [blame]1407 } gen6_dp_sampler_const_cache;
Xiang, Haihaoa8458d52010-10-09 11:09:47 +0800[diff] [blame]1408
Damien Lespiau1f1ad592013-01-15 17:35:24 +0000[diff] [blame]1409 /**
1410 * Message for the Sandybridge Render Cache Data Port.
1411 *
1412 * Most fields are defined in the Sandybridge PRM, Volume 4 Part 1,
1413 * Section 3.9.2.1.1: Message Descriptor.
1414 *
1415 * "Slot Group Select" and "Last Render Target" are part of the
1416 * 5-bit message control for Render Target Write messages. See
1417 * Section 3.9.9.2.1 of the same volume.
1418 */
1419 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1420 unsigned binding_table_index:8;
1421 unsigned msg_control:5;
1422 unsigned msg_type:4;
1423 unsigned send_commit_msg:1;
1424 unsigned pad0:1;
1425 unsigned header_present:1;
1426 unsigned response_length:5;
1427 unsigned msg_length:4;
1428 unsigned pad1:2;
1429 unsigned end_of_thread:1;
Damien Lespiau1f1ad592013-01-15 17:35:24 +0000[diff] [blame]1430 } gen6_dp;
Xiang, Haihao27050392011-06-10 16:04:30 +0800[diff] [blame]1431
Damien Lespiau8fa561d2013-01-15 18:47:05 +0000[diff] [blame]1432 /**
1433 * Message for any of the Gen7 Data Port caches.
1434 *
1435 * Most fields are defined in BSpec volume 5c.2 Data Port / Messages /
1436 * Data Port Messages / Message Descriptor. Once again, "Slot Group
1437 * Select" and "Last Render Target" are part of the 6-bit message
1438 * control for Render Target Writes.
1439 */
1440 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1441 unsigned binding_table_index:8;
1442 unsigned msg_control:6;
1443 unsigned msg_type:4;
1444 unsigned category:1;
1445 unsigned header_present:1;
1446 unsigned response_length:5;
1447 unsigned msg_length:4;
1448 unsigned pad2:2;
1449 unsigned end_of_thread:1;
Damien Lespiau8fa561d2013-01-15 18:47:05 +0000[diff] [blame]1450 } gen7_dp;
1451 /** @} */
Xiang, Haihaoc8d6bf32011-05-23 13:32:32 +0800[diff] [blame]1452
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1453 struct {
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1454 unsigned src1_subreg_nr_high:1;
1455 unsigned src1_reg_nr:8;
1456 unsigned pad0:1;
1457 unsigned src2_rep_ctrl:1;
1458 unsigned src2_swizzle:8;
1459 unsigned src2_subreg_nr:3;
1460 unsigned src2_reg_nr:8;
1461 unsigned pad1:2;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1462 } da3src;
Xiang Haihao549b7512009-06-30 10:02:33 +0800[diff] [blame]1463
Damien Lespiauf0365d42013-02-04 12:02:18 +0000[diff] [blame]1464 int d;
1465 unsigned ud;
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1466 float f;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]1467 } bits3;
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]1468};
1469
Damien Lespiauc35e0672013-01-16 14:56:40 +0000[diff] [blame]1470struct brw_compact_instruction {
1471 struct {
1472 unsigned opcode:7; /* 0- 6 */
1473 unsigned debug_control:1; /* 7- 7 */
1474 unsigned control_index:5; /* 8-12 */
1475 unsigned data_type_index:5; /* 13-17 */
1476 unsigned sub_reg_index:5; /* 18-22 */
1477 unsigned acc_wr_control:1; /* 23-23 */
1478 unsigned conditionalmod:4; /* 24-27 */
1479 unsigned flag_subreg_nr:1; /* 28-28 */
1480 unsigned cmpt_ctrl:1; /* 29-29 */
1481 unsigned src0_index:2; /* 30-31 */
1482 } dw0;
1483
1484 struct {
1485 unsigned src0_index:3; /* 32-24 */
1486 unsigned src1_index:5; /* 35-39 */
1487 unsigned dst_reg_nr:8; /* 40-47 */
1488 unsigned src0_reg_nr:8; /* 48-55 */
1489 unsigned src1_reg_nr:8; /* 56-63 */
1490 } dw1;
1491};
Eric Anholt22a10632006-08-22 10:15:33 -0700[diff] [blame]1492
1493#endif