blob: 63fe72eb70413ba5db1141e4cf9379a70caa10ca [file] [log] [blame]
Daniel Vetter924115b2014-03-22 20:18:51 +01001#include <intel_bufmgr.h>
2#include <i915_drm.h>
3
Xiang, Haihaobd384c22013-12-02 12:36:15 +08004#include "media_fill.h"
5#include "gen8_media.h"
Daniel Vetter6cfcd712014-03-22 20:07:35 +01006#include "intel_reg.h"
Tvrtko Ursulindc14bf42014-04-23 16:07:55 +01007#include "drmtest.h"
Katarzyna Dec081f7712018-04-11 10:14:58 +02008#include "gpu_fill.h"
Xiang, Haihaobd384c22013-12-02 12:36:15 +08009#include <assert.h>
10
Xiang, Haihaobd384c22013-12-02 12:36:15 +080011
12static const uint32_t media_kernel[][4] = {
13 { 0x00400001, 0x20202288, 0x00000020, 0x00000000 },
14 { 0x00600001, 0x20800208, 0x008d0000, 0x00000000 },
15 { 0x00200001, 0x20800208, 0x00450040, 0x00000000 },
16 { 0x00000001, 0x20880608, 0x00000000, 0x000f000f },
17 { 0x00800001, 0x20a00208, 0x00000020, 0x00000000 },
18 { 0x00800001, 0x20e00208, 0x00000020, 0x00000000 },
19 { 0x00800001, 0x21200208, 0x00000020, 0x00000000 },
20 { 0x00800001, 0x21600208, 0x00000020, 0x00000000 },
21 { 0x0c800031, 0x24000a40, 0x0e000080, 0x120a8000 },
22 { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 },
23 { 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 },
24};
25
Xiang, Haihaobd384c22013-12-02 12:36:15 +080026
Xiang, Haihaobd384c22013-12-02 12:36:15 +080027
28/*
29 * This sets up the media pipeline,
30 *
31 * +---------------+ <---- 4096
32 * | ^ |
33 * | | |
34 * | various |
35 * | state |
36 * | | |
37 * |_______|_______| <---- 2048 + ?
38 * | ^ |
39 * | | |
40 * | batch |
41 * | commands |
42 * | | |
43 * | | |
44 * +---------------+ <---- 0 + ?
45 *
46 */
47
48#define BATCH_STATE_SPLIT 2048
49
50void
51gen8_media_fillfunc(struct intel_batchbuffer *batch,
Daniel Vetter83a4c7d2014-03-22 15:44:48 +010052 struct igt_buf *dst,
Katarzyna Dec80e49102018-04-11 10:15:01 +020053 unsigned int x, unsigned int y,
54 unsigned int width, unsigned int height,
Xiang, Haihaobd384c22013-12-02 12:36:15 +080055 uint8_t color)
56{
57 uint32_t curbe_buffer, interface_descriptor;
58 uint32_t batch_end;
59
60 intel_batchbuffer_flush(batch);
61
62 /* setup states */
63 batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
64
Katarzyna Dec80996142018-04-11 10:14:59 +020065 curbe_buffer = gen7_fill_curbe_buffer_data(batch, color);
Katarzyna Dec80e49102018-04-11 10:15:01 +020066 interface_descriptor = gen8_fill_interface_descriptor(batch, dst,
67 media_kernel, sizeof(media_kernel));
Daniel Vetterbaa6f8b2014-08-26 15:03:40 +020068 igt_assert(batch->ptr < &batch->buffer[4095]);
Xiang, Haihaobd384c22013-12-02 12:36:15 +080069
70 /* media pipeline */
71 batch->ptr = batch->buffer;
72 OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
73 gen8_emit_state_base_address(batch);
74
75 gen8_emit_vfe_state(batch);
76
Katarzyna Dec80996142018-04-11 10:14:59 +020077 gen7_emit_curbe_load(batch, curbe_buffer);
Xiang, Haihaobd384c22013-12-02 12:36:15 +080078
Katarzyna Dec80996142018-04-11 10:14:59 +020079 gen7_emit_interface_descriptor_load(batch, interface_descriptor);
Xiang, Haihaobd384c22013-12-02 12:36:15 +080080
Katarzyna Dec80996142018-04-11 10:14:59 +020081 gen7_emit_media_objects(batch, x, y, width, height);
Xiang, Haihaobd384c22013-12-02 12:36:15 +080082
83 OUT_BATCH(MI_BATCH_BUFFER_END);
84
Kalamarz, Lukasze5e8daf2018-04-24 10:32:12 +020085 batch_end = intel_batchbuffer_align(batch, 8);
Daniel Vetterbaa6f8b2014-08-26 15:03:40 +020086 igt_assert(batch_end < BATCH_STATE_SPLIT);
Xiang, Haihaobd384c22013-12-02 12:36:15 +080087
Katarzyna Dec80996142018-04-11 10:14:59 +020088 gen7_render_flush(batch, batch_end);
Xiang, Haihaobd384c22013-12-02 12:36:15 +080089 intel_batchbuffer_reset(batch);
90}