Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 1 | /************************************************************************** |
| 2 | * |
| 3 | * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 4 | * All Rights Reserved. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the |
| 8 | * "Software"), to deal in the Software without restriction, including |
| 9 | * without limitation the rights to use, copy, modify, merge, publish, |
| 10 | * distribute, sub license, and/or sell copies of the Software, and to |
| 11 | * permit persons to whom the Software is furnished to do so, subject to |
| 12 | * the following conditions: |
| 13 | * |
| 14 | * The above copyright notice and this permission notice (including the |
| 15 | * next paragraph) shall be included in all copies or substantial portions |
| 16 | * of the Software. |
| 17 | * |
| 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 21 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 22 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 23 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 24 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 25 | * |
| 26 | **************************************************************************/ |
| 27 | |
| 28 | #include <inttypes.h> |
| 29 | #include <stdlib.h> |
| 30 | #include <stdio.h> |
| 31 | #include <string.h> |
| 32 | #include <assert.h> |
Chris Wilson | 9537422 | 2010-04-08 11:56:57 +0100 | [diff] [blame] | 33 | |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 34 | #include "drm.h" |
Chris Wilson | b7bd183 | 2012-03-29 12:45:59 +0100 | [diff] [blame] | 35 | #include "drmtest.h" |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 36 | #include "intel_batchbuffer.h" |
| 37 | #include "intel_bufmgr.h" |
Chris Wilson | 9537422 | 2010-04-08 11:56:57 +0100 | [diff] [blame] | 38 | #include "intel_chipset.h" |
| 39 | #include "intel_reg.h" |
Daniel Vetter | 7dc0001 | 2014-03-22 15:31:15 +0100 | [diff] [blame] | 40 | #include "rendercopy.h" |
Daniel Vetter | aaebbc5 | 2014-03-22 15:35:16 +0100 | [diff] [blame] | 41 | #include "media_fill.h" |
Damien Lespiau | 672e88a | 2015-03-03 14:11:00 +0000 | [diff] [blame] | 42 | #include "ioctl_wrappers.h" |
Jeff McGee | aef4605 | 2015-03-12 10:52:08 -0700 | [diff] [blame] | 43 | #include "media_spin.h" |
Dominik Zeromski | ed816d5 | 2015-07-17 11:25:43 +0200 | [diff] [blame] | 44 | #include "gpgpu_fill.h" |
Damien Lespiau | 672e88a | 2015-03-03 14:11:00 +0000 | [diff] [blame] | 45 | |
Chris Wilson | 9537422 | 2010-04-08 11:56:57 +0100 | [diff] [blame] | 46 | #include <i915_drm.h> |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 47 | |
Daniel Vetter | ec5f9e8 | 2014-03-13 01:13:28 +0100 | [diff] [blame] | 48 | /** |
| 49 | * SECTION:intel_batchbuffer |
| 50 | * @short_description: Batchbuffer and blitter support |
Damien Lespiau | 6ebd8c2 | 2015-06-26 14:28:41 +0100 | [diff] [blame] | 51 | * @title: Batch Buffer |
Thomas Wood | f0381d1 | 2015-09-07 09:26:01 +0100 | [diff] [blame] | 52 | * @include: igt.h |
Daniel Vetter | cd6d5a6 | 2014-03-22 19:35:40 +0100 | [diff] [blame] | 53 | * |
Daniel Vetter | ec5f9e8 | 2014-03-13 01:13:28 +0100 | [diff] [blame] | 54 | * This library provides some basic support for batchbuffers and using the |
| 55 | * blitter engine based upon libdrm. A new batchbuffer is allocated with |
| 56 | * intel_batchbuffer_alloc() and for simple blitter commands submitted with |
| 57 | * intel_batchbuffer_flush(). |
| 58 | * |
| 59 | * It also provides some convenient macros to easily emit commands into |
| 60 | * batchbuffers. All those macros presume that a pointer to a #intel_batchbuffer |
| 61 | * structure called batch is in scope. The basic macros are #BEGIN_BATCH, |
| 62 | * #OUT_BATCH, #OUT_RELOC and #ADVANCE_BATCH. |
Daniel Vetter | 816c947 | 2014-03-23 15:14:16 +0100 | [diff] [blame] | 63 | * |
| 64 | * Note that this library's header pulls in the [i-g-t core](intel-gpu-tools-i-g-t-core.html) |
Daniel Vetter | c6c2b2b | 2014-03-26 15:15:49 +0100 | [diff] [blame] | 65 | * library as a dependency. |
Daniel Vetter | ec5f9e8 | 2014-03-13 01:13:28 +0100 | [diff] [blame] | 66 | */ |
| 67 | |
| 68 | /** |
| 69 | * intel_batchbuffer_reset: |
| 70 | * @batch: batchbuffer object |
| 71 | * |
| 72 | * Resets @batch by allocating a new gem buffer object as backing storage. |
| 73 | */ |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 74 | void |
| 75 | intel_batchbuffer_reset(struct intel_batchbuffer *batch) |
| 76 | { |
| 77 | if (batch->bo != NULL) { |
| 78 | drm_intel_bo_unreference(batch->bo); |
| 79 | batch->bo = NULL; |
| 80 | } |
| 81 | |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 82 | batch->bo = drm_intel_bo_alloc(batch->bufmgr, "batchbuffer", |
| 83 | BATCH_SZ, 4096); |
| 84 | |
Xiang, Haihao | 4570e1b | 2013-12-06 16:54:44 +0800 | [diff] [blame] | 85 | memset(batch->buffer, 0, sizeof(batch->buffer)); |
Chris Wilson | 107151c | 2014-09-09 16:27:57 +0100 | [diff] [blame] | 86 | batch->ctx = NULL; |
Xiang, Haihao | 4570e1b | 2013-12-06 16:54:44 +0800 | [diff] [blame] | 87 | |
Chris Wilson | 371f87f | 2011-02-01 10:53:57 +0000 | [diff] [blame] | 88 | batch->ptr = batch->buffer; |
Chris Wilson | 961578f | 2014-09-09 14:17:08 +0100 | [diff] [blame] | 89 | batch->end = NULL; |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 90 | } |
| 91 | |
Daniel Vetter | ec5f9e8 | 2014-03-13 01:13:28 +0100 | [diff] [blame] | 92 | /** |
Thomas Wood | ae3a946 | 2014-11-25 11:59:37 +0000 | [diff] [blame] | 93 | * intel_batchbuffer_alloc: |
Daniel Vetter | ec5f9e8 | 2014-03-13 01:13:28 +0100 | [diff] [blame] | 94 | * @bufmgr: libdrm buffer manager |
| 95 | * @devid: pci device id of the drm device |
| 96 | * |
| 97 | * Allocates a new batchbuffer object. @devid must be supplied since libdrm |
| 98 | * doesn't expose it directly. |
| 99 | * |
| 100 | * Returns: The allocated and initialized batchbuffer object. |
| 101 | */ |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 102 | struct intel_batchbuffer * |
Chris Wilson | d4d769a | 2010-10-26 10:59:18 +0100 | [diff] [blame] | 103 | intel_batchbuffer_alloc(drm_intel_bufmgr *bufmgr, uint32_t devid) |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 104 | { |
| 105 | struct intel_batchbuffer *batch = calloc(sizeof(*batch), 1); |
| 106 | |
| 107 | batch->bufmgr = bufmgr; |
Chris Wilson | d4d769a | 2010-10-26 10:59:18 +0100 | [diff] [blame] | 108 | batch->devid = devid; |
Chris Wilson | 23d961e | 2014-08-29 14:49:59 +0100 | [diff] [blame] | 109 | batch->gen = intel_gen(devid); |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 110 | intel_batchbuffer_reset(batch); |
| 111 | |
| 112 | return batch; |
| 113 | } |
| 114 | |
Daniel Vetter | ec5f9e8 | 2014-03-13 01:13:28 +0100 | [diff] [blame] | 115 | /** |
Thomas Wood | ae3a946 | 2014-11-25 11:59:37 +0000 | [diff] [blame] | 116 | * intel_batchbuffer_free: |
Daniel Vetter | ec5f9e8 | 2014-03-13 01:13:28 +0100 | [diff] [blame] | 117 | * @batch: batchbuffer object |
| 118 | * |
| 119 | * Releases all resource of the batchbuffer object @batch. |
| 120 | */ |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 121 | void |
| 122 | intel_batchbuffer_free(struct intel_batchbuffer *batch) |
| 123 | { |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 124 | drm_intel_bo_unreference(batch->bo); |
| 125 | batch->bo = NULL; |
| 126 | free(batch); |
| 127 | } |
| 128 | |
Daniel Vetter | ad515f8 | 2011-03-25 22:09:28 +0100 | [diff] [blame] | 129 | #define CMD_POLY_STIPPLE_OFFSET 0x7906 |
| 130 | |
Ben Widawsky | a635a5a | 2012-01-15 14:52:33 -0800 | [diff] [blame] | 131 | static unsigned int |
| 132 | flush_on_ring_common(struct intel_batchbuffer *batch, int ring) |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 133 | { |
Chris Wilson | 371f87f | 2011-02-01 10:53:57 +0000 | [diff] [blame] | 134 | unsigned int used = batch->ptr - batch->buffer; |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 135 | |
| 136 | if (used == 0) |
Ben Widawsky | a635a5a | 2012-01-15 14:52:33 -0800 | [diff] [blame] | 137 | return 0; |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 138 | |
Daniel Vetter | ad515f8 | 2011-03-25 22:09:28 +0100 | [diff] [blame] | 139 | if (IS_GEN5(batch->devid)) { |
Daniel Vetter | bfbe813 | 2012-05-29 22:14:06 +0200 | [diff] [blame] | 140 | /* emit gen5 w/a without batch space checks - we reserve that |
| 141 | * already. */ |
| 142 | *(uint32_t *) (batch->ptr) = CMD_POLY_STIPPLE_OFFSET << 16; |
Imre Deak | 4f496ba | 2013-09-04 17:02:19 +0300 | [diff] [blame] | 143 | batch->ptr += 4; |
Daniel Vetter | bfbe813 | 2012-05-29 22:14:06 +0200 | [diff] [blame] | 144 | *(uint32_t *) (batch->ptr) = 0; |
Imre Deak | 4f496ba | 2013-09-04 17:02:19 +0300 | [diff] [blame] | 145 | batch->ptr += 4; |
Daniel Vetter | ad515f8 | 2011-03-25 22:09:28 +0100 | [diff] [blame] | 146 | } |
| 147 | |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 148 | /* Round batchbuffer usage to 2 DWORDs. */ |
| 149 | if ((used & 4) == 0) { |
| 150 | *(uint32_t *) (batch->ptr) = 0; /* noop */ |
| 151 | batch->ptr += 4; |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 152 | } |
| 153 | |
| 154 | /* Mark the end of the buffer. */ |
Chris Wilson | 371f87f | 2011-02-01 10:53:57 +0000 | [diff] [blame] | 155 | *(uint32_t *)(batch->ptr) = MI_BATCH_BUFFER_END; /* noop */ |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 156 | batch->ptr += 4; |
Ben Widawsky | a635a5a | 2012-01-15 14:52:33 -0800 | [diff] [blame] | 157 | return batch->ptr - batch->buffer; |
| 158 | } |
| 159 | |
Daniel Vetter | ec5f9e8 | 2014-03-13 01:13:28 +0100 | [diff] [blame] | 160 | /** |
| 161 | * intel_batchbuffer_flush_on_ring: |
| 162 | * @batch: batchbuffer object |
| 163 | * @ring: execbuf ring flag |
| 164 | * |
| 165 | * Submits the batch for execution on @ring. |
| 166 | */ |
Ben Widawsky | a635a5a | 2012-01-15 14:52:33 -0800 | [diff] [blame] | 167 | void |
| 168 | intel_batchbuffer_flush_on_ring(struct intel_batchbuffer *batch, int ring) |
| 169 | { |
Ben Widawsky | a635a5a | 2012-01-15 14:52:33 -0800 | [diff] [blame] | 170 | unsigned int used = flush_on_ring_common(batch, ring); |
Chris Wilson | 107151c | 2014-09-09 16:27:57 +0100 | [diff] [blame] | 171 | drm_intel_context *ctx; |
Ben Widawsky | a635a5a | 2012-01-15 14:52:33 -0800 | [diff] [blame] | 172 | |
| 173 | if (used == 0) |
| 174 | return; |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 175 | |
Chris Wilson | b7bd183 | 2012-03-29 12:45:59 +0100 | [diff] [blame] | 176 | do_or_die(drm_intel_bo_subdata(batch->bo, 0, used, batch->buffer)); |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 177 | |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 178 | batch->ptr = NULL; |
| 179 | |
Chris Wilson | 107151c | 2014-09-09 16:27:57 +0100 | [diff] [blame] | 180 | /* XXX bad kernel API */ |
| 181 | ctx = batch->ctx; |
| 182 | if (ring != I915_EXEC_RENDER) |
| 183 | ctx = NULL; |
| 184 | do_or_die(drm_intel_gem_bo_context_exec(batch->bo, ctx, used, ring)); |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 185 | |
| 186 | intel_batchbuffer_reset(batch); |
| 187 | } |
| 188 | |
Chris Wilson | 107151c | 2014-09-09 16:27:57 +0100 | [diff] [blame] | 189 | void |
| 190 | intel_batchbuffer_set_context(struct intel_batchbuffer *batch, |
| 191 | drm_intel_context *context) |
| 192 | { |
| 193 | batch->ctx = context; |
| 194 | } |
| 195 | |
Daniel Vetter | ec5f9e8 | 2014-03-13 01:13:28 +0100 | [diff] [blame] | 196 | /** |
| 197 | * intel_batchbuffer_flush_with_context: |
| 198 | * @batch: batchbuffer object |
| 199 | * @context: libdrm hardware context object |
| 200 | * |
| 201 | * Submits the batch for execution on the render engine with the supplied |
| 202 | * hardware context. |
| 203 | */ |
Daniel Vetter | d42b7f9 | 2011-09-07 09:20:36 +0200 | [diff] [blame] | 204 | void |
Ben Widawsky | a635a5a | 2012-01-15 14:52:33 -0800 | [diff] [blame] | 205 | intel_batchbuffer_flush_with_context(struct intel_batchbuffer *batch, |
| 206 | drm_intel_context *context) |
| 207 | { |
| 208 | int ret; |
| 209 | unsigned int used = flush_on_ring_common(batch, I915_EXEC_RENDER); |
| 210 | |
| 211 | if (used == 0) |
| 212 | return; |
| 213 | |
| 214 | ret = drm_intel_bo_subdata(batch->bo, 0, used, batch->buffer); |
Daniel Vetter | 257a51e | 2014-08-26 15:26:34 +0200 | [diff] [blame] | 215 | igt_assert(ret == 0); |
Ben Widawsky | a635a5a | 2012-01-15 14:52:33 -0800 | [diff] [blame] | 216 | |
| 217 | batch->ptr = NULL; |
| 218 | |
| 219 | ret = drm_intel_gem_bo_context_exec(batch->bo, context, used, |
| 220 | I915_EXEC_RENDER); |
Daniel Vetter | 257a51e | 2014-08-26 15:26:34 +0200 | [diff] [blame] | 221 | igt_assert(ret == 0); |
Ben Widawsky | a635a5a | 2012-01-15 14:52:33 -0800 | [diff] [blame] | 222 | |
| 223 | intel_batchbuffer_reset(batch); |
| 224 | } |
| 225 | |
Daniel Vetter | ec5f9e8 | 2014-03-13 01:13:28 +0100 | [diff] [blame] | 226 | /** |
| 227 | * intel_batchbuffer_flush: |
| 228 | * @batch: batchbuffer object |
| 229 | * |
| 230 | * Submits the batch for execution on the blitter engine, selecting the right |
| 231 | * ring depending upon the hardware platform. |
| 232 | */ |
Ben Widawsky | a635a5a | 2012-01-15 14:52:33 -0800 | [diff] [blame] | 233 | void |
Daniel Vetter | d42b7f9 | 2011-09-07 09:20:36 +0200 | [diff] [blame] | 234 | intel_batchbuffer_flush(struct intel_batchbuffer *batch) |
| 235 | { |
| 236 | int ring = 0; |
| 237 | if (HAS_BLT_RING(batch->devid)) |
| 238 | ring = I915_EXEC_BLT; |
| 239 | intel_batchbuffer_flush_on_ring(batch, ring); |
| 240 | } |
| 241 | |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 242 | |
Daniel Vetter | ec5f9e8 | 2014-03-13 01:13:28 +0100 | [diff] [blame] | 243 | /** |
| 244 | * intel_batchbuffer_emit_reloc: |
| 245 | * @batch: batchbuffer object |
| 246 | * @buffer: relocation target libdrm buffer object |
| 247 | * @delta: delta value to add to @buffer's gpu address |
| 248 | * @read_domains: gem domain bits for the relocation |
| 249 | * @write_domain: gem domain bit for the relocation |
| 250 | * @fenced: whether this gpu access requires fences |
| 251 | * |
| 252 | * Emits both a libdrm relocation entry pointing at @buffer and the pre-computed |
| 253 | * DWORD of @batch's presumed gpu address plus the supplied @delta into @batch. |
| 254 | * |
| 255 | * Note that @fenced is only relevant if @buffer is actually tiled. |
| 256 | * |
| 257 | * This is the only way buffers get added to the validate list. |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 258 | */ |
| 259 | void |
| 260 | intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch, |
Chris Wilson | 982f7eb | 2014-08-29 15:19:57 +0100 | [diff] [blame] | 261 | drm_intel_bo *buffer, uint64_t delta, |
Daniel Vetter | 8ab88c9 | 2011-03-27 16:17:54 +0200 | [diff] [blame] | 262 | uint32_t read_domains, uint32_t write_domain, |
| 263 | int fenced) |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 264 | { |
Chris Wilson | 982f7eb | 2014-08-29 15:19:57 +0100 | [diff] [blame] | 265 | uint64_t offset; |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 266 | int ret; |
| 267 | |
Chris Wilson | 371f87f | 2011-02-01 10:53:57 +0000 | [diff] [blame] | 268 | if (batch->ptr - batch->buffer > BATCH_SZ) |
Daniel Vetter | 257a51e | 2014-08-26 15:26:34 +0200 | [diff] [blame] | 269 | igt_info("bad relocation ptr %p map %p offset %d size %d\n", |
| 270 | batch->ptr, batch->buffer, |
| 271 | (int)(batch->ptr - batch->buffer), BATCH_SZ); |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 272 | |
Daniel Vetter | 8ab88c9 | 2011-03-27 16:17:54 +0200 | [diff] [blame] | 273 | if (fenced) |
| 274 | ret = drm_intel_bo_emit_reloc_fence(batch->bo, batch->ptr - batch->buffer, |
| 275 | buffer, delta, |
| 276 | read_domains, write_domain); |
| 277 | else |
| 278 | ret = drm_intel_bo_emit_reloc(batch->bo, batch->ptr - batch->buffer, |
| 279 | buffer, delta, |
| 280 | read_domains, write_domain); |
Chris Wilson | 982f7eb | 2014-08-29 15:19:57 +0100 | [diff] [blame] | 281 | |
| 282 | offset = buffer->offset64; |
| 283 | offset += delta; |
| 284 | intel_batchbuffer_emit_dword(batch, offset); |
| 285 | if (batch->gen >= 8) |
| 286 | intel_batchbuffer_emit_dword(batch, offset >> 32); |
Daniel Vetter | 257a51e | 2014-08-26 15:26:34 +0200 | [diff] [blame] | 287 | igt_assert(ret == 0); |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 288 | } |
| 289 | |
Daniel Vetter | ec5f9e8 | 2014-03-13 01:13:28 +0100 | [diff] [blame] | 290 | /** |
| 291 | * intel_batchbuffer_data: |
| 292 | * @batch: batchbuffer object |
| 293 | * @data: pointer to the data to write into the batchbuffer |
| 294 | * @bytes: number of bytes to write into the batchbuffer |
| 295 | * |
| 296 | * This transfers the given @data into the batchbuffer. Note that the length |
| 297 | * must be DWORD aligned, i.e. multiples of 32bits. |
| 298 | */ |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 299 | void |
| 300 | intel_batchbuffer_data(struct intel_batchbuffer *batch, |
| 301 | const void *data, unsigned int bytes) |
| 302 | { |
Daniel Vetter | 257a51e | 2014-08-26 15:26:34 +0200 | [diff] [blame] | 303 | igt_assert((bytes & 3) == 0); |
Eric Anholt | 8c64183 | 2009-03-26 17:15:11 -0700 | [diff] [blame] | 304 | intel_batchbuffer_require_space(batch, bytes); |
| 305 | memcpy(batch->ptr, data, bytes); |
| 306 | batch->ptr += bytes; |
| 307 | } |
Chris Wilson | 9537422 | 2010-04-08 11:56:57 +0100 | [diff] [blame] | 308 | |
Daniel Vetter | ec5f9e8 | 2014-03-13 01:13:28 +0100 | [diff] [blame] | 309 | /** |
| 310 | * intel_blt_copy: |
| 311 | * @batch: batchbuffer object |
| 312 | * @src_bo: source libdrm buffer object |
| 313 | * @src_x1: source pixel x-coordination |
| 314 | * @src_y1: source pixel y-coordination |
| 315 | * @src_pitch: @src_bo's pitch in bytes |
| 316 | * @dst_bo: destination libdrm buffer object |
Daniel Vetter | 7754c4d | 2014-03-22 18:16:30 +0100 | [diff] [blame] | 317 | * @dst_x1: destination pixel x-coordination |
| 318 | * @dst_y1: destination pixel y-coordination |
Daniel Vetter | ec5f9e8 | 2014-03-13 01:13:28 +0100 | [diff] [blame] | 319 | * @dst_pitch: @dst_bo's pitch in bytes |
| 320 | * @width: width of the copied rectangle |
| 321 | * @height: height of the copied rectangle |
| 322 | * @bpp: bits per pixel |
| 323 | * |
| 324 | * This emits a 2D copy operation using blitter commands into the supplied batch |
| 325 | * buffer object. |
| 326 | */ |
Chris Wilson | 9537422 | 2010-04-08 11:56:57 +0100 | [diff] [blame] | 327 | void |
Imre Deak | c1ee0bb | 2013-07-29 16:43:31 +0300 | [diff] [blame] | 328 | intel_blt_copy(struct intel_batchbuffer *batch, |
Daniel Vetter | 53a4d9e | 2014-03-22 15:49:02 +0100 | [diff] [blame] | 329 | drm_intel_bo *src_bo, int src_x1, int src_y1, int src_pitch, |
| 330 | drm_intel_bo *dst_bo, int dst_x1, int dst_y1, int dst_pitch, |
| 331 | int width, int height, int bpp) |
Chris Wilson | 9537422 | 2010-04-08 11:56:57 +0100 | [diff] [blame] | 332 | { |
Chris Wilson | 23d961e | 2014-08-29 14:49:59 +0100 | [diff] [blame] | 333 | const int gen = batch->gen; |
Chris Wilson | 9537422 | 2010-04-08 11:56:57 +0100 | [diff] [blame] | 334 | uint32_t src_tiling, dst_tiling, swizzle; |
Chris Wilson | 9537422 | 2010-04-08 11:56:57 +0100 | [diff] [blame] | 335 | uint32_t cmd_bits = 0; |
Imre Deak | c1ee0bb | 2013-07-29 16:43:31 +0300 | [diff] [blame] | 336 | uint32_t br13_bits; |
Chris Wilson | 9537422 | 2010-04-08 11:56:57 +0100 | [diff] [blame] | 337 | |
Chris Wilson | fbfa754 | 2014-08-29 19:28:34 +0100 | [diff] [blame] | 338 | igt_assert(bpp*(src_x1 + width) <= 8*src_pitch); |
| 339 | igt_assert(bpp*(dst_x1 + width) <= 8*dst_pitch); |
| 340 | igt_assert(src_pitch * (src_y1 + height) <= src_bo->size); |
| 341 | igt_assert(dst_pitch * (dst_y1 + height) <= dst_bo->size); |
| 342 | |
Chris Wilson | 9537422 | 2010-04-08 11:56:57 +0100 | [diff] [blame] | 343 | drm_intel_bo_get_tiling(src_bo, &src_tiling, &swizzle); |
| 344 | drm_intel_bo_get_tiling(dst_bo, &dst_tiling, &swizzle); |
| 345 | |
Chris Wilson | 23d961e | 2014-08-29 14:49:59 +0100 | [diff] [blame] | 346 | if (gen >= 4 && src_tiling != I915_TILING_NONE) { |
Chris Wilson | 9537422 | 2010-04-08 11:56:57 +0100 | [diff] [blame] | 347 | src_pitch /= 4; |
| 348 | cmd_bits |= XY_SRC_COPY_BLT_SRC_TILED; |
| 349 | } |
| 350 | |
Chris Wilson | 23d961e | 2014-08-29 14:49:59 +0100 | [diff] [blame] | 351 | if (gen >= 4 && dst_tiling != I915_TILING_NONE) { |
Chris Wilson | 9537422 | 2010-04-08 11:56:57 +0100 | [diff] [blame] | 352 | dst_pitch /= 4; |
| 353 | cmd_bits |= XY_SRC_COPY_BLT_DST_TILED; |
| 354 | } |
| 355 | |
Chris Wilson | d3e9316 | 2015-03-18 08:33:22 +0000 | [diff] [blame] | 356 | #define CHECK_RANGE(x) ((x) >= 0 && (x) < (1 << 15)) |
| 357 | igt_assert(CHECK_RANGE(src_x1) && CHECK_RANGE(src_y1) && |
| 358 | CHECK_RANGE(dst_x1) && CHECK_RANGE(dst_y1) && |
| 359 | CHECK_RANGE(width) && CHECK_RANGE(height) && |
| 360 | CHECK_RANGE(src_x1 + width) && |
| 361 | CHECK_RANGE(src_y1 + height) && |
| 362 | CHECK_RANGE(dst_x1 + width) && |
| 363 | CHECK_RANGE(dst_y1 + height) && |
| 364 | CHECK_RANGE(src_pitch) && |
| 365 | CHECK_RANGE(dst_pitch)); |
| 366 | #undef CHECK_RANGE |
| 367 | |
Imre Deak | c1ee0bb | 2013-07-29 16:43:31 +0300 | [diff] [blame] | 368 | br13_bits = 0; |
| 369 | switch (bpp) { |
| 370 | case 8: |
| 371 | break; |
| 372 | case 16: /* supporting only RGB565, not ARGB1555 */ |
| 373 | br13_bits |= 1 << 24; |
| 374 | break; |
| 375 | case 32: |
| 376 | br13_bits |= 3 << 24; |
| 377 | cmd_bits |= XY_SRC_COPY_BLT_WRITE_ALPHA | |
| 378 | XY_SRC_COPY_BLT_WRITE_RGB; |
| 379 | break; |
| 380 | default: |
Thomas Wood | b47032e | 2015-04-09 09:24:12 +0100 | [diff] [blame] | 381 | igt_fail(IGT_EXIT_FAILURE); |
Imre Deak | c1ee0bb | 2013-07-29 16:43:31 +0300 | [diff] [blame] | 382 | } |
| 383 | |
Chris Wilson | 10552b5 | 2014-08-30 11:44:51 +0100 | [diff] [blame] | 384 | BLIT_COPY_BATCH_START(cmd_bits); |
Imre Deak | c1ee0bb | 2013-07-29 16:43:31 +0300 | [diff] [blame] | 385 | OUT_BATCH((br13_bits) | |
Chris Wilson | 9537422 | 2010-04-08 11:56:57 +0100 | [diff] [blame] | 386 | (0xcc << 16) | /* copy ROP */ |
| 387 | dst_pitch); |
Imre Deak | c1ee0bb | 2013-07-29 16:43:31 +0300 | [diff] [blame] | 388 | OUT_BATCH((dst_y1 << 16) | dst_x1); /* dst x1,y1 */ |
| 389 | OUT_BATCH(((dst_y1 + height) << 16) | (dst_x1 + width)); /* dst x2,y2 */ |
Chris Wilson | 982f7eb | 2014-08-29 15:19:57 +0100 | [diff] [blame] | 390 | OUT_RELOC_FENCED(dst_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); |
Imre Deak | c1ee0bb | 2013-07-29 16:43:31 +0300 | [diff] [blame] | 391 | OUT_BATCH((src_y1 << 16) | src_x1); /* src x1,y1 */ |
Chris Wilson | 9537422 | 2010-04-08 11:56:57 +0100 | [diff] [blame] | 392 | OUT_BATCH(src_pitch); |
Chris Wilson | 982f7eb | 2014-08-29 15:19:57 +0100 | [diff] [blame] | 393 | OUT_RELOC_FENCED(src_bo, I915_GEM_DOMAIN_RENDER, 0, 0); |
Chris Wilson | 9537422 | 2010-04-08 11:56:57 +0100 | [diff] [blame] | 394 | ADVANCE_BATCH(); |
| 395 | |
Chris Wilson | 982f7eb | 2014-08-29 15:19:57 +0100 | [diff] [blame] | 396 | #define CMD_POLY_STIPPLE_OFFSET 0x7906 |
| 397 | if (gen == 5) { |
Chris Wilson | 10552b5 | 2014-08-30 11:44:51 +0100 | [diff] [blame] | 398 | BEGIN_BATCH(2, 0); |
Chris Wilson | 982f7eb | 2014-08-29 15:19:57 +0100 | [diff] [blame] | 399 | OUT_BATCH(CMD_POLY_STIPPLE_OFFSET << 16); |
| 400 | OUT_BATCH(0); |
Chris Wilson | 10552b5 | 2014-08-30 11:44:51 +0100 | [diff] [blame] | 401 | ADVANCE_BATCH(); |
Chris Wilson | 982f7eb | 2014-08-29 15:19:57 +0100 | [diff] [blame] | 402 | } |
| 403 | |
| 404 | if (gen >= 6 && src_bo == dst_bo) { |
Chris Wilson | 10552b5 | 2014-08-30 11:44:51 +0100 | [diff] [blame] | 405 | BEGIN_BATCH(3, 0); |
Chris Wilson | 982f7eb | 2014-08-29 15:19:57 +0100 | [diff] [blame] | 406 | OUT_BATCH(XY_SETUP_CLIP_BLT_CMD); |
| 407 | OUT_BATCH(0); |
| 408 | OUT_BATCH(0); |
| 409 | ADVANCE_BATCH(); |
| 410 | } |
| 411 | |
Chris Wilson | 9537422 | 2010-04-08 11:56:57 +0100 | [diff] [blame] | 412 | intel_batchbuffer_flush(batch); |
| 413 | } |
Imre Deak | c1ee0bb | 2013-07-29 16:43:31 +0300 | [diff] [blame] | 414 | |
Daniel Vetter | ec5f9e8 | 2014-03-13 01:13:28 +0100 | [diff] [blame] | 415 | /** |
| 416 | * intel_copy_bo: |
| 417 | * @batch: batchbuffer object |
| 418 | * @src_bo: source libdrm buffer object |
| 419 | * @dst_bo: destination libdrm buffer object |
Daniel Vetter | eaccd44 | 2014-03-13 03:35:02 +0100 | [diff] [blame] | 420 | * @size: size of the copy range in bytes |
Daniel Vetter | ec5f9e8 | 2014-03-13 01:13:28 +0100 | [diff] [blame] | 421 | * |
| 422 | * This emits a copy operation using blitter commands into the supplied batch |
Daniel Vetter | eaccd44 | 2014-03-13 03:35:02 +0100 | [diff] [blame] | 423 | * buffer object. A total of @size bytes from the start of @src_bo is copied |
| 424 | * over to @dst_bo. Note that @size must be page-aligned. |
Daniel Vetter | ec5f9e8 | 2014-03-13 01:13:28 +0100 | [diff] [blame] | 425 | */ |
Imre Deak | c1ee0bb | 2013-07-29 16:43:31 +0300 | [diff] [blame] | 426 | void |
| 427 | intel_copy_bo(struct intel_batchbuffer *batch, |
| 428 | drm_intel_bo *dst_bo, drm_intel_bo *src_bo, |
Daniel Vetter | eaccd44 | 2014-03-13 03:35:02 +0100 | [diff] [blame] | 429 | long int size) |
Imre Deak | c1ee0bb | 2013-07-29 16:43:31 +0300 | [diff] [blame] | 430 | { |
Daniel Vetter | 257a51e | 2014-08-26 15:26:34 +0200 | [diff] [blame] | 431 | igt_assert(size % 4096 == 0); |
Daniel Vetter | eaccd44 | 2014-03-13 03:35:02 +0100 | [diff] [blame] | 432 | |
Imre Deak | c1ee0bb | 2013-07-29 16:43:31 +0300 | [diff] [blame] | 433 | intel_blt_copy(batch, |
Daniel Vetter | eaccd44 | 2014-03-13 03:35:02 +0100 | [diff] [blame] | 434 | src_bo, 0, 0, 4096, |
| 435 | dst_bo, 0, 0, 4096, |
| 436 | 4096/4, size/4096, 32); |
Imre Deak | c1ee0bb | 2013-07-29 16:43:31 +0300 | [diff] [blame] | 437 | } |
Daniel Vetter | 7dc0001 | 2014-03-22 15:31:15 +0100 | [diff] [blame] | 438 | |
Daniel Vetter | 7754c4d | 2014-03-22 18:16:30 +0100 | [diff] [blame] | 439 | /** |
| 440 | * igt_buf_width: |
| 441 | * @buf: the i-g-t buffer object |
| 442 | * |
Thomas Wood | d01ebbd | 2015-06-29 16:47:14 +0100 | [diff] [blame] | 443 | * Computes the width in 32-bit pixels of the given buffer. |
Daniel Vetter | 7754c4d | 2014-03-22 18:16:30 +0100 | [diff] [blame] | 444 | * |
| 445 | * Returns: |
| 446 | * The width of the buffer. |
| 447 | */ |
Daniel Vetter | 83a4c7d | 2014-03-22 15:44:48 +0100 | [diff] [blame] | 448 | unsigned igt_buf_width(struct igt_buf *buf) |
Daniel Vetter | 82c6dff | 2014-03-22 15:41:42 +0100 | [diff] [blame] | 449 | { |
| 450 | return buf->stride/sizeof(uint32_t); |
| 451 | } |
| 452 | |
Daniel Vetter | 7754c4d | 2014-03-22 18:16:30 +0100 | [diff] [blame] | 453 | /** |
| 454 | * igt_buf_height: |
| 455 | * @buf: the i-g-t buffer object |
| 456 | * |
| 457 | * Computes the height in 32-bit pixels of the given buffer. |
| 458 | * |
| 459 | * Returns: |
| 460 | * The height of the buffer. |
| 461 | */ |
Daniel Vetter | 83a4c7d | 2014-03-22 15:44:48 +0100 | [diff] [blame] | 462 | unsigned igt_buf_height(struct igt_buf *buf) |
Daniel Vetter | 82c6dff | 2014-03-22 15:41:42 +0100 | [diff] [blame] | 463 | { |
| 464 | return buf->size/buf->stride; |
| 465 | } |
| 466 | |
Damien Lespiau | cbd927c | 2015-03-03 14:10:57 +0000 | [diff] [blame] | 467 | /* |
| 468 | * pitches are in bytes if the surfaces are linear, number of dwords |
| 469 | * otherwise |
| 470 | */ |
Damien Lespiau | 672e88a | 2015-03-03 14:11:00 +0000 | [diff] [blame] | 471 | static uint32_t fast_copy_pitch(unsigned int stride, unsigned int tiling) |
Damien Lespiau | cbd927c | 2015-03-03 14:10:57 +0000 | [diff] [blame] | 472 | { |
Damien Lespiau | 130221b | 2015-03-03 14:10:58 +0000 | [diff] [blame] | 473 | if (tiling != I915_TILING_NONE) |
| 474 | return stride / 4; |
Damien Lespiau | cbd927c | 2015-03-03 14:10:57 +0000 | [diff] [blame] | 475 | else |
Damien Lespiau | 130221b | 2015-03-03 14:10:58 +0000 | [diff] [blame] | 476 | return stride; |
Damien Lespiau | cbd927c | 2015-03-03 14:10:57 +0000 | [diff] [blame] | 477 | } |
| 478 | |
Damien Lespiau | 6533d11 | 2015-03-03 14:10:59 +0000 | [diff] [blame] | 479 | static uint32_t fast_copy_dword0(unsigned int src_tiling, |
| 480 | unsigned int dst_tiling) |
| 481 | { |
| 482 | uint32_t dword0 = 0; |
| 483 | |
| 484 | dword0 |= XY_FAST_COPY_BLT; |
| 485 | |
| 486 | switch (src_tiling) { |
| 487 | case I915_TILING_X: |
| 488 | dword0 |= XY_FAST_COPY_SRC_TILING_X; |
| 489 | break; |
| 490 | case I915_TILING_Y: |
| 491 | case I915_TILING_Yf: |
| 492 | dword0 |= XY_FAST_COPY_SRC_TILING_Yb_Yf; |
| 493 | break; |
| 494 | case I915_TILING_Ys: |
| 495 | dword0 |= XY_FAST_COPY_SRC_TILING_Ys; |
| 496 | break; |
| 497 | case I915_TILING_NONE: |
| 498 | default: |
| 499 | break; |
| 500 | } |
| 501 | |
| 502 | switch (dst_tiling) { |
| 503 | case I915_TILING_X: |
| 504 | dword0 |= XY_FAST_COPY_DST_TILING_X; |
| 505 | break; |
| 506 | case I915_TILING_Y: |
| 507 | case I915_TILING_Yf: |
| 508 | dword0 |= XY_FAST_COPY_DST_TILING_Yb_Yf; |
| 509 | break; |
| 510 | case I915_TILING_Ys: |
| 511 | dword0 |= XY_FAST_COPY_DST_TILING_Ys; |
| 512 | break; |
| 513 | case I915_TILING_NONE: |
| 514 | default: |
| 515 | break; |
| 516 | } |
| 517 | |
| 518 | return dword0; |
| 519 | } |
| 520 | |
| 521 | static uint32_t fast_copy_dword1(unsigned int src_tiling, |
| 522 | unsigned int dst_tiling) |
| 523 | { |
| 524 | uint32_t dword1 = 0; |
| 525 | |
| 526 | if (src_tiling == I915_TILING_Yf) |
| 527 | dword1 |= XY_FAST_COPY_SRC_TILING_Yf; |
| 528 | if (dst_tiling == I915_TILING_Yf) |
| 529 | dword1 |= XY_FAST_COPY_DST_TILING_Yf; |
| 530 | |
| 531 | dword1 |= XY_FAST_COPY_COLOR_DEPTH_32; |
| 532 | |
| 533 | return dword1; |
| 534 | } |
| 535 | |
Damien Lespiau | 672e88a | 2015-03-03 14:11:00 +0000 | [diff] [blame] | 536 | static void |
| 537 | fill_relocation(struct drm_i915_gem_relocation_entry *reloc, |
| 538 | uint32_t gem_handle, uint32_t offset, /* in dwords */ |
| 539 | uint32_t read_domains, uint32_t write_domains) |
| 540 | { |
| 541 | reloc->target_handle = gem_handle; |
| 542 | reloc->delta = 0; |
| 543 | reloc->offset = offset * sizeof(uint32_t); |
| 544 | reloc->presumed_offset = 0; |
| 545 | reloc->read_domains = read_domains; |
| 546 | reloc->write_domain = write_domains; |
| 547 | } |
| 548 | |
| 549 | static void |
| 550 | fill_object(struct drm_i915_gem_exec_object2 *obj, uint32_t gem_handle, |
| 551 | struct drm_i915_gem_relocation_entry *relocs, uint32_t count) |
| 552 | { |
| 553 | memset(obj, 0, sizeof(*obj)); |
| 554 | obj->handle = gem_handle; |
| 555 | obj->relocation_count = count; |
Chris Wilson | 39858a1 | 2017-01-02 11:05:21 +0000 | [diff] [blame] | 556 | obj->relocs_ptr = to_user_pointer(relocs); |
Damien Lespiau | 672e88a | 2015-03-03 14:11:00 +0000 | [diff] [blame] | 557 | } |
| 558 | |
| 559 | static void exec_blit(int fd, |
| 560 | struct drm_i915_gem_exec_object2 *objs, uint32_t count, |
| 561 | uint32_t batch_len /* in dwords */) |
| 562 | { |
| 563 | struct drm_i915_gem_execbuffer2 exec; |
| 564 | |
Chris Wilson | 39858a1 | 2017-01-02 11:05:21 +0000 | [diff] [blame] | 565 | exec.buffers_ptr = to_user_pointer(objs); |
Damien Lespiau | 672e88a | 2015-03-03 14:11:00 +0000 | [diff] [blame] | 566 | exec.buffer_count = count; |
| 567 | exec.batch_start_offset = 0; |
| 568 | exec.batch_len = batch_len * 4; |
| 569 | exec.DR1 = exec.DR4 = 0; |
| 570 | exec.num_cliprects = 0; |
| 571 | exec.cliprects_ptr = 0; |
| 572 | exec.flags = I915_EXEC_BLT; |
| 573 | i915_execbuffer2_set_context_id(exec, 0); |
| 574 | exec.rsvd2 = 0; |
| 575 | |
| 576 | gem_execbuf(fd, &exec); |
| 577 | } |
| 578 | |
| 579 | /** |
| 580 | * igt_blitter_fast_copy__raw: |
| 581 | * @fd: file descriptor of the i915 driver |
| 582 | * @src_handle: GEM handle of the source buffer |
| 583 | * @src_stride: Stride (in bytes) of the source buffer |
| 584 | * @src_tiling: Tiling mode of the source buffer |
| 585 | * @src_x: X coordinate of the source region to copy |
| 586 | * @src_y: Y coordinate of the source region to copy |
| 587 | * @width: Width of the region to copy |
| 588 | * @height: Height of the region to copy |
| 589 | * @dst_handle: GEM handle of the source buffer |
| 590 | * @dst_stride: Stride (in bytes) of the destination buffer |
| 591 | * @dst_tiling: Tiling mode of the destination buffer |
| 592 | * @dst_x: X coordinate of destination |
| 593 | * @dst_y: Y coordinate of destination |
| 594 | * |
| 595 | * Like igt_blitter_fast_copy(), but talking to the kernel directly. |
| 596 | */ |
| 597 | void igt_blitter_fast_copy__raw(int fd, |
| 598 | /* src */ |
| 599 | uint32_t src_handle, |
| 600 | unsigned int src_stride, |
| 601 | unsigned int src_tiling, |
| 602 | unsigned int src_x, unsigned src_y, |
| 603 | |
| 604 | /* size */ |
| 605 | unsigned int width, unsigned int height, |
| 606 | |
| 607 | /* dst */ |
| 608 | uint32_t dst_handle, |
| 609 | unsigned int dst_stride, |
| 610 | unsigned int dst_tiling, |
| 611 | unsigned int dst_x, unsigned dst_y) |
| 612 | { |
| 613 | uint32_t batch[12]; |
| 614 | struct drm_i915_gem_exec_object2 objs[3]; |
| 615 | struct drm_i915_gem_relocation_entry relocs[2]; |
| 616 | uint32_t batch_handle; |
| 617 | uint32_t dword0, dword1; |
| 618 | uint32_t src_pitch, dst_pitch; |
| 619 | int i = 0; |
| 620 | |
| 621 | src_pitch = fast_copy_pitch(src_stride, src_tiling); |
| 622 | dst_pitch = fast_copy_pitch(dst_stride, dst_tiling); |
| 623 | dword0 = fast_copy_dword0(src_tiling, dst_tiling); |
| 624 | dword1 = fast_copy_dword1(src_tiling, dst_tiling); |
| 625 | |
| 626 | #define CHECK_RANGE(x) ((x) >= 0 && (x) < (1 << 15)) |
| 627 | assert(CHECK_RANGE(src_x) && CHECK_RANGE(src_y) && |
| 628 | CHECK_RANGE(dst_x) && CHECK_RANGE(dst_y) && |
| 629 | CHECK_RANGE(width) && CHECK_RANGE(height) && |
| 630 | CHECK_RANGE(src_x + width) && CHECK_RANGE(src_y + height) && |
| 631 | CHECK_RANGE(dst_x + width) && CHECK_RANGE(dst_y + height) && |
| 632 | CHECK_RANGE(src_pitch) && CHECK_RANGE(dst_pitch)); |
| 633 | #undef CHECK_RANGE |
| 634 | |
| 635 | batch[i++] = dword0; |
| 636 | batch[i++] = dword1 | dst_pitch; |
| 637 | batch[i++] = (dst_y << 16) | dst_x; /* dst x1,y1 */ |
| 638 | batch[i++] = ((dst_y + height) << 16) | (dst_x + width); /* dst x2,y2 */ |
| 639 | batch[i++] = 0; /* dst address lower bits */ |
| 640 | batch[i++] = 0; /* dst address upper bits */ |
| 641 | batch[i++] = (src_y << 16) | src_x; /* src x1,y1 */ |
| 642 | batch[i++] = src_pitch; |
| 643 | batch[i++] = 0; /* src address lower bits */ |
| 644 | batch[i++] = 0; /* src address upper bits */ |
| 645 | batch[i++] = MI_BATCH_BUFFER_END; |
| 646 | batch[i++] = MI_NOOP; |
| 647 | |
| 648 | igt_assert(i == ARRAY_SIZE(batch)); |
| 649 | |
| 650 | batch_handle = gem_create(fd, 4096); |
| 651 | gem_write(fd, batch_handle, 0, batch, sizeof(batch)); |
| 652 | |
| 653 | fill_relocation(&relocs[0], dst_handle, 4, |
| 654 | I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); |
| 655 | fill_relocation(&relocs[1], src_handle, 8, I915_GEM_DOMAIN_RENDER, 0); |
| 656 | |
| 657 | fill_object(&objs[0], dst_handle, NULL, 0); |
| 658 | fill_object(&objs[1], src_handle, NULL, 0); |
| 659 | fill_object(&objs[2], batch_handle, relocs, 2); |
| 660 | |
| 661 | exec_blit(fd, objs, 3, ARRAY_SIZE(batch)); |
| 662 | |
| 663 | gem_close(fd, batch_handle); |
| 664 | } |
| 665 | |
Damien Lespiau | cbd927c | 2015-03-03 14:10:57 +0000 | [diff] [blame] | 666 | /** |
| 667 | * igt_blitter_fast_copy: |
| 668 | * @batch: batchbuffer object |
Damien Lespiau | cbd927c | 2015-03-03 14:10:57 +0000 | [diff] [blame] | 669 | * @src: source i-g-t buffer object |
| 670 | * @src_x: source pixel x-coordination |
| 671 | * @src_y: source pixel y-coordination |
| 672 | * @width: width of the copied rectangle |
| 673 | * @height: height of the copied rectangle |
| 674 | * @dst: destination i-g-t buffer object |
| 675 | * @dst_x: destination pixel x-coordination |
| 676 | * @dst_y: destination pixel y-coordination |
| 677 | * |
Thomas Wood | d01ebbd | 2015-06-29 16:47:14 +0100 | [diff] [blame] | 678 | * Copy @src into @dst using the gen9 fast copy blitter command. |
Damien Lespiau | cbd927c | 2015-03-03 14:10:57 +0000 | [diff] [blame] | 679 | * |
| 680 | * The source and destination surfaces cannot overlap. |
| 681 | */ |
| 682 | void igt_blitter_fast_copy(struct intel_batchbuffer *batch, |
| 683 | struct igt_buf *src, unsigned src_x, unsigned src_y, |
| 684 | unsigned width, unsigned height, |
| 685 | struct igt_buf *dst, unsigned dst_x, unsigned dst_y) |
| 686 | { |
| 687 | uint32_t src_pitch, dst_pitch; |
Damien Lespiau | 6533d11 | 2015-03-03 14:10:59 +0000 | [diff] [blame] | 688 | uint32_t dword0, dword1; |
Damien Lespiau | cbd927c | 2015-03-03 14:10:57 +0000 | [diff] [blame] | 689 | |
Damien Lespiau | 130221b | 2015-03-03 14:10:58 +0000 | [diff] [blame] | 690 | src_pitch = fast_copy_pitch(src->stride, src->tiling); |
| 691 | dst_pitch = fast_copy_pitch(dst->stride, src->tiling); |
Damien Lespiau | 6533d11 | 2015-03-03 14:10:59 +0000 | [diff] [blame] | 692 | dword0 = fast_copy_dword0(src->tiling, dst->tiling); |
| 693 | dword1 = fast_copy_dword1(src->tiling, dst->tiling); |
Damien Lespiau | cbd927c | 2015-03-03 14:10:57 +0000 | [diff] [blame] | 694 | |
| 695 | #define CHECK_RANGE(x) ((x) >= 0 && (x) < (1 << 15)) |
| 696 | assert(CHECK_RANGE(src_x) && CHECK_RANGE(src_y) && |
| 697 | CHECK_RANGE(dst_x) && CHECK_RANGE(dst_y) && |
| 698 | CHECK_RANGE(width) && CHECK_RANGE(height) && |
| 699 | CHECK_RANGE(src_x + width) && CHECK_RANGE(src_y + height) && |
| 700 | CHECK_RANGE(dst_x + width) && CHECK_RANGE(dst_y + height) && |
| 701 | CHECK_RANGE(src_pitch) && CHECK_RANGE(dst_pitch)); |
| 702 | #undef CHECK_RANGE |
| 703 | |
Damien Lespiau | cbd927c | 2015-03-03 14:10:57 +0000 | [diff] [blame] | 704 | BEGIN_BATCH(10, 2); |
| 705 | OUT_BATCH(dword0); |
| 706 | OUT_BATCH(dword1 | dst_pitch); |
| 707 | OUT_BATCH((dst_y << 16) | dst_x); /* dst x1,y1 */ |
| 708 | OUT_BATCH(((dst_y + height) << 16) | (dst_x + width)); /* dst x2,y2 */ |
| 709 | OUT_RELOC(dst->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); |
| 710 | OUT_BATCH(0); /* dst address upper bits */ |
| 711 | OUT_BATCH((src_y << 16) | src_x); /* src x1,y1 */ |
| 712 | OUT_BATCH(src_pitch); |
| 713 | OUT_RELOC(src->bo, I915_GEM_DOMAIN_RENDER, 0, 0); |
| 714 | OUT_BATCH(0); /* src address upper bits */ |
| 715 | ADVANCE_BATCH(); |
| 716 | |
| 717 | intel_batchbuffer_flush(batch); |
| 718 | } |
| 719 | |
Daniel Vetter | 7754c4d | 2014-03-22 18:16:30 +0100 | [diff] [blame] | 720 | /** |
| 721 | * igt_get_render_copyfunc: |
| 722 | * @devid: pci device id |
| 723 | * |
| 724 | * Returns: |
| 725 | * |
| 726 | * The platform-specific render copy function pointer for the device |
| 727 | * specified with @devid. Will return NULL when no render copy function is |
| 728 | * implemented. |
| 729 | */ |
Daniel Vetter | 53a4d9e | 2014-03-22 15:49:02 +0100 | [diff] [blame] | 730 | igt_render_copyfunc_t igt_get_render_copyfunc(int devid) |
Daniel Vetter | 7dc0001 | 2014-03-22 15:31:15 +0100 | [diff] [blame] | 731 | { |
Daniel Vetter | 53a4d9e | 2014-03-22 15:49:02 +0100 | [diff] [blame] | 732 | igt_render_copyfunc_t copy = NULL; |
Daniel Vetter | 7dc0001 | 2014-03-22 15:31:15 +0100 | [diff] [blame] | 733 | |
| 734 | if (IS_GEN2(devid)) |
| 735 | copy = gen2_render_copyfunc; |
| 736 | else if (IS_GEN3(devid)) |
| 737 | copy = gen3_render_copyfunc; |
| 738 | else if (IS_GEN6(devid)) |
| 739 | copy = gen6_render_copyfunc; |
| 740 | else if (IS_GEN7(devid)) |
| 741 | copy = gen7_render_copyfunc; |
| 742 | else if (IS_GEN8(devid)) |
| 743 | copy = gen8_render_copyfunc; |
Rodrigo Vivi | be2e7ba | 2017-06-29 14:16:57 -0700 | [diff] [blame] | 744 | else if (IS_GEN9(devid) || IS_GEN10(devid)) |
Xiang, Haihao | 781a048 | 2014-04-11 21:57:21 +0800 | [diff] [blame] | 745 | copy = gen9_render_copyfunc; |
Daniel Vetter | 7dc0001 | 2014-03-22 15:31:15 +0100 | [diff] [blame] | 746 | |
| 747 | return copy; |
| 748 | } |
Daniel Vetter | aaebbc5 | 2014-03-22 15:35:16 +0100 | [diff] [blame] | 749 | |
Daniel Vetter | 7754c4d | 2014-03-22 18:16:30 +0100 | [diff] [blame] | 750 | /** |
| 751 | * igt_get_media_fillfunc: |
| 752 | * @devid: pci device id |
| 753 | * |
| 754 | * Returns: |
| 755 | * |
| 756 | * The platform-specific media fill function pointer for the device specified |
| 757 | * with @devid. Will return NULL when no media fill function is implemented. |
| 758 | */ |
Zhenyu Wang | 106f0bf | 2014-12-03 18:56:39 +0800 | [diff] [blame] | 759 | igt_fillfunc_t igt_get_media_fillfunc(int devid) |
Daniel Vetter | aaebbc5 | 2014-03-22 15:35:16 +0100 | [diff] [blame] | 760 | { |
Zhenyu Wang | 106f0bf | 2014-12-03 18:56:39 +0800 | [diff] [blame] | 761 | igt_fillfunc_t fill = NULL; |
Daniel Vetter | aaebbc5 | 2014-03-22 15:35:16 +0100 | [diff] [blame] | 762 | |
Xiang, Haihao | 781a048 | 2014-04-11 21:57:21 +0800 | [diff] [blame] | 763 | if (IS_GEN9(devid)) |
| 764 | fill = gen9_media_fillfunc; |
| 765 | else if (IS_BROADWELL(devid)) |
Daniel Vetter | aaebbc5 | 2014-03-22 15:35:16 +0100 | [diff] [blame] | 766 | fill = gen8_media_fillfunc; |
| 767 | else if (IS_GEN7(devid)) |
| 768 | fill = gen7_media_fillfunc; |
Sean V Kelley | 17d63e4 | 2014-08-05 13:53:49 -0700 | [diff] [blame] | 769 | else if (IS_CHERRYVIEW(devid)) |
| 770 | fill = gen8lp_media_fillfunc; |
Daniel Vetter | aaebbc5 | 2014-03-22 15:35:16 +0100 | [diff] [blame] | 771 | |
| 772 | return fill; |
| 773 | } |
Zhenyu Wang | 10c6ad3 | 2014-12-03 19:05:09 +0800 | [diff] [blame] | 774 | |
| 775 | /** |
| 776 | * igt_get_gpgpu_fillfunc: |
| 777 | * @devid: pci device id |
| 778 | * |
| 779 | * Returns: |
| 780 | * |
| 781 | * The platform-specific gpgpu fill function pointer for the device specified |
| 782 | * with @devid. Will return NULL when no gpgpu fill function is implemented. |
| 783 | */ |
| 784 | igt_fillfunc_t igt_get_gpgpu_fillfunc(int devid) |
| 785 | { |
| 786 | igt_fillfunc_t fill = NULL; |
| 787 | |
| 788 | if (IS_GEN7(devid)) |
| 789 | fill = gen7_gpgpu_fillfunc; |
Dominik Zeromski | a017c29 | 2015-07-17 11:25:44 +0200 | [diff] [blame] | 790 | else if (IS_BROADWELL(devid)) |
| 791 | fill = gen8_gpgpu_fillfunc; |
Rodrigo Vivi | be2e7ba | 2017-06-29 14:16:57 -0700 | [diff] [blame] | 792 | else if (IS_GEN9(devid) || IS_GEN10(devid)) |
Dominik Zeromski | 3676912 | 2015-07-17 11:25:45 +0200 | [diff] [blame] | 793 | fill = gen9_gpgpu_fillfunc; |
Zhenyu Wang | 10c6ad3 | 2014-12-03 19:05:09 +0800 | [diff] [blame] | 794 | |
| 795 | return fill; |
| 796 | } |
Jeff McGee | aef4605 | 2015-03-12 10:52:08 -0700 | [diff] [blame] | 797 | |
| 798 | /** |
| 799 | * igt_get_media_spinfunc: |
| 800 | * @devid: pci device id |
| 801 | * |
| 802 | * Returns: |
| 803 | * |
| 804 | * The platform-specific media spin function pointer for the device specified |
| 805 | * with @devid. Will return NULL when no media spin function is implemented. |
| 806 | */ |
| 807 | igt_media_spinfunc_t igt_get_media_spinfunc(int devid) |
| 808 | { |
| 809 | igt_media_spinfunc_t spin = NULL; |
| 810 | |
| 811 | if (IS_GEN9(devid)) |
| 812 | spin = gen9_media_spinfunc; |
| 813 | else if (IS_BROADWELL(devid)) |
| 814 | spin = gen8_media_spinfunc; |
| 815 | else if (IS_CHERRYVIEW(devid)) |
| 816 | spin = gen8lp_media_spinfunc; |
| 817 | |
| 818 | return spin; |
| 819 | } |