Gitiles
Code Review Sign In
gerrit-public.fairphone.software / platform / external / libavc / 3f6c941de5cd959072fa046c9d6cb26fa0f01dc6 / . / decoder / ih264d_api.c
blob: f244f4c00f7da3060e49bec32c758fb9ff9d42c9 [file] [log] [blame]
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1/******************************************************************************
2 *
3 * Copyright (C) 2015 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19*/
20
21/*****************************************************************************/
22/* */
23/* File Name : ih264d_api.c */
24/* */
25/* Description : Has all API related functions */
26/* */
27/* */
28/* List of Functions : api_check_struct_sanity */
29/* ih264d_set_processor */
30/* ih264d_get_num_rec */
31/* ih264d_init_decoder */
32/* ih264d_init_video_decoder */
33/* ih264d_fill_num_mem_rec */
34/* ih264d_clr */
35/* ih264d_init */
36/* ih264d_map_error */
37/* ih264d_video_decode */
38/* ih264d_get_version */
39/* ih264d_get_display_frame */
40/* ih264d_set_display_frame */
41/* ih264d_set_flush_mode */
42/* ih264d_get_status */
43/* ih264d_get_buf_info */
44/* ih264d_set_params */
45/* ih264d_set_default_params */
46/* ih264d_reset */
47/* ih264d_ctl */
48/* ih264d_rel_display_frame */
49/* ih264d_set_degrade */
50/* ih264d_get_frame_dimensions */
51/* ih264d_set_num_cores */
52/* ih264d_fill_output_struct_from_context */
53/* ih264d_api_function */
54/* */
55/* Issues / Problems : None */
56/* */
57/* Revision History : */
58/* */
59/* DD MM YYYY Author(s) Changes (Describe the changes made) */
60/* 14 10 2008 100356(SKV) Draft */
61/* */
62/*****************************************************************************/
63#include "ih264_typedefs.h"
64#include "ih264_macros.h"
65#include "ih264_platform_macros.h"
66#include "ih264d_tables.h"
67#include "iv.h"
68#include "ivd.h"
69#include "ih264d.h"
70#include "ih264d_defs.h"
71
72#include <string.h>
73#include <limits.h>
74#include <stddef.h>
75
76#include "ih264d_inter_pred.h"
77
78#include "ih264d_structs.h"
79#include "ih264d_nal.h"
80#include "ih264d_error_handler.h"
81
82#include "ih264d_defs.h"
83
84#include "ithread.h"
85#include "ih264d_parse_slice.h"
86#include "ih264d_function_selector.h"
87#include "ih264_error.h"
88#include "ih264_disp_mgr.h"
89#include "ih264_buf_mgr.h"
90#include "ih264d_deblocking.h"
91#include "ih264d_parse_cavlc.h"
92#include "ih264d_parse_cabac.h"
93#include "ih264d_utils.h"
94#include "ih264d_format_conv.h"
95#include "ih264d_parse_headers.h"
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]96#include "ih264d_thread_compute_bs.h"
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]97#include <assert.h>
98
99
100/*********************/
101/* Codec Versioning */
102/*********************/
103//Move this to where it is used
104#define CODEC_NAME "H264VDEC"
105#define CODEC_RELEASE_TYPE "production"
106#define CODEC_RELEASE_VER "04.00"
107#define CODEC_VENDOR "ITTIAM"
108#define MAXVERSION_STRLEN 511
109#define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
Martin Storsjo85a43d22015-05-20 00:12:28 +0300[diff] [blame]110 snprintf(version_string, MAXVERSION_STRLEN, \
111 "@(#)Id:%s_%s Ver:%s Released by %s Build: %s @ %s", \
112 codec_name, codec_release_type, codec_release_ver, codec_vendor, __DATE__, __TIME__)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]113
114#define MAX_NAL_UNIT_SIZE MAX((H264_MAX_FRAME_HEIGHT * H264_MAX_FRAME_HEIGHT),MIN_NALUNIT_SIZE)
115#define MIN_NALUNIT_SIZE 200000
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]116
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]117
118#define MIN_IN_BUFS 1
119#define MIN_OUT_BUFS_420 3
120#define MIN_OUT_BUFS_422ILE 1
121#define MIN_OUT_BUFS_RGB565 1
122#define MIN_OUT_BUFS_420SP 2
123#define MIN_IN_BUF_SIZE (2*1024*1024) // Currently, i4_size set to 500kb, CHECK LATER
124
125#define NUM_FRAMES_LIMIT_ENABLED 0
126
127#if NUM_FRAMES_LIMIT_ENABLED
128#define NUM_FRAMES_LIMIT 10000
129#else
130#define NUM_FRAMES_LIMIT 0x7FFFFFFF
131#endif
132
133
134UWORD32 ih264d_get_extra_mem_external(UWORD32 width, UWORD32 height);
135WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl,
136 void *pv_api_ip,
137 void *pv_api_op);
138WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op);
139
140WORD32 ih264d_deblock_display(dec_struct_t *ps_dec);
141
142void ih264d_signal_decode_thread(dec_struct_t *ps_dec);
143
144void ih264d_signal_bs_deblk_thread(dec_struct_t *ps_dec);
145void ih264d_decode_picture_thread(dec_struct_t *ps_dec);
146
147WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj,
148 void *pv_api_ip,
149 void *pv_api_op);
150
151void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec,
152 ivd_video_decode_op_t *ps_dec_op);
153
154static IV_API_CALL_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle,
155 void *pv_api_ip,
156 void *pv_api_op)
157{
158 IVD_API_COMMAND_TYPE_T e_cmd;
159 UWORD32 *pu4_api_ip;
160 UWORD32 *pu4_api_op;
161 UWORD32 i, j;
162
163 if(NULL == pv_api_op)
164 return (IV_FAIL);
165
166 if(NULL == pv_api_ip)
167 return (IV_FAIL);
168
169 pu4_api_ip = (UWORD32 *)pv_api_ip;
170 pu4_api_op = (UWORD32 *)pv_api_op;
171 e_cmd = *(pu4_api_ip + 1);
172
173 /* error checks on handle */
174 switch((WORD32)e_cmd)
175 {
176 case IV_CMD_GET_NUM_MEM_REC:
177 case IV_CMD_FILL_NUM_MEM_REC:
178 break;
179 case IV_CMD_INIT:
180 if(ps_handle == NULL)
181 {
182 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
183 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
184 return IV_FAIL;
185 }
186
187 if(ps_handle->u4_size != sizeof(iv_obj_t))
188 {
189 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
190 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
191 H264_DEC_DEBUG_PRINT(
192 "Sizes do not match. Expected: %d, Got: %d",
193 sizeof(iv_obj_t), ps_handle->u4_size);
194 return IV_FAIL;
195 }
196 break;
197 case IVD_CMD_REL_DISPLAY_FRAME:
198 case IVD_CMD_SET_DISPLAY_FRAME:
199 case IVD_CMD_GET_DISPLAY_FRAME:
200 case IVD_CMD_VIDEO_DECODE:
201 case IV_CMD_RETRIEVE_MEMREC:
202 case IVD_CMD_VIDEO_CTL:
203 if(ps_handle == NULL)
204 {
205 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
206 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
207 return IV_FAIL;
208 }
209
210 if(ps_handle->u4_size != sizeof(iv_obj_t))
211 {
212 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
213 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
214 return IV_FAIL;
215 }
216
217 if(ps_handle->pv_fxns != ih264d_api_function)
218 {
219 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
220 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
221 return IV_FAIL;
222 }
223
224 if(ps_handle->pv_codec_handle == NULL)
225 {
226 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
227 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
228 return IV_FAIL;
229 }
230 break;
231 default:
232 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
233 *(pu4_api_op + 1) |= IVD_INVALID_API_CMD;
234 return IV_FAIL;
235 }
236
237 switch((WORD32)e_cmd)
238 {
239 case IV_CMD_GET_NUM_MEM_REC:
240 {
241 ih264d_num_mem_rec_ip_t *ps_ip =
242 (ih264d_num_mem_rec_ip_t *)pv_api_ip;
243 ih264d_num_mem_rec_op_t *ps_op =
244 (ih264d_num_mem_rec_op_t *)pv_api_op;
245 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code = 0;
246
247 if(ps_ip->s_ivd_num_mem_rec_ip_t.u4_size
248 != sizeof(ih264d_num_mem_rec_ip_t))
249 {
250 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1
251 << IVD_UNSUPPORTEDPARAM;
252 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |=
253 IVD_IP_API_STRUCT_SIZE_INCORRECT;
254 return (IV_FAIL);
255 }
256
257 if(ps_op->s_ivd_num_mem_rec_op_t.u4_size
258 != sizeof(ih264d_num_mem_rec_op_t))
259 {
260 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1
261 << IVD_UNSUPPORTEDPARAM;
262 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |=
263 IVD_OP_API_STRUCT_SIZE_INCORRECT;
264 return (IV_FAIL);
265 }
266 }
267 break;
268 case IV_CMD_FILL_NUM_MEM_REC:
269 {
270 ih264d_fill_mem_rec_ip_t *ps_ip =
271 (ih264d_fill_mem_rec_ip_t *)pv_api_ip;
272 ih264d_fill_mem_rec_op_t *ps_op =
273 (ih264d_fill_mem_rec_op_t *)pv_api_op;
274 iv_mem_rec_t *ps_mem_rec;
275 WORD32 max_wd = ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd;
276 WORD32 max_ht = ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht;
277
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]278 max_wd = ALIGN16(max_wd);
279 max_ht = ALIGN32(max_ht);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]280
281 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0;
282
283 if((ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size
284 > sizeof(ih264d_fill_mem_rec_ip_t))
285 || (ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size
286 < sizeof(iv_fill_mem_rec_ip_t)))
287 {
288 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
289 << IVD_UNSUPPORTEDPARAM;
290 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
291 IVD_IP_API_STRUCT_SIZE_INCORRECT;
292 return (IV_FAIL);
293 }
294
295 if((ps_op->s_ivd_fill_mem_rec_op_t.u4_size
296 != sizeof(ih264d_fill_mem_rec_op_t))
297 && (ps_op->s_ivd_fill_mem_rec_op_t.u4_size
298 != sizeof(iv_fill_mem_rec_op_t)))
299 {
300 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
301 << IVD_UNSUPPORTEDPARAM;
302 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
303 IVD_OP_API_STRUCT_SIZE_INCORRECT;
304 return (IV_FAIL);
305 }
306
307 if(max_wd < H264_MIN_FRAME_WIDTH)
308 {
309 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
310 << IVD_UNSUPPORTEDPARAM;
311 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
312 IVD_REQUESTED_WIDTH_NOT_SUPPPORTED;
313 return (IV_FAIL);
314 }
315
316 if(max_wd > H264_MAX_FRAME_WIDTH)
317 {
318 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
319 << IVD_UNSUPPORTEDPARAM;
320 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
321 IVD_REQUESTED_WIDTH_NOT_SUPPPORTED;
322 return (IV_FAIL);
323 }
324
325 if(max_ht < H264_MIN_FRAME_HEIGHT)
326 {
327 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
328 << IVD_UNSUPPORTEDPARAM;
329 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
330 IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED;
331 return (IV_FAIL);
332 }
333
334 if((max_ht * max_wd)
335 > (H264_MAX_FRAME_HEIGHT * H264_MAX_FRAME_WIDTH))
336
337 {
338 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
339 << IVD_UNSUPPORTEDPARAM;
340 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
341 IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED;
342 return (IV_FAIL);
343 }
344
345 if(NULL == ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location)
346 {
347 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
348 << IVD_UNSUPPORTEDPARAM;
349 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
350 IVD_NUM_REC_NOT_SUFFICIENT;
351 return (IV_FAIL);
352 }
353
354 /* check memrecords sizes are correct */
355 ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location;
356 for(i = 0; i < MEM_REC_CNT; i++)
357 {
358 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
359 {
360 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
361 << IVD_UNSUPPORTEDPARAM;
362 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
363 IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
364 return IV_FAIL;
365 }
366 }
367 }
368 break;
369
370 case IV_CMD_INIT:
371 {
372 ih264d_init_ip_t *ps_ip = (ih264d_init_ip_t *)pv_api_ip;
373 ih264d_init_op_t *ps_op = (ih264d_init_op_t *)pv_api_op;
374 iv_mem_rec_t *ps_mem_rec;
375 WORD32 max_wd = ps_ip->s_ivd_init_ip_t.u4_frm_max_wd;
376 WORD32 max_ht = ps_ip->s_ivd_init_ip_t.u4_frm_max_ht;
377
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]378 max_wd = ALIGN16(max_wd);
379 max_ht = ALIGN32(max_ht);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]380
381 ps_op->s_ivd_init_op_t.u4_error_code = 0;
382
383 if((ps_ip->s_ivd_init_ip_t.u4_size > sizeof(ih264d_init_ip_t))
384 || (ps_ip->s_ivd_init_ip_t.u4_size
385 < sizeof(ivd_init_ip_t)))
386 {
387 ps_op->s_ivd_init_op_t.u4_error_code |= 1
388 << IVD_UNSUPPORTEDPARAM;
389 ps_op->s_ivd_init_op_t.u4_error_code |=
390 IVD_IP_API_STRUCT_SIZE_INCORRECT;
391 H264_DEC_DEBUG_PRINT("\n");
392 return (IV_FAIL);
393 }
394
395 if((ps_op->s_ivd_init_op_t.u4_size != sizeof(ih264d_init_op_t))
396 && (ps_op->s_ivd_init_op_t.u4_size
397 != sizeof(ivd_init_op_t)))
398 {
399 ps_op->s_ivd_init_op_t.u4_error_code |= 1
400 << IVD_UNSUPPORTEDPARAM;
401 ps_op->s_ivd_init_op_t.u4_error_code |=
402 IVD_OP_API_STRUCT_SIZE_INCORRECT;
403 H264_DEC_DEBUG_PRINT("\n");
404 return (IV_FAIL);
405 }
406
407 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec != MEM_REC_CNT)
408 {
409 ps_op->s_ivd_init_op_t.u4_error_code |= 1
410 << IVD_UNSUPPORTEDPARAM;
411 ps_op->s_ivd_init_op_t.u4_error_code |=
412 IVD_INIT_DEC_NOT_SUFFICIENT;
413 H264_DEC_DEBUG_PRINT("\n");
414 return (IV_FAIL);
415 }
416
417 if(max_wd < H264_MIN_FRAME_WIDTH)
418 {
419 ps_op->s_ivd_init_op_t.u4_error_code |= 1
420 << IVD_UNSUPPORTEDPARAM;
421 ps_op->s_ivd_init_op_t.u4_error_code |=
422 IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED;
423 H264_DEC_DEBUG_PRINT("\n");
424 return (IV_FAIL);
425 }
426
427 if(max_wd > H264_MAX_FRAME_WIDTH)
428 {
429 ps_op->s_ivd_init_op_t.u4_error_code |= 1
430 << IVD_UNSUPPORTEDPARAM;
431 ps_op->s_ivd_init_op_t.u4_error_code |=
432 IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED;
433 H264_DEC_DEBUG_PRINT("\n");
434 return (IV_FAIL);
435 }
436
437 if(max_ht < H264_MIN_FRAME_HEIGHT)
438 {
439 ps_op->s_ivd_init_op_t.u4_error_code |= 1
440 << IVD_UNSUPPORTEDPARAM;
441 ps_op->s_ivd_init_op_t.u4_error_code |=
442 IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED;
443 H264_DEC_DEBUG_PRINT("\n");
444 return (IV_FAIL);
445 }
446
447 if((max_ht * max_wd)
448 > (H264_MAX_FRAME_HEIGHT * H264_MAX_FRAME_WIDTH))
449
450 {
451 ps_op->s_ivd_init_op_t.u4_error_code |= 1
452 << IVD_UNSUPPORTEDPARAM;
453 ps_op->s_ivd_init_op_t.u4_error_code |=
454 IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED;
455 H264_DEC_DEBUG_PRINT("\n");
456 return (IV_FAIL);
457 }
458
459 if(NULL == ps_ip->s_ivd_init_ip_t.pv_mem_rec_location)
460 {
461 ps_op->s_ivd_init_op_t.u4_error_code |= 1
462 << IVD_UNSUPPORTEDPARAM;
463 ps_op->s_ivd_init_op_t.u4_error_code |=
464 IVD_NUM_REC_NOT_SUFFICIENT;
465 H264_DEC_DEBUG_PRINT("\n");
466 return (IV_FAIL);
467 }
468
469 if((ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420P)
470 && (ps_ip->s_ivd_init_ip_t.e_output_format
471 != IV_YUV_422ILE)
472 && (ps_ip->s_ivd_init_ip_t.e_output_format
473 != IV_RGB_565)
474 && (ps_ip->s_ivd_init_ip_t.e_output_format
475 != IV_YUV_420SP_UV)
476 && (ps_ip->s_ivd_init_ip_t.e_output_format
477 != IV_YUV_420SP_VU))
478 {
479 ps_op->s_ivd_init_op_t.u4_error_code |= 1
480 << IVD_UNSUPPORTEDPARAM;
481 ps_op->s_ivd_init_op_t.u4_error_code |=
482 IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
483 H264_DEC_DEBUG_PRINT("\n");
484 return (IV_FAIL);
485 }
486
487 /* verify number of mem records */
488 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec < MEM_REC_CNT)
489 {
490 ps_op->s_ivd_init_op_t.u4_error_code |= 1
491 << IVD_UNSUPPORTEDPARAM;
492 ps_op->s_ivd_init_op_t.u4_error_code |=
493 IVD_INIT_DEC_MEM_REC_NOT_SUFFICIENT;
494 H264_DEC_DEBUG_PRINT("\n");
495 return IV_FAIL;
496 }
497
498 ps_mem_rec = ps_ip->s_ivd_init_ip_t.pv_mem_rec_location;
499 /* check memrecords sizes are correct */
500 for(i = 0; i < ps_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++)
501 {
502 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
503 {
504 ps_op->s_ivd_init_op_t.u4_error_code |= 1
505 << IVD_UNSUPPORTEDPARAM;
506 ps_op->s_ivd_init_op_t.u4_error_code |=
507 IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
508 H264_DEC_DEBUG_PRINT("i: %d\n", i);
509 return IV_FAIL;
510 }
511 /* check memrecords pointers are not NULL */
512
513 if(ps_mem_rec[i].pv_base == NULL)
514 {
515
516 ps_op->s_ivd_init_op_t.u4_error_code |= 1
517 << IVD_UNSUPPORTEDPARAM;
518 ps_op->s_ivd_init_op_t.u4_error_code |=
519 IVD_INIT_DEC_MEM_REC_BASE_NULL;
520 H264_DEC_DEBUG_PRINT("i: %d\n", i);
521 return IV_FAIL;
522
523 }
524
525 }
526
527 /* verify memtabs for overlapping regions */
528 {
529 void *start[MEM_REC_CNT];
530 void *end[MEM_REC_CNT];
531
532 start[0] = (void *)(ps_mem_rec[0].pv_base);
533 end[0] = (void *)((UWORD8 *)ps_mem_rec[0].pv_base
534 + ps_mem_rec[0].u4_mem_size - 1);
535 for(i = 1; i < MEM_REC_CNT; i++)
536 {
537 /* This array is populated to check memtab overlapp */
538 start[i] = (void *)(ps_mem_rec[i].pv_base);
539 end[i] = (void *)((UWORD8 *)ps_mem_rec[i].pv_base
540 + ps_mem_rec[i].u4_mem_size - 1);
541
542 for(j = 0; j < i; j++)
543 {
544 if((start[i] >= start[j]) && (start[i] <= end[j]))
545 {
546 ps_op->s_ivd_init_op_t.u4_error_code |= 1
547 << IVD_UNSUPPORTEDPARAM;
548 ps_op->s_ivd_init_op_t.u4_error_code |=
549 IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
550 H264_DEC_DEBUG_PRINT("i: %d, j: %d\n", i, j);
551 return IV_FAIL;
552 }
553
554 if((end[i] >= start[j]) && (end[i] <= end[j]))
555 {
556 ps_op->s_ivd_init_op_t.u4_error_code |= 1
557 << IVD_UNSUPPORTEDPARAM;
558 ps_op->s_ivd_init_op_t.u4_error_code |=
559 IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
560 H264_DEC_DEBUG_PRINT("i: %d, j: %d\n", i, j);
561 return IV_FAIL;
562 }
563
564 if((start[i] < start[j]) && (end[i] > end[j]))
565 {
566 ps_op->s_ivd_init_op_t.u4_error_code |= 1
567 << IVD_UNSUPPORTEDPARAM;
568 ps_op->s_ivd_init_op_t.u4_error_code |=
569 IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
570 H264_DEC_DEBUG_PRINT("i: %d, j: %d\n", i, j);
571 return IV_FAIL;
572 }
573 }
574
575 }
576 }
577
578 {
579 iv_mem_rec_t mem_rec_ittiam_api[MEM_REC_CNT];
580 ih264d_fill_mem_rec_ip_t s_fill_mem_rec_ip;
581 ih264d_fill_mem_rec_op_t s_fill_mem_rec_op;
582 IV_API_CALL_STATUS_T e_status;
583
584 UWORD32 i;
585 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.e_cmd =
586 IV_CMD_FILL_NUM_MEM_REC;
587 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location =
588 mem_rec_ittiam_api;
589 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd =
590 max_wd;
591 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht =
592 max_ht;
593
594 if(ps_ip->s_ivd_init_ip_t.u4_size
595 > offsetof(ih264d_init_ip_t, i4_level))
596 {
597 s_fill_mem_rec_ip.i4_level = ps_ip->i4_level;
598 }
599 else
600 {
601 s_fill_mem_rec_ip.i4_level = H264_LEVEL_3_1;
602 }
603
604 if(ps_ip->s_ivd_init_ip_t.u4_size
605 > offsetof(ih264d_init_ip_t, u4_num_ref_frames))
606 {
607 s_fill_mem_rec_ip.u4_num_ref_frames =
608 ps_ip->u4_num_ref_frames;
609 }
610 else
611 {
612 s_fill_mem_rec_ip.u4_num_ref_frames =
613 (H264_MAX_REF_PICS + 1);
614 }
615
616 if(ps_ip->s_ivd_init_ip_t.u4_size
617 > offsetof(ih264d_init_ip_t,
618 u4_num_reorder_frames))
619 {
620 s_fill_mem_rec_ip.u4_num_reorder_frames =
621 ps_ip->u4_num_reorder_frames;
622 }
623 else
624 {
625 s_fill_mem_rec_ip.u4_num_reorder_frames = (H264_MAX_REF_PICS
626 + 1);
627 }
628
629 if(ps_ip->s_ivd_init_ip_t.u4_size
630 > offsetof(ih264d_init_ip_t,
631 u4_num_extra_disp_buf))
632 {
633 s_fill_mem_rec_ip.u4_num_extra_disp_buf =
634 ps_ip->u4_num_extra_disp_buf;
635 }
636 else
637 {
638 s_fill_mem_rec_ip.u4_num_extra_disp_buf = 0;
639 }
640
641 if(ps_ip->s_ivd_init_ip_t.u4_size
642 > offsetof(ih264d_init_ip_t, u4_share_disp_buf))
643 {
644#ifndef LOGO_EN
645 s_fill_mem_rec_ip.u4_share_disp_buf =
646 ps_ip->u4_share_disp_buf;
647#else
648 s_fill_mem_rec_ip.u4_share_disp_buf = 0;
649#endif
650 }
651 else
652 {
653 s_fill_mem_rec_ip.u4_share_disp_buf = 0;
654 }
655
656 s_fill_mem_rec_ip.e_output_format =
657 ps_ip->s_ivd_init_ip_t.e_output_format;
658
659 if((s_fill_mem_rec_ip.e_output_format != IV_YUV_420P)
660 && (s_fill_mem_rec_ip.e_output_format
661 != IV_YUV_420SP_UV)
662 && (s_fill_mem_rec_ip.e_output_format
663 != IV_YUV_420SP_VU))
664 {
665 s_fill_mem_rec_ip.u4_share_disp_buf = 0;
666 }
667
668 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_size =
669 sizeof(ih264d_fill_mem_rec_ip_t);
670 s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_size =
671 sizeof(ih264d_fill_mem_rec_op_t);
672
673 for(i = 0; i < MEM_REC_CNT; i++)
674 mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t);
675
676 e_status = ih264d_api_function(NULL,
677 (void *)&s_fill_mem_rec_ip,
678 (void *)&s_fill_mem_rec_op);
679 if(IV_FAIL == e_status)
680 {
681 ps_op->s_ivd_init_op_t.u4_error_code =
682 s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_error_code;
683 H264_DEC_DEBUG_PRINT("Fail\n");
684 return (IV_FAIL);
685 }
686
687 for(i = 0; i < MEM_REC_CNT; i++)
688 {
689 if(ps_mem_rec[i].u4_mem_size
690 < mem_rec_ittiam_api[i].u4_mem_size)
691 {
692 ps_op->s_ivd_init_op_t.u4_error_code |= 1
693 << IVD_UNSUPPORTEDPARAM;
694 ps_op->s_ivd_init_op_t.u4_error_code |=
695 IVD_INIT_DEC_MEM_REC_INSUFFICIENT_SIZE;
696 H264_DEC_DEBUG_PRINT("i: %d \n", i);
697 return IV_FAIL;
698 }
699 if(ps_mem_rec[i].u4_mem_alignment
700 != mem_rec_ittiam_api[i].u4_mem_alignment)
701 {
702 ps_op->s_ivd_init_op_t.u4_error_code |= 1
703 << IVD_UNSUPPORTEDPARAM;
704 ps_op->s_ivd_init_op_t.u4_error_code |=
705 IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR;
706 H264_DEC_DEBUG_PRINT("i: %d \n", i);
707 return IV_FAIL;
708 }
709 if(ps_mem_rec[i].e_mem_type
710 != mem_rec_ittiam_api[i].e_mem_type)
711 {
712 UWORD32 check = IV_SUCCESS;
713 UWORD32 diff = mem_rec_ittiam_api[i].e_mem_type
714 - ps_mem_rec[i].e_mem_type;
715
716 if((ps_mem_rec[i].e_mem_type
717 <= IV_EXTERNAL_CACHEABLE_SCRATCH_MEM)
718 && (mem_rec_ittiam_api[i].e_mem_type
719 >= IV_INTERNAL_NONCACHEABLE_PERSISTENT_MEM))
720 {
721 check = IV_FAIL;
722 }
723 if(3 != MOD(mem_rec_ittiam_api[i].e_mem_type, 4))
724 {
725 /*
726 * It is not IV_EXTERNAL_NONCACHEABLE_PERSISTENT_MEM or IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM
727 */
728 if((diff < 1) || (diff > 3))
729 {
730 // Difference between 1 and 3 is okay for all cases other than the two filtered
731 // with the MOD condition above
732 check = IV_FAIL;
733 }
734 }
735 else
736 {
737 if(diff == 1)
738 {
739 /*
740 * This particular case is when codec asked for External Persistent, but got
741 * Internal Scratch.
742 */
743 check = IV_FAIL;
744 }
745 if((diff != 2) && (diff != 3))
746 {
747 check = IV_FAIL;
748 }
749 }
750 if(check == IV_FAIL)
751 {
752 ps_op->s_ivd_init_op_t.u4_error_code |= 1
753 << IVD_UNSUPPORTEDPARAM;
754 ps_op->s_ivd_init_op_t.u4_error_code |=
755 IVD_INIT_DEC_MEM_REC_INCORRECT_TYPE;
756 H264_DEC_DEBUG_PRINT("i: %d \n", i);
757 return IV_FAIL;
758 }
759 }
760 }
761 }
762
763 }
764 break;
765
766 case IVD_CMD_GET_DISPLAY_FRAME:
767 {
768 ih264d_get_display_frame_ip_t *ps_ip =
769 (ih264d_get_display_frame_ip_t *)pv_api_ip;
770 ih264d_get_display_frame_op_t *ps_op =
771 (ih264d_get_display_frame_op_t *)pv_api_op;
772
773 ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0;
774
775 if((ps_ip->s_ivd_get_display_frame_ip_t.u4_size
776 != sizeof(ih264d_get_display_frame_ip_t))
777 && (ps_ip->s_ivd_get_display_frame_ip_t.u4_size
778 != sizeof(ivd_get_display_frame_ip_t)))
779 {
780 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1
781 << IVD_UNSUPPORTEDPARAM;
782 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |=
783 IVD_IP_API_STRUCT_SIZE_INCORRECT;
784 return (IV_FAIL);
785 }
786
787 if((ps_op->s_ivd_get_display_frame_op_t.u4_size
788 != sizeof(ih264d_get_display_frame_op_t))
789 && (ps_op->s_ivd_get_display_frame_op_t.u4_size
790 != sizeof(ivd_get_display_frame_op_t)))
791 {
792 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1
793 << IVD_UNSUPPORTEDPARAM;
794 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |=
795 IVD_OP_API_STRUCT_SIZE_INCORRECT;
796 return (IV_FAIL);
797 }
798 }
799 break;
800
801 case IVD_CMD_REL_DISPLAY_FRAME:
802 {
803 ih264d_rel_display_frame_ip_t *ps_ip =
804 (ih264d_rel_display_frame_ip_t *)pv_api_ip;
805 ih264d_rel_display_frame_op_t *ps_op =
806 (ih264d_rel_display_frame_op_t *)pv_api_op;
807
808 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0;
809
810 if((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size
811 != sizeof(ih264d_rel_display_frame_ip_t))
812 && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size
813 != sizeof(ivd_rel_display_frame_ip_t)))
814 {
815 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1
816 << IVD_UNSUPPORTEDPARAM;
817 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |=
818 IVD_IP_API_STRUCT_SIZE_INCORRECT;
819 return (IV_FAIL);
820 }
821
822 if((ps_op->s_ivd_rel_display_frame_op_t.u4_size
823 != sizeof(ih264d_rel_display_frame_op_t))
824 && (ps_op->s_ivd_rel_display_frame_op_t.u4_size
825 != sizeof(ivd_rel_display_frame_op_t)))
826 {
827 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1
828 << IVD_UNSUPPORTEDPARAM;
829 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |=
830 IVD_OP_API_STRUCT_SIZE_INCORRECT;
831 return (IV_FAIL);
832 }
833
834 }
835 break;
836
837 case IVD_CMD_SET_DISPLAY_FRAME:
838 {
839 ih264d_set_display_frame_ip_t *ps_ip =
840 (ih264d_set_display_frame_ip_t *)pv_api_ip;
841 ih264d_set_display_frame_op_t *ps_op =
842 (ih264d_set_display_frame_op_t *)pv_api_op;
843 UWORD32 j;
844
845 ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0;
846
847 if((ps_ip->s_ivd_set_display_frame_ip_t.u4_size
848 != sizeof(ih264d_set_display_frame_ip_t))
849 && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size
850 != sizeof(ivd_set_display_frame_ip_t)))
851 {
852 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
853 << IVD_UNSUPPORTEDPARAM;
854 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
855 IVD_IP_API_STRUCT_SIZE_INCORRECT;
856 return (IV_FAIL);
857 }
858
859 if((ps_op->s_ivd_set_display_frame_op_t.u4_size
860 != sizeof(ih264d_set_display_frame_op_t))
861 && (ps_op->s_ivd_set_display_frame_op_t.u4_size
862 != sizeof(ivd_set_display_frame_op_t)))
863 {
864 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
865 << IVD_UNSUPPORTEDPARAM;
866 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
867 IVD_OP_API_STRUCT_SIZE_INCORRECT;
868 return (IV_FAIL);
869 }
870
871 if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0)
872 {
873 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
874 << IVD_UNSUPPORTEDPARAM;
875 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
876 IVD_DISP_FRM_ZERO_OP_BUFS;
877 return IV_FAIL;
878 }
879
880 for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs;
881 j++)
882 {
883 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs
884 == 0)
885 {
886 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
887 << IVD_UNSUPPORTEDPARAM;
888 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
889 IVD_DISP_FRM_ZERO_OP_BUFS;
890 return IV_FAIL;
891 }
892
893 for(i = 0;
894 i
895 < ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs;
896 i++)
897 {
898 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i]
899 == NULL)
900 {
901 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
902 << IVD_UNSUPPORTEDPARAM;
903 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
904 IVD_DISP_FRM_OP_BUF_NULL;
905 return IV_FAIL;
906 }
907
908 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i]
909 == 0)
910 {
911 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
912 << IVD_UNSUPPORTEDPARAM;
913 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
914 IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
915 return IV_FAIL;
916 }
917 }
918 }
919 }
920 break;
921
922 case IVD_CMD_VIDEO_DECODE:
923 {
924 ih264d_video_decode_ip_t *ps_ip =
925 (ih264d_video_decode_ip_t *)pv_api_ip;
926 ih264d_video_decode_op_t *ps_op =
927 (ih264d_video_decode_op_t *)pv_api_op;
928
929 H264_DEC_DEBUG_PRINT("The input bytes is: %d",
930 ps_ip->s_ivd_video_decode_ip_t.u4_num_Bytes);
931 ps_op->s_ivd_video_decode_op_t.u4_error_code = 0;
932
933 if(ps_ip->s_ivd_video_decode_ip_t.u4_size
934 != sizeof(ih264d_video_decode_ip_t)&&
935 ps_ip->s_ivd_video_decode_ip_t.u4_size != offsetof(ivd_video_decode_ip_t, s_out_buffer))
936 {
937 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
938 << IVD_UNSUPPORTEDPARAM;
939 ps_op->s_ivd_video_decode_op_t.u4_error_code |=
940 IVD_IP_API_STRUCT_SIZE_INCORRECT;
941 return (IV_FAIL);
942 }
943
944 if(ps_op->s_ivd_video_decode_op_t.u4_size
945 != sizeof(ih264d_video_decode_op_t)&&
946 ps_op->s_ivd_video_decode_op_t.u4_size != offsetof(ivd_video_decode_op_t, u4_output_present))
947 {
948 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
949 << IVD_UNSUPPORTEDPARAM;
950 ps_op->s_ivd_video_decode_op_t.u4_error_code |=
951 IVD_OP_API_STRUCT_SIZE_INCORRECT;
952 return (IV_FAIL);
953 }
954
955 }
956 break;
957
958 case IV_CMD_RETRIEVE_MEMREC:
959 {
960 ih264d_retrieve_mem_rec_ip_t *ps_ip =
961 (ih264d_retrieve_mem_rec_ip_t *)pv_api_ip;
962 ih264d_retrieve_mem_rec_op_t *ps_op =
963 (ih264d_retrieve_mem_rec_op_t *)pv_api_op;
964 iv_mem_rec_t *ps_mem_rec;
965
966 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = 0;
967
968 if(ps_ip->s_ivd_retrieve_mem_rec_ip_t.u4_size
969 != sizeof(ih264d_retrieve_mem_rec_ip_t))
970 {
971 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1
972 << IVD_UNSUPPORTEDPARAM;
973 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |=
974 IVD_IP_API_STRUCT_SIZE_INCORRECT;
975 return (IV_FAIL);
976 }
977
978 if(ps_op->s_ivd_retrieve_mem_rec_op_t.u4_size
979 != sizeof(ih264d_retrieve_mem_rec_op_t))
980 {
981 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1
982 << IVD_UNSUPPORTEDPARAM;
983 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |=
984 IVD_OP_API_STRUCT_SIZE_INCORRECT;
985 return (IV_FAIL);
986 }
987
988 ps_mem_rec = ps_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location;
989 /* check memrecords sizes are correct */
990 for(i = 0; i < MEM_REC_CNT; i++)
991 {
992 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
993 {
994 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1
995 << IVD_UNSUPPORTEDPARAM;
996 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |=
997 IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
998 return IV_FAIL;
999 }
1000 }
1001 }
1002 break;
1003
1004 case IVD_CMD_VIDEO_CTL:
1005 {
1006 UWORD32 *pu4_ptr_cmd;
1007 UWORD32 sub_command;
1008
1009 pu4_ptr_cmd = (UWORD32 *)pv_api_ip;
1010 pu4_ptr_cmd += 2;
1011 sub_command = *pu4_ptr_cmd;
1012
1013 switch(sub_command)
1014 {
1015 case IVD_CMD_CTL_SETPARAMS:
1016 {
1017 ih264d_ctl_set_config_ip_t *ps_ip;
1018 ih264d_ctl_set_config_op_t *ps_op;
1019 ps_ip = (ih264d_ctl_set_config_ip_t *)pv_api_ip;
1020 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op;
1021
1022 if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size
1023 != sizeof(ih264d_ctl_set_config_ip_t))
1024 {
1025 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1
1026 << IVD_UNSUPPORTEDPARAM;
1027 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |=
1028 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1029 return IV_FAIL;
1030 }
1031 }
1032 //no break; is needed here
1033 case IVD_CMD_CTL_SETDEFAULT:
1034 {
1035 ih264d_ctl_set_config_op_t *ps_op;
1036 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op;
1037 if(ps_op->s_ivd_ctl_set_config_op_t.u4_size
1038 != sizeof(ih264d_ctl_set_config_op_t))
1039 {
1040 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1
1041 << IVD_UNSUPPORTEDPARAM;
1042 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |=
1043 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1044 return IV_FAIL;
1045 }
1046 }
1047 break;
1048
1049 case IVD_CMD_CTL_GETPARAMS:
1050 {
1051 ih264d_ctl_getstatus_ip_t *ps_ip;
1052 ih264d_ctl_getstatus_op_t *ps_op;
1053
1054 ps_ip = (ih264d_ctl_getstatus_ip_t *)pv_api_ip;
1055 ps_op = (ih264d_ctl_getstatus_op_t *)pv_api_op;
1056 if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size
1057 != sizeof(ih264d_ctl_getstatus_ip_t))
1058 {
1059 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1
1060 << IVD_UNSUPPORTEDPARAM;
1061 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |=
1062 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1063 return IV_FAIL;
1064 }
1065 if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size
1066 != sizeof(ih264d_ctl_getstatus_op_t))
1067 {
1068 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1
1069 << IVD_UNSUPPORTEDPARAM;
1070 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |=
1071 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1072 return IV_FAIL;
1073 }
1074 }
1075 break;
1076
1077 case IVD_CMD_CTL_GETBUFINFO:
1078 {
1079 ih264d_ctl_getbufinfo_ip_t *ps_ip;
1080 ih264d_ctl_getbufinfo_op_t *ps_op;
1081 ps_ip = (ih264d_ctl_getbufinfo_ip_t *)pv_api_ip;
1082 ps_op = (ih264d_ctl_getbufinfo_op_t *)pv_api_op;
1083
1084 if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size
1085 != sizeof(ih264d_ctl_getbufinfo_ip_t))
1086 {
1087 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1
1088 << IVD_UNSUPPORTEDPARAM;
1089 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |=
1090 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1091 return IV_FAIL;
1092 }
1093 if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size
1094 != sizeof(ih264d_ctl_getbufinfo_op_t))
1095 {
1096 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1
1097 << IVD_UNSUPPORTEDPARAM;
1098 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |=
1099 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1100 return IV_FAIL;
1101 }
1102 }
1103 break;
1104
1105 case IVD_CMD_CTL_GETVERSION:
1106 {
1107 ih264d_ctl_getversioninfo_ip_t *ps_ip;
1108 ih264d_ctl_getversioninfo_op_t *ps_op;
1109 ps_ip = (ih264d_ctl_getversioninfo_ip_t *)pv_api_ip;
1110 ps_op = (ih264d_ctl_getversioninfo_op_t *)pv_api_op;
1111 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size
1112 != sizeof(ih264d_ctl_getversioninfo_ip_t))
1113 {
1114 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1
1115 << IVD_UNSUPPORTEDPARAM;
1116 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |=
1117 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1118 return IV_FAIL;
1119 }
1120 if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size
1121 != sizeof(ih264d_ctl_getversioninfo_op_t))
1122 {
1123 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1
1124 << IVD_UNSUPPORTEDPARAM;
1125 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |=
1126 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1127 return IV_FAIL;
1128 }
1129 }
1130 break;
1131
1132 case IVD_CMD_CTL_FLUSH:
1133 {
1134 ih264d_ctl_flush_ip_t *ps_ip;
1135 ih264d_ctl_flush_op_t *ps_op;
1136 ps_ip = (ih264d_ctl_flush_ip_t *)pv_api_ip;
1137 ps_op = (ih264d_ctl_flush_op_t *)pv_api_op;
1138 if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size
1139 != sizeof(ih264d_ctl_flush_ip_t))
1140 {
1141 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1
1142 << IVD_UNSUPPORTEDPARAM;
1143 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |=
1144 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1145 return IV_FAIL;
1146 }
1147 if(ps_op->s_ivd_ctl_flush_op_t.u4_size
1148 != sizeof(ih264d_ctl_flush_op_t))
1149 {
1150 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1
1151 << IVD_UNSUPPORTEDPARAM;
1152 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |=
1153 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1154 return IV_FAIL;
1155 }
1156 }
1157 break;
1158
1159 case IVD_CMD_CTL_RESET:
1160 {
1161 ih264d_ctl_reset_ip_t *ps_ip;
1162 ih264d_ctl_reset_op_t *ps_op;
1163 ps_ip = (ih264d_ctl_reset_ip_t *)pv_api_ip;
1164 ps_op = (ih264d_ctl_reset_op_t *)pv_api_op;
1165 if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size
1166 != sizeof(ih264d_ctl_reset_ip_t))
1167 {
1168 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1
1169 << IVD_UNSUPPORTEDPARAM;
1170 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |=
1171 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1172 return IV_FAIL;
1173 }
1174 if(ps_op->s_ivd_ctl_reset_op_t.u4_size
1175 != sizeof(ih264d_ctl_reset_op_t))
1176 {
1177 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1
1178 << IVD_UNSUPPORTEDPARAM;
1179 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |=
1180 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1181 return IV_FAIL;
1182 }
1183 }
1184 break;
1185
1186 case IH264D_CMD_CTL_DEGRADE:
1187 {
1188 ih264d_ctl_degrade_ip_t *ps_ip;
1189 ih264d_ctl_degrade_op_t *ps_op;
1190
1191 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip;
1192 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op;
1193
1194 if(ps_ip->u4_size != sizeof(ih264d_ctl_degrade_ip_t))
1195 {
1196 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1197 ps_op->u4_error_code |=
1198 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1199 return IV_FAIL;
1200 }
1201
1202 if(ps_op->u4_size != sizeof(ih264d_ctl_degrade_op_t))
1203 {
1204 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1205 ps_op->u4_error_code |=
1206 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1207 return IV_FAIL;
1208 }
1209
1210 if((ps_ip->i4_degrade_pics < 0)
1211 || (ps_ip->i4_degrade_pics > 4)
1212 || (ps_ip->i4_nondegrade_interval < 0)
1213 || (ps_ip->i4_degrade_type < 0)
1214 || (ps_ip->i4_degrade_type > 15))
1215 {
1216 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1217 return IV_FAIL;
1218 }
1219
1220 break;
1221 }
1222
1223 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS:
1224 {
1225 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip;
1226 ih264d_ctl_get_frame_dimensions_op_t *ps_op;
1227
1228 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
1229 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op;
1230
1231 if(ps_ip->u4_size
1232 != sizeof(ih264d_ctl_get_frame_dimensions_ip_t))
1233 {
1234 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1235 ps_op->u4_error_code |=
1236 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1237 return IV_FAIL;
1238 }
1239
1240 if(ps_op->u4_size
1241 != sizeof(ih264d_ctl_get_frame_dimensions_op_t))
1242 {
1243 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1244 ps_op->u4_error_code |=
1245 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1246 return IV_FAIL;
1247 }
1248
1249 break;
1250 }
1251
1252 case IH264D_CMD_CTL_SET_NUM_CORES:
1253 {
1254 ih264d_ctl_set_num_cores_ip_t *ps_ip;
1255 ih264d_ctl_set_num_cores_op_t *ps_op;
1256
1257 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip;
1258 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op;
1259
1260 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_num_cores_ip_t))
1261 {
1262 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1263 ps_op->u4_error_code |=
1264 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1265 return IV_FAIL;
1266 }
1267
1268 if(ps_op->u4_size != sizeof(ih264d_ctl_set_num_cores_op_t))
1269 {
1270 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1271 ps_op->u4_error_code |=
1272 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1273 return IV_FAIL;
1274 }
1275
1276 if((ps_ip->u4_num_cores != 1) && (ps_ip->u4_num_cores != 2)
1277 && (ps_ip->u4_num_cores != 3)
1278 && (ps_ip->u4_num_cores != 4))
1279 {
1280 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1281 return IV_FAIL;
1282 }
1283 break;
1284 }
1285 case IH264D_CMD_CTL_SET_PROCESSOR:
1286 {
1287 ih264d_ctl_set_processor_ip_t *ps_ip;
1288 ih264d_ctl_set_processor_op_t *ps_op;
1289
1290 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip;
1291 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op;
1292
1293 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_processor_ip_t))
1294 {
1295 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1296 ps_op->u4_error_code |=
1297 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1298 return IV_FAIL;
1299 }
1300
1301 if(ps_op->u4_size != sizeof(ih264d_ctl_set_processor_op_t))
1302 {
1303 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1304 ps_op->u4_error_code |=
1305 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1306 return IV_FAIL;
1307 }
1308
1309 break;
1310 }
1311 default:
1312 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
1313 *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD;
1314 return IV_FAIL;
1315 break;
1316 }
1317 }
1318 break;
1319 }
1320
1321 return IV_SUCCESS;
1322}
1323
1324
1325/**
1326 *******************************************************************************
1327 *
1328 * @brief
1329 * Sets Processor type
1330 *
1331 * @par Description:
1332 * Sets Processor type
1333 *
1334 * @param[in] ps_codec_obj
1335 * Pointer to codec object at API level
1336 *
1337 * @param[in] pv_api_ip
1338 * Pointer to input argument structure
1339 *
1340 * @param[out] pv_api_op
1341 * Pointer to output argument structure
1342 *
1343 * @returns Status
1344 *
1345 * @remarks
1346 *
1347 *
1348 *******************************************************************************
1349 */
1350
1351WORD32 ih264d_set_processor(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
1352{
1353 ih264d_ctl_set_processor_ip_t *ps_ip;
1354 ih264d_ctl_set_processor_op_t *ps_op;
1355 dec_struct_t *ps_codec = (dec_struct_t *)dec_hdl->pv_codec_handle;
1356
1357 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip;
1358 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op;
1359
1360 ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch;
1361 ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc;
1362
1363 ih264d_init_function_ptr(ps_codec);
1364
1365 ps_op->u4_error_code = 0;
1366 return IV_SUCCESS;
1367}
1368/*****************************************************************************/
1369/* */
1370/* Function Name : ih264d_get_num_rec */
1371/* */
1372/* Description : returns number of mem records required */
1373/* */
1374/* Inputs : pv_api_ip input api structure */
1375/* : pv_api_op output api structure */
1376/* Outputs : */
1377/* Outputs : */
1378/* Returns : void */
1379/* */
1380/* Issues : none */
1381/* */
1382/* Revision History: */
1383/* */
1384/* DD MM YYYY Author(s) Changes (Describe the changes made) */
1385/* 22 10 2008 100356 Draft */
1386/* */
1387/*****************************************************************************/
1388WORD32 ih264d_get_num_rec(void *pv_api_ip, void *pv_api_op)
1389{
1390 iv_num_mem_rec_ip_t *ps_mem_q_ip;
1391 iv_num_mem_rec_op_t *ps_mem_q_op;
1392 ps_mem_q_ip = (iv_num_mem_rec_ip_t *)pv_api_ip;
1393 ps_mem_q_op = (iv_num_mem_rec_op_t *)pv_api_op;
1394 UNUSED(ps_mem_q_ip);
1395 ps_mem_q_op->u4_num_mem_rec = MEM_REC_CNT;
1396
1397 return IV_SUCCESS;
1398
1399}
1400
1401
1402/**************************************************************************
1403 * \if Function name : ih264d_init_decoder \endif
1404 *
1405 *
1406 * \brief
1407 * Initializes the decoder
1408 *
1409 * \param apiVersion : Version of the api being used.
1410 * \param errorHandlingMechanism : Mechanism to be used for errror handling.
1411 * \param postFilteringType: Type of post filtering operation to be used.
1412 * \param uc_outputFormat: Format of the decoded picture [default 4:2:0].
1413 * \param uc_dispBufs: Number of Display Buffers.
1414 * \param p_NALBufAPI: Pointer to NAL Buffer API.
1415 * \param p_DispBufAPI: Pointer to Display Buffer API.
1416 * \param ih264d_dec_mem_manager :Pointer to the function that will be called by decoder
1417 * for memory allocation and freeing.
1418 *
1419 * \return
1420 * 0 on Success and -1 on error
1421 *
1422 **************************************************************************
1423 */
1424void ih264d_init_decoder(void * ps_dec_params)
1425{
1426 dec_struct_t * ps_dec = (dec_struct_t *)ps_dec_params;
1427 dec_slice_params_t *ps_cur_slice;
1428 pocstruct_t *ps_prev_poc, *ps_cur_poc;
Harish Mahendrakar43a1cf62016-05-11 15:26:19 +0530[diff] [blame]1429 WORD32 size;
1430
1431 size = sizeof(dec_err_status_t);
1432 memset(ps_dec->ps_dec_err_status, 0, size);
1433
1434 size = sizeof(sei);
1435 memset(ps_dec->ps_sei, 0, size);
1436
1437 size = sizeof(dpb_commands_t);
1438 memset(ps_dec->ps_dpb_cmds, 0, size);
1439
1440 size = sizeof(dec_bit_stream_t);
1441 memset(ps_dec->ps_bitstrm, 0, size);
1442
1443 size = sizeof(dec_slice_params_t);
1444 memset(ps_dec->ps_cur_slice, 0, size);
1445
1446 size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t));
1447 memset(ps_dec->pv_scratch_sps_pps, 0, size);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1448
1449
1450
1451 /* Set pic_parameter_set_id to -1 */
1452
1453
1454
1455 ps_cur_slice = ps_dec->ps_cur_slice;
1456 ps_dec->init_done = 0;
1457
1458 ps_dec->u4_num_cores = 1;
1459
1460 ps_dec->u2_pic_ht = ps_dec->u2_pic_wd = 0;
1461
1462 ps_dec->u1_separate_parse = DEFAULT_SEPARATE_PARSE;
1463 ps_dec->u4_app_disable_deblk_frm = 0;
1464 ps_dec->i4_degrade_type = 0;
1465 ps_dec->i4_degrade_pics = 0;
1466
1467 ps_dec->i4_app_skip_mode = IVD_SKIP_NONE;
1468 ps_dec->i4_dec_skip_mode = IVD_SKIP_NONE;
1469
1470 memset(ps_dec->ps_pps, 0,
1471 ((sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS));
1472 memset(ps_dec->ps_sps, 0,
1473 ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS));
1474
1475 /* Initialization of function pointers ih264d_deblock_picture function*/
1476
1477 ps_dec->p_DeblockPicture[0] = ih264d_deblock_picture_non_mbaff;
1478 ps_dec->p_DeblockPicture[1] = ih264d_deblock_picture_mbaff;
1479
1480 ps_dec->s_cab_dec_env.pv_codec_handle = ps_dec;
1481
1482 ps_dec->u4_num_fld_in_frm = 0;
1483
1484 ps_dec->ps_dpb_mgr->pv_codec_handle = ps_dec;
1485
1486 /* Initialize the sei validity u4_flag with zero indiacting sei is not valid*/
1487 ps_dec->ps_sei->u1_is_valid = 0;
1488
1489 /* decParams Initializations */
1490 ps_dec->ps_cur_pps = NULL;
1491 ps_dec->ps_cur_sps = NULL;
1492 ps_dec->u1_init_dec_flag = 0;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]1493 ps_dec->u1_first_slice_in_stream = 1;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1494 ps_dec->u1_last_pic_not_decoded = 0;
1495 ps_dec->u4_app_disp_width = 0;
1496 ps_dec->i4_header_decoded = 0;
1497 ps_dec->u4_total_frames_decoded = 0;
1498
1499 ps_dec->i4_error_code = 0;
1500 ps_dec->i4_content_type = -1;
1501 ps_dec->ps_cur_slice->u1_mbaff_frame_flag = 0;
1502
1503 ps_dec->ps_dec_err_status->u1_err_flag = ACCEPT_ALL_PICS; //REJECT_PB_PICS;
1504 ps_dec->ps_dec_err_status->u1_cur_pic_type = PIC_TYPE_UNKNOWN;
1505 ps_dec->ps_dec_err_status->u4_frm_sei_sync = SYNC_FRM_DEFAULT;
1506 ps_dec->ps_dec_err_status->u4_cur_frm = INIT_FRAME;
1507 ps_dec->ps_dec_err_status->u1_pic_aud_i = PIC_TYPE_UNKNOWN;
1508
1509 ps_dec->u1_pr_sl_type = 0xFF;
1510 ps_dec->u2_mbx = 0xffff;
1511 ps_dec->u2_mby = 0;
1512 ps_dec->u2_total_mbs_coded = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1513
1514 /* POC initializations */
1515 ps_prev_poc = &ps_dec->s_prev_pic_poc;
1516 ps_cur_poc = &ps_dec->s_cur_pic_poc;
1517 ps_prev_poc->i4_pic_order_cnt_lsb = ps_cur_poc->i4_pic_order_cnt_lsb = 0;
1518 ps_prev_poc->i4_pic_order_cnt_msb = ps_cur_poc->i4_pic_order_cnt_msb = 0;
1519 ps_prev_poc->i4_delta_pic_order_cnt_bottom =
1520 ps_cur_poc->i4_delta_pic_order_cnt_bottom = 0;
1521 ps_prev_poc->i4_delta_pic_order_cnt[0] =
1522 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0;
1523 ps_prev_poc->i4_delta_pic_order_cnt[1] =
1524 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0;
1525 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0;
1526 ps_prev_poc->i4_top_field_order_count = ps_cur_poc->i4_top_field_order_count =
1527 0;
1528 ps_prev_poc->i4_bottom_field_order_count =
1529 ps_cur_poc->i4_bottom_field_order_count = 0;
1530 ps_prev_poc->u1_bot_field = ps_cur_poc->u1_bot_field = 0;
1531 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0;
1532 ps_prev_poc->i4_prev_frame_num_ofst = ps_cur_poc->i4_prev_frame_num_ofst = 0;
1533 ps_cur_slice->u1_mmco_equalto5 = 0;
1534 ps_cur_slice->u2_frame_num = 0;
1535
1536 ps_dec->i4_max_poc = 0;
1537 ps_dec->i4_prev_max_display_seq = 0;
1538 ps_dec->u1_recon_mb_grp = 4;
1539
1540 /* Field PIC initializations */
1541 ps_dec->u1_second_field = 0;
1542 ps_dec->s_prev_seq_params.u1_eoseq_pending = 0;
1543
1544 /* Set the cropping parameters as zero */
1545 ps_dec->u2_crop_offset_y = 0;
1546 ps_dec->u2_crop_offset_uv = 0;
1547
1548 /* The Initial Frame Rate Info is not Present */
1549 ps_dec->i4_vui_frame_rate = -1;
1550 ps_dec->i4_pic_type = -1;
1551 ps_dec->i4_frametype = -1;
1552 ps_dec->i4_content_type = -1;
1553
1554 ps_dec->u1_res_changed = 0;
1555
1556
1557 ps_dec->u1_frame_decoded_flag = 0;
1558
1559 /* Set the default frame seek mask mode */
1560 ps_dec->u4_skip_frm_mask = SKIP_NONE;
1561
1562 /********************************************************/
1563 /* Initialize CAVLC residual decoding function pointers */
1564 /********************************************************/
1565 ps_dec->pf_cavlc_4x4res_block[0] = ih264d_cavlc_4x4res_block_totalcoeff_1;
1566 ps_dec->pf_cavlc_4x4res_block[1] =
1567 ih264d_cavlc_4x4res_block_totalcoeff_2to10;
1568 ps_dec->pf_cavlc_4x4res_block[2] =
1569 ih264d_cavlc_4x4res_block_totalcoeff_11to16;
1570
1571 ps_dec->pf_cavlc_parse4x4coeff[0] = ih264d_cavlc_parse4x4coeff_n0to7;
1572 ps_dec->pf_cavlc_parse4x4coeff[1] = ih264d_cavlc_parse4x4coeff_n8;
1573
1574 ps_dec->pf_cavlc_parse_8x8block[0] =
1575 ih264d_cavlc_parse_8x8block_none_available;
1576 ps_dec->pf_cavlc_parse_8x8block[1] =
1577 ih264d_cavlc_parse_8x8block_left_available;
1578 ps_dec->pf_cavlc_parse_8x8block[2] =
1579 ih264d_cavlc_parse_8x8block_top_available;
1580 ps_dec->pf_cavlc_parse_8x8block[3] =
1581 ih264d_cavlc_parse_8x8block_both_available;
1582
1583 /***************************************************************************/
1584 /* Initialize Bs calculation function pointers for P and B, 16x16/non16x16 */
1585 /***************************************************************************/
1586 ps_dec->pf_fill_bs1[0][0] = ih264d_fill_bs1_16x16mb_pslice;
1587 ps_dec->pf_fill_bs1[0][1] = ih264d_fill_bs1_non16x16mb_pslice;
1588
1589 ps_dec->pf_fill_bs1[1][0] = ih264d_fill_bs1_16x16mb_bslice;
1590 ps_dec->pf_fill_bs1[1][1] = ih264d_fill_bs1_non16x16mb_bslice;
1591
1592 ps_dec->pf_fill_bs_xtra_left_edge[0] =
1593 ih264d_fill_bs_xtra_left_edge_cur_frm;
1594 ps_dec->pf_fill_bs_xtra_left_edge[1] =
1595 ih264d_fill_bs_xtra_left_edge_cur_fld;
1596
1597 /* Initialize Reference Pic Buffers */
1598 ih264d_init_ref_bufs(ps_dec->ps_dpb_mgr);
1599
1600#if VERT_SCALE_UP_AND_422
1601 ps_dec->u1_vert_up_scale_flag = 1;
1602#else
1603 ps_dec->u1_vert_up_scale_flag = 0;
1604#endif
1605
1606 ps_dec->u2_prv_frame_num = 0;
1607 ps_dec->u1_top_bottom_decoded = 0;
1608 ps_dec->u1_dangling_field = 0;
1609
1610 ps_dec->s_cab_dec_env.cabac_table = gau4_ih264d_cabac_table;
1611
1612 ps_dec->pu1_left_mv_ctxt_inc = ps_dec->u1_left_mv_ctxt_inc_arr[0];
1613 ps_dec->pi1_left_ref_idx_ctxt_inc =
1614 &ps_dec->i1_left_ref_idx_ctx_inc_arr[0][0];
1615 ps_dec->pu1_left_yuv_dc_csbp = &ps_dec->u1_yuv_dc_csbp_topmb;
1616
1617 /* ! */
1618 /* Initializing flush frame u4_flag */
1619 ps_dec->u1_flushfrm = 0;
1620
1621 {
1622 ps_dec->s_cab_dec_env.pv_codec_handle = (void*)ps_dec;
1623 ps_dec->ps_bitstrm->pv_codec_handle = (void*)ps_dec;
1624 ps_dec->ps_cur_slice->pv_codec_handle = (void*)ps_dec;
1625 ps_dec->ps_dpb_mgr->pv_codec_handle = (void*)ps_dec;
1626 }
1627
1628 memset(ps_dec->disp_bufs, 0, (MAX_DISP_BUFS_NEW) * sizeof(disp_buf_t));
1629 memset(ps_dec->u4_disp_buf_mapping, 0,
1630 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
1631 memset(ps_dec->u4_disp_buf_to_be_freed, 0,
1632 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
Harish Mahendrakarcdfd7572016-05-24 13:11:51 -0700[diff] [blame]1633 memset(ps_dec->ps_cur_slice, 0, sizeof(dec_slice_params_t));
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1634
1635 ih264d_init_arch(ps_dec);
1636 ih264d_init_function_ptr(ps_dec);
1637
1638 ps_dec->init_done = 1;
1639 ps_dec->process_called = 1;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]1640
1641 ps_dec->pv_pic_buf_mgr = NULL;
1642 ps_dec->pv_mv_buf_mgr = NULL;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1643}
1644
1645/**************************************************************************
1646 * \if Function name : ih264d_init_video_decoder \endif
1647 *
1648 * \brief
1649 * Wrapper for the decoder init
1650 *
1651 * \param p_NALBufAPI: Pointer to NAL Buffer API.
1652 * \param ih264d_dec_mem_manager :Pointer to the function that will be called by decoder
1653 * for memory allocation and freeing.
1654 *
1655 * \return
1656 * pointer to the decparams
1657 *
1658 **************************************************************************
1659 */
1660
1661WORD32 ih264d_init_video_decoder(iv_obj_t *dec_hdl,
1662 ih264d_init_ip_t *ps_init_ip,
1663 ih264d_init_op_t *ps_init_op)
1664{
1665 dec_struct_t * ps_dec;
1666 iv_mem_rec_t *memtab;
1667 UWORD8 *pu1_extra_mem_base,*pu1_mem_base;
1668
1669 memtab = ps_init_ip->s_ivd_init_ip_t.pv_mem_rec_location;
1670
1671 dec_hdl->pv_codec_handle = memtab[MEM_REC_CODEC].pv_base;
1672 ps_dec = dec_hdl->pv_codec_handle;
1673
1674 memset(ps_dec, 0, sizeof(dec_struct_t));
1675
1676 if(ps_init_ip->s_ivd_init_ip_t.u4_size
1677 > offsetof(ih264d_init_ip_t, i4_level))
1678 {
1679 ps_dec->u4_level_at_init = ps_init_ip->i4_level;
1680 }
1681 else
1682 {
1683 ps_dec->u4_level_at_init = H264_LEVEL_3_1;
1684 }
1685
1686 if(ps_init_ip->s_ivd_init_ip_t.u4_size
1687 > offsetof(ih264d_init_ip_t, u4_num_ref_frames))
1688 {
1689 ps_dec->u4_num_ref_frames_at_init = ps_init_ip->u4_num_ref_frames;
1690 }
1691 else
1692 {
1693 ps_dec->u4_num_ref_frames_at_init = H264_MAX_REF_PICS;
1694 }
1695
1696 if(ps_init_ip->s_ivd_init_ip_t.u4_size
1697 > offsetof(ih264d_init_ip_t, u4_num_reorder_frames))
1698 {
1699 ps_dec->u4_num_reorder_frames_at_init =
1700 ps_init_ip->u4_num_reorder_frames;
1701 }
1702 else
1703 {
1704 ps_dec->u4_num_reorder_frames_at_init = H264_MAX_REF_PICS;
1705 }
1706
1707 if(ps_init_ip->s_ivd_init_ip_t.u4_size
1708 > offsetof(ih264d_init_ip_t, u4_num_extra_disp_buf))
1709 {
1710 ps_dec->u4_num_extra_disp_bufs_at_init =
1711 ps_init_ip->u4_num_extra_disp_buf;
1712 }
1713 else
1714 {
1715 ps_dec->u4_num_extra_disp_bufs_at_init = 0;
1716 }
1717
1718 if(ps_init_ip->s_ivd_init_ip_t.u4_size
1719 > offsetof(ih264d_init_ip_t, u4_share_disp_buf))
1720 {
1721#ifndef LOGO_EN
1722 ps_dec->u4_share_disp_buf = ps_init_ip->u4_share_disp_buf;
1723#else
1724 ps_dec->u4_share_disp_buf = 0;
1725#endif
1726 }
1727 else
1728 {
1729 ps_dec->u4_share_disp_buf = 0;
1730 }
1731
1732 if((ps_init_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420P)
1733 && (ps_init_ip->s_ivd_init_ip_t.e_output_format
1734 != IV_YUV_420SP_UV)
1735 && (ps_init_ip->s_ivd_init_ip_t.e_output_format
1736 != IV_YUV_420SP_VU))
1737 {
1738 ps_dec->u4_share_disp_buf = 0;
1739 }
1740
1741 if((ps_dec->u4_level_at_init < MIN_LEVEL_SUPPORTED)
1742 || (ps_dec->u4_level_at_init > MAX_LEVEL_SUPPORTED))
1743 {
1744 ps_init_op->s_ivd_init_op_t.u4_error_code |= ERROR_LEVEL_UNSUPPORTED;
1745 return (IV_FAIL);
1746 }
1747
1748 if(ps_dec->u4_num_ref_frames_at_init > H264_MAX_REF_PICS)
1749 {
1750 ps_init_op->s_ivd_init_op_t.u4_error_code |= ERROR_NUM_REF;
1751 ps_dec->u4_num_ref_frames_at_init = H264_MAX_REF_PICS;
1752 }
1753
1754 if(ps_dec->u4_num_reorder_frames_at_init > H264_MAX_REF_PICS)
1755 {
1756 ps_init_op->s_ivd_init_op_t.u4_error_code |= ERROR_NUM_REF;
1757 ps_dec->u4_num_reorder_frames_at_init = H264_MAX_REF_PICS;
1758 }
1759
1760 if(ps_dec->u4_num_extra_disp_bufs_at_init > H264_MAX_REF_PICS)
1761 {
1762 ps_init_op->s_ivd_init_op_t.u4_error_code |= ERROR_NUM_REF;
1763 ps_dec->u4_num_extra_disp_bufs_at_init = 0;
1764 }
1765
1766 if(0 == ps_dec->u4_share_disp_buf)
1767 ps_dec->u4_num_extra_disp_bufs_at_init = 0;
1768
1769 ps_dec->u4_num_disp_bufs_requested = 1;
1770
1771 ps_dec->u4_width_at_init = ps_init_ip->s_ivd_init_ip_t.u4_frm_max_wd;
1772 ps_dec->u4_height_at_init = ps_init_ip->s_ivd_init_ip_t.u4_frm_max_ht;
1773
1774 ps_dec->u4_width_at_init = ALIGN16(ps_dec->u4_width_at_init);
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]1775 ps_dec->u4_height_at_init = ALIGN32(ps_dec->u4_height_at_init);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1776
1777 ps_dec->pv_dec_thread_handle = memtab[MEM_REC_THREAD_HANDLE].pv_base;
1778
1779 pu1_mem_base = memtab[MEM_REC_THREAD_HANDLE].pv_base;
1780 ps_dec->pv_bs_deblk_thread_handle = pu1_mem_base
1781 + ithread_get_handle_size();
1782
1783 ps_dec->u4_extra_mem_used = 0;
1784
1785 pu1_extra_mem_base = memtab[MEM_REC_EXTRA_MEM].pv_base;
1786
1787 ps_dec->ps_dec_err_status = (dec_err_status_t *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used);
1788 ps_dec->u4_extra_mem_used += (((sizeof(dec_err_status_t) + 127) >> 7) << 7);
1789
1790 ps_dec->ps_mem_tab = memtab[MEM_REC_BACKUP].pv_base;
1791
1792 memcpy(ps_dec->ps_mem_tab, memtab, sizeof(iv_mem_rec_t) * MEM_REC_CNT);
1793
1794 ps_dec->ps_pps = memtab[MEM_REC_PPS].pv_base;
1795
1796 ps_dec->ps_sps = memtab[MEM_REC_SPS].pv_base;
1797
1798 ps_dec->ps_sei = (sei *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used);
1799 ps_dec->u4_extra_mem_used += sizeof(sei);
1800
1801 ps_dec->ps_dpb_mgr = memtab[MEM_REC_DPB_MGR].pv_base;
1802
1803 ps_dec->ps_dpb_cmds = (dpb_commands_t *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used);
1804 ps_dec->u4_extra_mem_used += sizeof(dpb_commands_t);
1805
1806 ps_dec->ps_bitstrm = (dec_bit_stream_t *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used);
1807 ps_dec->u4_extra_mem_used += sizeof(dec_bit_stream_t);
1808
1809 ps_dec->ps_cur_slice =(dec_slice_params_t *) (pu1_extra_mem_base + ps_dec->u4_extra_mem_used);
1810 ps_dec->u4_extra_mem_used += sizeof(dec_slice_params_t);
1811
1812 ps_dec->pv_scratch_sps_pps = (void *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used);
1813
1814
1815 ps_dec->u4_extra_mem_used += MAX(sizeof(dec_seq_params_t),
1816 sizeof(dec_pic_params_t));
1817 ps_dec->ps_pred_pkd = memtab[MEM_REC_PRED_INFO_PKD].pv_base;
1818
1819
1820 ps_dec->ps_dpb_mgr->pv_codec_handle = ps_dec;
1821
1822 ps_dec->pv_dec_out = (void *)ps_init_op;
1823 ps_dec->pv_dec_in = (void *)ps_init_ip;
1824
1825 ps_dec->u1_chroma_format =
1826 (UWORD8)(ps_init_ip->s_ivd_init_ip_t.e_output_format);
1827
1828
1829
1830 ih264d_init_decoder(ps_dec);
1831
1832 return (IV_SUCCESS);
1833
1834}
1835
1836
1837/*****************************************************************************/
1838/* */
1839/* Function Name : ih264d_fill_num_mem_rec */
1840/* */
1841/* Description : fills memory records */
1842/* */
1843/* Inputs : pv_api_ip input api structure */
1844/* : pv_api_op output api structure */
1845/* Outputs : */
1846/* Returns : void */
1847/* */
1848/* Issues : none */
1849/* */
1850/* Revision History: */
1851/* */
1852/* DD MM YYYY Author(s) Changes (Describe the changes made) */
1853/* 22 10 2008 100356 Draft */
1854/* */
1855/*****************************************************************************/
1856WORD32 ih264d_fill_num_mem_rec(void *pv_api_ip, void *pv_api_op)
1857{
1858
1859 ih264d_fill_mem_rec_ip_t *ps_mem_q_ip;
1860 ih264d_fill_mem_rec_op_t *ps_mem_q_op;
1861 WORD32 level;
1862 UWORD32 num_reorder_frames;
1863 UWORD32 num_ref_frames;
1864 UWORD32 num_extra_disp_bufs;
1865 UWORD32 u4_dpb_size_num_frames;
1866 iv_mem_rec_t *memTab;
1867
1868 UWORD32 chroma_format, u4_share_disp_buf;
1869 UWORD32 u4_total_num_mbs;
1870 UWORD32 luma_width, luma_width_in_mbs;
1871 UWORD32 luma_height, luma_height_in_mbs;
1872 UWORD32 max_dpb_size;
1873
1874 ps_mem_q_ip = (ih264d_fill_mem_rec_ip_t *)pv_api_ip;
1875 ps_mem_q_op = (ih264d_fill_mem_rec_op_t *)pv_api_op;
1876
1877 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size
1878 > offsetof(ih264d_fill_mem_rec_ip_t, i4_level))
1879 {
1880 level = ps_mem_q_ip->i4_level;
1881 }
1882 else
1883 {
1884 level = H264_LEVEL_3_1;
1885 }
1886
1887 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size
1888 > offsetof(ih264d_fill_mem_rec_ip_t, u4_num_reorder_frames))
1889 {
1890 num_reorder_frames = ps_mem_q_ip->u4_num_reorder_frames;
1891 }
1892 else
1893 {
1894 num_reorder_frames = H264_MAX_REF_PICS;
1895 }
1896
1897 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size
1898 > offsetof(ih264d_fill_mem_rec_ip_t, u4_num_ref_frames))
1899 {
1900 num_ref_frames = ps_mem_q_ip->u4_num_ref_frames;
1901 }
1902 else
1903 {
1904 num_ref_frames = H264_MAX_REF_PICS;
1905 }
1906
1907 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size
1908 > offsetof(ih264d_fill_mem_rec_ip_t, u4_num_extra_disp_buf))
1909 {
1910 num_extra_disp_bufs = ps_mem_q_ip->u4_num_extra_disp_buf;
1911 }
1912 else
1913 {
1914 num_extra_disp_bufs = 0;
1915 }
1916
1917 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size
1918 > offsetof(ih264d_fill_mem_rec_ip_t, u4_share_disp_buf))
1919 {
1920#ifndef LOGO_EN
1921 u4_share_disp_buf = ps_mem_q_ip->u4_share_disp_buf;
1922#else
1923 u4_share_disp_buf = 0;
1924#endif
1925 }
1926 else
1927 {
1928 u4_share_disp_buf = 0;
1929 }
1930
1931 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size
1932 > offsetof(ih264d_fill_mem_rec_ip_t, e_output_format))
1933 {
1934 chroma_format = ps_mem_q_ip->e_output_format;
1935 }
1936 else
1937 {
1938 chroma_format = -1;
1939 }
1940
1941 if((chroma_format != IV_YUV_420P) && (chroma_format != IV_YUV_420SP_UV)
1942 && (chroma_format != IV_YUV_420SP_VU))
1943 {
1944 u4_share_disp_buf = 0;
1945 }
1946 if(0 == u4_share_disp_buf)
1947 num_extra_disp_bufs = 0;
1948
1949 {
1950
1951 luma_height = ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht;
1952 luma_width = ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd;
1953
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]1954 luma_height = ALIGN32(luma_height);
1955 luma_width = ALIGN16(luma_width);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1956 luma_width_in_mbs = luma_width >> 4;
1957 luma_height_in_mbs = luma_height >> 4;
1958 u4_total_num_mbs = (luma_height * luma_width) >> 8;
1959 }
1960 /*
1961 * If level is lesser than 31 and the resolution required is higher,
1962 * then make the level at least 31.
1963 */
1964 if(u4_total_num_mbs > MAX_MBS_LEVEL_30 && level < H264_LEVEL_3_1)
1965 {
1966 level = H264_LEVEL_3_1;
1967 }
1968
1969 if((level < MIN_LEVEL_SUPPORTED) || (level > MAX_LEVEL_SUPPORTED))
1970 {
1971 ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
1972 ERROR_LEVEL_UNSUPPORTED;
1973 return (IV_FAIL);
1974 }
1975
1976 if(num_ref_frames > H264_MAX_REF_PICS)
1977 {
1978 ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= ERROR_NUM_REF;
1979 num_ref_frames = H264_MAX_REF_PICS;
1980 }
1981
1982 if(num_reorder_frames > H264_MAX_REF_PICS)
1983 {
1984 ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= ERROR_NUM_REF;
1985 num_reorder_frames = H264_MAX_REF_PICS;
1986 }
1987 memTab = ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location;
1988
1989 memTab[MEM_REC_IV_OBJ].u4_mem_size = sizeof(iv_obj_t);
1990 memTab[MEM_REC_IV_OBJ].u4_mem_alignment = (128 * 8) / CHAR_BIT;
1991 memTab[MEM_REC_IV_OBJ].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
1992 H264_DEC_DEBUG_PRINT("MEM_REC_IV_OBJ MEM Size = %d\n",
1993 memTab[MEM_REC_IV_OBJ].u4_mem_size);
1994
1995 memTab[MEM_REC_CODEC].u4_mem_alignment = (128 * 8) / CHAR_BIT;
1996 memTab[MEM_REC_CODEC].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
1997 memTab[MEM_REC_CODEC].u4_mem_size = sizeof(dec_struct_t);
1998
1999 {
2000 UWORD32 mvinfo_size, mv_info_size_pad;
2001 UWORD32 MVbank, MVbank_pad;
2002 UWORD32 Ysize;
2003 UWORD32 UVsize;
2004 UWORD32 one_frm_size;
2005
2006 UWORD32 extra_mem = 0;
2007
2008 UWORD32 pad_len_h, pad_len_v;
2009
2010 /*
2011 * For low_delay, use num_buf as 2 -
2012 * num_buf = (num_buf_ref) + 1;
2013 * where num_buf_ref is 1.
2014 */
2015 UWORD32 num_buf;
2016
2017 {
2018 UWORD32 num_bufs_app, num_bufs_level;
2019
2020 num_bufs_app = num_ref_frames + num_reorder_frames + 1;
2021
2022 if(num_bufs_app <= 1)
2023 num_bufs_app = 2;
2024
2025 num_bufs_level = ih264d_get_dpb_size_new(level, (luma_width >> 4),
2026 (luma_height >> 4));
2027
2028 max_dpb_size = num_bufs_level;
2029
2030 num_bufs_level = num_bufs_level * 2 + 1;
2031
2032 num_buf = MIN(num_bufs_level, num_bufs_app);
2033
2034 num_buf += num_extra_disp_bufs;
2035
2036 }
2037
2038 mvinfo_size = ((luma_width * (luma_height)) >> 4);
2039
2040 mv_info_size_pad = ((luma_width * (PAD_MV_BANK_ROW)) >> 4);
2041
2042 Ysize = ALIGN32((luma_width + (PAD_LEN_Y_H << 1)))
2043 * (luma_height + (PAD_LEN_Y_V << 2));
2044
2045
2046 UVsize = Ysize >> 2;
2047 if(u4_share_disp_buf == 1)
2048 {
2049 /* In case of buffers getting shared between application and library
2050 there is no need of reference memtabs. Instead of setting the i4_size
2051 to zero, it is reduced to a small i4_size to ensure that changes
2052 in the code are minimal */
2053
2054 if((chroma_format == IV_YUV_420P)
2055 || (chroma_format == IV_YUV_420SP_UV)
2056 || (chroma_format == IV_YUV_420SP_VU))
2057 {
2058 Ysize = 64;
2059 }
2060 if(chroma_format == IV_YUV_420SP_UV)
2061 {
2062 UVsize = 64;
2063 }
2064 }
2065
2066 one_frm_size = (((Ysize + 127) >> 7) << 7)
2067 + ((((UVsize << 1) + 127) >> 7) << 7);
2068
2069 //Note that for ARM RVDS WS the sizeof(mv_pred_t) is 16
2070
2071 /*Add memory for colocated MB*/
2072 MVbank = sizeof(mv_pred_t) * mvinfo_size;
2073 MVbank_pad = sizeof(mv_pred_t) * mv_info_size_pad;
2074
2075 MVbank = (((MVbank + 127) >> 7) << 7);
2076
2077 MVbank_pad = (((MVbank_pad + 127) >> 7) << 7);
2078
2079 memTab[MEM_REC_MVBANK].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2080 memTab[MEM_REC_MVBANK].e_mem_type =
2081 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2082 memTab[MEM_REC_MVBANK].u4_mem_size = (MVbank + MVbank_pad)
2083 * (MIN(max_dpb_size, num_ref_frames) + 1);
2084
2085
2086 memTab[MEM_REC_REF_PIC].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2087 memTab[MEM_REC_REF_PIC].e_mem_type =
2088 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2089 memTab[MEM_REC_REF_PIC].u4_mem_size = one_frm_size * num_buf;
2090
2091 }
2092
2093 memTab[MEM_REC_DEBLK_MB_INFO].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2094 memTab[MEM_REC_DEBLK_MB_INFO].e_mem_type =
2095 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2096 memTab[MEM_REC_DEBLK_MB_INFO].u4_mem_size = (((((u4_total_num_mbs
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2097 + (luma_width >> 4)) * sizeof(deblk_mb_t)) + 127) >> 7) << 7);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2098
2099 memTab[MEM_REC_NEIGHBOR_INFO].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2100 memTab[MEM_REC_NEIGHBOR_INFO].e_mem_type =
2101 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2102 memTab[MEM_REC_NEIGHBOR_INFO].u4_mem_size = sizeof(mb_neigbour_params_t)
2103 * ((luma_width + 16) >> 4) * 2 * 2;
2104 {
2105 WORD32 size;
2106 WORD32 num_entries;
2107
2108 num_entries = MIN(MAX_FRAMES, num_ref_frames);
2109 num_entries = 2 * ((2 * num_entries) + 1);
2110
2111 size = num_entries * sizeof(void *);
2112 size += PAD_MAP_IDX_POC * sizeof(void *);
2113 size *= u4_total_num_mbs;
2114 size += sizeof(dec_slice_struct_t) * u4_total_num_mbs;
2115 memTab[MEM_REC_SLICE_HDR].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2116 memTab[MEM_REC_SLICE_HDR].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2117 memTab[MEM_REC_SLICE_HDR].u4_mem_size = size;
2118 }
2119 {
2120
2121 UWORD32 u4_num_entries;
2122
2123 u4_num_entries = u4_total_num_mbs;
2124
2125 memTab[MEM_REC_MB_INFO].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2126 memTab[MEM_REC_MB_INFO].e_mem_type =
2127 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2128 memTab[MEM_REC_MB_INFO].u4_mem_size = sizeof(dec_mb_info_t)
2129 * u4_num_entries;
2130
2131 memTab[MEM_REC_PRED_INFO].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2132 memTab[MEM_REC_PRED_INFO].e_mem_type =
2133 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2134
2135 memTab[MEM_REC_PRED_INFO].u4_mem_size = sizeof(pred_info_t) * 2*32;
2136
2137 memTab[MEM_REC_COEFF_DATA].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2138 memTab[MEM_REC_COEFF_DATA].e_mem_type =
2139 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2140 memTab[MEM_REC_COEFF_DATA].u4_mem_size = MB_LUM_SIZE * sizeof(WORD16);
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2141 /*For I16x16 MBs, 16 4x4 AC coeffs and 1 4x4 DC coeff TU blocks will be sent
2142 For all MBs along with 8 4x4 AC coeffs 2 2x2 DC coeff TU blocks will be sent
2143 So use 17 4x4 TU blocks for luma and 9 4x4 TU blocks for chroma */
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2144 memTab[MEM_REC_COEFF_DATA].u4_mem_size += u4_num_entries
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2145 * (MAX(17 * sizeof(tu_sblk4x4_coeff_data_t),4 * sizeof(tu_blk8x8_coeff_data_t))
2146 + 9 * sizeof(tu_sblk4x4_coeff_data_t));
2147 //32 bytes for each mb to store u1_prev_intra4x4_pred_mode and u1_rem_intra4x4_pred_mode data
2148 memTab[MEM_REC_COEFF_DATA].u4_mem_size += u4_num_entries * 32;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2149
2150 }
2151
2152 memTab[MEM_REC_SPS].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2153 memTab[MEM_REC_SPS].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2154 memTab[MEM_REC_SPS].u4_mem_size = ((sizeof(dec_seq_params_t))
2155 * MAX_NUM_SEQ_PARAMS);
2156
2157 memTab[MEM_REC_PPS].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2158 memTab[MEM_REC_PPS].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2159 memTab[MEM_REC_PPS].u4_mem_size = (sizeof(dec_pic_params_t))
2160 * MAX_NUM_PIC_PARAMS;
2161
2162 {
2163 UWORD32 u4_mem_size;
2164
2165 u4_mem_size = 0;
2166 u4_mem_size += (((sizeof(dec_err_status_t) + 127) >> 7) << 7);
2167 u4_mem_size += sizeof(sei);
2168 u4_mem_size += sizeof(dpb_commands_t);
2169 u4_mem_size += sizeof(dec_bit_stream_t);
2170 u4_mem_size += sizeof(dec_slice_params_t);
2171 u4_mem_size += MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t));
2172
2173 memTab[MEM_REC_EXTRA_MEM].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2174 memTab[MEM_REC_EXTRA_MEM].e_mem_type =
2175 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2176 memTab[MEM_REC_EXTRA_MEM].u4_mem_size = u4_mem_size;
2177 }
2178
2179 {
2180
2181 UWORD32 u4_mem_size;
2182
2183 u4_mem_size = 0;
2184 u4_mem_size += ((TOTAL_LIST_ENTRIES + PAD_MAP_IDX_POC) * sizeof(void *));
2185 u4_mem_size = ALIGN64(u4_mem_size);
2186 u4_mem_size += (sizeof(bin_ctxt_model_t) * NUM_CABAC_CTXTS);
2187 u4_mem_size = ALIGN64(u4_mem_size);
2188 u4_mem_size += sizeof(ctxt_inc_mb_info_t);
2189 u4_mem_size = ALIGN64(u4_mem_size);
2190 u4_mem_size += sizeof(UWORD32) * (MAX_REF_BUFS * MAX_REF_BUFS);
2191 u4_mem_size = ALIGN64(u4_mem_size);
2192
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2193 u4_mem_size += MAX_REF_BUF_SIZE * 2;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2194 u4_mem_size = ALIGN64(u4_mem_size);
2195 u4_mem_size += ((sizeof(WORD16)) * PRED_BUFFER_WIDTH
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2196 * PRED_BUFFER_HEIGHT * 2);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2197 u4_mem_size = ALIGN64(u4_mem_size);
2198 u4_mem_size += sizeof(UWORD8) * (MB_LUM_SIZE);
2199 u4_mem_size = ALIGN64(u4_mem_size);
2200 u4_mem_size += sizeof(parse_pmbarams_t) * luma_width_in_mbs; //Max recon mb group*/
2201 u4_mem_size = ALIGN64(u4_mem_size);
2202 u4_mem_size += (sizeof(parse_part_params_t) * luma_width_in_mbs) << 4; //Max recon mb group*/
2203 u4_mem_size = ALIGN64(u4_mem_size);
2204
2205 u4_mem_size += 2 * MAX_REF_BUFS * sizeof(struct pic_buffer_t);
2206 u4_mem_size = ALIGN64(u4_mem_size);
2207 u4_mem_size += 2 * MAX_REF_BUFS * sizeof(struct pic_buffer_t);
2208 u4_mem_size = ALIGN64(u4_mem_size);
2209 u4_mem_size += (sizeof(UWORD32) * 3 * (MAX_REF_BUFS * MAX_REF_BUFS)) << 3;
2210 u4_mem_size = ALIGN64(u4_mem_size);
2211
Harish Mahendrakar74f03b62017-01-13 14:56:49 +0530[diff] [blame]2212 u4_mem_size += sizeof(UWORD32) * 2 * 3
2213 * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1));
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2214 u4_mem_size = ALIGN64(u4_mem_size);
2215
2216 memTab[MEM_REC_INTERNAL_SCRATCH].u4_mem_alignment =
2217 (128 * 8) / CHAR_BIT;
2218 memTab[MEM_REC_INTERNAL_SCRATCH].e_mem_type =
2219 IV_EXTERNAL_CACHEABLE_SCRATCH_MEM;
2220 memTab[MEM_REC_INTERNAL_SCRATCH].u4_mem_size = u4_mem_size;
2221 }
2222
2223 {
2224
2225 UWORD32 u4_mem_used;
2226 UWORD32 u4_numRows = MB_SIZE << 1;
2227 UWORD32 u4_blk_wd = ((luma_width_in_mbs << 4) >> 1) + 8;
2228
2229 u4_mem_used = 0;
2230 u4_mem_used += ((luma_width_in_mbs * sizeof(deblkmb_neighbour_t)) << 1);
2231 u4_mem_used = ALIGN64(u4_mem_used);
2232 u4_mem_used += (sizeof(neighbouradd_t) << 2);
2233 u4_mem_used = ALIGN64(u4_mem_used);
2234 u4_mem_used += ((sizeof(ctxt_inc_mb_info_t))
2235 * (((luma_width_in_mbs + 1) << 1) + 1));
2236 u4_mem_used = ALIGN64(u4_mem_used);
2237
2238 u4_mem_used += (sizeof(mv_pred_t) * luma_width_in_mbs * 16);
2239 u4_mem_used = ALIGN64(u4_mem_used);
2240 u4_mem_used += (sizeof(mv_pred_t) * luma_width_in_mbs * 16);
2241 u4_mem_used = ALIGN64(u4_mem_used);
2242 u4_mem_used += (sizeof(mv_pred_t) * luma_width_in_mbs * 4
2243 * MV_SCRATCH_BUFS);
2244 u4_mem_used = ALIGN64(u4_mem_used);
2245 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd;
2246 u4_mem_used = ALIGN64(u4_mem_used);
2247 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd;
2248 u4_mem_used = ALIGN64(u4_mem_used);
2249 u4_numRows = BLK8x8SIZE << 1;
2250
2251 u4_blk_wd = ((luma_width_in_mbs << 3) >> 1) + 8;
2252
2253 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd;
2254 u4_mem_used = ALIGN64(u4_mem_used);
2255 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd;
2256 u4_mem_used = ALIGN64(u4_mem_used);
2257 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd;
2258 u4_mem_used = ALIGN64(u4_mem_used);
2259 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd;
2260 u4_mem_used += 32;
2261 u4_mem_used = ALIGN64(u4_mem_used);
2262 u4_mem_used += sizeof(UWORD8) * (luma_width + 16) * 2;
2263 u4_mem_used = ALIGN64(u4_mem_used);
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2264 u4_mem_used += sizeof(UWORD8) * (luma_width + 16) * 2;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2265 u4_mem_used = ALIGN64(u4_mem_used);
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2266 u4_mem_used += sizeof(UWORD8) * (luma_width + 16) * 2;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2267 u4_mem_used = ALIGN64(u4_mem_used);
2268 u4_mem_used += sizeof(mb_neigbour_params_t) * (luma_width_in_mbs + 1)
2269 * luma_height_in_mbs;
2270 u4_mem_used += luma_width;
2271 u4_mem_used = ALIGN64(u4_mem_used);
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2272 u4_mem_used += luma_width;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2273 u4_mem_used = ALIGN64(u4_mem_used);
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2274 u4_mem_used += luma_width;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2275 u4_mem_used = ALIGN64(u4_mem_used);
2276
2277 u4_mem_used += ((MB_SIZE + 4) << 1) * PAD_LEN_Y_H;
2278 u4_mem_used = ALIGN64(u4_mem_used);
2279 u4_mem_used += ((BLK8x8SIZE + 2) << 1) * PAD_LEN_UV_H;
2280 u4_mem_used = ALIGN64(u4_mem_used);
2281 u4_mem_used += ((BLK8x8SIZE + 2) << 1) * PAD_LEN_UV_H;
2282 u4_mem_used = ALIGN64(u4_mem_used);
2283 memTab[MEM_REC_INTERNAL_PERSIST].u4_mem_alignment =
2284 (128 * 8) / CHAR_BIT;
2285 memTab[MEM_REC_INTERNAL_PERSIST].e_mem_type =
2286 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2287 memTab[MEM_REC_INTERNAL_PERSIST].u4_mem_size = u4_mem_used;
2288 }
2289
2290 memTab[MEM_REC_BITSBUF].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2291 memTab[MEM_REC_BITSBUF].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2292 memTab[MEM_REC_BITSBUF].u4_mem_size = MAX(256000, (luma_width * luma_height * 3 / 2));
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2293
2294 {
2295
2296 UWORD32 u4_thread_struct_size = ithread_get_handle_size();
2297
2298 memTab[MEM_REC_THREAD_HANDLE].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2299 memTab[MEM_REC_THREAD_HANDLE].e_mem_type =
2300 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2301 memTab[MEM_REC_THREAD_HANDLE].u4_mem_size = u4_thread_struct_size * 2;
2302
2303 }
2304
2305 memTab[MEM_REC_PARSE_MAP].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2306 memTab[MEM_REC_PARSE_MAP].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2307 memTab[MEM_REC_PARSE_MAP].u4_mem_size = u4_total_num_mbs;
2308
2309 memTab[MEM_REC_PROC_MAP].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2310 memTab[MEM_REC_PROC_MAP].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2311 memTab[MEM_REC_PROC_MAP].u4_mem_size = u4_total_num_mbs;
2312
2313 memTab[MEM_REC_SLICE_NUM_MAP].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2314 memTab[MEM_REC_SLICE_NUM_MAP].e_mem_type =
2315 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2316 memTab[MEM_REC_SLICE_NUM_MAP].u4_mem_size = u4_total_num_mbs
2317 * sizeof(UWORD16);
2318
2319 memTab[MEM_REC_DPB_MGR].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2320 memTab[MEM_REC_DPB_MGR].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2321 memTab[MEM_REC_DPB_MGR].u4_mem_size = sizeof(dpb_manager_t);
2322
2323 memTab[MEM_REC_BACKUP].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2324 memTab[MEM_REC_BACKUP].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2325 memTab[MEM_REC_BACKUP].u4_mem_size = sizeof(iv_mem_rec_t) * MEM_REC_CNT;
2326
2327 {
2328
2329 UWORD32 u4_mem_size;
2330
2331 u4_mem_size = sizeof(disp_mgr_t);
2332 u4_mem_size += sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
2333 u4_mem_size += sizeof(struct pic_buffer_t) * (H264_MAX_REF_PICS * 2);
2334
2335 memTab[MEM_REC_PIC_BUF_MGR].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2336 memTab[MEM_REC_PIC_BUF_MGR].e_mem_type =
2337 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2338 memTab[MEM_REC_PIC_BUF_MGR].u4_mem_size = u4_mem_size;
2339 }
2340
2341 {
2342 UWORD32 u4_mem_size;
2343
2344 u4_mem_size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
2345 u4_mem_size += sizeof(col_mv_buf_t) * (H264_MAX_REF_PICS * 2);
2346 u4_mem_size = ALIGN128(u4_mem_size);
2347 u4_mem_size += ((luma_width * luma_height) >> 4)
2348 * (MIN(max_dpb_size, num_ref_frames) + 1);
2349 memTab[MEM_REC_MV_BUF_MGR].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2350 memTab[MEM_REC_MV_BUF_MGR].e_mem_type =
2351 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2352 memTab[MEM_REC_MV_BUF_MGR].u4_mem_size = u4_mem_size;
2353 }
2354
2355 memTab[MEM_REC_PRED_INFO_PKD].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2356 memTab[MEM_REC_PRED_INFO_PKD].e_mem_type =
2357 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2358
2359 {
2360 UWORD32 u4_num_entries;
2361 u4_num_entries = u4_total_num_mbs;
2362
Hamsalekha S6a5cb802017-05-08 18:59:04 +0530[diff] [blame]2363
2364 u4_num_entries *= 16 * 2;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2365
2366 memTab[MEM_REC_PRED_INFO_PKD].u4_mem_size = sizeof(pred_info_pkd_t)
2367 * u4_num_entries;
2368 }
2369
2370 ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_num_mem_rec_filled = MEM_REC_CNT;
2371
2372
2373 return IV_SUCCESS;
2374}
2375/*****************************************************************************/
2376/* */
2377/* Function Name : ih264d_clr */
2378/* */
2379/* Description : returns memory records to app */
2380/* */
2381/* Inputs :iv_obj_t decoder handle */
2382/* :pv_api_ip pointer to input structure */
2383/* :pv_api_op pointer to output structure */
2384/* Outputs : */
2385/* Returns : void */
2386/* */
2387/* Issues : none */
2388/* */
2389/* Revision History: */
2390/* */
2391/* DD MM YYYY Author(s) Changes (Describe the changes made) */
2392/* 22 10 2008 100356 Draft */
2393/* */
2394/*****************************************************************************/
2395WORD32 ih264d_clr(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2396{
2397
2398 dec_struct_t * ps_dec;
2399 iv_retrieve_mem_rec_ip_t *dec_clr_ip;
2400 iv_retrieve_mem_rec_op_t *dec_clr_op;
2401
2402 dec_clr_ip = (iv_retrieve_mem_rec_ip_t *)pv_api_ip;
2403 dec_clr_op = (iv_retrieve_mem_rec_op_t *)pv_api_op;
2404 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
2405
2406 if(ps_dec->init_done != 1)
2407 {
2408 //return a proper Error Code
2409 return IV_FAIL;
2410 }
2411
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2412 if(ps_dec->pv_pic_buf_mgr)
2413 ih264_buf_mgr_free((buf_mgr_t *)ps_dec->pv_pic_buf_mgr);
2414 if(ps_dec->pv_mv_buf_mgr)
2415 ih264_buf_mgr_free((buf_mgr_t *)ps_dec->pv_mv_buf_mgr);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2416
2417 memcpy(dec_clr_ip->pv_mem_rec_location, ps_dec->ps_mem_tab,
2418 MEM_REC_CNT * (sizeof(iv_mem_rec_t)));
2419 dec_clr_op->u4_num_mem_rec_filled = MEM_REC_CNT;
2420
2421 H264_DEC_DEBUG_PRINT("The clear non-conceal num mem recs: %d\n",
2422 dec_clr_op->u4_num_mem_rec_filled);
2423
2424 return IV_SUCCESS;
2425
2426}
2427
2428/*****************************************************************************/
2429/* */
2430/* Function Name : ih264d_init */
2431/* */
2432/* Description : initializes decoder */
2433/* */
2434/* Inputs :iv_obj_t decoder handle */
2435/* :pv_api_ip pointer to input structure */
2436/* :pv_api_op pointer to output structure */
2437/* Outputs : */
2438/* Returns : void */
2439/* */
2440/* Issues : none */
2441/* */
2442/* Revision History: */
2443/* */
2444/* DD MM YYYY Author(s) Changes (Describe the changes made) */
2445/* 22 10 2008 100356 Draft */
2446/* */
2447/*****************************************************************************/
2448WORD32 ih264d_init(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2449{
2450 ih264d_init_ip_t *ps_init_ip;
2451 ih264d_init_op_t *ps_init_op;
Martin Storsjo086dd8e2015-06-13 00:35:01 +0300[diff] [blame]2452 WORD32 init_status = IV_SUCCESS;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2453 ps_init_ip = (ih264d_init_ip_t *)pv_api_ip;
2454 ps_init_op = (ih264d_init_op_t *)pv_api_op;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2455
2456 init_status = ih264d_init_video_decoder(dec_hdl, ps_init_ip, ps_init_op);
2457
2458 if(IV_SUCCESS != init_status)
2459 {
2460 return init_status;
2461 }
2462
2463 return init_status;
2464}
2465/*****************************************************************************/
2466/* */
2467/* Function Name : ih264d_map_error */
2468/* */
2469/* Description : Maps error codes to IVD error groups */
2470/* */
2471/* Inputs : */
2472/* Globals : <Does it use any global variables?> */
2473/* Outputs : */
2474/* Returns : void */
2475/* */
2476/* Issues : none */
2477/* */
2478/* Revision History: */
2479/* */
2480/* DD MM YYYY Author(s) Changes (Describe the changes made) */
2481/* 22 10 2008 100356 Draft */
2482/* */
2483/*****************************************************************************/
2484UWORD32 ih264d_map_error(UWORD32 i4_err_status)
2485{
2486 UWORD32 temp = 0;
2487
2488 switch(i4_err_status)
2489 {
2490 case ERROR_MEM_ALLOC_ISRAM_T:
2491 case ERROR_MEM_ALLOC_SDRAM_T:
2492 case ERROR_BUF_MGR:
2493 case ERROR_MB_GROUP_ASSGN_T:
2494 case ERROR_FRAME_LIMIT_OVER:
2495 case ERROR_ACTUAL_RESOLUTION_GREATER_THAN_INIT:
2496 case ERROR_PROFILE_NOT_SUPPORTED:
2497 case ERROR_INIT_NOT_DONE:
2498 temp = 1 << IVD_FATALERROR;
2499 H264_DEC_DEBUG_PRINT("\nFatal Error\n");
2500 break;
2501
2502 case ERROR_DBP_MANAGER_T:
2503 case ERROR_GAPS_IN_FRM_NUM:
2504 case ERROR_UNKNOWN_NAL:
2505 case ERROR_INV_MB_SLC_GRP_T:
2506 case ERROR_MULTIPLE_SLC_GRP_T:
2507 case ERROR_UNKNOWN_LEVEL:
2508 case ERROR_UNAVAIL_PICBUF_T:
2509 case ERROR_UNAVAIL_MVBUF_T:
2510 case ERROR_UNAVAIL_DISPBUF_T:
2511 case ERROR_NUM_REF:
2512 case ERROR_REFIDX_ORDER_T:
2513 case ERROR_PIC0_NOT_FOUND_T:
2514 case ERROR_MB_TYPE:
2515 case ERROR_SUB_MB_TYPE:
2516 case ERROR_CBP:
2517 case ERROR_REF_IDX:
2518 case ERROR_NUM_MV:
2519 case ERROR_CHROMA_PRED_MODE:
2520 case ERROR_INTRAPRED:
2521 case ERROR_NEXT_MB_ADDRESS_T:
2522 case ERROR_MB_ADDRESS_T:
2523 case ERROR_PIC1_NOT_FOUND_T:
2524 case ERROR_CAVLC_NUM_COEFF_T:
2525 case ERROR_CAVLC_SCAN_POS_T:
2526 case ERROR_PRED_WEIGHT_TABLE_T:
2527 case ERROR_CORRUPTED_SLICE:
2528 temp = 1 << IVD_CORRUPTEDDATA;
2529 break;
2530
2531 case ERROR_NOT_SUPP_RESOLUTION:
2532 case ERROR_FEATURE_UNAVAIL:
2533 case ERROR_ACTUAL_LEVEL_GREATER_THAN_INIT:
2534 temp = 1 << IVD_UNSUPPORTEDINPUT;
2535 break;
2536
2537 case ERROR_INVALID_PIC_PARAM:
2538 case ERROR_INVALID_SEQ_PARAM:
2539 case ERROR_EGC_EXCEED_32_1_T:
2540 case ERROR_EGC_EXCEED_32_2_T:
2541 case ERROR_INV_RANGE_TEV_T:
2542 case ERROR_INV_SLC_TYPE_T:
2543 case ERROR_INV_POC_TYPE_T:
2544 case ERROR_INV_RANGE_QP_T:
2545 case ERROR_INV_SPS_PPS_T:
2546 case ERROR_INV_SLICE_HDR_T:
2547 temp = 1 << IVD_CORRUPTEDHEADER;
2548 break;
2549
2550 case ERROR_EOB_FLUSHBITS_T:
2551 case ERROR_EOB_GETBITS_T:
2552 case ERROR_EOB_GETBIT_T:
2553 case ERROR_EOB_BYPASS_T:
2554 case ERROR_EOB_DECISION_T:
2555 case ERROR_EOB_TERMINATE_T:
2556 case ERROR_EOB_READCOEFF4X4CAB_T:
2557 temp = 1 << IVD_INSUFFICIENTDATA;
2558 break;
2559 case ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED:
2560 case ERROR_DISP_WIDTH_RESET_TO_PIC_WIDTH:
2561 temp = 1 << IVD_UNSUPPORTEDPARAM | 1 << IVD_FATALERROR;
2562 break;
2563
2564 case ERROR_DANGLING_FIELD_IN_PIC:
2565 temp = 1 << IVD_APPLIEDCONCEALMENT;
2566 break;
2567
2568 }
2569
2570 return temp;
2571
2572}
2573
Hamsalekha S3f6c9412017-06-01 11:44:39 +0530[diff] [blame^]2574UWORD32 ih264d_get_outbuf_size(WORD32 pic_wd,
2575 UWORD32 pic_ht,
2576 UWORD8 u1_chroma_format,
2577 UWORD32 *p_buf_size)
2578{
2579 UWORD32 u4_min_num_out_bufs = 0;
2580
2581 if(u1_chroma_format == IV_YUV_420P)
2582 u4_min_num_out_bufs = MIN_OUT_BUFS_420;
2583 else if(u1_chroma_format == IV_YUV_422ILE)
2584 u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
2585 else if(u1_chroma_format == IV_RGB_565)
2586 u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
2587 else if((u1_chroma_format == IV_YUV_420SP_UV)
2588 || (u1_chroma_format == IV_YUV_420SP_VU))
2589 u4_min_num_out_bufs = MIN_OUT_BUFS_420SP;
2590
2591 if(u1_chroma_format == IV_YUV_420P)
2592 {
2593 p_buf_size[0] = (pic_wd * pic_ht);
2594 p_buf_size[1] = (pic_wd * pic_ht) >> 2;
2595 p_buf_size[2] = (pic_wd * pic_ht) >> 2;
2596 }
2597 else if(u1_chroma_format == IV_YUV_422ILE)
2598 {
2599 p_buf_size[0] = (pic_wd * pic_ht) * 2;
2600 p_buf_size[1] = p_buf_size[2] = 0;
2601 }
2602 else if(u1_chroma_format == IV_RGB_565)
2603 {
2604 p_buf_size[0] = (pic_wd * pic_ht) * 2;
2605 p_buf_size[1] = p_buf_size[2] = 0;
2606 }
2607 else if((u1_chroma_format == IV_YUV_420SP_UV)
2608 || (u1_chroma_format == IV_YUV_420SP_VU))
2609 {
2610 p_buf_size[0] = (pic_wd * pic_ht);
2611 p_buf_size[1] = (pic_wd * pic_ht) >> 1;
2612 p_buf_size[2] = 0;
2613 }
2614
2615 return u4_min_num_out_bufs;
2616}
2617
2618WORD32 check_app_out_buf_size(dec_struct_t *ps_dec)
2619{
2620 UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS];
2621 UWORD32 u4_min_num_out_bufs, i;
2622 UWORD32 pic_wd, pic_ht;
2623
2624 if(0 == ps_dec->u4_share_disp_buf)
2625 {
2626 pic_wd = ps_dec->u2_disp_width;
2627 pic_ht = ps_dec->u2_disp_height;
2628
2629 }
2630 else
2631 {
2632 /* In case of shared mode, do not check validity of ps_dec->ps_out_buffer */
2633 return (IV_SUCCESS);
2634 }
2635
2636 if(ps_dec->u4_app_disp_width > pic_wd)
2637 pic_wd = ps_dec->u4_app_disp_width;
2638
2639 u4_min_num_out_bufs = ih264d_get_outbuf_size(pic_wd, pic_ht,
2640 ps_dec->u1_chroma_format,
2641 &au4_min_out_buf_size[0]);
2642
2643 if(ps_dec->ps_out_buffer->u4_num_bufs < u4_min_num_out_bufs)
2644 return IV_FAIL;
2645
2646 for(i = 0; i < u4_min_num_out_bufs; i++)
2647 {
2648 if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i]
2649 < au4_min_out_buf_size[i])
2650 return (IV_FAIL);
2651 }
2652
2653 return (IV_SUCCESS);
2654}
2655
2656
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2657/*****************************************************************************/
2658/* */
2659/* Function Name : ih264d_video_decode */
2660/* */
2661/* Description : handle video decode API command */
2662/* */
2663/* Inputs :iv_obj_t decoder handle */
2664/* :pv_api_ip pointer to input structure */
2665/* :pv_api_op pointer to output structure */
2666/* Outputs : */
2667/* Returns : void */
2668/* */
2669/* Issues : none */
2670/* */
2671/* Revision History: */
2672/* */
2673/* DD MM YYYY Author(s) Changes (Describe the changes made) */
2674/* 22 10 2008 100356 Draft */
2675/* */
2676/*****************************************************************************/
2677
2678WORD32 ih264d_video_decode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2679{
2680 /* ! */
2681
2682 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
2683
2684 WORD32 i4_err_status = 0;
2685 UWORD8 *pu1_buf = NULL;
2686 WORD32 buflen;
2687 UWORD32 u4_max_ofst, u4_length_of_start_code = 0;
2688
2689 UWORD32 bytes_consumed = 0;
2690 UWORD32 cur_slice_is_nonref = 0;
2691 UWORD32 u4_next_is_aud;
2692 UWORD32 u4_first_start_code_found = 0;
Hamsalekha Se789d1d2015-07-10 13:41:00 +0530[diff] [blame]2693 WORD32 ret = 0,api_ret_value = IV_SUCCESS;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2694 WORD32 header_data_left = 0,frame_data_left = 0;
2695 UWORD8 *pu1_bitstrm_buf;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2696 ivd_video_decode_ip_t *ps_dec_ip;
2697 ivd_video_decode_op_t *ps_dec_op;
Martin Storsjo086dd8e2015-06-13 00:35:01 +0300[diff] [blame]2698
2699 ithread_set_name((void*)"Parse_thread");
2700
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2701 ps_dec_ip = (ivd_video_decode_ip_t *)pv_api_ip;
2702 ps_dec_op = (ivd_video_decode_op_t *)pv_api_op;
Harish Mahendrakar33db7a02016-04-20 16:13:52 +0530[diff] [blame]2703
2704 {
2705 UWORD32 u4_size;
2706 u4_size = ps_dec_op->u4_size;
2707 memset(ps_dec_op, 0, sizeof(ivd_video_decode_op_t));
2708 ps_dec_op->u4_size = u4_size;
2709 }
2710
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2711 ps_dec->pv_dec_out = ps_dec_op;
2712 ps_dec->process_called = 1;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2713 if(ps_dec->init_done != 1)
2714 {
2715 return IV_FAIL;
2716 }
2717
2718 /*Data memory barries instruction,so that bitstream write by the application is complete*/
2719 DATA_SYNC();
2720
2721 if(0 == ps_dec->u1_flushfrm)
2722 {
2723 if(ps_dec_ip->pv_stream_buffer == NULL)
2724 {
2725 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2726 ps_dec_op->u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL;
2727 return IV_FAIL;
2728 }
2729 if(ps_dec_ip->u4_num_Bytes <= 0)
2730 {
2731 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2732 ps_dec_op->u4_error_code |= IVD_DEC_NUMBYTES_INV;
2733 return IV_FAIL;
2734
2735 }
2736 }
2737 ps_dec->u1_pic_decode_done = 0;
2738
2739 ps_dec_op->u4_num_bytes_consumed = 0;
2740
2741 ps_dec->ps_out_buffer = NULL;
2742
2743 if(ps_dec_ip->u4_size
2744 >= offsetof(ivd_video_decode_ip_t, s_out_buffer))
2745 ps_dec->ps_out_buffer = &ps_dec_ip->s_out_buffer;
2746
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2747 ps_dec->u4_fmt_conv_cur_row = 0;
2748
2749 ps_dec->u4_output_present = 0;
2750 ps_dec->s_disp_op.u4_error_code = 1;
2751 ps_dec->u4_fmt_conv_num_rows = FMT_CONV_NUM_ROWS;
2752 ps_dec->u4_stop_threads = 0;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2753 if(0 == ps_dec->u4_share_disp_buf
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2754 && ps_dec->i4_decode_header == 0)
2755 {
2756 UWORD32 i;
2757 if(ps_dec->ps_out_buffer->u4_num_bufs == 0)
2758 {
2759 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2760 ps_dec_op->u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2761 return IV_FAIL;
2762 }
2763
2764 for(i = 0; i < ps_dec->ps_out_buffer->u4_num_bufs; i++)
2765 {
2766 if(ps_dec->ps_out_buffer->pu1_bufs[i] == NULL)
2767 {
2768 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2769 ps_dec_op->u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
2770 return IV_FAIL;
2771 }
2772
2773 if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i] == 0)
2774 {
2775 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2776 ps_dec_op->u4_error_code |=
2777 IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2778 return IV_FAIL;
2779 }
2780 }
2781 }
2782
2783 if(ps_dec->u4_total_frames_decoded >= NUM_FRAMES_LIMIT)
2784 {
2785 ps_dec_op->u4_error_code = ERROR_FRAME_LIMIT_OVER;
2786 return IV_FAIL;
2787 }
2788
2789 /* ! */
2790 ps_dec->u4_ts = ps_dec_ip->u4_ts;
2791
2792 ps_dec_op->u4_error_code = 0;
2793 ps_dec_op->e_pic_type = -1;
2794 ps_dec_op->u4_output_present = 0;
2795 ps_dec_op->u4_frame_decoded_flag = 0;
2796
2797 ps_dec->i4_frametype = -1;
2798 ps_dec->i4_content_type = -1;
Harish Mahendrakar49456122017-01-05 12:10:47 +0530[diff] [blame]2799
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2800 ps_dec->u4_slice_start_code_found = 0;
2801
2802 /* In case the deocder is not in flush mode(in shared mode),
2803 then decoder has to pick up a buffer to write current frame.
2804 Check if a frame is available in such cases */
2805
2806 if(ps_dec->u1_init_dec_flag == 1 && ps_dec->u4_share_disp_buf == 1
2807 && ps_dec->u1_flushfrm == 0)
2808 {
2809 UWORD32 i;
2810
2811 WORD32 disp_avail = 0, free_id;
2812
2813 /* Check if at least one buffer is available with the codec */
2814 /* If not then return to application with error */
2815 for(i = 0; i < ps_dec->u1_pic_bufs; i++)
2816 {
2817 if(0 == ps_dec->u4_disp_buf_mapping[i]
2818 || 1 == ps_dec->u4_disp_buf_to_be_freed[i])
2819 {
2820 disp_avail = 1;
2821 break;
2822 }
2823
2824 }
2825
2826 if(0 == disp_avail)
2827 {
2828 /* If something is queued for display wait for that buffer to be returned */
2829
2830 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL;
2831 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
2832 return (IV_FAIL);
2833 }
2834
2835 while(1)
2836 {
2837 pic_buffer_t *ps_pic_buf;
2838 ps_pic_buf = (pic_buffer_t *)ih264_buf_mgr_get_next_free(
2839 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, &free_id);
2840
2841 if(ps_pic_buf == NULL)
2842 {
2843 UWORD32 i, display_queued = 0;
2844
2845 /* check if any buffer was given for display which is not returned yet */
2846 for(i = 0; i < (MAX_DISP_BUFS_NEW); i++)
2847 {
2848 if(0 != ps_dec->u4_disp_buf_mapping[i])
2849 {
2850 display_queued = 1;
2851 break;
2852 }
2853 }
2854 /* If some buffer is queued for display, then codec has to singal an error and wait
2855 for that buffer to be returned.
2856 If nothing is queued for display then codec has ownership of all display buffers
2857 and it can reuse any of the existing buffers and continue decoding */
2858
2859 if(1 == display_queued)
2860 {
2861 /* If something is queued for display wait for that buffer to be returned */
2862 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL;
2863 ps_dec_op->u4_error_code |= (1
2864 << IVD_UNSUPPORTEDPARAM);
2865 return (IV_FAIL);
2866 }
2867 }
2868 else
2869 {
2870 /* If the buffer is with display, then mark it as in use and then look for a buffer again */
2871 if(1 == ps_dec->u4_disp_buf_mapping[free_id])
2872 {
2873 ih264_buf_mgr_set_status(
2874 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
2875 free_id,
2876 BUF_MGR_IO);
2877 }
2878 else
2879 {
2880 /**
2881 * Found a free buffer for present call. Release it now.
2882 * Will be again obtained later.
2883 */
2884 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
2885 free_id,
2886 BUF_MGR_IO);
2887 break;
2888 }
2889 }
2890 }
2891
2892 }
2893
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2894 if(ps_dec->u1_flushfrm && ps_dec->u1_init_dec_flag)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2895 {
2896
2897 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer,
2898 &(ps_dec->s_disp_op));
2899 if(0 == ps_dec->s_disp_op.u4_error_code)
2900 {
Hamsalekha S3f6c9412017-06-01 11:44:39 +0530[diff] [blame^]2901 /* check output buffer size given by the application */
2902 if(check_app_out_buf_size(ps_dec) != IV_SUCCESS)
2903 {
2904 ps_dec_op->u4_error_code= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2905 return (IV_FAIL);
2906 }
2907
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2908 ps_dec->u4_fmt_conv_cur_row = 0;
2909 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht;
2910 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op),
2911 ps_dec->u4_fmt_conv_cur_row,
2912 ps_dec->u4_fmt_conv_num_rows);
2913 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows;
2914 ps_dec->u4_output_present = 1;
2915
2916 }
2917 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op));
2918
2919 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
2920 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
2921
2922 ps_dec_op->u4_new_seq = 0;
2923
2924 ps_dec_op->u4_output_present = ps_dec->u4_output_present;
2925 ps_dec_op->u4_progressive_frame_flag =
2926 ps_dec->s_disp_op.u4_progressive_frame_flag;
2927 ps_dec_op->e_output_format =
2928 ps_dec->s_disp_op.e_output_format;
2929 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf;
2930 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type;
2931 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts;
2932 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
2933
2934 /*In the case of flush ,since no frame is decoded set pic type as invalid*/
2935 ps_dec_op->u4_is_ref_flag = -1;
2936 ps_dec_op->e_pic_type = IV_NA_FRAME;
2937 ps_dec_op->u4_frame_decoded_flag = 0;
2938
2939 if(0 == ps_dec->s_disp_op.u4_error_code)
2940 {
2941 return (IV_SUCCESS);
2942 }
2943 else
2944 return (IV_FAIL);
2945
2946 }
2947 if(ps_dec->u1_res_changed == 1)
2948 {
2949 /*if resolution has changed and all buffers have been flushed, reset decoder*/
2950 ih264d_init_decoder(ps_dec);
2951 }
2952
2953 ps_dec->u4_prev_nal_skipped = 0;
2954
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2955 ps_dec->u2_cur_mb_addr = 0;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2956 ps_dec->u2_total_mbs_coded = 0;
2957 ps_dec->u2_cur_slice_num = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2958 ps_dec->cur_dec_mb_num = 0;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2959 ps_dec->cur_recon_mb_num = 0;
Harish Mahendrakar0b23c812017-01-16 14:43:42 +0530[diff] [blame]2960 ps_dec->u4_first_slice_in_pic = 1;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2961 ps_dec->u1_slice_header_done = 0;
Hamsalekha S9f0dcba2015-06-09 15:54:31 +0530[diff] [blame]2962 ps_dec->u1_dangling_field = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2963
2964 ps_dec->u4_dec_thread_created = 0;
2965 ps_dec->u4_bs_deblk_thread_created = 0;
2966 ps_dec->u4_cur_bs_mb_num = 0;
Harish Mahendrakar5e4f64c2016-06-01 13:31:45 +0530[diff] [blame]2967 ps_dec->u4_start_recon_deblk = 0;
Hamsalekha Sfe183752017-05-22 14:10:15 +0530[diff] [blame]2968 ps_dec->u4_sps_cnt_in_process = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2969
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2970 DEBUG_THREADS_PRINTF(" Starting process call\n");
2971
2972 ps_dec->u4_pic_buf_got = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2973
2974 do
2975 {
2976
2977 pu1_buf = (UWORD8*)ps_dec_ip->pv_stream_buffer
2978 + ps_dec_op->u4_num_bytes_consumed;
2979
2980 u4_max_ofst = ps_dec_ip->u4_num_Bytes
2981 - ps_dec_op->u4_num_bytes_consumed;
2982 pu1_bitstrm_buf = ps_dec->ps_mem_tab[MEM_REC_BITSBUF].pv_base;
2983
2984 u4_next_is_aud = 0;
2985
2986 buflen = ih264d_find_start_code(pu1_buf, 0, u4_max_ofst,
2987 &u4_length_of_start_code,
2988 &u4_next_is_aud);
2989
2990 if(buflen == -1)
2991 buflen = 0;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2992 /* Ignore bytes beyond the allocated size of intermediate buffer */
Harish Mahendrakar1f0ab0b2016-12-23 15:29:14 +0530[diff] [blame]2993 /* Since 8 bytes are read ahead, ensure 8 bytes are free at the
2994 end of the buffer, which will be memset to 0 after emulation prevention */
2995 buflen = MIN(buflen, (WORD32)(ps_dec->ps_mem_tab[MEM_REC_BITSBUF].u4_mem_size - 8));
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2996
2997 bytes_consumed = buflen + u4_length_of_start_code;
2998 ps_dec_op->u4_num_bytes_consumed += bytes_consumed;
2999
3000 if(buflen >= MAX_NAL_UNIT_SIZE)
3001 {
3002
3003 ih264d_fill_output_struct_from_context(ps_dec, ps_dec_op);
3004 H264_DEC_DEBUG_PRINT(
3005 "\nNal Size exceeded %d, Processing Stopped..\n",
3006 MAX_NAL_UNIT_SIZE);
3007 ps_dec->i4_error_code = 1 << IVD_CORRUPTEDDATA;
3008
3009 ps_dec_op->e_pic_type = -1;
3010 /*signal the decode thread*/
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3011 ih264d_signal_decode_thread(ps_dec);
3012 /*signal end of frame decode for curren frame*/
3013
3014 if(ps_dec->u4_pic_buf_got == 0)
3015 {
3016 if(ps_dec->i4_header_decoded == 3)
3017 {
3018 ps_dec->u2_total_mbs_coded =
3019 ps_dec->ps_cur_sps->u2_max_mb_addr + 1;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3020 }
3021
3022 /* close deblock thread if it is not closed yet*/
3023 if(ps_dec->u4_num_cores == 3)
3024 {
3025 ih264d_signal_bs_deblk_thread(ps_dec);
3026 }
3027 return IV_FAIL;
3028 }
3029 else
3030 {
3031 ps_dec->u1_pic_decode_done = 1;
3032 continue;
3033 }
3034 }
3035
3036 {
3037 UWORD8 u1_firstbyte, u1_nal_ref_idc;
3038
3039 if(ps_dec->i4_app_skip_mode == IVD_SKIP_B)
3040 {
3041 u1_firstbyte = *(pu1_buf + u4_length_of_start_code);
3042 u1_nal_ref_idc = (UWORD8)(NAL_REF_IDC(u1_firstbyte));
3043 if(u1_nal_ref_idc == 0)
3044 {
3045 /*skip non reference frames*/
3046 cur_slice_is_nonref = 1;
3047 continue;
3048 }
3049 else
3050 {
3051 if(1 == cur_slice_is_nonref)
3052 {
3053 /*We have encountered a referenced frame,return to app*/
3054 ps_dec_op->u4_num_bytes_consumed -=
3055 bytes_consumed;
3056 ps_dec_op->e_pic_type = IV_B_FRAME;
3057 ps_dec_op->u4_error_code =
3058 IVD_DEC_FRM_SKIPPED;
3059 ps_dec_op->u4_error_code |= (1
3060 << IVD_UNSUPPORTEDPARAM);
3061 ps_dec_op->u4_frame_decoded_flag = 0;
3062 ps_dec_op->u4_size =
3063 sizeof(ivd_video_decode_op_t);
3064 /*signal the decode thread*/
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3065 ih264d_signal_decode_thread(ps_dec);
3066 /* close deblock thread if it is not closed yet*/
3067 if(ps_dec->u4_num_cores == 3)
3068 {
3069 ih264d_signal_bs_deblk_thread(ps_dec);
3070 }
3071
3072 return (IV_FAIL);
3073 }
3074 }
3075
3076 }
3077
3078 }
3079
3080
3081 if(buflen)
3082 {
3083 memcpy(pu1_bitstrm_buf, pu1_buf + u4_length_of_start_code,
3084 buflen);
3085 u4_first_start_code_found = 1;
3086
3087 }
3088 else
3089 {
3090 /*start code not found*/
3091
3092 if(u4_first_start_code_found == 0)
3093 {
3094 /*no start codes found in current process call*/
3095
3096 ps_dec->i4_error_code = ERROR_START_CODE_NOT_FOUND;
3097 ps_dec_op->u4_error_code |= 1 << IVD_INSUFFICIENTDATA;
3098
3099 if(ps_dec->u4_pic_buf_got == 0)
3100 {
3101
3102 ih264d_fill_output_struct_from_context(ps_dec,
3103 ps_dec_op);
3104
3105 ps_dec_op->u4_error_code = ps_dec->i4_error_code;
3106 ps_dec_op->u4_frame_decoded_flag = 0;
3107
3108 return (IV_FAIL);
3109 }
3110 else
3111 {
3112 ps_dec->u1_pic_decode_done = 1;
3113 continue;
3114 }
3115 }
3116 else
3117 {
3118 /* a start code has already been found earlier in the same process call*/
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3119 frame_data_left = 0;
Harish Mahendrakar2cd2f7a2017-01-16 11:26:26 +0530[diff] [blame]3120 header_data_left = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3121 continue;
3122 }
3123
3124 }
3125
3126 ps_dec->u4_return_to_app = 0;
3127 ret = ih264d_parse_nal_unit(dec_hdl, ps_dec_op,
3128 pu1_bitstrm_buf, buflen);
3129 if(ret != OK)
3130 {
3131 UWORD32 error = ih264d_map_error(ret);
3132 ps_dec_op->u4_error_code = error | ret;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3133 api_ret_value = IV_FAIL;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3134
Hamsalekha Se789d1d2015-07-10 13:41:00 +0530[diff] [blame]3135 if((ret == IVD_RES_CHANGED)
3136 || (ret == IVD_STREAM_WIDTH_HEIGHT_NOT_SUPPORTED)
3137 || (ret == ERROR_UNAVAIL_PICBUF_T)
Harish Mahendrakar3a419ea2016-05-26 10:46:21 +0530[diff] [blame]3138 || (ret == ERROR_UNAVAIL_MVBUF_T)
Hamsalekha S3f6c9412017-06-01 11:44:39 +0530[diff] [blame^]3139 || (ret == ERROR_INV_SPS_PPS_T)
3140 || (ret == IVD_DISP_FRM_ZERO_OP_BUF_SIZE))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3141 {
Harish Mahendrakar3a419ea2016-05-26 10:46:21 +0530[diff] [blame]3142 ps_dec->u4_slice_start_code_found = 0;
Hamsalekha Se789d1d2015-07-10 13:41:00 +0530[diff] [blame]3143 break;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3144 }
Hamsalekha S9f0dcba2015-06-09 15:54:31 +0530[diff] [blame]3145
3146 if((ret == ERROR_INCOMPLETE_FRAME) || (ret == ERROR_DANGLING_FIELD_IN_PIC))
3147 {
3148 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed;
3149 api_ret_value = IV_FAIL;
3150 break;
3151 }
3152
3153 if(ret == ERROR_IN_LAST_SLICE_OF_PIC)
3154 {
3155 api_ret_value = IV_FAIL;
3156 break;
3157 }
3158
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3159 }
3160
3161 if(ps_dec->u4_return_to_app)
3162 {
3163 /*We have encountered a referenced frame,return to app*/
3164 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed;
3165 ps_dec_op->u4_error_code = IVD_DEC_FRM_SKIPPED;
3166 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
3167 ps_dec_op->u4_frame_decoded_flag = 0;
3168 ps_dec_op->u4_size = sizeof(ivd_video_decode_op_t);
3169 /*signal the decode thread*/
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3170 ih264d_signal_decode_thread(ps_dec);
3171 /* close deblock thread if it is not closed yet*/
3172 if(ps_dec->u4_num_cores == 3)
3173 {
3174 ih264d_signal_bs_deblk_thread(ps_dec);
3175 }
3176 return (IV_FAIL);
3177
3178 }
3179
3180
3181
3182 header_data_left = ((ps_dec->i4_decode_header == 1)
3183 && (ps_dec->i4_header_decoded != 3)
3184 && (ps_dec_op->u4_num_bytes_consumed
3185 < ps_dec_ip->u4_num_Bytes));
3186 frame_data_left = (((ps_dec->i4_decode_header == 0)
3187 && ((ps_dec->u1_pic_decode_done == 0)
3188 || (u4_next_is_aud == 1)))
3189 && (ps_dec_op->u4_num_bytes_consumed
3190 < ps_dec_ip->u4_num_Bytes));
3191 }
3192 while(( header_data_left == 1)||(frame_data_left == 1));
3193
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3194 if((ps_dec->u4_slice_start_code_found == 1)
3195 && ps_dec->u2_total_mbs_coded < ps_dec->u2_frm_ht_in_mbs * ps_dec->u2_frm_wd_in_mbs)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3196 {
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3197 // last slice - missing/corruption
3198 WORD32 num_mb_skipped;
Hamsalekha S9f0dcba2015-06-09 15:54:31 +0530[diff] [blame]3199 WORD32 prev_slice_err;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3200 pocstruct_t temp_poc;
Hamsalekha Se789d1d2015-07-10 13:41:00 +0530[diff] [blame]3201 WORD32 ret1;
Harish Mahendrakare1cf7ea2016-12-26 11:21:07 +0530[diff] [blame]3202 WORD32 ht_in_mbs;
3203 ht_in_mbs = ps_dec->u2_pic_ht >> (4 + ps_dec->ps_cur_slice->u1_field_pic_flag);
3204 num_mb_skipped = (ht_in_mbs * ps_dec->u2_frm_wd_in_mbs)
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3205 - ps_dec->u2_total_mbs_coded;
Hamsalekha S9f0dcba2015-06-09 15:54:31 +0530[diff] [blame]3206
Harish Mahendrakarc7a1cf42016-02-01 15:08:19 +0530[diff] [blame]3207 if(ps_dec->u4_first_slice_in_pic && (ps_dec->u4_pic_buf_got == 0))
Hamsalekha S9f0dcba2015-06-09 15:54:31 +0530[diff] [blame]3208 prev_slice_err = 1;
3209 else
3210 prev_slice_err = 2;
3211
Harish Mahendrakarb9269052016-07-12 10:37:28 +0530[diff] [blame]3212 if(ps_dec->u4_first_slice_in_pic && (ps_dec->u2_total_mbs_coded == 0))
3213 prev_slice_err = 1;
3214
Hamsalekha Se789d1d2015-07-10 13:41:00 +0530[diff] [blame]3215 ret1 = ih264d_mark_err_slice_skip(ps_dec, num_mb_skipped, ps_dec->u1_nal_unit_type == IDR_SLICE_NAL, ps_dec->ps_cur_slice->u2_frame_num,
Hamsalekha S9f0dcba2015-06-09 15:54:31 +0530[diff] [blame]3216 &temp_poc, prev_slice_err);
3217
Harish Mahendrakarc2e8ffe2016-09-17 14:04:29 +0530[diff] [blame]3218 if((ret1 == ERROR_UNAVAIL_PICBUF_T) || (ret1 == ERROR_UNAVAIL_MVBUF_T) ||
3219 (ret1 == ERROR_INV_SPS_PPS_T))
Hamsalekha S9f0dcba2015-06-09 15:54:31 +0530[diff] [blame]3220 {
Harish Mahendrakarc2e8ffe2016-09-17 14:04:29 +0530[diff] [blame]3221 ret = ret1;
Hamsalekha S9f0dcba2015-06-09 15:54:31 +0530[diff] [blame]3222 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3223 }
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3224
Hamsalekha Se789d1d2015-07-10 13:41:00 +0530[diff] [blame]3225 if((ret == IVD_RES_CHANGED)
3226 || (ret == IVD_STREAM_WIDTH_HEIGHT_NOT_SUPPORTED)
3227 || (ret == ERROR_UNAVAIL_PICBUF_T)
Harish Mahendrakar3a419ea2016-05-26 10:46:21 +0530[diff] [blame]3228 || (ret == ERROR_UNAVAIL_MVBUF_T)
3229 || (ret == ERROR_INV_SPS_PPS_T))
Hamsalekha Se789d1d2015-07-10 13:41:00 +0530[diff] [blame]3230 {
3231
3232 /* signal the decode thread */
3233 ih264d_signal_decode_thread(ps_dec);
3234 /* close deblock thread if it is not closed yet */
3235 if(ps_dec->u4_num_cores == 3)
3236 {
3237 ih264d_signal_bs_deblk_thread(ps_dec);
3238 }
Harish Mahendrakarc7a1cf42016-02-01 15:08:19 +0530[diff] [blame]3239 /* dont consume bitstream for change in resolution case */
3240 if(ret == IVD_RES_CHANGED)
3241 {
3242 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed;
3243 }
Hamsalekha Se789d1d2015-07-10 13:41:00 +0530[diff] [blame]3244 return IV_FAIL;
3245 }
3246
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3247
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3248 if(ps_dec->u1_separate_parse)
3249 {
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3250 /* If Format conversion is not complete,
3251 complete it here */
3252 if(ps_dec->u4_num_cores == 2)
3253 {
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3254
3255 /*do deblocking of all mbs*/
3256 if((ps_dec->u4_nmb_deblk == 0) &&(ps_dec->u4_start_recon_deblk == 1) && (ps_dec->ps_cur_sps->u1_mb_aff_flag == 0))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3257 {
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3258 UWORD32 u4_num_mbs,u4_max_addr;
3259 tfr_ctxt_t s_tfr_ctxt;
3260 tfr_ctxt_t *ps_tfr_cxt = &s_tfr_ctxt;
3261 pad_mgr_t *ps_pad_mgr = &ps_dec->s_pad_mgr;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3262
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3263 /*BS is done for all mbs while parsing*/
3264 u4_max_addr = (ps_dec->u2_frm_wd_in_mbs * ps_dec->u2_frm_ht_in_mbs) - 1;
3265 ps_dec->u4_cur_bs_mb_num = u4_max_addr + 1;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3266
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3267
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3268 ih264d_init_deblk_tfr_ctxt(ps_dec, ps_pad_mgr, ps_tfr_cxt,
3269 ps_dec->u2_frm_wd_in_mbs, 0);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3270
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3271
3272 u4_num_mbs = u4_max_addr
3273 - ps_dec->u4_cur_deblk_mb_num + 1;
3274
3275 DEBUG_PERF_PRINTF("mbs left for deblocking= %d \n",u4_num_mbs);
3276
3277 if(u4_num_mbs != 0)
3278 ih264d_check_mb_map_deblk(ps_dec, u4_num_mbs,
3279 ps_tfr_cxt,1);
3280
3281 ps_dec->u4_start_recon_deblk = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3282
3283 }
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3284
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3285 }
3286
3287 /*signal the decode thread*/
3288 ih264d_signal_decode_thread(ps_dec);
3289 /* close deblock thread if it is not closed yet*/
3290 if(ps_dec->u4_num_cores == 3)
3291 {
3292 ih264d_signal_bs_deblk_thread(ps_dec);
3293 }
3294 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3295
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3296
3297 DATA_SYNC();
3298
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3299
3300 if((ps_dec_op->u4_error_code & 0xff)
3301 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED)
3302 {
3303 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
3304 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
3305 }
3306
3307//Report if header (sps and pps) has not been decoded yet
3308 if(ps_dec->i4_header_decoded != 3)
3309 {
3310 ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA);
3311
3312 }
3313
3314 if(ps_dec->i4_decode_header == 1 && ps_dec->i4_header_decoded != 3)
3315 {
3316 ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA);
3317
3318 }
3319 if(ps_dec->u4_prev_nal_skipped)
3320 {
3321 /*We have encountered a referenced frame,return to app*/
3322 ps_dec_op->u4_error_code = IVD_DEC_FRM_SKIPPED;
3323 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
3324 ps_dec_op->u4_frame_decoded_flag = 0;
3325 ps_dec_op->u4_size = sizeof(ivd_video_decode_op_t);
3326 /* close deblock thread if it is not closed yet*/
3327 if(ps_dec->u4_num_cores == 3)
3328 {
3329 ih264d_signal_bs_deblk_thread(ps_dec);
3330 }
3331 return (IV_FAIL);
3332
3333 }
3334
3335 if((ps_dec->u4_slice_start_code_found == 1)
3336 && (ERROR_DANGLING_FIELD_IN_PIC != i4_err_status))
3337 {
3338 /*
3339 * For field pictures, set the bottom and top picture decoded u4_flag correctly.
3340 */
3341
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3342 if(ps_dec->ps_cur_slice->u1_field_pic_flag)
3343 {
3344 if(1 == ps_dec->ps_cur_slice->u1_bottom_field_flag)
3345 {
3346 ps_dec->u1_top_bottom_decoded |= BOT_FIELD_ONLY;
3347 }
3348 else
3349 {
3350 ps_dec->u1_top_bottom_decoded |= TOP_FIELD_ONLY;
3351 }
3352 }
Hamsalekha S77038222017-05-08 17:03:06 +0530[diff] [blame]3353 else
3354 {
3355 ps_dec->u1_top_bottom_decoded = TOP_FIELD_ONLY | BOT_FIELD_ONLY;
3356 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3357
Hamsalekha S9f0dcba2015-06-09 15:54:31 +0530[diff] [blame]3358 /* if new frame in not found (if we are still getting slices from previous frame)
3359 * ih264d_deblock_display is not called. Such frames will not be added to reference /display
3360 */
Harish Mahendrakar31836842016-12-26 11:02:13 +0530[diff] [blame]3361 if (((ps_dec->ps_dec_err_status->u1_err_flag & REJECT_CUR_PIC) == 0)
3362 && (ps_dec->u4_pic_buf_got == 1))
Hamsalekha S9f0dcba2015-06-09 15:54:31 +0530[diff] [blame]3363 {
3364 /* Calling Function to deblock Picture and Display */
3365 ret = ih264d_deblock_display(ps_dec);
Hamsalekha S9f0dcba2015-06-09 15:54:31 +0530[diff] [blame]3366 }
3367
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3368
3369 /*set to complete ,as we dont support partial frame decode*/
3370 if(ps_dec->i4_header_decoded == 3)
3371 {
3372 ps_dec->u2_total_mbs_coded = ps_dec->ps_cur_sps->u2_max_mb_addr + 1;
3373 }
3374
3375 /*Update the i4_frametype at the end of picture*/
3376 if(ps_dec->ps_cur_slice->u1_nal_unit_type == IDR_SLICE_NAL)
3377 {
3378 ps_dec->i4_frametype = IV_IDR_FRAME;
3379 }
3380 else if(ps_dec->i4_pic_type == B_SLICE)
3381 {
3382 ps_dec->i4_frametype = IV_B_FRAME;
3383 }
3384 else if(ps_dec->i4_pic_type == P_SLICE)
3385 {
3386 ps_dec->i4_frametype = IV_P_FRAME;
3387 }
3388 else if(ps_dec->i4_pic_type == I_SLICE)
3389 {
3390 ps_dec->i4_frametype = IV_I_FRAME;
3391 }
3392 else
3393 {
3394 H264_DEC_DEBUG_PRINT("Shouldn't come here\n");
3395 }
3396
3397 //Update the content type
3398 ps_dec->i4_content_type = ps_dec->ps_cur_slice->u1_field_pic_flag;
3399
3400 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded + 2;
3401 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded
3402 - ps_dec->ps_cur_slice->u1_field_pic_flag;
3403
3404 }
3405
3406 /* close deblock thread if it is not closed yet*/
3407 if(ps_dec->u4_num_cores == 3)
3408 {
3409 ih264d_signal_bs_deblk_thread(ps_dec);
3410 }
3411
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3412
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3413 {
3414 /* In case the decoder is configured to run in low delay mode,
3415 * then get display buffer and then format convert.
3416 * Note in this mode, format conversion does not run paralelly in a thread and adds to the codec cycles
3417 */
3418
3419 if((0 == ps_dec->u4_num_reorder_frames_at_init)
3420 && ps_dec->u1_init_dec_flag)
3421 {
3422
3423 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer,
3424 &(ps_dec->s_disp_op));
3425 if(0 == ps_dec->s_disp_op.u4_error_code)
3426 {
3427 ps_dec->u4_fmt_conv_cur_row = 0;
3428 ps_dec->u4_output_present = 1;
3429 }
3430 }
3431
3432 ih264d_fill_output_struct_from_context(ps_dec, ps_dec_op);
3433
3434 /* If Format conversion is not complete,
3435 complete it here */
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3436 if(ps_dec->u4_output_present &&
3437 (ps_dec->u4_fmt_conv_cur_row < ps_dec->s_disp_frame_info.u4_y_ht))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3438 {
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3439 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht
3440 - ps_dec->u4_fmt_conv_cur_row;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3441 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op),
3442 ps_dec->u4_fmt_conv_cur_row,
3443 ps_dec->u4_fmt_conv_num_rows);
3444 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows;
3445 }
3446
3447 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op));
3448 }
3449
3450 if(ps_dec->i4_decode_header == 1 && (ps_dec->i4_header_decoded & 1) == 1)
3451 {
3452 ps_dec_op->u4_progressive_frame_flag = 1;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3453 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3454 {
3455 if((0 == ps_dec->ps_sps->u1_frame_mbs_only_flag)
3456 && (0 == ps_dec->ps_sps->u1_mb_aff_flag))
3457 ps_dec_op->u4_progressive_frame_flag = 0;
3458
3459 }
3460 }
3461
Harish Mahendrakar49456122017-01-05 12:10:47 +0530[diff] [blame]3462 if((TOP_FIELD_ONLY | BOT_FIELD_ONLY) == ps_dec->u1_top_bottom_decoded)
3463 {
3464 ps_dec->u1_top_bottom_decoded = 0;
3465 }
3466 /*--------------------------------------------------------------------*/
3467 /* Do End of Pic processing. */
3468 /* Should be called only if frame was decoded in previous process call*/
3469 /*--------------------------------------------------------------------*/
3470 if(ps_dec->u4_pic_buf_got == 1)
3471 {
3472 if(1 == ps_dec->u1_last_pic_not_decoded)
3473 {
3474 ret = ih264d_end_of_pic_dispbuf_mgr(ps_dec);
3475
3476 if(ret != OK)
3477 return ret;
3478
3479 ret = ih264d_end_of_pic(ps_dec);
3480 if(ret != OK)
3481 return ret;
3482 }
3483 else
3484 {
3485 ret = ih264d_end_of_pic(ps_dec);
3486 if(ret != OK)
3487 return ret;
3488 }
3489
3490 }
3491
3492
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3493 /*Data memory barrier instruction,so that yuv write by the library is complete*/
3494 DATA_SYNC();
3495
3496 H264_DEC_DEBUG_PRINT("The num bytes consumed: %d\n",
3497 ps_dec_op->u4_num_bytes_consumed);
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3498 return api_ret_value;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3499}
3500
3501WORD32 ih264d_get_version(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3502{
3503 char version_string[MAXVERSION_STRLEN + 1];
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3504 UWORD32 version_string_len;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3505
3506 ivd_ctl_getversioninfo_ip_t *ps_ip;
3507 ivd_ctl_getversioninfo_op_t *ps_op;
3508
3509 ps_ip = (ivd_ctl_getversioninfo_ip_t *)pv_api_ip;
3510 ps_op = (ivd_ctl_getversioninfo_op_t *)pv_api_op;
3511 UNUSED(dec_hdl);
3512 ps_op->u4_error_code = IV_SUCCESS;
3513
3514 VERSION(version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER,
3515 CODEC_VENDOR);
3516
3517 if((WORD32)ps_ip->u4_version_buffer_size <= 0)
3518 {
3519 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT;
3520 return (IV_FAIL);
3521 }
3522
Martin Storsjo85a43d22015-05-20 00:12:28 +0300[diff] [blame]3523 version_string_len = strlen(version_string) + 1;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3524
3525 if(ps_ip->u4_version_buffer_size >= version_string_len) //(WORD32)sizeof(sizeof(version_string)))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3526 {
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3527 memcpy(ps_ip->pv_version_buffer, version_string, version_string_len);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3528 ps_op->u4_error_code = IV_SUCCESS;
3529 }
3530 else
3531 {
3532 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT;
3533 return IV_FAIL;
3534 }
3535 return (IV_SUCCESS);
3536}
3537
3538/*****************************************************************************/
3539/* */
3540/* Function Name : ih264d_get_display_frame */
3541/* */
3542/* Description : */
3543/* Inputs :iv_obj_t decoder handle */
3544/* :pv_api_ip pointer to input structure */
3545/* :pv_api_op pointer to output structure */
3546/* Outputs : */
3547/* Returns : void */
3548/* */
3549/* Issues : none */
3550/* */
3551/* Revision History: */
3552/* */
3553/* DD MM YYYY Author(s) Changes (Describe the changes made) */
3554/* 22 10 2008 100356 Draft */
3555/* */
3556/*****************************************************************************/
3557WORD32 ih264d_get_display_frame(iv_obj_t *dec_hdl,
3558 void *pv_api_ip,
3559 void *pv_api_op)
3560{
3561
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3562 UNUSED(dec_hdl);
3563 UNUSED(pv_api_ip);
3564 UNUSED(pv_api_op);
3565 // This function is no longer needed, output is returned in the process()
3566 return IV_FAIL;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3567}
3568
3569/*****************************************************************************/
3570/* */
3571/* Function Name : ih264d_set_display_frame */
3572/* */
3573/* Description : */
3574/* */
3575/* Inputs :iv_obj_t decoder handle */
3576/* :pv_api_ip pointer to input structure */
3577/* :pv_api_op pointer to output structure */
3578/* Outputs : */
3579/* Returns : void */
3580/* */
3581/* Issues : none */
3582/* */
3583/* Revision History: */
3584/* */
3585/* DD MM YYYY Author(s) Changes (Describe the changes made) */
3586/* 22 10 2008 100356 Draft */
3587/* */
3588/*****************************************************************************/
3589WORD32 ih264d_set_display_frame(iv_obj_t *dec_hdl,
3590 void *pv_api_ip,
3591 void *pv_api_op)
3592{
3593
3594 ivd_set_display_frame_ip_t *dec_disp_ip;
3595 ivd_set_display_frame_op_t *dec_disp_op;
3596
3597 UWORD32 i, num_mvbank_req;
3598 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3599
3600 dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip;
3601 dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op;
3602 dec_disp_op->u4_error_code = 0;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3603 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3604 {
3605 UWORD32 level, width_mbs, height_mbs;
3606
3607 level = ps_dec->u4_level_at_init;
3608 width_mbs = ps_dec->u2_frm_wd_in_mbs;
3609 height_mbs = ps_dec->u2_frm_ht_in_mbs;
3610
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3611 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1)
3612 && (ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames != 64))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3613 {
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3614 num_mvbank_req = ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 2;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3615 }
3616 else
3617 {
3618 /*if VUI is not present assume maximum possible refrence frames for the level,
3619 * as max reorder frames*/
3620 num_mvbank_req = ih264d_get_dpb_size_new(level, width_mbs,
3621 height_mbs);
3622 }
3623
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3624 num_mvbank_req += ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3625 }
3626 else
3627 {
3628 UWORD32 num_bufs_app, num_bufs_level;
3629 UWORD32 num_ref_frames, num_reorder_frames, luma_width;
3630 UWORD32 luma_height, level;
3631
3632 num_ref_frames = ps_dec->u4_num_ref_frames_at_init;
3633 num_reorder_frames = ps_dec->u4_num_reorder_frames_at_init;
3634 level = ps_dec->u4_level_at_init;
3635 luma_width = ps_dec->u4_width_at_init;
3636 luma_height = ps_dec->u4_height_at_init;
3637
3638 num_bufs_app = num_ref_frames + num_reorder_frames + 1;
3639
3640 if(num_bufs_app <= 1)
3641 num_bufs_app = 2;
3642
3643 num_bufs_level = ih264d_get_dpb_size_new(level, (luma_width >> 4),
3644 (luma_height >> 4));
3645
3646 num_bufs_level = num_bufs_level * 2 + 1;
3647
3648 num_mvbank_req = MIN(num_bufs_level, num_bufs_app);
3649
3650 num_mvbank_req += ps_dec->u4_num_extra_disp_bufs_at_init;
3651
3652 }
3653
3654 ps_dec->u4_num_disp_bufs = 0;
3655 if(ps_dec->u4_share_disp_buf)
3656 {
3657 UWORD32 u4_num_bufs = dec_disp_ip->num_disp_bufs;
3658 if(u4_num_bufs > MAX_DISP_BUFS_NEW)
3659 u4_num_bufs = MAX_DISP_BUFS_NEW;
3660
3661 u4_num_bufs = MIN(u4_num_bufs, MAX_DISP_BUFS_NEW);
3662 u4_num_bufs = MIN(u4_num_bufs, num_mvbank_req);
3663
3664 ps_dec->u4_num_disp_bufs = u4_num_bufs;
3665 for(i = 0; i < u4_num_bufs; i++)
3666 {
3667 ps_dec->disp_bufs[i].u4_num_bufs =
3668 dec_disp_ip->s_disp_buffer[i].u4_num_bufs;
3669
3670 ps_dec->disp_bufs[i].buf[0] =
3671 dec_disp_ip->s_disp_buffer[i].pu1_bufs[0];
3672 ps_dec->disp_bufs[i].buf[1] =
3673 dec_disp_ip->s_disp_buffer[i].pu1_bufs[1];
3674 ps_dec->disp_bufs[i].buf[2] =
3675 dec_disp_ip->s_disp_buffer[i].pu1_bufs[2];
3676
3677 ps_dec->disp_bufs[i].u4_bufsize[0] =
3678 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0];
3679 ps_dec->disp_bufs[i].u4_bufsize[1] =
3680 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1];
3681 ps_dec->disp_bufs[i].u4_bufsize[2] =
3682 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2];
3683
3684 }
3685 }
3686 return IV_SUCCESS;
3687
3688}
3689
3690/*****************************************************************************/
3691/* */
3692/* Function Name : ih264d_set_flush_mode */
3693/* */
3694/* Description : */
3695/* */
3696/* Inputs :iv_obj_t decoder handle */
3697/* :pv_api_ip pointer to input structure */
3698/* :pv_api_op pointer to output structure */
3699/* Globals : <Does it use any global variables?> */
3700/* Outputs : */
3701/* Returns : void */
3702/* */
3703/* Issues : none */
3704/* */
3705/* Revision History: */
3706/* */
3707/* DD MM YYYY Author(s) Changes (Describe the changes made) */
3708/* 22 10 2008 100356 Draft */
3709/* */
3710/*****************************************************************************/
3711WORD32 ih264d_set_flush_mode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3712{
3713
3714 dec_struct_t * ps_dec;
3715 ivd_ctl_flush_op_t *ps_ctl_op = (ivd_ctl_flush_op_t*)pv_api_op;
3716 ps_ctl_op->u4_error_code = 0;
3717
3718 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3719 UNUSED(pv_api_ip);
3720 /* ! */
3721 /* Signal flush frame control call */
3722 ps_dec->u1_flushfrm = 1;
3723
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3724 if( ps_dec->u1_init_dec_flag == 1)
3725 {
3726
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3727 ih264d_release_pics_in_dpb((void *)ps_dec,
3728 ps_dec->u1_pic_bufs);
3729 ih264d_release_display_bufs(ps_dec);
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3730 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3731
3732 ps_ctl_op->u4_error_code =
3733 ((ivd_ctl_flush_op_t*)ps_dec->pv_dec_out)->u4_error_code; //verify the value
3734
3735 return IV_SUCCESS;
3736
3737}
3738
3739/*****************************************************************************/
3740/* */
3741/* Function Name : ih264d_get_status */
3742/* */
3743/* Description : */
3744/* */
3745/* Inputs :iv_obj_t decoder handle */
3746/* :pv_api_ip pointer to input structure */
3747/* :pv_api_op pointer to output structure */
3748/* Globals : <Does it use any global variables?> */
3749/* Outputs : */
3750/* Returns : void */
3751/* */
3752/* Issues : none */
3753/* */
3754/* Revision History: */
3755/* */
3756/* DD MM YYYY Author(s) Changes (Describe the changes made) */
3757/* 22 10 2008 100356 Draft */
3758/* */
3759/*****************************************************************************/
3760
3761WORD32 ih264d_get_status(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3762{
3763
3764 UWORD32 i;
3765 dec_struct_t * ps_dec;
3766 UWORD32 pic_wd, pic_ht;
3767 ivd_ctl_getstatus_op_t *ps_ctl_op = (ivd_ctl_getstatus_op_t*)pv_api_op;
3768 UNUSED(pv_api_ip);
3769 ps_ctl_op->u4_error_code = 0;
3770
3771 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3772
3773 pic_wd = ps_dec->u4_width_at_init;
3774 pic_ht = ps_dec->u4_height_at_init;
3775
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3776 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3777 {
3778 ps_ctl_op->u4_pic_ht = ps_dec->u2_disp_height;
3779 ps_ctl_op->u4_pic_wd = ps_dec->u2_disp_width;
3780
3781 if(0 == ps_dec->u4_share_disp_buf)
3782 {
3783 pic_wd = ps_dec->u2_disp_width;
3784 pic_ht = ps_dec->u2_disp_height;
3785
3786 }
3787 else
3788 {
3789 pic_wd = ps_dec->u2_frm_wd_y;
3790 pic_ht = ps_dec->u2_frm_ht_y;
3791 }
3792 }
3793 else
3794 {
3795 ps_ctl_op->u4_pic_ht = pic_wd;
3796 ps_ctl_op->u4_pic_wd = pic_ht;
3797
3798 if(1 == ps_dec->u4_share_disp_buf)
3799 {
3800 pic_wd += (PAD_LEN_Y_H << 1);
3801 pic_ht += (PAD_LEN_Y_V << 2);
3802
3803 }
3804
3805 }
3806
3807 if(ps_dec->u4_app_disp_width > pic_wd)
3808 pic_wd = ps_dec->u4_app_disp_width;
3809 if(0 == ps_dec->u4_share_disp_buf)
3810 ps_ctl_op->u4_num_disp_bufs = 1;
3811 else
3812 {
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3813 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3814 {
3815 UWORD32 level, width_mbs, height_mbs;
3816
3817 level = ps_dec->u4_level_at_init;
3818 width_mbs = ps_dec->u2_frm_wd_in_mbs;
3819 height_mbs = ps_dec->u2_frm_ht_in_mbs;
3820
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3821 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1)
3822 && (ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3823 != 64))
3824 {
3825 ps_ctl_op->u4_num_disp_bufs =
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3826 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 2;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3827 }
3828 else
3829 {
3830 /*if VUI is not present assume maximum possible refrence frames for the level,
3831 * as max reorder frames*/
3832 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size_new(
3833 level, width_mbs, height_mbs);
3834 }
3835
3836 ps_ctl_op->u4_num_disp_bufs +=
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3837 ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3838 }
3839 else
3840 {
3841 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size_new(
3842 ps_dec->u4_level_at_init,
3843 (ps_dec->u4_width_at_init >> 4),
3844 (ps_dec->u4_height_at_init >> 4));
3845
3846 ps_ctl_op->u4_num_disp_bufs +=
3847 ps_ctl_op->u4_num_disp_bufs;
3848
3849 ps_ctl_op->u4_num_disp_bufs =
3850 MIN(ps_ctl_op->u4_num_disp_bufs,
3851 (ps_dec->u4_num_ref_frames_at_init
3852 + ps_dec->u4_num_reorder_frames_at_init));
3853
3854 }
3855
3856 ps_ctl_op->u4_num_disp_bufs = MAX(
3857 ps_ctl_op->u4_num_disp_bufs, 6);
3858 ps_ctl_op->u4_num_disp_bufs = MIN(
3859 ps_ctl_op->u4_num_disp_bufs, 32);
3860 }
3861
3862 ps_ctl_op->u4_error_code = ps_dec->i4_error_code;
3863
3864 ps_ctl_op->u4_frame_rate = 0; //make it proper
3865 ps_ctl_op->u4_bit_rate = 0; //make it proper
3866 ps_ctl_op->e_content_type = ps_dec->i4_content_type;
3867 ps_ctl_op->e_output_chroma_format = ps_dec->u1_chroma_format;
3868 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS;
3869
3870 if(ps_dec->u1_chroma_format == IV_YUV_420P)
3871 {
3872 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420;
3873 }
3874 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE)
3875 {
3876 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
3877 }
3878 else if(ps_dec->u1_chroma_format == IV_RGB_565)
3879 {
3880 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
3881 }
3882 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
3883 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
3884 {
3885 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420SP;
3886 }
3887
3888 else
3889 {
3890 //Invalid chroma format; Error code may be updated, verify in testing if needed
3891 ps_ctl_op->u4_error_code = ERROR_FEATURE_UNAVAIL;
3892 return IV_FAIL;
3893 }
3894
3895 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++)
3896 {
3897 ps_ctl_op->u4_min_in_buf_size[i] = MIN_IN_BUF_SIZE;
3898 }
3899
3900 /*!*/
3901 if(ps_dec->u1_chroma_format == IV_YUV_420P)
3902 {
3903 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
3904 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
3905 >> 2;
3906 ps_ctl_op->u4_min_out_buf_size[2] = (pic_wd * pic_ht)
3907 >> 2;
3908 }
3909 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE)
3910 {
3911 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
3912 * 2;
3913 ps_ctl_op->u4_min_out_buf_size[1] =
3914 ps_ctl_op->u4_min_out_buf_size[2] = 0;
3915 }
3916 else if(ps_dec->u1_chroma_format == IV_RGB_565)
3917 {
3918 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
3919 * 2;
3920 ps_ctl_op->u4_min_out_buf_size[1] =
3921 ps_ctl_op->u4_min_out_buf_size[2] = 0;
3922 }
3923 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
3924 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
3925 {
3926 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
3927 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
3928 >> 1;
3929 ps_ctl_op->u4_min_out_buf_size[2] = 0;
3930 }
3931
3932 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs;
3933 return IV_SUCCESS;
3934}
3935
3936/*****************************************************************************/
3937/* */
3938/* Function Name : ih264d_get_buf_info */
3939/* */
3940/* Description : */
3941/* */
3942/* Inputs :iv_obj_t decoder handle */
3943/* :pv_api_ip pointer to input structure */
3944/* :pv_api_op pointer to output structure */
3945/* Globals : <Does it use any global variables?> */
3946/* Outputs : */
3947/* Returns : void */
3948/* */
3949/* Issues : none */
3950/* */
3951/* Revision History: */
3952/* */
3953/* DD MM YYYY Author(s) Changes (Describe the changes made) */
3954/* 22 10 2008 100356 Draft */
3955/* */
3956/*****************************************************************************/
3957WORD32 ih264d_get_buf_info(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3958{
3959
3960 dec_struct_t * ps_dec;
3961 UWORD8 i = 0; // Default for 420P format
3962 UWORD16 pic_wd, pic_ht;
3963 ivd_ctl_getbufinfo_op_t *ps_ctl_op =
3964 (ivd_ctl_getbufinfo_op_t*)pv_api_op;
Hamsalekha S3f6c9412017-06-01 11:44:39 +0530[diff] [blame^]3965 UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS];
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3966 UNUSED(pv_api_ip);
Hamsalekha S3f6c9412017-06-01 11:44:39 +0530[diff] [blame^]3967
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3968 ps_ctl_op->u4_error_code = 0;
3969
3970 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3971
3972 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3973
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3974
3975 ps_ctl_op->u4_num_disp_bufs = 1;
3976
3977 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++)
3978 {
3979 ps_ctl_op->u4_min_in_buf_size[i] = MIN_IN_BUF_SIZE;
3980 }
3981
3982 pic_wd = ps_dec->u4_width_at_init;
3983 pic_ht = ps_dec->u4_height_at_init;
3984
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3985 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3986 {
3987
3988 if(0 == ps_dec->u4_share_disp_buf)
3989 {
3990 pic_wd = ps_dec->u2_disp_width;
3991 pic_ht = ps_dec->u2_disp_height;
3992
3993 }
3994 else
3995 {
3996 pic_wd = ps_dec->u2_frm_wd_y;
3997 pic_ht = ps_dec->u2_frm_ht_y;
3998 }
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3999
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4000 }
4001 else
4002 {
4003 if(1 == ps_dec->u4_share_disp_buf)
4004 {
4005 pic_wd += (PAD_LEN_Y_H << 1);
4006 pic_ht += (PAD_LEN_Y_V << 2);
4007
4008 }
4009 }
4010
4011 if((WORD32)ps_dec->u4_app_disp_width > pic_wd)
4012 pic_wd = ps_dec->u4_app_disp_width;
4013
4014 if(0 == ps_dec->u4_share_disp_buf)
4015 ps_ctl_op->u4_num_disp_bufs = 1;
4016 else
4017 {
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]4018 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4019 {
4020 UWORD32 level, width_mbs, height_mbs;
4021
4022 level = ps_dec->u4_level_at_init;
4023 width_mbs = ps_dec->u2_frm_wd_in_mbs;
4024 height_mbs = ps_dec->u2_frm_ht_in_mbs;
4025
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]4026 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1)
4027 && (ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4028 != 64))
4029 {
4030 ps_ctl_op->u4_num_disp_bufs =
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]4031 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 2;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4032 }
4033 else
4034 {
4035 /*if VUI is not present assume maximum possible refrence frames for the level,
4036 * as max reorder frames*/
4037 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size_new(
4038 level, width_mbs, height_mbs);
4039 }
4040
4041 ps_ctl_op->u4_num_disp_bufs +=
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]4042 ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4043
4044 }
4045 else
4046 {
4047 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size_new(
4048 ps_dec->u4_level_at_init,
4049 (ps_dec->u4_width_at_init >> 4),
4050 (ps_dec->u4_height_at_init >> 4));
4051
4052 ps_ctl_op->u4_num_disp_bufs +=
4053 ps_ctl_op->u4_num_disp_bufs;
4054
4055 ps_ctl_op->u4_num_disp_bufs =
4056 MIN(ps_ctl_op->u4_num_disp_bufs,
4057 (ps_dec->u4_num_ref_frames_at_init
4058 + ps_dec->u4_num_reorder_frames_at_init));
4059
4060 }
4061
4062 ps_ctl_op->u4_num_disp_bufs = MAX(
4063 ps_ctl_op->u4_num_disp_bufs, 6);
4064 ps_ctl_op->u4_num_disp_bufs = MIN(
4065 ps_ctl_op->u4_num_disp_bufs, 32);
4066 }
4067
Hamsalekha S3f6c9412017-06-01 11:44:39 +0530[diff] [blame^]4068 ps_ctl_op->u4_min_num_out_bufs = ih264d_get_outbuf_size(
4069 pic_wd, pic_ht, ps_dec->u1_chroma_format,
4070 &au4_min_out_buf_size[0]);
4071
4072 for(i = 0; i < ps_ctl_op->u4_min_num_out_bufs; i++)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4073 {
Hamsalekha S3f6c9412017-06-01 11:44:39 +0530[diff] [blame^]4074 ps_ctl_op->u4_min_out_buf_size[i] = au4_min_out_buf_size[i];
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4075 }
Hamsalekha S3f6c9412017-06-01 11:44:39 +0530[diff] [blame^]4076
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4077 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs;
4078
4079 return IV_SUCCESS;
4080}
4081
4082/*****************************************************************************/
4083/* */
4084/* Function Name : ih264d_set_params */
4085/* */
4086/* Description : */
4087/* */
4088/* Inputs :iv_obj_t decoder handle */
4089/* :pv_api_ip pointer to input structure */
4090/* :pv_api_op pointer to output structure */
4091/* Outputs : */
4092/* Returns : void */
4093/* */
4094/* Issues : none */
4095/* */
4096/* Revision History: */
4097/* */
4098/* DD MM YYYY Author(s) Changes (Describe the changes made) */
4099/* 22 10 2008 100356 Draft */
4100/* */
4101/*****************************************************************************/
4102WORD32 ih264d_set_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
4103{
4104
4105 dec_struct_t * ps_dec;
4106 WORD32 ret = IV_SUCCESS;
4107
4108 ivd_ctl_set_config_ip_t *ps_ctl_ip =
4109 (ivd_ctl_set_config_ip_t *)pv_api_ip;
4110 ivd_ctl_set_config_op_t *ps_ctl_op =
4111 (ivd_ctl_set_config_op_t *)pv_api_op;
4112
4113 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
4114
4115 ps_dec->u4_skip_frm_mask = 0;
4116
4117 ps_ctl_op->u4_error_code = 0;
4118
4119 ps_dec->i4_app_skip_mode = ps_ctl_ip->e_frm_skip_mode;
4120
4121 /*Is it really supported test it when you so the corner testing using test app*/
4122
4123 if(ps_ctl_ip->e_frm_skip_mode != IVD_SKIP_NONE)
4124 {
4125
4126 if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_P)
4127 ps_dec->u4_skip_frm_mask |= 1 << P_SLC_BIT;
4128 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_B)
4129 ps_dec->u4_skip_frm_mask |= 1 << B_SLC_BIT;
4130 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_PB)
4131 {
4132 ps_dec->u4_skip_frm_mask |= 1 << B_SLC_BIT;
4133 ps_dec->u4_skip_frm_mask |= 1 << P_SLC_BIT;
4134 }
4135 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_I)
4136 ps_dec->u4_skip_frm_mask |= 1 << I_SLC_BIT;
4137 else
4138 {
4139 //dynamic parameter not supported
4140 //Put an appropriate error code to return the error..
4141 //when you do the error code tests and after that remove this comment
4142 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
4143 ret = IV_FAIL;
4144 }
4145 }
4146
4147 if((0 != ps_dec->u4_app_disp_width)
4148 && (ps_ctl_ip->u4_disp_wd
4149 != ps_dec->u4_app_disp_width))
4150 {
4151 ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
4152 ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID;
4153 ret = IV_FAIL;
4154 }
4155 else
4156 {
4157 if((ps_ctl_ip->u4_disp_wd >= ps_dec->u2_pic_wd)/* && (ps_ctl_ip->u4_disp_wd <= ps_dec->u4_width_at_init) */)
4158 {
4159 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd;
4160 }
4161 else if((0 == ps_dec->i4_header_decoded) /*&& (ps_ctl_ip->u4_disp_wd <= ps_dec->u4_width_at_init)*/)
4162 {
4163 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd;
4164 }
4165 else if(ps_ctl_ip->u4_disp_wd == 0)
4166 {
4167 ps_dec->u4_app_disp_width = 0;
4168 }
4169 else
4170 {
4171 /*
4172 * Set the display width to zero. This will ensure that the wrong value we had stored (0xFFFFFFFF)
4173 * does not propogate.
4174 */
4175 ps_dec->u4_app_disp_width = 0;
4176 ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
4177 ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID;
4178 ret = IV_FAIL;
4179 }
4180 }
4181 if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_FRAME)
4182 ps_dec->i4_decode_header = 0;
4183 else if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_HEADER)
4184 ps_dec->i4_decode_header = 1;
4185 else
4186 {
4187 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
4188 ps_dec->i4_decode_header = 1;
4189 ret = IV_FAIL;
4190 }
4191
4192 return ret;
4193
4194}
4195
4196/*****************************************************************************/
4197/* */
4198/* Function Name : ih264d_set_default_params */
4199/* */
4200/* Description : */
4201/* */
4202/* Inputs :iv_obj_t decoder handle */
4203/* :pv_api_ip pointer to input structure */
4204/* :pv_api_op pointer to output structure */
4205/* Outputs : */
4206/* Returns : void */
4207/* */
4208/* Issues : none */
4209/* */
4210/* Revision History: */
4211/* */
4212/* DD MM YYYY Author(s) Changes (Describe the changes made) */
4213/* 08 08 2011 100421 Copied from set_params */
4214/* */
4215/*****************************************************************************/
4216WORD32 ih264d_set_default_params(iv_obj_t *dec_hdl,
4217 void *pv_api_ip,
4218 void *pv_api_op)
4219{
4220
4221 dec_struct_t * ps_dec;
4222 WORD32 ret = IV_SUCCESS;
4223
4224 ivd_ctl_set_config_op_t *ps_ctl_op =
4225 (ivd_ctl_set_config_op_t *)pv_api_op;
4226 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
4227 UNUSED(pv_api_ip);
4228
4229
4230 {
4231 ps_dec->u4_app_disp_width = 0;
4232 ps_dec->u4_skip_frm_mask = 0;
4233 ps_dec->i4_decode_header = 1;
4234
4235 ps_ctl_op->u4_error_code = 0;
4236 }
4237
4238
4239 return ret;
4240}
4241
4242/*****************************************************************************/
4243/* */
4244/* Function Name : ih264d_reset */
4245/* */
4246/* Description : */
4247/* */
4248/* Inputs :iv_obj_t decoder handle */
4249/* :pv_api_ip pointer to input structure */
4250/* :pv_api_op pointer to output structure */
4251/* Globals : <Does it use any global variables?> */
4252/* Outputs : */
4253/* Returns : void */
4254/* */
4255/* Issues : none */
4256/* */
4257/* Revision History: */
4258/* */
4259/* DD MM YYYY Author(s) Changes (Describe the changes made) */
4260/* 22 10 2008 100356 Draft */
4261/* */
4262/*****************************************************************************/
4263WORD32 ih264d_reset(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
4264{
4265 dec_struct_t * ps_dec;
4266 ivd_ctl_reset_op_t *ps_ctl_op = (ivd_ctl_reset_op_t *)pv_api_op;
4267 UNUSED(pv_api_ip);
4268 ps_ctl_op->u4_error_code = 0;
4269
4270 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
4271//CHECK
4272 if(ps_dec != NULL)
4273 {
4274
4275 ih264d_init_decoder(ps_dec);
4276
4277 /*
4278 memset(ps_dec->disp_bufs, 0, (MAX_DISP_BUFS_NEW) * sizeof(disp_buf_t));
4279 memset(ps_dec->u4_disp_buf_mapping, 0, (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
4280 memset(ps_dec->u4_disp_buf_to_be_freed, 0, (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
4281 */
4282 }
4283 else
4284 {
4285 H264_DEC_DEBUG_PRINT(
4286 "\nReset called without Initializing the decoder\n");
4287 ps_ctl_op->u4_error_code = ERROR_INIT_NOT_DONE;
4288 }
4289
4290 return IV_SUCCESS;
4291}
4292
4293/*****************************************************************************/
4294/* */
4295/* Function Name : ih264d_ctl */
4296/* */
4297/* Description : */
4298/* */
4299/* Inputs :iv_obj_t decoder handle */
4300/* :pv_api_ip pointer to input structure */
4301/* :pv_api_op pointer to output structure */
4302/* Outputs : */
4303/* Returns : void */
4304/* */
4305/* Issues : none */
4306/* */
4307/* Revision History: */
4308/* */
4309/* DD MM YYYY Author(s) Changes (Describe the changes made) */
4310/* 22 10 2008 100356 Draft */
4311/* */
4312/*****************************************************************************/
4313WORD32 ih264d_ctl(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
4314{
4315 ivd_ctl_set_config_ip_t *ps_ctl_ip;
4316 ivd_ctl_set_config_op_t *ps_ctl_op;
4317 WORD32 ret = IV_SUCCESS;
4318 UWORD32 subcommand;
4319 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4320
4321 if(ps_dec->init_done != 1)
4322 {
4323 //Return proper Error Code
4324 return IV_FAIL;
4325 }
4326 ps_ctl_ip = (ivd_ctl_set_config_ip_t*)pv_api_ip;
4327 ps_ctl_op = (ivd_ctl_set_config_op_t*)pv_api_op;
4328 ps_ctl_op->u4_error_code = 0;
4329 subcommand = ps_ctl_ip->e_sub_cmd;
4330
4331 switch(subcommand)
4332 {
4333 case IVD_CMD_CTL_GETPARAMS:
4334 ret = ih264d_get_status(dec_hdl, (void *)pv_api_ip,
4335 (void *)pv_api_op);
4336 break;
4337 case IVD_CMD_CTL_SETPARAMS:
4338 ret = ih264d_set_params(dec_hdl, (void *)pv_api_ip,
4339 (void *)pv_api_op);
4340 break;
4341 case IVD_CMD_CTL_RESET:
4342 ret = ih264d_reset(dec_hdl, (void *)pv_api_ip, (void *)pv_api_op);
4343 break;
4344 case IVD_CMD_CTL_SETDEFAULT:
4345 ret = ih264d_set_default_params(dec_hdl, (void *)pv_api_ip,
4346 (void *)pv_api_op);
4347 break;
4348 case IVD_CMD_CTL_FLUSH:
4349 ret = ih264d_set_flush_mode(dec_hdl, (void *)pv_api_ip,
4350 (void *)pv_api_op);
4351 break;
4352 case IVD_CMD_CTL_GETBUFINFO:
4353 ret = ih264d_get_buf_info(dec_hdl, (void *)pv_api_ip,
4354 (void *)pv_api_op);
4355 break;
4356 case IVD_CMD_CTL_GETVERSION:
4357 ret = ih264d_get_version(dec_hdl, (void *)pv_api_ip,
4358 (void *)pv_api_op);
4359 break;
4360 case IH264D_CMD_CTL_DEGRADE:
4361 ret = ih264d_set_degrade(dec_hdl, (void *)pv_api_ip,
4362 (void *)pv_api_op);
4363 break;
4364
4365 case IH264D_CMD_CTL_SET_NUM_CORES:
4366 ret = ih264d_set_num_cores(dec_hdl, (void *)pv_api_ip,
4367 (void *)pv_api_op);
4368 break;
4369 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS:
4370 ret = ih264d_get_frame_dimensions(dec_hdl, (void *)pv_api_ip,
4371 (void *)pv_api_op);
4372 break;
4373 case IH264D_CMD_CTL_SET_PROCESSOR:
4374 ret = ih264d_set_processor(dec_hdl, (void *)pv_api_ip,
4375 (void *)pv_api_op);
4376 break;
4377 default:
4378 H264_DEC_DEBUG_PRINT("\ndo nothing\n")
4379 ;
4380 break;
4381 }
4382
4383 return ret;
4384}
4385/*****************************************************************************/
4386/* */
4387/* Function Name : ih264d_rel_display_frame */
4388/* */
4389/* Description : */
4390/* */
4391/* Inputs :iv_obj_t decoder handle */
4392/* :pv_api_ip pointer to input structure */
4393/* :pv_api_op pointer to output structure */
4394/* Outputs : */
4395/* Returns : void */
4396/* */
4397/* Issues : none */
4398/* */
4399/* Revision History: */
4400/* */
4401/* DD MM YYYY Author(s) Changes (Describe the changes made) */
4402/* 22 10 2008 100356 Draft */
4403/* */
4404/*****************************************************************************/
4405WORD32 ih264d_rel_display_frame(iv_obj_t *dec_hdl,
4406 void *pv_api_ip,
4407 void *pv_api_op)
4408{
4409
4410 ivd_rel_display_frame_ip_t *ps_rel_ip;
4411 ivd_rel_display_frame_op_t *ps_rel_op;
4412 UWORD32 buf_released = 0;
4413
4414 UWORD32 u4_ts = -1;
4415 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4416
4417 ps_rel_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip;
4418 ps_rel_op = (ivd_rel_display_frame_op_t *)pv_api_op;
4419 ps_rel_op->u4_error_code = 0;
4420 u4_ts = ps_rel_ip->u4_disp_buf_id;
4421
4422 if(0 == ps_dec->u4_share_disp_buf)
4423 {
4424 ps_dec->u4_disp_buf_mapping[u4_ts] = 0;
4425 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 0;
4426 return IV_SUCCESS;
4427 }
4428
4429 if(ps_dec->pv_pic_buf_mgr != NULL)
4430 {
4431 if(1 == ps_dec->u4_disp_buf_mapping[u4_ts])
4432 {
4433 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
4434 ps_rel_ip->u4_disp_buf_id,
4435 BUF_MGR_IO);
4436 ps_dec->u4_disp_buf_mapping[u4_ts] = 0;
4437 buf_released = 1;
4438 }
4439 }
4440
4441 if((1 == ps_dec->u4_share_disp_buf) && (0 == buf_released))
4442 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 1;
4443
4444 return IV_SUCCESS;
4445}
4446
4447/**
4448 *******************************************************************************
4449 *
4450 * @brief
4451 * Sets degrade params
4452 *
4453 * @par Description:
4454 * Sets degrade params.
4455 * Refer to ih264d_ctl_degrade_ip_t definition for details
4456 *
4457 * @param[in] ps_codec_obj
4458 * Pointer to codec object at API level
4459 *
4460 * @param[in] pv_api_ip
4461 * Pointer to input argument structure
4462 *
4463 * @param[out] pv_api_op
4464 * Pointer to output argument structure
4465 *
4466 * @returns Status
4467 *
4468 * @remarks
4469 *
4470 *
4471 *******************************************************************************
4472 */
4473
4474WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj,
4475 void *pv_api_ip,
4476 void *pv_api_op)
4477{
4478 ih264d_ctl_degrade_ip_t *ps_ip;
4479 ih264d_ctl_degrade_op_t *ps_op;
4480 dec_struct_t *ps_codec = (dec_struct_t *)ps_codec_obj->pv_codec_handle;
4481
4482 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip;
4483 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op;
4484
4485 ps_codec->i4_degrade_type = ps_ip->i4_degrade_type;
4486 ps_codec->i4_nondegrade_interval = ps_ip->i4_nondegrade_interval;
4487 ps_codec->i4_degrade_pics = ps_ip->i4_degrade_pics;
4488
4489 ps_op->u4_error_code = 0;
4490 ps_codec->i4_degrade_pic_cnt = 0;
4491
4492 return IV_SUCCESS;
4493}
4494
4495WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl,
4496 void *pv_api_ip,
4497 void *pv_api_op)
4498{
4499 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip;
4500 ih264d_ctl_get_frame_dimensions_op_t *ps_op;
4501 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4502 UWORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset;
4503
4504 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
4505
4506 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op;
4507 UNUSED(ps_ip);
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]4508 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4509 {
4510 disp_wd = ps_dec->u2_disp_width;
4511 disp_ht = ps_dec->u2_disp_height;
4512
4513 if(0 == ps_dec->u4_share_disp_buf)
4514 {
4515 buffer_wd = disp_wd;
4516 buffer_ht = disp_ht;
4517 }
4518 else
4519 {
4520 buffer_wd = ps_dec->u2_frm_wd_y;
4521 buffer_ht = ps_dec->u2_frm_ht_y;
4522 }
4523 }
4524 else
4525 {
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4526 disp_wd = ps_dec->u4_width_at_init;
4527 disp_ht = ps_dec->u4_height_at_init;
4528
4529 if(0 == ps_dec->u4_share_disp_buf)
4530 {
4531 buffer_wd = disp_wd;
4532 buffer_ht = disp_ht;
4533 }
4534 else
4535 {
4536 buffer_wd = ALIGN16(disp_wd) + (PAD_LEN_Y_H << 1);
4537 buffer_ht = ALIGN16(disp_ht) + (PAD_LEN_Y_V << 2);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4538 }
4539 }
4540 if(ps_dec->u4_app_disp_width > buffer_wd)
4541 buffer_wd = ps_dec->u4_app_disp_width;
4542
4543 if(0 == ps_dec->u4_share_disp_buf)
4544 {
4545 x_offset = 0;
4546 y_offset = 0;
4547 }
4548 else
4549 {
4550 y_offset = (PAD_LEN_Y_V << 1);
4551 x_offset = PAD_LEN_Y_H;
4552
4553 if((NULL != ps_dec->ps_sps) && (1 == (ps_dec->ps_sps->u1_is_valid))
4554 && (0 != ps_dec->u2_crop_offset_y))
4555 {
4556 y_offset += ps_dec->u2_crop_offset_y / ps_dec->u2_frm_wd_y;
4557 x_offset += ps_dec->u2_crop_offset_y % ps_dec->u2_frm_wd_y;
4558 }
4559 }
4560
4561 ps_op->u4_disp_wd[0] = disp_wd;
4562 ps_op->u4_disp_ht[0] = disp_ht;
4563 ps_op->u4_buffer_wd[0] = buffer_wd;
4564 ps_op->u4_buffer_ht[0] = buffer_ht;
4565 ps_op->u4_x_offset[0] = x_offset;
4566 ps_op->u4_y_offset[0] = y_offset;
4567
4568 ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1)
4569 >> 1);
4570 ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1)
4571 >> 1);
4572 ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0]
4573 >> 1);
4574 ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0]
4575 >> 1);
4576 ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] =
4577 (ps_op->u4_x_offset[0] >> 1);
4578 ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] =
4579 (ps_op->u4_y_offset[0] >> 1);
4580
4581 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
4582 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
4583 {
4584 ps_op->u4_disp_wd[2] = 0;
4585 ps_op->u4_disp_ht[2] = 0;
4586 ps_op->u4_buffer_wd[2] = 0;
4587 ps_op->u4_buffer_ht[2] = 0;
4588 ps_op->u4_x_offset[2] = 0;
4589 ps_op->u4_y_offset[2] = 0;
4590
4591 ps_op->u4_disp_wd[1] <<= 1;
4592 ps_op->u4_buffer_wd[1] <<= 1;
4593 ps_op->u4_x_offset[1] <<= 1;
4594 }
4595
4596 return IV_SUCCESS;
4597
4598}
4599
4600WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
4601{
4602 ih264d_ctl_set_num_cores_ip_t *ps_ip;
4603 ih264d_ctl_set_num_cores_op_t *ps_op;
4604 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4605
4606 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip;
4607 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op;
4608 ps_op->u4_error_code = 0;
4609 ps_dec->u4_num_cores = ps_ip->u4_num_cores;
4610 if(ps_dec->u4_num_cores == 1)
4611 {
4612 ps_dec->u1_separate_parse = 0;
4613 ps_dec->pi4_ctxt_save_register_dec = ps_dec->pi4_ctxt_save_register;
4614 }
4615 else
4616 {
4617 ps_dec->u1_separate_parse = 1;
4618 }
4619
4620 /*using only upto three threads currently*/
4621 if(ps_dec->u4_num_cores > 3)
4622 ps_dec->u4_num_cores = 3;
4623
4624 return IV_SUCCESS;
4625}
4626
4627void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec,
4628 ivd_video_decode_op_t *ps_dec_op)
4629{
4630 if((ps_dec_op->u4_error_code & 0xff)
4631 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED)
4632 {
4633 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
4634 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
4635 }
4636 ps_dec_op->e_pic_type = ps_dec->i4_frametype;
4637
4638 ps_dec_op->u4_new_seq = 0;
4639 ps_dec_op->u4_output_present = ps_dec->u4_output_present;
4640 ps_dec_op->u4_progressive_frame_flag =
4641 ps_dec->s_disp_op.u4_progressive_frame_flag;
4642
4643 ps_dec_op->u4_is_ref_flag = 1;
4644 if(ps_dec_op->u4_frame_decoded_flag)
4645 {
4646 if(ps_dec->ps_cur_slice->u1_nal_ref_idc == 0)
4647 ps_dec_op->u4_is_ref_flag = 0;
4648 }
4649
4650 ps_dec_op->e_output_format = ps_dec->s_disp_op.e_output_format;
4651 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf;
4652 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type;
4653 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts;
4654 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
4655}
4656
4657/*****************************************************************************/
4658/* */
4659/* Function Name : ih264d_api_function */
4660/* */
4661/* Description : */
4662/* */
4663/* Inputs :iv_obj_t decoder handle */
4664/* :pv_api_ip pointer to input structure */
4665/* :pv_api_op pointer to output structure */
4666/* Outputs : */
4667/* Returns : void */
4668/* */
4669/* Issues : none */
4670/* */
4671/* Revision History: */
4672/* */
4673/* DD MM YYYY Author(s) Changes (Describe the changes made) */
4674/* 22 10 2008 100356 Draft */
4675/* */
4676/*****************************************************************************/
4677IV_API_CALL_STATUS_T ih264d_api_function(iv_obj_t *dec_hdl,
4678 void *pv_api_ip,
4679 void *pv_api_op)
4680{
4681 UWORD32 command;
4682 UWORD32 *pu2_ptr_cmd;
4683 UWORD32 u4_api_ret;
4684 IV_API_CALL_STATUS_T e_status;
4685 e_status = api_check_struct_sanity(dec_hdl, pv_api_ip, pv_api_op);
4686
4687 if(e_status != IV_SUCCESS)
4688 {
4689 UWORD32 *ptr_err;
4690
4691 ptr_err = (UWORD32 *)pv_api_op;
4692 UNUSED(ptr_err);
4693 H264_DEC_DEBUG_PRINT("error code = %d\n", *(ptr_err + 1));
4694 return IV_FAIL;
4695 }
4696
4697 pu2_ptr_cmd = (UWORD32 *)pv_api_ip;
4698 pu2_ptr_cmd++;
4699
4700 command = *pu2_ptr_cmd;
4701// H264_DEC_DEBUG_PRINT("inside lib = %d\n",command);
4702 switch(command)
4703 {
4704
4705 case IV_CMD_GET_NUM_MEM_REC:
4706 u4_api_ret = ih264d_get_num_rec((void *)pv_api_ip,
4707 (void *)pv_api_op);
4708
4709 break;
4710 case IV_CMD_FILL_NUM_MEM_REC:
4711
4712 u4_api_ret = ih264d_fill_num_mem_rec((void *)pv_api_ip,
4713 (void *)pv_api_op);
4714 break;
4715 case IV_CMD_INIT:
4716 u4_api_ret = ih264d_init(dec_hdl, (void *)pv_api_ip,
4717 (void *)pv_api_op);
4718 break;
4719
4720 case IVD_CMD_VIDEO_DECODE:
4721 u4_api_ret = ih264d_video_decode(dec_hdl, (void *)pv_api_ip,
4722 (void *)pv_api_op);
4723 break;
4724
4725 case IVD_CMD_GET_DISPLAY_FRAME:
4726 u4_api_ret = ih264d_get_display_frame(dec_hdl, (void *)pv_api_ip,
4727 (void *)pv_api_op);
4728
4729 break;
4730
4731 case IVD_CMD_SET_DISPLAY_FRAME:
4732 u4_api_ret = ih264d_set_display_frame(dec_hdl, (void *)pv_api_ip,
4733 (void *)pv_api_op);
4734
4735 break;
4736
4737 case IVD_CMD_REL_DISPLAY_FRAME:
4738 u4_api_ret = ih264d_rel_display_frame(dec_hdl, (void *)pv_api_ip,
4739 (void *)pv_api_op);
4740 break;
4741
4742 case IV_CMD_RETRIEVE_MEMREC:
4743 u4_api_ret = ih264d_clr(dec_hdl, (void *)pv_api_ip,
4744 (void *)pv_api_op);
4745 break;
4746
4747 case IVD_CMD_VIDEO_CTL:
4748 u4_api_ret = ih264d_ctl(dec_hdl, (void *)pv_api_ip,
4749 (void *)pv_api_op);
4750 break;
4751 default:
4752 u4_api_ret = IV_FAIL;
4753 break;
4754 }
4755
4756 return u4_api_ret;
4757}