Gitiles
Code Review Sign In
gerrit-public.fairphone.software / platform / external / libavc / refs/heads/int/10/fp2 / . / encoder / ih264e_api.c
blob: a9963030f94669636081cbb3ae687264775ca51d [file] [log] [blame]
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1/******************************************************************************
2 *
3 * Copyright (C) 2015 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19*/
20
21/**
22*******************************************************************************
23* @file
24* ih264e_api.c
25*
26* @brief
27* Contains api function definitions for H264 encoder
28*
29* @author
30* ittiam
31*
32* @par List of Functions:
33* - api_check_struct_sanity()
34* - ih264e_codec_update_config()
35* - ih264e_set_default_params()
36* - ih264e_init()
37* - ih264e_get_num_rec()
38* - ih264e_fill_num_mem_rec()
39* - ih264e_init_mem_rec()
40* - ih264e_retrieve_memrec()
41* - ih264e_set_flush_mode()
42* - ih264e_get_buf_info()
43* - ih264e_set_dimensions()
44* - ih264e_set_frame_rate()
45* - ih264e_set_bit_rate()
46* - ih264e_set_frame_type()
47* - ih264e_set_qp()
48* - ih264e_set_enc_mode()
49* - ih264e_set_vbv_params()
50* - ih264_set_air_params()
51* - ih264_set_me_params()
52* - ih264_set_ipe_params()
53* - ih264_set_gop_params()
54* - ih264_set_profile_params()
55* - ih264_set_deblock_params()
56* - ih264e_set_num_cores()
57* - ih264e_reset()
58* - ih264e_ctl()
59* - ih264e_api_function()
60*
61* @remarks
62* None
63*
64*******************************************************************************
65*/
66
67/*****************************************************************************/
68/* File Includes */
69/*****************************************************************************/
70
71/* System Include Files */
72#include <stdio.h>
73#include <stddef.h>
74#include <stdlib.h>
75#include <string.h>
76#include <assert.h>
77
78/* User Include Files */
79#include "ih264e_config.h"
80#include "ih264_typedefs.h"
81#include "ih264_size_defs.h"
82#include "iv2.h"
83#include "ive2.h"
84#include "ih264e.h"
85#include "ithread.h"
86#include "ih264_debug.h"
87#include "ih264_defs.h"
88#include "ih264_error.h"
89#include "ih264_structs.h"
90#include "ih264_trans_quant_itrans_iquant.h"
91#include "ih264_inter_pred_filters.h"
92#include "ih264_mem_fns.h"
93#include "ih264_padding.h"
94#include "ih264_intra_pred_filters.h"
95#include "ih264_deblk_edge_filters.h"
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame]96#include "ih264_cabac_tables.h"
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]97#include "ih264_macros.h"
98#include "ih264e_defs.h"
99#include "ih264e_globals.h"
100#include "ih264_buf_mgr.h"
101#include "irc_mem_req_and_acq.h"
102#include "irc_cntrl_param.h"
103#include "irc_frame_info_collector.h"
104#include "irc_rate_control_api.h"
105#include "ih264e_time_stamp.h"
106#include "ih264e_modify_frm_rate.h"
107#include "ih264e_rate_control.h"
108#include "ih264e_error.h"
109#include "ih264e_bitstream.h"
110#include "ime_defs.h"
111#include "ime_distortion_metrics.h"
112#include "ime_structs.h"
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame]113#include "ih264e_cabac_structs.h"
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]114#include "ih264e_structs.h"
115#include "ih264e_utils.h"
116#include "ih264e_core_coding.h"
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]117#include "ih264_platform_macros.h"
118#include "ih264e_platform_macros.h"
119#include "ih264_list.h"
120#include "ih264_dpb_mgr.h"
121#include "ih264_cavlc_tables.h"
122#include "ih264e_cavlc.h"
123#include "ih264_common_tables.h"
124#include "ih264e_master.h"
125#include "ih264e_fmt_conv.h"
126#include "ih264e_version.h"
127
128
129/*****************************************************************************/
130/* Function Declarations */
131/*****************************************************************************/
132WORD32 ih264e_get_rate_control_mem_tab(void *pv_rate_control,
133 iv_mem_rec_t *ps_mem,
134 ITT_FUNC_TYPE_E e_func_type);
135
136
137/*****************************************************************************/
138/* Function Definitions */
139/*****************************************************************************/
140
141/**
142*******************************************************************************
143*
144* @brief
145* Used to test arguments for corresponding API call
146*
147* @par Description:
148* For each command the arguments are validated
149*
150* @param[in] ps_handle
151* Codec handle at API level
152*
153* @param[in] pv_api_ip
154* Pointer to input structure
155*
156* @param[out] pv_api_op
157* Pointer to output structure
158*
159* @returns error status
160*
161* @remarks none
162*
163*******************************************************************************
164*/
165static IV_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle,
166 void *pv_api_ip,
167 void *pv_api_op)
168{
169 /* api call */
170 WORD32 command = IV_CMD_NA;
171
172 /* input structure expected by the api call */
173 UWORD32 *pu4_api_ip = pv_api_ip;
174
175 /* output structure expected by the api call */
176 UWORD32 *pu4_api_op = pv_api_op;
177
178 /* temp var */
179 WORD32 i, j;
180
181 if (NULL == pv_api_op || NULL == pv_api_ip)
182 {
183 return (IV_FAIL);
184 }
185
186 /* get command */
187 command = pu4_api_ip[1];
188
189 /* set error code */
190 pu4_api_op[1] = 0;
191
192 /* error checks on handle */
193 switch (command)
194 {
195 case IV_CMD_GET_NUM_MEM_REC:
196 case IV_CMD_FILL_NUM_MEM_REC:
197 break;
198
199 case IV_CMD_INIT:
200 if (ps_handle == NULL)
201 {
202 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
203 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_NULL;
204 return IV_FAIL;
205 }
206
207 if (ps_handle->u4_size != sizeof(iv_obj_t))
208 {
209 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
210 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_STRUCT_SIZE_INCORRECT;
211 return IV_FAIL;
212 }
213 break;
214
215 case IVE_CMD_QUEUE_INPUT:
216 case IVE_CMD_QUEUE_OUTPUT:
217 case IVE_CMD_DEQUEUE_OUTPUT:
218 case IVE_CMD_GET_RECON:
219 case IV_CMD_RETRIEVE_MEMREC:
220 case IVE_CMD_VIDEO_CTL:
221 case IVE_CMD_VIDEO_ENCODE:
222
223 if (ps_handle == NULL)
224 {
225 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
226 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_NULL;
227 return IV_FAIL;
228 }
229
230 if (ps_handle->u4_size != sizeof(iv_obj_t))
231 {
232 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
233 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_STRUCT_SIZE_INCORRECT;
234 return IV_FAIL;
235 }
236
237 if (ps_handle->pv_fxns != ih264e_api_function)
238 {
239 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
240 *(pu4_api_op + 1) |= IVE_ERR_API_FUNCTION_PTR_NULL;
241 return IV_FAIL;
242 }
243
244 if (ps_handle->pv_codec_handle == NULL)
245 {
246 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
247 *(pu4_api_op + 1) |= IVE_ERR_INVALID_CODEC_HANDLE;
248 return IV_FAIL;
249 }
250 break;
251
252 default:
253 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
254 *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_CMD;
255 return IV_FAIL;
256 }
257
258 /* error checks on input output structures */
259 switch (command)
260 {
261 case IV_CMD_GET_NUM_MEM_REC:
262 {
263 ih264e_num_mem_rec_ip_t *ps_ip = pv_api_ip;
264 ih264e_num_mem_rec_op_t *ps_op = pv_api_op;
265
266 ps_op->s_ive_op.u4_error_code = 0;
267
268 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_num_mem_rec_ip_t))
269 {
270 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
271 ps_op->s_ive_op.u4_error_code |=
272 IVE_ERR_IP_GET_MEM_REC_API_STRUCT_SIZE_INCORRECT;
273 return (IV_FAIL);
274 }
275
276 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_num_mem_rec_op_t))
277 {
278 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
279 ps_op->s_ive_op.u4_error_code |=
280 IVE_ERR_OP_GET_MEM_REC_API_STRUCT_SIZE_INCORRECT;
281 return (IV_FAIL);
282 }
283 break;
284 }
285
286 case IV_CMD_FILL_NUM_MEM_REC:
287 {
288 ih264e_fill_mem_rec_ip_t *ps_ip = pv_api_ip;
289 ih264e_fill_mem_rec_op_t *ps_op = pv_api_op;
290
291 iv_mem_rec_t *ps_mem_rec = NULL;
292
293 WORD32 max_wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
294 WORD32 max_ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
295
296 ps_op->s_ive_op.u4_error_code = 0;
297
298 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_fill_mem_rec_ip_t))
299 {
300 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
301 ps_op->s_ive_op.u4_error_code |=
302 IVE_ERR_IP_FILL_MEM_REC_API_STRUCT_SIZE_INCORRECT;
303 return (IV_FAIL);
304 }
305
306 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_fill_mem_rec_op_t))
307 {
308 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
309 ps_op->s_ive_op.u4_error_code |=
310 IVE_ERR_OP_FILL_MEM_REC_API_STRUCT_SIZE_INCORRECT;
311 return (IV_FAIL);
312 }
313
314 if (max_wd < MIN_WD || max_wd > MAX_WD)
315 {
316 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
317 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
318 return (IV_FAIL);
319 }
320
321 if (max_ht < MIN_HT || max_ht > MAX_HT)
322 {
323 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
324 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
325 return (IV_FAIL);
326 }
327
328 /* verify number of mem rec ptr */
329 if (NULL == ps_ip->s_ive_ip.ps_mem_rec)
330 {
331 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
332 ps_op->s_ive_op.u4_error_code |=
333 IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL;
334 return (IV_FAIL);
335 }
336
337 /* verify number of mem records */
338 if (ps_ip->s_ive_ip.u4_num_mem_rec != MEM_REC_CNT)
339 {
340 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
341 ps_op->s_ive_op.u4_error_code |=
342 IVE_ERR_NUM_MEM_REC_NOT_SUFFICIENT;
343 return IV_FAIL;
344 }
345
346 /* check mem records sizes are correct */
347 ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec;
348 for (i = 0; i < MEM_REC_CNT; i++)
349 {
350 if (ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
351 {
352 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
353 ps_op->s_ive_op.u4_error_code |=
354 IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT;
355 return IV_FAIL;
356 }
357 }
358 break;
359 }
360
361 case IV_CMD_INIT:
362 {
363 ih264e_init_ip_t *ps_ip = pv_api_ip;
364 ih264e_init_op_t *ps_op = pv_api_op;
365
366 iv_mem_rec_t *ps_mem_rec = NULL;
367
368 WORD32 max_wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
369 WORD32 max_ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
370
371 ps_op->s_ive_op.u4_error_code = 0;
372
373 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_init_ip_t))
374 {
375 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
376 ps_op->s_ive_op.u4_error_code |=
377 IVE_ERR_IP_INIT_API_STRUCT_SIZE_INCORRECT;
378 return (IV_FAIL);
379 }
380
381 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_init_op_t))
382 {
383 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
384 ps_op->s_ive_op.u4_error_code |=
385 IVE_ERR_OP_INIT_API_STRUCT_SIZE_INCORRECT;
386 return (IV_FAIL);
387 }
388
389 if (max_wd < MIN_WD || max_wd > MAX_WD)
390 {
391 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
392 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
393 return (IV_FAIL);
394 }
395
396 if (max_ht < MIN_HT || max_ht > MAX_HT)
397 {
398 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
399 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
400 return (IV_FAIL);
401 }
402
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame]403 if (ps_ip->s_ive_ip.u4_max_ref_cnt > MAX_REF_PIC_CNT ||
404 ps_ip->s_ive_ip.u4_max_ref_cnt < MIN_REF_PIC_CNT)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]405 {
406 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
407 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED;
408 return (IV_FAIL);
409 }
410
411 if (ps_ip->s_ive_ip.u4_max_reorder_cnt != 0)
412 {
413 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
414 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED;
415 return (IV_FAIL);
416 }
417
418 if ((ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_10)
419 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_1B)
420 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_11)
421 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_12)
422 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_13)
423 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_20)
424 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_21)
425 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_22)
426 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_30)
427 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_31)
428 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_32)
429 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_40)
430 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_41)
431 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_42)
432 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_50)
433 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_51))
434 {
435 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
436 ps_op->s_ive_op.u4_error_code |=
437 IH264E_CODEC_LEVEL_NOT_SUPPORTED;
438 return (IV_FAIL);
439 }
440
441 if ((ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420P)
442 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_422ILE)
443 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_UV)
444 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_VU))
445 {
446 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
447 ps_op->s_ive_op.u4_error_code |=
448 IH264E_INPUT_CHROMA_FORMAT_NOT_SUPPORTED;
449 return (IV_FAIL);
450 }
451
452 if ((ps_ip->s_ive_ip.e_recon_color_fmt != IV_YUV_420P)
453 && (ps_ip->s_ive_ip.e_recon_color_fmt != IV_YUV_420SP_UV)
454 && (ps_ip->s_ive_ip.e_recon_color_fmt != IV_YUV_420SP_VU))
455 {
456 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
457 ps_op->s_ive_op.u4_error_code |=
458 IH264E_RECON_CHROMA_FORMAT_NOT_SUPPORTED;
459 return (IV_FAIL);
460 }
461
462 if ((ps_ip->s_ive_ip.e_rc_mode != IVE_RC_NONE)
463 && (ps_ip->s_ive_ip.e_rc_mode != IVE_RC_STORAGE)
464 && (ps_ip->s_ive_ip.e_rc_mode != IVE_RC_CBR_NON_LOW_DELAY))
465 {
466 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
467 ps_op->s_ive_op.u4_error_code |=
468 IH264E_RATE_CONTROL_MODE_NOT_SUPPORTED;
469 return (IV_FAIL);
470 }
471
472 if (ps_ip->s_ive_ip.u4_max_framerate > DEFAULT_MAX_FRAMERATE)
473 {
474 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
475 ps_op->s_ive_op.u4_error_code |=
476 IH264E_FRAME_RATE_NOT_SUPPORTED;
477 return (IV_FAIL);
478 }
479
480 if (ps_ip->s_ive_ip.u4_max_bitrate > DEFAULT_MAX_BITRATE)
481 {
482 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
483 ps_op->s_ive_op.u4_error_code |= IH264E_BITRATE_NOT_SUPPORTED;
484 return (IV_FAIL);
485 }
486
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame]487 if (ps_ip->s_ive_ip.u4_num_bframes > MAX_NUM_BFRAMES)
488 {
489 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
490 ps_op->s_ive_op.u4_error_code |= IH264E_BFRAMES_NOT_SUPPORTED;
491 return (IV_FAIL);
492 }
493
494 if (ps_ip->s_ive_ip.u4_num_bframes
495 && (ps_ip->s_ive_ip.u4_max_ref_cnt < 2))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]496 {
497 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
498 ps_op->s_ive_op.u4_error_code |= IH264E_BFRAMES_NOT_SUPPORTED;
499 return (IV_FAIL);
500 }
501
502 if (ps_ip->s_ive_ip.e_content_type != IV_PROGRESSIVE)
503 {
504 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
505 ps_op->s_ive_op.u4_error_code |=
506 IH264E_CONTENT_TYPE_NOT_SUPPORTED;
507 return (IV_FAIL);
508 }
509
510 if (ps_ip->s_ive_ip.u4_max_srch_rng_x > DEFAULT_MAX_SRCH_RANGE_X)
511 {
512 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
513 ps_op->s_ive_op.u4_error_code |=
514 IH264E_HORIZONTAL_SEARCH_RANGE_NOT_SUPPORTED;
515 return (IV_FAIL);
516 }
517
518 if (ps_ip->s_ive_ip.u4_max_srch_rng_y > DEFAULT_MAX_SRCH_RANGE_Y)
519 {
520 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
521 ps_op->s_ive_op.u4_error_code |=
522 IH264E_VERTICAL_SEARCH_RANGE_NOT_SUPPORTED;
523 return (IV_FAIL);
524 }
525
526 if ((ps_ip->s_ive_ip.e_slice_mode != IVE_SLICE_MODE_NONE)
527 && (ps_ip->s_ive_ip.e_slice_mode != IVE_SLICE_MODE_BLOCKS))
528 {
529 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
530 ps_op->s_ive_op.u4_error_code |=
531 IH264E_SLICE_TYPE_INPUT_INVALID;
532 return (IV_FAIL);
533 }
534
535 if (ps_ip->s_ive_ip.e_slice_mode == IVE_SLICE_MODE_BLOCKS)
536 {
537 if (ps_ip->s_ive_ip.u4_slice_param == 0
538 || ps_ip->s_ive_ip.u4_slice_param > ((UWORD32)max_ht >> 4))
539 {
540 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
541 ps_op->s_ive_op.u4_error_code |=
542 IH264E_SLICE_PARAM_INPUT_INVALID;
543 return (IV_FAIL);
544 }
545 }
546
547 if (NULL == ps_ip->s_ive_ip.ps_mem_rec)
548 {
549 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
550 ps_op->s_ive_op.u4_error_code |=
551 IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL;
552 return (IV_FAIL);
553 }
554
555 /* verify number of mem records */
556 if (ps_ip->s_ive_ip.u4_num_mem_rec != MEM_REC_CNT)
557 {
558 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
559 ps_op->s_ive_op.u4_error_code |=
560 IVE_ERR_NUM_MEM_REC_NOT_SUFFICIENT;
561 return (IV_FAIL);
562 }
563
564 ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec;
565
566 /* check memrecords sizes are correct */
567 for (i = 0; i <((WORD32)ps_ip->s_ive_ip.u4_num_mem_rec); i++)
568 {
569 if (ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
570 {
571 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
572 ps_op->s_ive_op.u4_error_code |=
573 IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT;
574 return IV_FAIL;
575 }
576
577 /* check memrecords pointers are not NULL */
578 if (ps_mem_rec[i].pv_base == NULL)
579 {
580 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
581 ps_op->s_ive_op.u4_error_code |=
582 IVE_ERR_MEM_REC_BASE_POINTER_NULL;
583 return IV_FAIL;
584 }
585 }
586
587 /* verify memtabs for overlapping regions */
588 {
589 void *start[MEM_REC_CNT];
590 void *end[MEM_REC_CNT];
591
592 start[0] = (ps_mem_rec[0].pv_base);
593 end[0] = ((UWORD8 *) ps_mem_rec[0].pv_base)
594 + ps_mem_rec[0].u4_mem_size - 1;
595
596 for (i = 1; i < MEM_REC_CNT; i++)
597 {
598 /* This array is populated to check memtab overlap */
599 start[i] = (ps_mem_rec[i].pv_base);
600 end[i] = ((UWORD8 *) ps_mem_rec[i].pv_base)
601 + ps_mem_rec[i].u4_mem_size - 1;
602
603 for (j = 0; j < i; j++)
604 {
605 if ((start[i] >= start[j]) && (start[i] <= end[j]))
606 {
607 ps_op->s_ive_op.u4_error_code |= 1
608 << IVE_UNSUPPORTEDPARAM;
609 ps_op->s_ive_op.u4_error_code |=
610 IVE_ERR_MEM_REC_OVERLAP_ERR;
611 return IV_FAIL;
612 }
613
614 if ((end[i] >= start[j]) && (end[i] <= end[j]))
615 {
616 ps_op->s_ive_op.u4_error_code |= 1
617 << IVE_UNSUPPORTEDPARAM;
618 ps_op->s_ive_op.u4_error_code |=
619 IVE_ERR_MEM_REC_OVERLAP_ERR;
620 return IV_FAIL;
621 }
622
623 if ((start[i] < start[j]) && (end[i] > end[j]))
624 {
625 ps_op->s_ive_op.u4_error_code |= 1
626 << IVE_UNSUPPORTEDPARAM;
627 ps_op->s_ive_op.u4_error_code |=
628 IVE_ERR_MEM_REC_OVERLAP_ERR;
629 return IV_FAIL;
630 }
631 }
632 }
633 }
634
635 /* re-validate mem records with init config */
636 {
637 /* mem records */
638 iv_mem_rec_t s_mem_rec_ittiam_api[MEM_REC_CNT];
639
640 /* api interface structs */
641 ih264e_fill_mem_rec_ip_t s_ip;
642 ih264e_fill_mem_rec_op_t s_op;
643
644 /* error status */
645 IV_STATUS_T e_status;
646
647 /* temp var */
648 WORD32 i;
649
650 s_ip.s_ive_ip.u4_size = sizeof(ih264e_fill_mem_rec_ip_t);
651 s_op.s_ive_op.u4_size = sizeof(ih264e_fill_mem_rec_op_t);
652
653 s_ip.s_ive_ip.e_cmd = IV_CMD_FILL_NUM_MEM_REC;
654 s_ip.s_ive_ip.ps_mem_rec = s_mem_rec_ittiam_api;
655 s_ip.s_ive_ip.u4_max_wd = max_wd;
656 s_ip.s_ive_ip.u4_max_ht = max_ht;
657 s_ip.s_ive_ip.u4_num_mem_rec = ps_ip->s_ive_ip.u4_num_mem_rec;
658 s_ip.s_ive_ip.u4_max_level = ps_ip->s_ive_ip.u4_max_level;
659 s_ip.s_ive_ip.u4_max_ref_cnt = ps_ip->s_ive_ip.u4_max_ref_cnt;
660 s_ip.s_ive_ip.u4_max_reorder_cnt =
661 ps_ip->s_ive_ip.u4_max_reorder_cnt;
662 s_ip.s_ive_ip.e_color_format = ps_ip->s_ive_ip.e_inp_color_fmt;
663 s_ip.s_ive_ip.u4_max_srch_rng_x =
664 ps_ip->s_ive_ip.u4_max_srch_rng_x;
665 s_ip.s_ive_ip.u4_max_srch_rng_y =
666 ps_ip->s_ive_ip.u4_max_srch_rng_y;
667
668 for (i = 0; i < MEM_REC_CNT; i++)
669 {
670 s_mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t);
671 }
672
673 /* fill mem records */
674 e_status = ih264e_api_function(NULL, (void *) &s_ip,
675 (void *) &s_op);
676
677 if (IV_FAIL == e_status)
678 {
679 ps_op->s_ive_op.u4_error_code = s_op.s_ive_op.u4_error_code;
680 return (IV_FAIL);
681 }
682
683 /* verify mem records */
684 for (i = 0; i < MEM_REC_CNT; i++)
685 {
686 if (ps_mem_rec[i].u4_mem_size
687 < s_mem_rec_ittiam_api[i].u4_mem_size)
688 {
689 ps_op->s_ive_op.u4_error_code |= 1
690 << IVE_UNSUPPORTEDPARAM;
691 ps_op->s_ive_op.u4_error_code |=
692 IVE_ERR_MEM_REC_INSUFFICIENT_SIZE;
693
694 return IV_FAIL;
695 }
696
697 if (ps_mem_rec[i].u4_mem_alignment
698 != s_mem_rec_ittiam_api[i].u4_mem_alignment)
699 {
700 ps_op->s_ive_op.u4_error_code |= 1
701 << IVE_UNSUPPORTEDPARAM;
702 ps_op->s_ive_op.u4_error_code |=
703 IVE_ERR_MEM_REC_ALIGNMENT_ERR;
704
705 return IV_FAIL;
706 }
707
708 if (ps_mem_rec[i].e_mem_type
709 != s_mem_rec_ittiam_api[i].e_mem_type)
710 {
711 UWORD32 check = IV_SUCCESS;
712 UWORD32 diff = s_mem_rec_ittiam_api[i].e_mem_type
713 - ps_mem_rec[i].e_mem_type;
714
715 if ((ps_mem_rec[i].e_mem_type
716 <= IV_EXTERNAL_CACHEABLE_SCRATCH_MEM)
717 && (s_mem_rec_ittiam_api[i].e_mem_type
718 >= IV_INTERNAL_NONCACHEABLE_PERSISTENT_MEM))
719 {
720 check = IV_FAIL;
721 }
722
723 if (3 != (s_mem_rec_ittiam_api[i].e_mem_type % 4))
724 {
725 /* It is not IV_EXTERNAL_NONCACHEABLE_PERSISTENT_MEM or
726 * IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM */
727
728 if ((diff < 1) || (diff > 3))
729 {
730 /* Difference between 1 and 3 is okay for all cases other than the
731 * two filtered with the MOD condition above */
732 check = IV_FAIL;
733 }
734 }
735 else
736 {
737 if (diff == 1)
738 {
739 /* This particular case is when codec asked for External Persistent,
740 * but got Internal Scratch */
741 check = IV_FAIL;
742 }
743 if ((diff != 2) && (diff != 3))
744 {
745 check = IV_FAIL;
746 }
747 }
748
749 if (check == IV_FAIL)
750 {
751 ps_op->s_ive_op.u4_error_code |= 1
752 << IVE_UNSUPPORTEDPARAM;
753 ps_op->s_ive_op.u4_error_code |=
754 IVE_ERR_MEM_REC_INCORRECT_TYPE;
755
756 return IV_FAIL;
757 }
758 }
759 }
760 }
761 break;
762 }
763
764 case IVE_CMD_QUEUE_INPUT:
765 case IVE_CMD_QUEUE_OUTPUT:
766 case IVE_CMD_DEQUEUE_OUTPUT:
767 case IVE_CMD_GET_RECON:
768 break;
769
770 case IV_CMD_RETRIEVE_MEMREC:
771 {
772 ih264e_retrieve_mem_rec_ip_t *ps_ip = pv_api_ip;
773 ih264e_retrieve_mem_rec_op_t *ps_op = pv_api_op;
774
775 iv_mem_rec_t *ps_mem_rec = NULL;
776
777 ps_op->s_ive_op.u4_error_code = 0;
778
779 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_retrieve_mem_rec_ip_t))
780 {
781 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
782 ps_op->s_ive_op.u4_error_code |=
783 IVE_ERR_IP_RETRIEVE_MEM_REC_API_STRUCT_SIZE_INCORRECT;
784 return (IV_FAIL);
785 }
786
787 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_retrieve_mem_rec_op_t))
788 {
789 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
790 ps_op->s_ive_op.u4_error_code |=
791 IVE_ERR_OP_RETRIEVE_MEM_REC_API_STRUCT_SIZE_INCORRECT;
792 return (IV_FAIL);
793 }
794
795 if (NULL == ps_ip->s_ive_ip.ps_mem_rec)
796 {
797 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
798 ps_op->s_ive_op.u4_error_code |=
799 IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL;
800 return (IV_FAIL);
801 }
802
803 ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec;
804
805 /* check memrecords sizes are correct */
806 for (i = 0; i < MEM_REC_CNT; i++)
807 {
808 if (ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
809 {
810 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
811 ps_op->s_ive_op.u4_error_code |=
812 IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT;
813 return IV_FAIL;
814 }
815 }
816 break;
817 }
818
819 case IVE_CMD_VIDEO_ENCODE:
820 {
821 ih264e_video_encode_ip_t *ps_ip = pv_api_ip;
822 ih264e_video_encode_op_t *ps_op = pv_api_op;
823
824 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_video_encode_ip_t))
825 {
826 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
827 ps_op->s_ive_op.u4_error_code |=
828 IVE_ERR_IP_ENCODE_API_STRUCT_SIZE_INCORRECT;
829 return (IV_FAIL);
830 }
831
832 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_video_encode_op_t))
833 {
834 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
835 ps_op->s_ive_op.u4_error_code |=
836 IVE_ERR_OP_ENCODE_API_STRUCT_SIZE_INCORRECT;
837 return (IV_FAIL);
838 }
839 break;
840 }
841
842 case IVE_CMD_VIDEO_CTL:
843 {
844 /* ptr to input structure */
845 WORD32 *pu4_ptr_cmd = pv_api_ip;
846
847 /* sub command */
848 WORD32 sub_command = pu4_ptr_cmd[2];
849
850 switch (sub_command)
851 {
852 case IVE_CMD_CTL_SETDEFAULT:
853 {
854 ih264e_ctl_setdefault_ip_t *ps_ip = pv_api_ip;
855 ih264e_ctl_setdefault_op_t *ps_op = pv_api_op;
856
857 if (ps_ip->s_ive_ip.u4_size
858 != sizeof(ih264e_ctl_setdefault_ip_t))
859 {
860 ps_op->s_ive_op.u4_error_code |= 1
861 << IVE_UNSUPPORTEDPARAM;
862 ps_op->s_ive_op.u4_error_code |=
863 IVE_ERR_IP_CTL_SETDEF_API_STRUCT_SIZE_INCORRECT;
864 return IV_FAIL;
865 }
866
867 if (ps_op->s_ive_op.u4_size
868 != sizeof(ih264e_ctl_setdefault_op_t))
869 {
870 ps_op->s_ive_op.u4_error_code |= 1
871 << IVE_UNSUPPORTEDPARAM;
872 ps_op->s_ive_op.u4_error_code |=
873 IVE_ERR_OP_CTL_SETDEF_API_STRUCT_SIZE_INCORRECT;
874 return IV_FAIL;
875 }
876 break;
877 }
878
879 case IVE_CMD_CTL_GETBUFINFO:
880 {
881 codec_t *ps_codec = (codec_t *) (ps_handle->pv_codec_handle);
882
883 ih264e_ctl_getbufinfo_ip_t *ps_ip = pv_api_ip;
884 ih264e_ctl_getbufinfo_op_t *ps_op = pv_api_op;
885
886 if (ps_ip->s_ive_ip.u4_size
887 != sizeof(ih264e_ctl_getbufinfo_ip_t))
888 {
889 ps_op->s_ive_op.u4_error_code |= 1
890 << IVE_UNSUPPORTEDPARAM;
891 ps_op->s_ive_op.u4_error_code |=
892 IVE_ERR_IP_CTL_GETBUFINFO_API_STRUCT_SIZE_INCORRECT;
893 return IV_FAIL;
894 }
895
896 if (ps_op->s_ive_op.u4_size
897 != sizeof(ih264e_ctl_getbufinfo_op_t))
898 {
899 ps_op->s_ive_op.u4_error_code |= 1
900 << IVE_UNSUPPORTEDPARAM;
901 ps_op->s_ive_op.u4_error_code |=
902 IVE_ERR_OP_CTL_GETBUFINFO_API_STRUCT_SIZE_INCORRECT;
903 return IV_FAIL;
904 }
905
906 if (ps_ip->s_ive_ip.u4_max_wd < MIN_WD)
907 {
908 ps_op->s_ive_op.u4_error_code |= 1
909 << IVE_UNSUPPORTEDPARAM;
910 ps_op->s_ive_op.u4_error_code |=
911 IH264E_WIDTH_NOT_SUPPORTED;
912 return (IV_FAIL);
913 }
914
915 if (ps_ip->s_ive_ip.u4_max_wd > ps_codec->s_cfg.u4_max_wd)
916 {
917 ps_op->s_ive_op.u4_error_code |= 1
918 << IVE_UNSUPPORTEDPARAM;
919 ps_op->s_ive_op.u4_error_code |=
920 IH264E_WIDTH_NOT_SUPPORTED;
921 return (IV_FAIL);
922 }
923
924 if (ps_ip->s_ive_ip.u4_max_ht < MIN_HT)
925 {
926 ps_op->s_ive_op.u4_error_code |= 1
927 << IVE_UNSUPPORTEDPARAM;
928 ps_op->s_ive_op.u4_error_code |=
929 IH264E_HEIGHT_NOT_SUPPORTED;
930 return (IV_FAIL);
931 }
932
933 if (ps_ip->s_ive_ip.u4_max_ht > ps_codec->s_cfg.u4_max_ht)
934 {
935 ps_op->s_ive_op.u4_error_code |= 1
936 << IVE_UNSUPPORTEDPARAM;
937 ps_op->s_ive_op.u4_error_code |=
938 IH264E_HEIGHT_NOT_SUPPORTED;
939 return (IV_FAIL);
940 }
941
942 if ((ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420P)
943 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_422ILE)
944 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_UV)
945 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_VU))
946 {
947 ps_op->s_ive_op.u4_error_code |= 1
948 << IVE_UNSUPPORTEDPARAM;
949 ps_op->s_ive_op.u4_error_code |=
950 IH264E_INPUT_CHROMA_FORMAT_NOT_SUPPORTED;
951 return (IV_FAIL);
952 }
953 break;
954 }
955
956 case IVE_CMD_CTL_GETVERSION:
957 {
958 ih264e_ctl_getversioninfo_ip_t *ps_ip = pv_api_ip;
959 ih264e_ctl_getversioninfo_op_t *ps_op = pv_api_op;
960
961 if (ps_ip->s_ive_ip.u4_size
962 != sizeof(ih264e_ctl_getversioninfo_ip_t))
963 {
964 ps_op->s_ive_op.u4_error_code |= 1
965 << IVE_UNSUPPORTEDPARAM;
966 ps_op->s_ive_op.u4_error_code |=
967 IVE_ERR_IP_CTL_GETVERSION_API_STRUCT_SIZE_INCORRECT;
968 return IV_FAIL;
969 }
970
971 if (ps_op->s_ive_op.u4_size
972 != sizeof(ih264e_ctl_getversioninfo_op_t))
973 {
974 ps_op->s_ive_op.u4_error_code |= 1
975 << IVE_UNSUPPORTEDPARAM;
976 ps_op->s_ive_op.u4_error_code |=
977 IVE_ERR_OP_CTL_GETVERSION_API_STRUCT_SIZE_INCORRECT;
978 return IV_FAIL;
979 }
980
981 if (ps_ip->s_ive_ip.pu1_version == NULL)
982 {
983 ps_op->s_ive_op.u4_error_code |= 1
984 << IVE_UNSUPPORTEDPARAM;
985 ps_op->s_ive_op.u4_error_code |=
986 IVE_ERR_CTL_GET_VERSION_BUFFER_IS_NULL;
987 return IV_FAIL;
988 }
989
990 break;
991 }
992
993 case IVE_CMD_CTL_FLUSH:
994 {
995 ih264e_ctl_flush_ip_t *ps_ip = pv_api_ip;
996 ih264e_ctl_flush_op_t *ps_op = pv_api_op;
997
998 if (ps_ip->s_ive_ip.u4_size
999 != sizeof(ih264e_ctl_flush_ip_t))
1000 {
1001 ps_op->s_ive_op.u4_error_code |= 1
1002 << IVE_UNSUPPORTEDPARAM;
1003 ps_op->s_ive_op.u4_error_code |=
1004 IVE_ERR_IP_CTL_FLUSH_API_STRUCT_SIZE_INCORRECT;
1005 return IV_FAIL;
1006 }
1007
1008 if (ps_op->s_ive_op.u4_size
1009 != sizeof(ih264e_ctl_flush_op_t))
1010 {
1011 ps_op->s_ive_op.u4_error_code |= 1
1012 << IVE_UNSUPPORTEDPARAM;
1013 ps_op->s_ive_op.u4_error_code |=
1014 IVE_ERR_OP_CTL_FLUSH_API_STRUCT_SIZE_INCORRECT;
1015 return IV_FAIL;
1016 }
1017
1018 break;
1019 }
1020
1021 case IVE_CMD_CTL_RESET:
1022 {
1023 ih264e_ctl_reset_ip_t *ps_ip = pv_api_ip;
1024 ih264e_ctl_reset_op_t *ps_op = pv_api_op;
1025
1026 if (ps_ip->s_ive_ip.u4_size
1027 != sizeof(ih264e_ctl_reset_ip_t))
1028 {
1029 ps_op->s_ive_op.u4_error_code |= 1
1030 << IVE_UNSUPPORTEDPARAM;
1031 ps_op->s_ive_op.u4_error_code |=
1032 IVE_ERR_IP_CTL_RESET_API_STRUCT_SIZE_INCORRECT;
1033 return IV_FAIL;
1034 }
1035
1036 if (ps_op->s_ive_op.u4_size
1037 != sizeof(ih264e_ctl_reset_op_t))
1038 {
1039 ps_op->s_ive_op.u4_error_code |= 1
1040 << IVE_UNSUPPORTEDPARAM;
1041 ps_op->s_ive_op.u4_error_code |=
1042 IVE_ERR_OP_CTL_RESET_API_STRUCT_SIZE_INCORRECT;
1043 return IV_FAIL;
1044 }
1045
1046 break;
1047 }
1048
1049 case IVE_CMD_CTL_SET_NUM_CORES:
1050 {
1051 ih264e_ctl_set_num_cores_ip_t *ps_ip = pv_api_ip;
1052 ih264e_ctl_set_num_cores_op_t *ps_op = pv_api_op;
1053
1054 if (ps_ip->s_ive_ip.u4_size
1055 != sizeof(ih264e_ctl_set_num_cores_ip_t))
1056 {
1057 ps_op->s_ive_op.u4_error_code |= 1
1058 << IVE_UNSUPPORTEDPARAM;
1059 ps_op->s_ive_op.u4_error_code |=
1060 IVE_ERR_IP_CTL_SETCORES_API_STRUCT_SIZE_INCORRECT;
1061 return IV_FAIL;
1062 }
1063
1064 if (ps_op->s_ive_op.u4_size
1065 != sizeof(ih264e_ctl_set_num_cores_op_t))
1066 {
1067 ps_op->s_ive_op.u4_error_code |= 1
1068 << IVE_UNSUPPORTEDPARAM;
1069 ps_op->s_ive_op.u4_error_code |=
1070 IVE_ERR_OP_CTL_SETCORES_API_STRUCT_SIZE_INCORRECT;
1071 return IV_FAIL;
1072 }
1073
1074 if ((ps_ip->s_ive_ip.u4_num_cores < 1)
1075 || (ps_ip->s_ive_ip.u4_num_cores > MAX_NUM_CORES))
1076 {
1077 ps_op->s_ive_op.u4_error_code |= 1
1078 << IVE_UNSUPPORTEDPARAM;
1079 ps_op->s_ive_op.u4_error_code |=
1080 IH264E_INVALID_NUM_CORES;
1081 return IV_FAIL;
1082 }
1083
1084 break;
1085 }
1086
1087 case IVE_CMD_CTL_SET_DIMENSIONS:
1088 {
1089 codec_t *ps_codec = (codec_t *) (ps_handle->pv_codec_handle);
1090
1091 ih264e_ctl_set_dimensions_ip_t *ps_ip = pv_api_ip;
1092 ih264e_ctl_set_dimensions_op_t *ps_op = pv_api_op;
1093
1094 if (ps_ip->s_ive_ip.u4_size
1095 != sizeof(ih264e_ctl_set_dimensions_ip_t))
1096 {
1097 ps_op->s_ive_op.u4_error_code |= 1
1098 << IVE_UNSUPPORTEDPARAM;
1099 ps_op->s_ive_op.u4_error_code |=
1100 IVE_ERR_IP_CTL_SETDIM_API_STRUCT_SIZE_INCORRECT;
1101 return IV_FAIL;
1102 }
1103
1104 if (ps_op->s_ive_op.u4_size
1105 != sizeof(ih264e_ctl_set_dimensions_op_t))
1106 {
1107 ps_op->s_ive_op.u4_error_code |= 1
1108 << IVE_UNSUPPORTEDPARAM;
1109 ps_op->s_ive_op.u4_error_code |=
1110 IVE_ERR_OP_CTL_SETDIM_API_STRUCT_SIZE_INCORRECT;
1111 return IV_FAIL;
1112 }
1113
1114 if (ps_ip->s_ive_ip.u4_wd < MIN_WD)
1115 {
1116 ps_op->s_ive_op.u4_error_code |= 1
1117 << IVE_UNSUPPORTEDPARAM;
1118 ps_op->s_ive_op.u4_error_code |=
1119 IH264E_WIDTH_NOT_SUPPORTED;
1120 return (IV_FAIL);
1121 }
1122
1123 if (ps_ip->s_ive_ip.u4_wd > ps_codec->s_cfg.u4_max_wd)
1124 {
1125 ps_op->s_ive_op.u4_error_code |= 1
1126 << IVE_UNSUPPORTEDPARAM;
1127 ps_op->s_ive_op.u4_error_code |=
1128 IH264E_WIDTH_NOT_SUPPORTED;
1129 return (IV_FAIL);
1130 }
1131
1132 if (ps_ip->s_ive_ip.u4_ht < MIN_HT)
1133 {
1134 ps_op->s_ive_op.u4_error_code |= 1
1135 << IVE_UNSUPPORTEDPARAM;
1136 ps_op->s_ive_op.u4_error_code |=
1137 IH264E_HEIGHT_NOT_SUPPORTED;
1138 return (IV_FAIL);
1139 }
1140
1141 if (ps_ip->s_ive_ip.u4_ht > ps_codec->s_cfg.u4_max_ht)
1142 {
1143 ps_op->s_ive_op.u4_error_code |= 1
1144 << IVE_UNSUPPORTEDPARAM;
1145 ps_op->s_ive_op.u4_error_code |=
1146 IH264E_HEIGHT_NOT_SUPPORTED;
1147 return (IV_FAIL);
1148 }
1149
Akshata Jadhav9fa58d42018-02-21 11:39:52 +0530[diff] [blame]1150 if(ps_ip->s_ive_ip.u4_wd & 1)
1151 {
1152 ps_op->s_ive_op.u4_error_code |= 1
1153 << IVE_UNSUPPORTEDPARAM;
1154 ps_op->s_ive_op.u4_error_code |=
1155 IH264E_WIDTH_NOT_SUPPORTED;
1156 return (IV_FAIL);
1157 }
1158
1159 if(ps_ip->s_ive_ip.u4_ht & 1)
1160 {
1161 ps_op->s_ive_op.u4_error_code |= 1
1162 << IVE_UNSUPPORTEDPARAM;
1163 ps_op->s_ive_op.u4_error_code |=
1164 IH264E_HEIGHT_NOT_SUPPORTED;
1165 return (IV_FAIL);
1166 }
1167
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1168 break;
1169 }
1170
1171 case IVE_CMD_CTL_SET_FRAMERATE:
1172 {
1173 ih264e_ctl_set_frame_rate_ip_t *ps_ip = pv_api_ip;
1174 ih264e_ctl_set_frame_rate_op_t *ps_op = pv_api_op;
1175
1176 if (ps_ip->s_ive_ip.u4_size
1177 != sizeof(ih264e_ctl_set_frame_rate_ip_t))
1178 {
1179 ps_op->s_ive_op.u4_error_code |= 1
1180 << IVE_UNSUPPORTEDPARAM;
1181 ps_op->s_ive_op.u4_error_code |=
1182 IVE_ERR_IP_CTL_SETFRAMERATE_API_STRUCT_SIZE_INCORRECT;
1183 return IV_FAIL;
1184 }
1185
1186 if (ps_op->s_ive_op.u4_size
1187 != sizeof(ih264e_ctl_set_frame_rate_op_t))
1188 {
1189 ps_op->s_ive_op.u4_error_code |= 1
1190 << IVE_UNSUPPORTEDPARAM;
1191 ps_op->s_ive_op.u4_error_code |=
1192 IVE_ERR_OP_CTL_SETFRAMERATE_API_STRUCT_SIZE_INCORRECT;
1193 return IV_FAIL;
1194 }
1195
1196 if (((ps_ip->s_ive_ip.u4_src_frame_rate * 1000) > DEFAULT_MAX_FRAMERATE)
1197 || ((ps_ip->s_ive_ip.u4_tgt_frame_rate * 1000) > DEFAULT_MAX_FRAMERATE))
1198 {
1199 ps_op->s_ive_op.u4_error_code |= 1
1200 << IVE_UNSUPPORTEDPARAM;
1201 ps_op->s_ive_op.u4_error_code |=
1202 IH264E_FRAME_RATE_NOT_SUPPORTED;
1203 return (IV_FAIL);
1204 }
1205
1206 if ((ps_ip->s_ive_ip.u4_src_frame_rate == 0)
1207 || (ps_ip->s_ive_ip.u4_tgt_frame_rate == 0))
1208 {
1209 ps_op->s_ive_op.u4_error_code |= 1
1210 << IVE_UNSUPPORTEDPARAM;
1211 ps_op->s_ive_op.u4_error_code |=
1212 IH264E_FRAME_RATE_NOT_SUPPORTED;
1213 return (IV_FAIL);
1214 }
1215
1216 if (ps_ip->s_ive_ip.u4_tgt_frame_rate
1217 > ps_ip->s_ive_ip.u4_src_frame_rate)
1218 {
1219 ps_op->s_ive_op.u4_error_code |= 1
1220 << IVE_UNSUPPORTEDPARAM;
1221 ps_op->s_ive_op.u4_error_code |=
1222 IH264E_TGT_FRAME_RATE_EXCEEDS_SRC_FRAME_RATE;
1223 return (IV_FAIL);
1224 }
1225
1226 break;
1227 }
1228
1229 case IVE_CMD_CTL_SET_BITRATE:
1230 {
1231 ih264e_ctl_set_bitrate_ip_t *ps_ip = pv_api_ip;
1232 ih264e_ctl_set_bitrate_op_t *ps_op = pv_api_op;
1233
1234 if (ps_ip->s_ive_ip.u4_size
1235 != sizeof(ih264e_ctl_set_bitrate_ip_t))
1236 {
1237 ps_op->s_ive_op.u4_error_code |= 1
1238 << IVE_UNSUPPORTEDPARAM;
1239 ps_op->s_ive_op.u4_error_code |=
1240 IVE_ERR_IP_CTL_SETBITRATE_API_STRUCT_SIZE_INCORRECT;
1241 return IV_FAIL;
1242 }
1243
1244 if (ps_op->s_ive_op.u4_size
1245 != sizeof(ih264e_ctl_set_bitrate_op_t))
1246 {
1247 ps_op->s_ive_op.u4_error_code |= 1
1248 << IVE_UNSUPPORTEDPARAM;
1249 ps_op->s_ive_op.u4_error_code |=
1250 IVE_ERR_OP_CTL_SETBITRATE_API_STRUCT_SIZE_INCORRECT;
1251 return IV_FAIL;
1252 }
1253
1254 if ((ps_ip->s_ive_ip.u4_target_bitrate > DEFAULT_MAX_BITRATE)
1255 || (ps_ip->s_ive_ip.u4_target_bitrate == 0))
1256 {
1257 ps_op->s_ive_op.u4_error_code |= 1
1258 << IVE_UNSUPPORTEDPARAM;
1259 ps_op->s_ive_op.u4_error_code |=
1260 IH264E_BITRATE_NOT_SUPPORTED;
1261 return (IV_FAIL);
1262 }
1263
1264 break;
1265 }
1266
1267 case IVE_CMD_CTL_SET_FRAMETYPE:
1268 {
1269 ih264e_ctl_set_frame_type_ip_t *ps_ip = pv_api_ip;
1270 ih264e_ctl_set_frame_type_op_t *ps_op = pv_api_op;
1271
1272 if (ps_ip->s_ive_ip.u4_size
1273 != sizeof(ih264e_ctl_set_frame_type_ip_t))
1274 {
1275 ps_op->s_ive_op.u4_error_code |= 1
1276 << IVE_UNSUPPORTEDPARAM;
1277 ps_op->s_ive_op.u4_error_code |=
1278 IVE_ERR_IP_CTL_SETFRAMETYPE_API_STRUCT_SIZE_INCORRECT;
1279 return IV_FAIL;
1280 }
1281
1282 if (ps_op->s_ive_op.u4_size
1283 != sizeof(ih264e_ctl_set_frame_type_op_t))
1284 {
1285 ps_op->s_ive_op.u4_error_code |= 1
1286 << IVE_UNSUPPORTEDPARAM;
1287 ps_op->s_ive_op.u4_error_code |=
1288 IVE_ERR_OP_CTL_SETFRAMETYPE_API_STRUCT_SIZE_INCORRECT;
1289 return IV_FAIL;
1290 }
1291
1292 if ((ps_ip->s_ive_ip.e_frame_type != IV_NA_FRAME)
1293 && (ps_ip->s_ive_ip.e_frame_type != IV_I_FRAME)
1294 && (ps_ip->s_ive_ip.e_frame_type != IV_P_FRAME)
1295 && (ps_ip->s_ive_ip.e_frame_type != IV_IDR_FRAME))
1296 {
1297 ps_op->s_ive_op.u4_error_code |= 1
1298 << IVE_UNSUPPORTEDPARAM;
1299 ps_op->s_ive_op.u4_error_code |=
1300 IH264E_INVALID_FORCE_FRAME_INPUT;
1301 return IV_FAIL;
1302 }
1303 break;
1304 }
1305
1306 case IVE_CMD_CTL_SET_ME_PARAMS:
1307 {
1308 codec_t *ps_codec = (codec_t *) (ps_handle->pv_codec_handle);
1309
1310 ih264e_ctl_set_me_params_ip_t *ps_ip = pv_api_ip;
1311 ih264e_ctl_set_me_params_op_t *ps_op = pv_api_op;
1312
1313 if (ps_ip->s_ive_ip.u4_size
1314 != sizeof(ih264e_ctl_set_me_params_ip_t))
1315 {
1316 ps_op->s_ive_op.u4_error_code |= 1
1317 << IVE_UNSUPPORTEDPARAM;
1318 ps_op->s_ive_op.u4_error_code |=
1319 IVE_ERR_IP_CTL_SETMEPARAMS_API_STRUCT_SIZE_INCORRECT;
1320 return IV_FAIL;
1321 }
1322
1323 if (ps_op->s_ive_op.u4_size
1324 != sizeof(ih264e_ctl_set_me_params_op_t))
1325 {
1326 ps_op->s_ive_op.u4_error_code |= 1
1327 << IVE_UNSUPPORTEDPARAM;
1328 ps_op->s_ive_op.u4_error_code |=
1329 IVE_ERR_OP_CTL_SETMEPARAMS_API_STRUCT_SIZE_INCORRECT;
1330 return IV_FAIL;
1331 }
1332
1333 if ((ps_ip->s_ive_ip.u4_me_speed_preset != FULL_SRCH)
1334 && (ps_ip->s_ive_ip.u4_me_speed_preset != DMND_SRCH)
1335 && (ps_ip->s_ive_ip.u4_me_speed_preset != HEX_SRCH))
1336 {
1337 ps_op->s_ive_op.u4_error_code |= 1
1338 << IVE_UNSUPPORTEDPARAM;
1339 ps_op->s_ive_op.u4_error_code |=
1340 IH264E_INVALID_ME_SPEED_PRESET;
1341 return IV_FAIL;
1342 }
1343
1344 if ((ps_ip->s_ive_ip.u4_enable_hpel != 0)
1345 && (ps_ip->s_ive_ip.u4_enable_hpel != 1))
1346 {
1347 ps_op->s_ive_op.u4_error_code |= 1
1348 << IVE_UNSUPPORTEDPARAM;
1349 ps_op->s_ive_op.u4_error_code |=
1350 IH264E_INVALID_HALFPEL_OPTION;
1351 return IV_FAIL;
1352 }
1353
1354 if ((ps_ip->s_ive_ip.u4_enable_qpel != 0)
1355 && (ps_ip->s_ive_ip.u4_enable_qpel != 1))
1356 {
1357 ps_op->s_ive_op.u4_error_code |= 1
1358 << IVE_UNSUPPORTEDPARAM;
1359 ps_op->s_ive_op.u4_error_code |=
1360 IH264E_INVALID_QPEL_OPTION;
1361 return IV_FAIL;
1362 }
1363
1364 if ((ps_ip->s_ive_ip.u4_enable_fast_sad != 0)
1365 && (ps_ip->s_ive_ip.u4_enable_fast_sad != 1))
1366 {
1367 ps_op->s_ive_op.u4_error_code |= 1
1368 << IVE_UNSUPPORTEDPARAM;
1369 ps_op->s_ive_op.u4_error_code |=
1370 IH264E_INVALID_FAST_SAD_OPTION;
1371 return IV_FAIL;
1372 }
1373
1374 if (ps_ip->s_ive_ip.u4_enable_alt_ref > 255)
1375 {
1376 ps_op->s_ive_op.u4_error_code |= 1
1377 << IVE_UNSUPPORTEDPARAM;
1378 ps_op->s_ive_op.u4_error_code |=
1379 IH264E_INVALID_ALT_REF_OPTION;
1380 return IV_FAIL;
1381 }
1382
1383 if (ps_ip->s_ive_ip.u4_srch_rng_x
1384 > ps_codec->s_cfg.u4_max_srch_rng_x)
1385 {
1386 ps_op->s_ive_op.u4_error_code |= 1
1387 << IVE_UNSUPPORTEDPARAM;
1388 ps_op->s_ive_op.u4_error_code |=
1389 IH264E_HORIZONTAL_SEARCH_RANGE_NOT_SUPPORTED;
1390 return (IV_FAIL);
1391 }
1392
1393 if (ps_ip->s_ive_ip.u4_srch_rng_y
1394 > ps_codec->s_cfg.u4_max_srch_rng_y)
1395 {
1396 ps_op->s_ive_op.u4_error_code |= 1
1397 << IVE_UNSUPPORTEDPARAM;
1398 ps_op->s_ive_op.u4_error_code |=
1399 IH264E_VERTICAL_SEARCH_RANGE_NOT_SUPPORTED;
1400 return (IV_FAIL);
1401 }
1402
1403 break;
1404 }
1405
1406 case IVE_CMD_CTL_SET_IPE_PARAMS:
1407 {
1408 ih264e_ctl_set_ipe_params_ip_t *ps_ip = pv_api_ip;
1409 ih264e_ctl_set_ipe_params_op_t *ps_op = pv_api_op;
1410
1411 if (ps_ip->s_ive_ip.u4_size
1412 != sizeof(ih264e_ctl_set_ipe_params_ip_t))
1413 {
1414 ps_op->s_ive_op.u4_error_code |= 1
1415 << IVE_UNSUPPORTEDPARAM;
1416 ps_op->s_ive_op.u4_error_code |=
1417 IVE_ERR_IP_CTL_SETIPEPARAMS_API_STRUCT_SIZE_INCORRECT;
1418 return IV_FAIL;
1419 }
1420
1421 if (ps_op->s_ive_op.u4_size
1422 != sizeof(ih264e_ctl_set_ipe_params_op_t))
1423 {
1424 ps_op->s_ive_op.u4_error_code |= 1
1425 << IVE_UNSUPPORTEDPARAM;
1426 ps_op->s_ive_op.u4_error_code |=
1427 IVE_ERR_OP_CTL_SETIPEPARAMS_API_STRUCT_SIZE_INCORRECT;
1428 return IV_FAIL;
1429 }
1430
1431 if ((ps_ip->s_ive_ip.u4_enable_intra_4x4 != 0)
1432 && (ps_ip->s_ive_ip.u4_enable_intra_4x4 != 1))
1433 {
1434 ps_op->s_ive_op.u4_error_code |= 1
1435 << IVE_UNSUPPORTEDPARAM;
1436 ps_op->s_ive_op.u4_error_code |=
1437 IH264E_INVALID_INTRA4x4_OPTION;
1438 return IV_FAIL;
1439 }
1440
Doney Alexdfe686a2016-02-24 12:00:03 +0530[diff] [blame]1441 if ((ps_ip->s_ive_ip.u4_constrained_intra_pred != 0)
1442 && (ps_ip->s_ive_ip.u4_constrained_intra_pred != 1))
1443 {
1444 ps_op->s_ive_op.u4_error_code |= 1
1445 << IVE_UNSUPPORTEDPARAM;
1446 ps_op->s_ive_op.u4_error_code |=
1447 IH264E_INVALID_CONSTRAINED_INTRA_PREDICTION_MODE;
1448 return IV_FAIL;
1449 }
1450
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1451 if ((ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_CONFIG)
1452 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_SLOWEST)
1453 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_NORMAL)
1454 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_FAST)
1455 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_HIGH_SPEED)
1456 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_FASTEST))
1457 {
1458 ps_op->s_ive_op.u4_error_code |= 1
1459 << IVE_UNSUPPORTEDPARAM;
1460 ps_op->s_ive_op.u4_error_code |=
1461 IH264E_INVALID_ENC_SPEED_PRESET;
1462 return IV_FAIL;
1463 }
1464
1465 break;
1466 }
1467
1468 case IVE_CMD_CTL_SET_GOP_PARAMS:
1469 {
1470 ih264e_ctl_set_gop_params_ip_t *ps_ip = pv_api_ip;
1471 ih264e_ctl_set_gop_params_op_t *ps_op = pv_api_op;
1472
1473 if (ps_ip->s_ive_ip.u4_size
1474 != sizeof(ih264e_ctl_set_gop_params_ip_t))
1475 {
1476 ps_op->s_ive_op.u4_error_code |= 1
1477 << IVE_UNSUPPORTEDPARAM;
1478 ps_op->s_ive_op.u4_error_code |=
1479 IVE_ERR_IP_CTL_SETGOPPARAMS_API_STRUCT_SIZE_INCORRECT;
1480 return IV_FAIL;
1481 }
1482
1483 if (ps_op->s_ive_op.u4_size
1484 != sizeof(ih264e_ctl_set_gop_params_op_t))
1485 {
1486 ps_op->s_ive_op.u4_error_code |= 1
1487 << IVE_UNSUPPORTEDPARAM;
1488 ps_op->s_ive_op.u4_error_code |=
1489 IVE_ERR_OP_CTL_SETGOPPARAMS_API_STRUCT_SIZE_INCORRECT;
1490 return IV_FAIL;
1491 }
1492
1493 if ((ps_ip->s_ive_ip.u4_i_frm_interval < DEFAULT_MIN_INTRA_FRAME_RATE)
1494 || (ps_ip->s_ive_ip.u4_i_frm_interval > DEFAULT_MAX_INTRA_FRAME_RATE))
1495 {
1496 ps_op->s_ive_op.u4_error_code |= 1
1497 << IVE_UNSUPPORTEDPARAM;
1498 ps_op->s_ive_op.u4_error_code |=
1499 IH264E_INVALID_INTRA_FRAME_INTERVAL;
1500 return IV_FAIL;
1501 }
1502
1503 if ((ps_ip->s_ive_ip.u4_idr_frm_interval < DEFAULT_MIN_INTRA_FRAME_RATE)
1504 || (ps_ip->s_ive_ip.u4_idr_frm_interval > DEFAULT_MAX_INTRA_FRAME_RATE))
1505 {
1506 ps_op->s_ive_op.u4_error_code |= 1
1507 << IVE_UNSUPPORTEDPARAM;
1508 ps_op->s_ive_op.u4_error_code |=
1509 IH264E_INVALID_IDR_FRAME_INTERVAL;
1510 return IV_FAIL;
1511 }
1512
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1513 break;
1514 }
1515
1516 case IVE_CMD_CTL_SET_DEBLOCK_PARAMS:
1517 {
1518 ih264e_ctl_set_deblock_params_ip_t *ps_ip = pv_api_ip;
1519 ih264e_ctl_set_deblock_params_op_t *ps_op = pv_api_op;
1520
1521 if (ps_ip->s_ive_ip.u4_size
1522 != sizeof(ih264e_ctl_set_deblock_params_ip_t))
1523 {
1524 ps_op->s_ive_op.u4_error_code |= 1
1525 << IVE_UNSUPPORTEDPARAM;
1526 ps_op->s_ive_op.u4_error_code |=
1527 IVE_ERR_IP_CTL_SETDEBLKPARAMS_API_STRUCT_SIZE_INCORRECT;
1528 return IV_FAIL;
1529 }
1530
1531 if (ps_op->s_ive_op.u4_size
1532 != sizeof(ih264e_ctl_set_deblock_params_op_t))
1533 {
1534 ps_op->s_ive_op.u4_error_code |= 1
1535 << IVE_UNSUPPORTEDPARAM;
1536 ps_op->s_ive_op.u4_error_code |=
1537 IVE_ERR_OP_CTL_SETDEBLKPARAMS_API_STRUCT_SIZE_INCORRECT;
1538 return IV_FAIL;
1539 }
1540
1541 if ((ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_0)
1542 && (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_2)
1543 && (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_3)
1544 && (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_4))
1545 {
1546 ps_op->s_ive_op.u4_error_code |= 1
1547 << IVE_UNSUPPORTEDPARAM;
1548 ps_op->s_ive_op.u4_error_code |=
1549 IH264E_INVALID_DEBLOCKING_TYPE_INPUT;
1550 return IV_FAIL;
1551 }
1552
1553 break;
1554 }
1555
1556 case IVE_CMD_CTL_SET_QP:
1557 {
1558 ih264e_ctl_set_qp_ip_t *ps_ip = pv_api_ip;
1559 ih264e_ctl_set_qp_op_t *ps_op = pv_api_op;
1560
1561 if (ps_ip->s_ive_ip.u4_size
1562 != sizeof(ih264e_ctl_set_qp_ip_t))
1563 {
1564 ps_op->s_ive_op.u4_error_code |= 1
1565 << IVE_UNSUPPORTEDPARAM;
1566 ps_op->s_ive_op.u4_error_code |=
1567 IVE_ERR_IP_CTL_SETQPPARAMS_API_STRUCT_SIZE_INCORRECT;
1568 return IV_FAIL;
1569 }
1570
1571 if (ps_op->s_ive_op.u4_size
1572 != sizeof(ih264e_ctl_set_qp_op_t))
1573 {
1574 ps_op->s_ive_op.u4_error_code |= 1
1575 << IVE_UNSUPPORTEDPARAM;
1576 ps_op->s_ive_op.u4_error_code |=
1577 IVE_ERR_OP_CTL_SETQPPARAMS_API_STRUCT_SIZE_INCORRECT;
1578 return IV_FAIL;
1579 }
1580
1581 if ((ps_ip->s_ive_ip.u4_i_qp_max > MAX_H264_QP)
1582 || (ps_ip->s_ive_ip.u4_p_qp_max > MAX_H264_QP)
1583 || (ps_ip->s_ive_ip.u4_b_qp_max > MAX_H264_QP))
1584 {
1585 ps_op->s_ive_op.u4_error_code |= 1
1586 << IVE_UNSUPPORTEDPARAM;
1587 ps_op->s_ive_op.u4_error_code |=
1588 IH264E_INVALID_MAX_FRAME_QP;
1589 return IV_FAIL;
1590 }
1591
Harinarayanan K K85883032015-06-19 11:39:42 +0530[diff] [blame]1592 /* We donot support QP < 4 */
1593 if ((ps_ip->s_ive_ip.u4_i_qp_min < 4)
1594 || (ps_ip->s_ive_ip.u4_p_qp_min < 4)
1595 || (ps_ip->s_ive_ip.u4_b_qp_min < 4)
1596 || (ps_ip->s_ive_ip.u4_i_qp_min > ps_ip->s_ive_ip.u4_i_qp_max)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1597 || (ps_ip->s_ive_ip.u4_p_qp_min > ps_ip->s_ive_ip.u4_p_qp_max)
1598 || (ps_ip->s_ive_ip.u4_b_qp_min > ps_ip->s_ive_ip.u4_b_qp_max))
1599 {
1600 ps_op->s_ive_op.u4_error_code |= 1
1601 << IVE_UNSUPPORTEDPARAM;
1602 ps_op->s_ive_op.u4_error_code |=
1603 IH264E_INVALID_MIN_FRAME_QP;
1604 return IV_FAIL;
1605 }
1606
1607 if ((ps_ip->s_ive_ip.u4_i_qp > ps_ip->s_ive_ip.u4_i_qp_max)
1608 || (ps_ip->s_ive_ip.u4_p_qp > ps_ip->s_ive_ip.u4_p_qp_max)
1609 || (ps_ip->s_ive_ip.u4_b_qp > ps_ip->s_ive_ip.u4_b_qp_max))
1610 {
1611 ps_op->s_ive_op.u4_error_code |= 1
1612 << IVE_UNSUPPORTEDPARAM;
1613 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_INIT_QP;
1614 return IV_FAIL;
1615 }
1616
1617 if ((ps_ip->s_ive_ip.u4_i_qp < ps_ip->s_ive_ip.u4_i_qp_min)
1618 || (ps_ip->s_ive_ip.u4_p_qp < ps_ip->s_ive_ip.u4_p_qp_min)
1619 || (ps_ip->s_ive_ip.u4_b_qp < ps_ip->s_ive_ip.u4_b_qp_min))
1620 {
1621 ps_op->s_ive_op.u4_error_code |= 1
1622 << IVE_UNSUPPORTEDPARAM;
1623 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_INIT_QP;
1624 return IV_FAIL;
1625 }
1626
1627 break;
1628 }
1629
Doney Alex983e1ae2016-03-30 17:31:26 +0530[diff] [blame]1630 case IVE_CMD_CTL_SET_VUI_PARAMS:
1631 {
1632 ih264e_vui_ip_t *ps_ip = pv_api_ip;
1633 ih264e_vui_op_t *ps_op = pv_api_op;
1634
1635 if(ps_ip->u4_size != sizeof(ih264e_vui_ip_t))
1636 {
1637 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1638 ps_op->u4_error_code |=
1639 IVE_ERR_IP_CTL_SET_VUI_STRUCT_SIZE_INCORRECT;
1640 return IV_FAIL;
1641 }
1642
1643 if(ps_op->u4_size != sizeof(ih264e_vui_op_t))
1644 {
1645 ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
1646 ps_op->u4_error_code |=
1647 IVE_ERR_OP_CTL_SET_VUI_STRUCT_SIZE_INCORRECT;
1648 return IV_FAIL;
1649 }
1650
1651 break;
1652 }
1653
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1654 case IVE_CMD_CTL_SET_ENC_MODE:
1655 {
1656 ih264e_ctl_set_enc_mode_ip_t *ps_ip = pv_api_ip;
1657 ih264e_ctl_set_enc_mode_op_t *ps_op = pv_api_op;
1658
1659 if (ps_ip->s_ive_ip.u4_size
1660 != sizeof(ih264e_ctl_set_enc_mode_ip_t))
1661 {
1662 ps_op->s_ive_op.u4_error_code |= 1
1663 << IVE_UNSUPPORTEDPARAM;
1664 ps_op->s_ive_op.u4_error_code |=
1665 IVE_ERR_IP_CTL_SETENCMODE_API_STRUCT_SIZE_INCORRECT;
1666 return IV_FAIL;
1667 }
1668
1669 if (ps_op->s_ive_op.u4_size
1670 != sizeof(ih264e_ctl_set_enc_mode_op_t))
1671 {
1672 ps_op->s_ive_op.u4_error_code |= 1
1673 << IVE_UNSUPPORTEDPARAM;
1674 ps_op->s_ive_op.u4_error_code |=
1675 IVE_ERR_OP_CTL_SETENCMODE_API_STRUCT_SIZE_INCORRECT;
1676 return IV_FAIL;
1677 }
1678
1679 if ((ps_ip->s_ive_ip.e_enc_mode != IVE_ENC_MODE_HEADER)
1680 && (ps_ip->s_ive_ip.e_enc_mode != IVE_ENC_MODE_PICTURE))
1681 {
1682 ps_op->s_ive_op.u4_error_code |= 1
1683 << IVE_UNSUPPORTEDPARAM;
1684 ps_op->s_ive_op.u4_error_code |=
1685 IH264E_INVALID_ENC_OPERATION_MODE;
1686 return IV_FAIL;
1687 }
1688
1689 break;
1690 }
1691
1692 case IVE_CMD_CTL_SET_VBV_PARAMS:
1693 {
1694 ih264e_ctl_set_vbv_params_ip_t *ps_ip = pv_api_ip;
1695 ih264e_ctl_set_vbv_params_op_t *ps_op = pv_api_op;
1696
1697 if (ps_ip->s_ive_ip.u4_size
1698 != sizeof(ih264e_ctl_set_vbv_params_ip_t))
1699 {
1700 ps_op->s_ive_op.u4_error_code |= 1
1701 << IVE_UNSUPPORTEDPARAM;
1702 ps_op->s_ive_op.u4_error_code |=
1703 IVE_ERR_IP_CTL_SETVBVPARAMS_API_STRUCT_SIZE_INCORRECT;
1704 return IV_FAIL;
1705 }
1706
1707 if (ps_op->s_ive_op.u4_size
1708 != sizeof(ih264e_ctl_set_vbv_params_op_t))
1709 {
1710 ps_op->s_ive_op.u4_error_code |= 1
1711 << IVE_UNSUPPORTEDPARAM;
1712 ps_op->s_ive_op.u4_error_code |=
1713 IVE_ERR_OP_CTL_SETVBVPARAMS_API_STRUCT_SIZE_INCORRECT;
1714 return IV_FAIL;
1715 }
1716
1717 if ((ps_ip->s_ive_ip.u4_vbv_buffer_delay < DEFAULT_MIN_BUFFER_DELAY)
1718 || (ps_ip->s_ive_ip.u4_vbv_buffer_delay > DEFAULT_MAX_BUFFER_DELAY))
1719 {
1720 ps_op->s_ive_op.u4_error_code |= 1
1721 << IVE_UNSUPPORTEDPARAM;
1722 ps_op->s_ive_op.u4_error_code |=
1723 IH264E_INVALID_BUFFER_DELAY;
1724 return IV_FAIL;
1725 }
1726
1727 break;
1728 }
1729
1730 case IVE_CMD_CTL_SET_AIR_PARAMS:
1731 {
1732 ih264e_ctl_set_air_params_ip_t *ps_ip = pv_api_ip;
1733 ih264e_ctl_set_air_params_op_t *ps_op = pv_api_op;
1734
1735 if (ps_ip->s_ive_ip.u4_size
1736 != sizeof(ih264e_ctl_set_air_params_ip_t))
1737 {
1738 ps_op->s_ive_op.u4_error_code |= 1
1739 << IVE_UNSUPPORTEDPARAM;
1740 ps_op->s_ive_op.u4_error_code |=
1741 IVE_ERR_IP_CTL_SETAIRPARAMS_API_STRUCT_SIZE_INCORRECT;
1742 return IV_FAIL;
1743 }
1744
1745 if (ps_op->s_ive_op.u4_size
1746 != sizeof(ih264e_ctl_set_air_params_op_t))
1747 {
1748 ps_op->s_ive_op.u4_error_code |= 1
1749 << IVE_UNSUPPORTEDPARAM;
1750 ps_op->s_ive_op.u4_error_code |=
1751 IVE_ERR_OP_CTL_SETAIRPARAMS_API_STRUCT_SIZE_INCORRECT;
1752 return IV_FAIL;
1753 }
1754
1755 if ((ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_NONE)
1756 && (ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_CYCLIC)
1757 && (ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_RANDOM))
1758 {
1759 ps_op->s_ive_op.u4_error_code |= 1
1760 << IVE_UNSUPPORTEDPARAM;
1761 ps_op->s_ive_op.u4_error_code |=
1762 IH264E_INVALID_AIR_MODE;
1763 return IV_FAIL;
1764 }
1765
1766 if (ps_ip->s_ive_ip.u4_air_refresh_period == 0)
1767 {
1768 ps_op->s_ive_op.u4_error_code |= 1
1769 << IVE_UNSUPPORTEDPARAM;
1770 ps_op->s_ive_op.u4_error_code |=
1771 IH264E_INVALID_AIR_REFRESH_PERIOD;
1772 return IV_FAIL;
1773 }
1774
1775 break;
1776 }
1777
1778 case IVE_CMD_CTL_SET_PROFILE_PARAMS:
1779 {
1780 ih264e_ctl_set_profile_params_ip_t *ps_ip = pv_api_ip;
1781 ih264e_ctl_set_profile_params_op_t *ps_op = pv_api_op;
1782
1783 if (ps_ip->s_ive_ip.u4_size
1784 != sizeof(ih264e_ctl_set_profile_params_ip_t))
1785 {
1786 ps_op->s_ive_op.u4_error_code |= 1
1787 << IVE_UNSUPPORTEDPARAM;
1788 ps_op->s_ive_op.u4_error_code |=
1789 IVE_ERR_IP_CTL_SETPROFILE_API_STRUCT_SIZE_INCORRECT;
1790 return IV_FAIL;
1791 }
1792
1793 if (ps_op->s_ive_op.u4_size
1794 != sizeof(ih264e_ctl_set_profile_params_op_t))
1795 {
1796 ps_op->s_ive_op.u4_error_code |= 1
1797 << IVE_UNSUPPORTEDPARAM;
1798 ps_op->s_ive_op.u4_error_code |=
1799 IVE_ERR_OP_CTL_SETPROFILE_API_STRUCT_SIZE_INCORRECT;
1800 return IV_FAIL;
1801 }
1802
Martin Storsjo517e0622015-06-20 21:46:30 +0300[diff] [blame]1803 if (ps_ip->s_ive_ip.e_profile != IV_PROFILE_BASE &&
1804 ps_ip->s_ive_ip.e_profile != IV_PROFILE_MAIN)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1805 {
1806 ps_op->s_ive_op.u4_error_code |= 1
1807 << IVE_UNSUPPORTEDPARAM;
1808 ps_op->s_ive_op.u4_error_code |=
1809 IH264E_PROFILE_NOT_SUPPORTED;
1810 return IV_FAIL;
1811 }
1812
Martin Storsjo5696adb2015-07-03 13:56:20 +0300[diff] [blame]1813 if (ps_ip->s_ive_ip.u4_entropy_coding_mode > 1)
1814 {
1815 ps_op->s_ive_op.u4_error_code |= 1
1816 << IVE_UNSUPPORTEDPARAM;
1817 ps_op->s_ive_op.u4_error_code |=
1818 IH264E_INVALID_ENTROPY_CODING_MODE;
1819 return IV_FAIL;
1820 }
1821
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1822 break;
1823 }
1824
1825 default:
1826 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
1827 *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_SUB_CMD;
1828 return IV_FAIL;
1829 }
1830
1831 break;
1832 }
1833
1834 default:
1835 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
1836 *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_CMD;
1837 return IV_FAIL;
1838 }
1839
1840 return IV_SUCCESS;
1841}
1842
1843/**
1844*******************************************************************************
1845*
1846* @brief update encoder configuration parameters
1847*
1848* @par Description:
1849* updates encoder configuration parameters from the given config set.
1850* Initialize/reinitialize codec parameters according to new configurations.
1851*
1852* @param[in] ps_codec
1853* Pointer to codec context
1854*
1855* @param[in] ps_cfg
1856* Pointer to config param set
1857*
1858* @remarks none
1859*
1860*******************************************************************************
1861*/
1862IH264E_ERROR_T ih264e_codec_update_config(codec_t *ps_codec,
1863 cfg_params_t *ps_cfg)
1864{
1865 /* config params */
1866 cfg_params_t *ps_curr_cfg = &ps_codec->s_cfg;
1867
1868 /* error status */
1869 IH264E_ERROR_T err = IH264E_SUCCESS;
1870
1871 /* temp var */
1872 UWORD32 u4_init_rc = 0;
1873
1874 /***********************/
1875 /* UPDATE CODEC CONFIG */
1876 /***********************/
1877 if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_DIMENSIONS)
1878 {
1879 UWORD32 wd_aln = ALIGN16(ps_cfg->u4_wd);
1880 UWORD32 ht_aln = ALIGN16(ps_cfg->u4_ht);
1881
1882 if (ps_curr_cfg->u4_wd != wd_aln || ps_curr_cfg->u4_ht != ht_aln
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1883 || ps_curr_cfg->u4_disp_wd != ps_cfg->u4_disp_wd
1884 || ps_curr_cfg->u4_disp_ht != ps_cfg->u4_disp_ht)
1885 {
1886 ps_curr_cfg->u4_wd = wd_aln;
1887 ps_curr_cfg->u4_ht = ht_aln;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1888
1889 ps_curr_cfg->u4_disp_wd = ps_cfg->u4_disp_wd;
1890 ps_curr_cfg->u4_disp_ht = ps_cfg->u4_disp_ht;
1891
1892 ps_curr_cfg->i4_wd_mbs = ps_curr_cfg->u4_wd >> 4;
1893 ps_curr_cfg->i4_ht_mbs = ps_curr_cfg->u4_ht >> 4;
1894
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1895 ps_codec->i4_rec_strd = ALIGN16(ps_cfg->u4_wd) + PAD_WD;
1896
1897 /* If number of MBs in a frame changes the air map also changes.
1898 * Hence recompute air map also reset air pic cnt */
1899 if (ps_codec->s_cfg.e_air_mode != IVE_AIR_MODE_NONE)
1900 {
1901 /* re-init the air map */
1902 ih264e_init_air_map(ps_codec);
1903
1904 /* reset air counter */
1905 ps_codec->i4_air_pic_cnt = -1;
1906 }
1907
1908 /* initialize mv bank buffer manager */
1909 err = ih264e_mv_buf_mgr_add_bufs(ps_codec);
1910 if (err != IH264E_SUCCESS)
1911 return err;
1912
1913 /* initialize ref bank buffer manager */
1914 err = ih264e_pic_buf_mgr_add_bufs(ps_codec);
1915 if (err != IH264E_SUCCESS)
1916 return err;
1917
1918 /* since dimension changed, start new sequence by forcing IDR */
1919 ps_codec->force_curr_frame_type = IV_IDR_FRAME;
1920
1921 /* in case dimension changes, we need to reinitialize RC as the
1922 * old model shall not fit further */
1923 u4_init_rc = 1;
1924
1925 /* when the dimension changes, the header needs to be regenerated */
Martin Storsjoafe8d032015-06-23 11:14:45 +0300[diff] [blame]1926 ps_codec->i4_gen_header = 1;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1927 }
1928 }
1929 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_FRAMERATE)
1930 {
1931 /* temp var */
1932 UWORD32 u4_src_ticks, u4_tgt_ticks;
1933
1934 u4_src_ticks = ih264e_frame_time_get_src_ticks(
1935 ps_codec->s_rate_control.pps_frame_time);
1936
1937 u4_tgt_ticks = ih264e_frame_time_get_tgt_ticks(
1938 ps_codec->s_rate_control.pps_frame_time);
1939
1940 /* Change frame rate */
1941 if (ps_codec->s_cfg.u4_src_frame_rate
1942 != ps_cfg->u4_src_frame_rate * 1000)
1943 {
1944 ps_codec->s_cfg.u4_src_frame_rate = ps_cfg->u4_src_frame_rate
1945 * 1000;
1946
1947 ih264e_frame_time_update_src_frame_rate(
1948 ps_codec->s_rate_control.pps_frame_time,
1949 ps_codec->s_cfg.u4_src_frame_rate);
1950
1951 ih264_time_stamp_update_frame_rate(
1952 ps_codec->s_rate_control.pps_time_stamp,
1953 ps_codec->s_cfg.u4_src_frame_rate);
1954
1955 irc_change_frame_rate(ps_codec->s_rate_control.pps_rate_control_api,
1956 ps_codec->s_cfg.u4_src_frame_rate,
1957 u4_src_ticks, u4_tgt_ticks);
1958 }
1959
1960 if (ps_codec->s_cfg.u4_tgt_frame_rate
1961 != ps_cfg->u4_tgt_frame_rate * 1000)
1962 {
1963 ps_codec->s_cfg.u4_tgt_frame_rate = ps_cfg->u4_tgt_frame_rate
1964 * 1000;
1965
1966 ih264e_frame_time_update_tgt_frame_rate(
1967 ps_codec->s_rate_control.pps_frame_time,
1968 ps_codec->s_cfg.u4_tgt_frame_rate);
1969
1970 irc_change_frame_rate(ps_codec->s_rate_control.pps_rate_control_api,
1971 ps_codec->s_cfg.u4_src_frame_rate,
1972 u4_src_ticks, u4_tgt_ticks);
1973
1974 irc_change_frm_rate_for_bit_alloc(
1975 ps_codec->s_rate_control.pps_rate_control_api,
1976 ps_codec->s_cfg.u4_tgt_frame_rate);
1977 }
1978
1979 }
1980 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_BITRATE)
1981 {
1982 if (ps_curr_cfg->u4_target_bitrate != ps_cfg->u4_target_bitrate)
1983 {
1984 if (IVE_RC_NONE != ps_curr_cfg->e_rc_mode)
1985 irc_change_avg_bit_rate(
1986 ps_codec->s_rate_control.pps_rate_control_api,
1987 ps_cfg->u4_target_bitrate);
1988
1989 ps_curr_cfg->u4_target_bitrate = ps_cfg->u4_target_bitrate;
1990 }
1991 }
1992 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_FRAMETYPE)
1993 {
1994 switch (ps_cfg->e_frame_type)
1995 {
1996 case IV_I_FRAME:
1997 ps_codec->force_curr_frame_type = IV_I_FRAME;
1998 break;
1999
2000 case IV_IDR_FRAME:
2001 ps_codec->force_curr_frame_type = IV_IDR_FRAME;
2002 break;
2003
2004 case IV_P_FRAME:
2005 default:
2006 break;
2007 }
2008 }
2009 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_ME_PARAMS)
2010 {
2011 if (ps_curr_cfg->u4_enc_speed_preset == IVE_CONFIG)
2012 {
2013 ps_codec->s_cfg.u4_enable_hpel = ps_cfg->u4_enable_hpel;
2014 ps_codec->s_cfg.u4_enable_fast_sad = ps_cfg->u4_enable_fast_sad;
2015 ps_codec->s_cfg.u4_me_speed_preset = ps_cfg->u4_me_speed_preset;
2016 ps_codec->s_cfg.u4_enable_qpel = ps_cfg->u4_enable_qpel;
2017 }
2018 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_FASTEST)
2019 {
2020 ps_codec->s_cfg.u4_enable_fast_sad = ps_cfg->u4_enable_fast_sad;
2021 }
2022 ps_codec->s_cfg.u4_srch_rng_x = ps_cfg->u4_srch_rng_x;
2023 ps_codec->s_cfg.u4_srch_rng_y = ps_cfg->u4_srch_rng_y;
2024
2025 if (ps_codec->s_cfg.u4_enable_alt_ref != ps_cfg->u4_enable_alt_ref)
2026 {
2027 ps_codec->s_cfg.u4_enable_alt_ref = ps_cfg->u4_enable_alt_ref;
2028 ps_codec->u4_is_curr_frm_ref = 1;
2029 }
2030 }
2031 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_IPE_PARAMS)
2032 {
2033 ps_curr_cfg->u4_enc_speed_preset = ps_cfg->u4_enc_speed_preset;
Doney Alexdfe686a2016-02-24 12:00:03 +0530[diff] [blame]2034 ps_curr_cfg->u4_constrained_intra_pred = ps_cfg->u4_constrained_intra_pred;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2035 if (ps_curr_cfg->u4_enc_speed_preset == IVE_SLOWEST)
2036 {/* high quality */
2037 /* enable diamond search */
2038 ps_curr_cfg->u4_me_speed_preset = DMND_SRCH;
2039 ps_curr_cfg->u4_enable_fast_sad = 0;
2040
2041 /* disable intra 4x4 */
2042 ps_curr_cfg->u4_enable_intra_4x4 = 1;
2043 ps_codec->luma_energy_compaction[1] =
2044 ih264e_code_luma_intra_macroblock_4x4_rdopt_on;
2045
2046 /* sub pel off */
2047 ps_curr_cfg->u4_enable_hpel = 1;
2048
2049 /* deblocking off */
2050 ps_curr_cfg->u4_disable_deblock_level = DISABLE_DEBLK_LEVEL_0;
2051
2052 /* disabled intra inter gating in Inter slices */
2053 ps_codec->u4_inter_gate = 0;
2054 }
2055 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_NORMAL)
2056 {/* normal */
2057 /* enable diamond search */
2058 ps_curr_cfg->u4_me_speed_preset = DMND_SRCH;
2059 ps_curr_cfg->u4_enable_fast_sad = 0;
2060
2061 /* disable intra 4x4 */
2062 ps_curr_cfg->u4_enable_intra_4x4 = 1;
2063
2064 /* sub pel off */
2065 ps_curr_cfg->u4_enable_hpel = 1;
2066
2067 /* deblocking off */
2068 ps_curr_cfg->u4_disable_deblock_level = DISABLE_DEBLK_LEVEL_0;
2069
2070 /* disabled intra inter gating in Inter slices */
2071 ps_codec->u4_inter_gate = 0;
2072 }
2073 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_FAST)
2074 {/* normal */
2075 /* enable diamond search */
2076 ps_curr_cfg->u4_me_speed_preset = DMND_SRCH;
2077 ps_curr_cfg->u4_enable_fast_sad = 0;
2078
2079 /* disable intra 4x4 */
2080 ps_curr_cfg->u4_enable_intra_4x4 = 0;
2081
2082 /* sub pel off */
2083 ps_curr_cfg->u4_enable_hpel = 1;
2084
2085 /* deblocking off */
2086 ps_curr_cfg->u4_disable_deblock_level = DISABLE_DEBLK_LEVEL_0;
2087
2088 /* disabled intra inter gating in Inter slices */
2089 ps_codec->u4_inter_gate = 1;
2090 }
2091 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_HIGH_SPEED)
2092 {/* fast */
2093 /* enable diamond search */
2094 ps_curr_cfg->u4_me_speed_preset = DMND_SRCH;
2095 ps_curr_cfg->u4_enable_fast_sad = 0;
2096
2097 /* disable intra 4x4 */
2098 ps_curr_cfg->u4_enable_intra_4x4 = 0;
2099
2100 /* sub pel off */
2101 ps_curr_cfg->u4_enable_hpel = 0;
2102
2103 /* deblocking off */
2104 ps_curr_cfg->u4_disable_deblock_level = DISABLE_DEBLK_LEVEL_4;
2105
2106 /* disabled intra inter gating in Inter slices */
2107 ps_codec->u4_inter_gate = 0;
2108 }
2109 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_FASTEST)
2110 {/* fastest */
2111 /* enable diamond search */
2112 ps_curr_cfg->u4_me_speed_preset = DMND_SRCH;
2113 //u4_num_layers = 4;
2114
2115 /* disable intra 4x4 */
2116 ps_curr_cfg->u4_enable_intra_4x4 = 0;
2117
2118 /* sub pel off */
2119 ps_curr_cfg->u4_enable_hpel = 0;
2120
2121 /* deblocking off */
2122 ps_curr_cfg->u4_disable_deblock_level = DISABLE_DEBLK_LEVEL_4;
2123
2124 /* disabled intra inter gating in Inter slices */
2125 ps_codec->u4_inter_gate = 1;
2126 }
2127 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_CONFIG)
2128 {
2129 ps_curr_cfg->u4_enable_intra_4x4 = ps_cfg->u4_enable_intra_4x4;
2130 }
2131 }
2132 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_GOP_PARAMS)
2133 {
2134 if (ps_curr_cfg->u4_i_frm_interval != ps_cfg->u4_i_frm_interval)
2135 {
2136 ps_curr_cfg->u4_i_frm_interval = ps_cfg->u4_i_frm_interval;
2137
2138 /* reset air counter */
2139 ps_codec->i4_air_pic_cnt = -1;
2140
2141 /* re-init air map */
2142 ih264e_init_air_map(ps_codec);
2143
2144 /*Effect intra frame interval change*/
2145
2146 irc_change_intra_frm_int_call(
2147 ps_codec->s_rate_control.pps_rate_control_api,
2148 ps_curr_cfg->u4_i_frm_interval);
2149 }
2150
2151 ps_curr_cfg->u4_idr_frm_interval = ps_cfg->u4_idr_frm_interval;
2152
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2153 }
2154 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_DEBLOCK_PARAMS)
2155 {
2156 if (ps_curr_cfg->u4_enc_speed_preset == IVE_CONFIG)
2157 {
2158 ps_curr_cfg->u4_disable_deblock_level =
2159 ps_cfg->u4_disable_deblock_level;
2160 }
2161 }
2162 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_QP)
2163 {
2164 UWORD8 au1_init_qp[MAX_PIC_TYPE];
2165 UWORD8 au1_min_max_qp[2 * MAX_PIC_TYPE];
2166
2167 ps_codec->s_cfg.u4_i_qp_max = ps_cfg->u4_i_qp_max;
2168 ps_codec->s_cfg.u4_i_qp_min = ps_cfg->u4_i_qp_min;
2169 ps_codec->s_cfg.u4_i_qp = ps_cfg->u4_i_qp;
2170
2171 ps_codec->s_cfg.u4_p_qp_max = ps_cfg->u4_p_qp_max;
2172 ps_codec->s_cfg.u4_p_qp_min = ps_cfg->u4_p_qp_min;
2173 ps_codec->s_cfg.u4_p_qp = ps_cfg->u4_p_qp;
2174
2175 ps_codec->s_cfg.u4_b_qp_max = ps_cfg->u4_b_qp_max;
2176 ps_codec->s_cfg.u4_b_qp_min = ps_cfg->u4_b_qp_min;
2177 ps_codec->s_cfg.u4_b_qp = ps_cfg->u4_b_qp;
2178
2179 /* update rc lib with modified qp */
2180 au1_init_qp[0] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp];
2181 au1_init_qp[1] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp];
2182 au1_init_qp[2] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp];
2183
2184 irc_change_init_qp(ps_codec->s_rate_control.pps_rate_control_api,
2185 au1_init_qp);
2186
2187 au1_min_max_qp[2 * I_PIC] =
2188 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_min];
2189 au1_min_max_qp[2 * I_PIC + 1] =
2190 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_max];
2191
2192 au1_min_max_qp[2 * P_PIC] =
2193 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_min];
2194 au1_min_max_qp[2 * P_PIC + 1] =
2195 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_max];
2196
2197 au1_min_max_qp[2 * B_PIC] =
2198 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_min];
2199 au1_min_max_qp[2 * B_PIC + 1] =
2200 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_max];
2201
2202 irc_change_min_max_qp(ps_codec->s_rate_control.pps_rate_control_api,
2203 au1_min_max_qp);
2204 }
2205 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_ENC_MODE)
2206 {
2207 ps_codec->s_cfg.e_enc_mode = ps_cfg->e_enc_mode;
2208
2209 if (ps_codec->s_cfg.e_enc_mode == IVE_ENC_MODE_HEADER)
2210 {
2211 ps_codec->i4_header_mode = 1;
2212 ps_codec->s_cfg.e_enc_mode = IVE_ENC_MODE_PICTURE;
2213 }
2214 else
2215 {
2216 ps_codec->i4_header_mode = 0;
2217 }
2218 }
2219 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_VBV_PARAMS
2220 && IVE_RC_NONE != ps_codec->s_cfg.e_rc_mode)
2221 {
2222 ps_codec->s_cfg.u4_vbv_buf_size = ps_cfg->u4_vbv_buf_size;
2223 ps_codec->s_cfg.u4_vbv_buffer_delay = ps_cfg->u4_vbv_buffer_delay;
2224
2225 // irc_change_buffer_delay(ps_codec->s_rate_control.pps_rate_control_api, ps_codec->s_cfg.u4_vbv_buffer_delay);
2226
2227 // TODO: remove this when the support for changing buffer dynamically
2228 // is yet to be added.
2229 u4_init_rc = 1;
2230 }
2231 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_AIR_PARAMS)
2232 {
2233 if (ps_curr_cfg->e_air_mode != ps_cfg->e_air_mode
2234 || ps_curr_cfg->u4_air_refresh_period
2235 != ps_cfg->u4_air_refresh_period)
2236 {
2237 ps_curr_cfg->e_air_mode = ps_cfg->e_air_mode;
2238 ps_curr_cfg->u4_air_refresh_period = ps_cfg->u4_air_refresh_period;
2239
2240 ih264e_init_air_map(ps_codec);
2241
2242 /* reset air counter */
2243 ps_codec->i4_air_pic_cnt = -1;
2244 }
2245 }
2246 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_PROFILE_PARAMS)
2247 {
2248 ps_codec->s_cfg.e_profile = ps_cfg->e_profile;
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame]2249 ps_codec->s_cfg.u4_entropy_coding_mode = ps_cfg->u4_entropy_coding_mode;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2250 }
2251 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_NUM_CORES)
2252 {
2253 ps_codec->s_cfg.u4_num_cores = ps_cfg->u4_num_cores;
2254 }
Doney Alex983e1ae2016-03-30 17:31:26 +0530[diff] [blame]2255 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_VUI_PARAMS)
2256 {
2257 ps_codec->s_cfg.s_vui = ps_cfg->s_vui;
2258 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2259 /* reset RC model */
2260 if (u4_init_rc)
2261 {
2262 /* init qp */
2263 UWORD8 au1_init_qp[MAX_PIC_TYPE];
2264
2265 /* min max qp */
2266 UWORD8 au1_min_max_qp[2 * MAX_PIC_TYPE];
2267
2268 /* init i,p,b qp */
2269 au1_init_qp[0] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp];
2270 au1_init_qp[1] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp];
2271 au1_init_qp[2] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp];
2272
2273 /* init min max qp */
2274 au1_min_max_qp[2 * I_PIC] =
2275 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_min];
2276 au1_min_max_qp[2 * I_PIC + 1] =
2277 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_max];
2278
2279 au1_min_max_qp[2 * P_PIC] =
2280 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_min];
2281 au1_min_max_qp[2 * P_PIC + 1] =
2282 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_max];
2283
2284 au1_min_max_qp[2 * B_PIC] =
2285 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_min];
2286 au1_min_max_qp[2 * B_PIC + 1] =
2287 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_max];
2288
2289 /* get rc mode */
2290 switch (ps_codec->s_cfg.e_rc_mode)
2291 {
2292 case IVE_RC_STORAGE:
2293 ps_codec->s_rate_control.e_rc_type = VBR_STORAGE;
2294 break;
2295
2296 case IVE_RC_CBR_NON_LOW_DELAY:
2297 ps_codec->s_rate_control.e_rc_type = CBR_NLDRC;
2298 break;
2299
2300 case IVE_RC_CBR_LOW_DELAY:
2301 ps_codec->s_rate_control.e_rc_type = CBR_LDRC;
2302 break;
2303
2304 case IVE_RC_NONE:
2305 ps_codec->s_rate_control.e_rc_type = CONST_QP;
2306 break;
2307
2308 default:
2309 break;
2310 }
2311
2312 /* init rate control */
2313 ih264e_rc_init(ps_codec->s_rate_control.pps_rate_control_api,
2314 ps_codec->s_rate_control.pps_frame_time,
2315 ps_codec->s_rate_control.pps_time_stamp,
2316 ps_codec->s_rate_control.pps_pd_frm_rate,
2317 ps_codec->s_cfg.u4_max_framerate,
2318 ps_codec->s_cfg.u4_src_frame_rate,
2319 ps_codec->s_cfg.u4_tgt_frame_rate,
2320 ps_codec->s_rate_control.e_rc_type,
2321 ps_codec->s_cfg.u4_target_bitrate,
2322 ps_codec->s_cfg.u4_max_bitrate,
2323 ps_codec->s_cfg.u4_vbv_buffer_delay,
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame]2324 ps_codec->s_cfg.u4_i_frm_interval,
2325 ps_codec->s_cfg.u4_num_bframes + 1, au1_init_qp,
2326 ps_codec->s_cfg.u4_num_bframes + 2, au1_min_max_qp,
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2327 ps_codec->s_cfg.u4_max_level);
2328 }
2329
2330 return err;
2331}
2332
2333/**
2334*******************************************************************************
2335*
2336* @brief
2337* Sets default encoder config parameters
2338*
2339* @par Description:
2340* Sets default dynamic parameters. Will be called in ih264e_init() to ensure
2341* that even if set_params is not called, codec continues to work
2342*
2343* @param[in] ps_cfg
2344* Pointer to encoder config params
2345*
2346* @returns error status
2347*
2348* @remarks none
2349*
2350*******************************************************************************
2351*/
2352static WORD32 ih264e_set_default_params(cfg_params_t *ps_cfg)
2353{
2354 WORD32 ret = IV_SUCCESS;
2355
2356 ps_cfg->u4_max_wd = MAX_WD;
2357 ps_cfg->u4_max_ht = MAX_HT;
2358 ps_cfg->u4_max_ref_cnt = MAX_REF_CNT;
2359 ps_cfg->u4_max_reorder_cnt = MAX_REF_CNT;
2360 ps_cfg->u4_max_level = DEFAULT_MAX_LEVEL;
2361 ps_cfg->e_inp_color_fmt = IV_YUV_420SP_UV;
2362 ps_cfg->u4_enable_recon = DEFAULT_RECON_ENABLE;
2363 ps_cfg->e_recon_color_fmt = IV_YUV_420P;
2364 ps_cfg->u4_enc_speed_preset = IVE_FASTEST;
2365 ps_cfg->e_rc_mode = DEFAULT_RC;
2366 ps_cfg->u4_max_framerate = DEFAULT_MAX_FRAMERATE;
2367 ps_cfg->u4_max_bitrate = DEFAULT_MAX_BITRATE;
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame]2368 ps_cfg->u4_num_bframes = DEFAULT_MAX_NUM_BFRAMES;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2369 ps_cfg->e_content_type = IV_PROGRESSIVE;
2370 ps_cfg->u4_max_srch_rng_x = DEFAULT_MAX_SRCH_RANGE_X;
2371 ps_cfg->u4_max_srch_rng_y = DEFAULT_MAX_SRCH_RANGE_Y;
2372 ps_cfg->e_slice_mode = IVE_SLICE_MODE_NONE;
2373 ps_cfg->u4_slice_param = DEFAULT_SLICE_PARAM;
2374 ps_cfg->e_arch = ih264e_default_arch();
2375 ps_cfg->e_soc = SOC_GENERIC;
2376 ps_cfg->u4_disp_wd = MAX_WD;
2377 ps_cfg->u4_disp_ht = MAX_HT;
2378 ps_cfg->u4_wd = MAX_WD;
2379 ps_cfg->u4_ht = MAX_HT;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2380 ps_cfg->u4_src_frame_rate = DEFAULT_SRC_FRAME_RATE;
2381 ps_cfg->u4_tgt_frame_rate = DEFAULT_TGT_FRAME_RATE;
2382 ps_cfg->u4_target_bitrate = DEFAULT_BITRATE;
2383 ps_cfg->e_frame_type = IV_NA_FRAME;
2384 ps_cfg->e_enc_mode = IVE_ENC_MODE_DEFAULT;
2385 ps_cfg->u4_i_qp = DEFAULT_I_QP;
2386 ps_cfg->u4_p_qp = DEFAULT_P_QP;
2387 ps_cfg->u4_b_qp = DEFAULT_B_QP;
2388 ps_cfg->u4_i_qp_min = DEFAULT_QP_MIN;
2389 ps_cfg->u4_i_qp_max = DEFAULT_QP_MAX;
2390 ps_cfg->u4_p_qp_min = DEFAULT_QP_MIN;
2391 ps_cfg->u4_p_qp_max = DEFAULT_QP_MAX;
2392 ps_cfg->u4_b_qp_min = DEFAULT_QP_MIN;
2393 ps_cfg->u4_b_qp_max = DEFAULT_QP_MAX;
2394 ps_cfg->e_air_mode = DEFAULT_AIR_MODE;
2395 ps_cfg->u4_air_refresh_period = DEFAULT_AIR_REFRESH_PERIOD;
2396 ps_cfg->u4_vbv_buffer_delay = DEFAULT_VBV_DELAY;
2397 ps_cfg->u4_vbv_buf_size = DEFAULT_VBV_SIZE;
2398 ps_cfg->u4_num_cores = DEFAULT_NUM_CORES;
2399 ps_cfg->u4_me_speed_preset = DEFAULT_ME_SPEED_PRESET;
2400 ps_cfg->u4_enable_hpel = DEFAULT_HPEL;
2401 ps_cfg->u4_enable_qpel = DEFAULT_QPEL;
2402 ps_cfg->u4_enable_intra_4x4 = DEFAULT_I4;
2403 ps_cfg->u4_enable_intra_8x8 = DEFAULT_I8;
2404 ps_cfg->u4_enable_intra_16x16 = DEFAULT_I16;
2405 ps_cfg->u4_enable_fast_sad = DEFAULT_ENABLE_FAST_SAD;
2406 ps_cfg->u4_enable_satqd = DEFAULT_ENABLE_SATQD;
2407 ps_cfg->i4_min_sad =
2408 (ps_cfg->u4_enable_satqd == DEFAULT_ENABLE_SATQD) ?
2409 DEFAULT_MIN_SAD_ENABLE :
2410 DEFAULT_MIN_SAD_DISABLE;
2411 ps_cfg->u4_srch_rng_x = DEFAULT_SRCH_RNG_X;
2412 ps_cfg->u4_srch_rng_y = DEFAULT_SRCH_RNG_Y;
2413 ps_cfg->u4_i_frm_interval = DEFAULT_I_INTERVAL;
2414 ps_cfg->u4_idr_frm_interval = DEFAULT_IDR_INTERVAL;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2415 ps_cfg->u4_disable_deblock_level = DEFAULT_DISABLE_DEBLK_LEVEL;
2416 ps_cfg->e_profile = DEFAULT_PROFILE;
2417 ps_cfg->u4_timestamp_low = 0;
2418 ps_cfg->u4_timestamp_high = 0;
2419 ps_cfg->u4_is_valid = 1;
2420 ps_cfg->e_cmd = IVE_CMD_CT_NA;
2421 ps_cfg->i4_wd_mbs = ps_cfg->u4_max_wd >> 4;
2422 ps_cfg->i4_ht_mbs = ps_cfg->u4_max_ht >> 4;
2423 ps_cfg->u4_entropy_coding_mode = CAVLC;
2424 ps_cfg->u4_weighted_prediction = 0;
2425 ps_cfg->u4_constrained_intra_pred = 0;
2426 ps_cfg->u4_pic_info_type = 0;
2427 ps_cfg->u4_mb_info_type = 0;
2428
2429 return ret;
2430}
2431
2432/**
2433*******************************************************************************
2434*
2435* @brief
2436* Initialize encoder context. This will be called by init_mem_rec and during
2437* codec reset
2438*
2439* @par Description:
2440* Initializes the context
2441*
2442* @param[in] ps_codec
2443* Codec context pointer
2444*
2445* @returns error status
2446*
2447* @remarks none
2448*
2449*******************************************************************************
2450*/
2451static WORD32 ih264e_init(codec_t *ps_codec)
2452{
2453 /* enc config param set */
2454 cfg_params_t *ps_cfg = &(ps_codec->s_cfg);
2455
2456 /* temp var */
2457 WORD32 i;
2458
2459 /* coded pic count */
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame]2460 ps_codec->i4_poc = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2461
2462 /* Number of API calls to encode are made */
2463 ps_codec->i4_encode_api_call_cnt = -1;
2464
2465 /* Indicates no header has been generated yet */
2466 ps_codec->u4_header_generated = 0;
2467
2468 /* Number of pictures encoded */
2469 ps_codec->i4_pic_cnt = -1;
2470
2471 /* Number of threads created */
2472 ps_codec->i4_proc_thread_cnt = 0;
2473
2474 /* ctl mutex init */
2475 ithread_mutex_init(ps_codec->pv_ctl_mutex);
2476
2477 /* Set encoder chroma format */
2478 ps_codec->e_codec_color_format =
2479 (ps_cfg->e_inp_color_fmt == IV_YUV_420SP_VU) ?
2480 IV_YUV_420SP_VU : IV_YUV_420SP_UV;
2481
2482 /* Number of continuous frames where deblocking was disabled */
2483 ps_codec->i4_disable_deblk_pic_cnt = 0;
2484
2485 /* frame num */
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame]2486 ps_codec->i4_frame_num = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2487
2488 /* set the current frame type to I frame, since we are going to start encoding*/
2489 ps_codec->force_curr_frame_type = IV_NA_FRAME;
2490
2491 /* idr_pic_id */
2492 ps_codec->i4_idr_pic_id = -1;
2493
2494 /* Flush mode */
2495 ps_codec->i4_flush_mode = 0;
2496
2497 /* Encode header mode */
2498 ps_codec->i4_header_mode = 0;
2499
2500 /* Encode generate header */
2501 ps_codec->i4_gen_header = 0;
2502
2503 /* To signal successful completion of init */
2504 ps_codec->i4_init_done = 1;
2505
2506 /* To signal that at least one picture was decoded */
2507 ps_codec->i4_first_pic_done = 0;
2508
2509 /* Reset Codec */
2510 ps_codec->i4_reset_flag = 0;
2511
2512 /* Current error code */
2513 ps_codec->i4_error_code = IH264E_SUCCESS;
2514
2515 /* threshold residue */
2516 ps_codec->u4_thres_resi = 1;
2517
2518 /* inter gating enable */
2519 ps_codec->u4_inter_gate = 0;
2520
2521 /* entropy mutex init */
2522 ithread_mutex_init(ps_codec->pv_entropy_mutex);
2523
2524 /* sps id */
2525 ps_codec->i4_sps_id = 0;
2526
2527 /* sps id */
2528 ps_codec->i4_pps_id = 0;
2529
2530 /* Process thread created status */
2531 memset(ps_codec->ai4_process_thread_created, 0, MAX_PROCESS_THREADS);
2532
2533 /* Number of MBs processed together */
2534 ps_codec->i4_proc_nmb = 8;
2535
2536 /* Previous POC msb */
2537 ps_codec->i4_prev_poc_msb = 0;
2538
2539 /* Previous POC lsb */
2540 ps_codec->i4_prev_poc_lsb = -1;
2541
2542 /* max Previous POC lsb */
2543 ps_codec->i4_max_prev_poc_lsb = -1;
2544
2545 /* sps, pps status */
2546 {
2547 sps_t *ps_sps = ps_codec->ps_sps_base;
2548 pps_t *ps_pps = ps_codec->ps_pps_base;
2549
2550 for (i = 0; i < MAX_SPS_CNT; i++)
2551 {
2552 ps_sps->i1_sps_valid = 0;
2553 ps_sps++;
2554 }
2555
2556 for (i = 0; i < MAX_PPS_CNT; i++)
2557 {
2558 ps_pps->i1_pps_valid = 0;
2559 ps_pps++;
2560 }
2561 }
2562
2563 {
2564 WORD32 max_mb_rows = ps_cfg->i4_ht_mbs;
2565
Harinarayanan K K6cb67722015-06-19 14:44:42 +0530[diff] [blame]2566 WORD32 num_jobs = max_mb_rows * MAX_CTXT_SETS;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2567 WORD32 clz;
2568
2569 /* Use next power of two number of entries*/
2570 clz = CLZ(num_jobs);
2571 num_jobs = 1 << (32 - clz);
2572
2573 /* init process jobq */
2574 ps_codec->pv_proc_jobq = ih264_list_init(
2575 ps_codec->pv_proc_jobq_buf,
2576 ps_codec->i4_proc_jobq_buf_size, num_jobs,
2577 sizeof(job_t), 10);
2578 RETURN_IF((ps_codec->pv_proc_jobq == NULL), IV_FAIL);
2579 ih264_list_reset(ps_codec->pv_proc_jobq);
2580
2581 /* init entropy jobq */
2582 ps_codec->pv_entropy_jobq = ih264_list_init(
2583 ps_codec->pv_entropy_jobq_buf,
2584 ps_codec->i4_entropy_jobq_buf_size, num_jobs,
2585 sizeof(job_t), 10);
2586 RETURN_IF((ps_codec->pv_entropy_jobq == NULL), IV_FAIL);
2587 ih264_list_reset(ps_codec->pv_entropy_jobq);
2588 }
2589
2590 /* Update the jobq context to all the threads */
2591 for (i = 0; i < MAX_PROCESS_CTXT; i++)
2592 {
2593 ps_codec->as_process[i].pv_proc_jobq = ps_codec->pv_proc_jobq;
2594 ps_codec->as_process[i].pv_entropy_jobq = ps_codec->pv_entropy_jobq;
2595
2596 /* i4_id always stays between 0 and MAX_PROCESS_THREADS */
2597 ps_codec->as_process[i].i4_id =
2598 (i >= MAX_PROCESS_THREADS) ?
2599 (i - MAX_PROCESS_THREADS) : i;
2600 ps_codec->as_process[i].ps_codec = ps_codec;
2601
2602 ps_codec->as_process[i].s_entropy.pv_proc_jobq = ps_codec->pv_proc_jobq;
2603 ps_codec->as_process[i].s_entropy.pv_entropy_jobq =
2604 ps_codec->pv_entropy_jobq;
2605 ps_codec->as_process[i].s_entropy.i4_abs_pic_order_cnt = -1;
2606 }
2607
2608 /* Initialize MV Bank buffer manager */
2609 ps_codec->pv_mv_buf_mgr = ih264_buf_mgr_init(ps_codec->pv_mv_buf_mgr_base);
2610
2611 /* Initialize Picture buffer manager for reference buffers*/
2612 ps_codec->pv_ref_buf_mgr = ih264_buf_mgr_init(
2613 ps_codec->pv_ref_buf_mgr_base);
2614
2615 /* Initialize Picture buffer manager for input buffers*/
2616 ps_codec->pv_inp_buf_mgr = ih264_buf_mgr_init(
2617 ps_codec->pv_inp_buf_mgr_base);
2618
2619 /* Initialize buffer manager for output buffers*/
2620 ps_codec->pv_out_buf_mgr = ih264_buf_mgr_init(
2621 ps_codec->pv_out_buf_mgr_base);
2622
2623 /* buffer cnt in buffer manager */
2624 ps_codec->i4_inp_buf_cnt = 0;
2625 ps_codec->i4_out_buf_cnt = 0;
2626 ps_codec->i4_ref_buf_cnt = 0;
2627
2628 ps_codec->ps_pic_buf = (pic_buf_t *) ps_codec->pv_pic_buf_base;
2629 memset(ps_codec->ps_pic_buf, 0, BUF_MGR_MAX_CNT * sizeof(pic_buf_t));
2630
2631 /* Initialize dpb manager */
2632 ih264_dpb_mgr_init((dpb_mgr_t*) ps_codec->pv_dpb_mgr);
2633
2634 memset(ps_codec->as_ref_set, 0,
2635 sizeof(ref_set_t) * (MAX_DPB_SIZE + MAX_CTXT_SETS));
2636 for (i = 0; i < (MAX_DPB_SIZE + MAX_CTXT_SETS); i++)
2637 {
2638 ps_codec->as_ref_set[i].i4_pic_cnt = -1;
2639 }
2640
2641 /* fn ptr init */
2642 ih264e_init_function_ptr(ps_codec);
2643
2644 /* reset status flags */
2645 for (i = 0; i < MAX_CTXT_SETS; i++)
2646 {
2647 ps_codec->au4_entropy_thread_active[i] = 0;
2648 ps_codec->ai4_pic_cnt[i] = -1;
2649
2650 ps_codec->s_rate_control.pre_encode_skip[i] = 0;
2651 ps_codec->s_rate_control.post_encode_skip[i] = 0;
2652 }
2653
2654 ps_codec->s_rate_control.num_intra_in_prev_frame = 0;
2655 ps_codec->s_rate_control.i4_avg_activity = 0;
2656
2657 return IV_SUCCESS;
2658}
2659
2660/**
2661*******************************************************************************
2662*
2663* @brief
2664* Gets number of memory records required by the codec
2665*
2666* @par Description:
2667* Gets codec memory requirements
2668*
2669* @param[in] pv_api_ip
2670* Pointer to input argument structure
2671*
2672* @param[out] pv_api_op
2673* Pointer to output argument structure
2674*
2675* @returns status
2676*
2677* @remarks
2678*
2679*******************************************************************************
2680*/
2681static WORD32 ih264e_get_num_rec(void *pv_api_ip, void *pv_api_op)
2682{
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2683 /* api call I/O structures */
2684 ih264e_num_mem_rec_op_t *ps_op = pv_api_op;
2685
Martin Storsjocc872412015-06-13 00:35:01 +0300[diff] [blame]2686 UNUSED(pv_api_ip);
2687
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2688 ps_op->s_ive_op.u4_num_mem_rec = MEM_REC_CNT;
2689
2690 return IV_SUCCESS;
2691}
2692
2693/**
2694*******************************************************************************
2695*
2696* @brief
2697* Fills memory records of the codec
2698*
2699* @par Description:
2700* Fills codec memory requirements
2701*
2702* @param[in] pv_api_ip
2703* Pointer to input argument structure
2704*
2705* @param[out] pv_api_op
2706* Pointer to output argument structure
2707*
2708* @returns error status
2709*
2710* @remarks none
2711*
2712*******************************************************************************
2713*/
2714static WORD32 ih264e_fill_num_mem_rec(void *pv_api_ip, void *pv_api_op)
2715{
2716 /* api call I/O structures */
2717 ih264e_fill_mem_rec_ip_t *ps_ip = pv_api_ip;
2718 ih264e_fill_mem_rec_op_t *ps_op = pv_api_op;
2719
2720 /* profile / level info */
2721 WORD32 level;
2722 WORD32 num_reorder_frames;
2723 WORD32 num_ref_frames;
2724
2725 /* mem records */
2726 WORD32 no_of_mem_rec;
2727 iv_mem_rec_t *ps_mem_rec_base, *ps_mem_rec;
2728
2729 /* frame dimensions */
2730 WORD32 max_wd_luma, max_ht_luma;
2731 WORD32 max_mb_rows, max_mb_cols, max_mb_cnt;
2732
2733 /* temp var */
2734 WORD32 i;
2735
2736 /* error status */
2737 IV_STATUS_T status = IV_SUCCESS;
2738
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2739 num_reorder_frames = ps_ip->s_ive_ip.u4_max_reorder_cnt;
2740 num_ref_frames = ps_ip->s_ive_ip.u4_max_ref_cnt;
2741
2742 /* mem records */
2743 ps_mem_rec_base = ps_ip->s_ive_ip.ps_mem_rec;
2744 no_of_mem_rec = ps_ip->s_ive_ip.u4_num_mem_rec;
2745
2746 /* frame dimensions */
2747 max_ht_luma = ps_ip->s_ive_ip.u4_max_ht;
2748 max_wd_luma = ps_ip->s_ive_ip.u4_max_wd;
2749 max_ht_luma = ALIGN16(max_ht_luma);
2750 max_wd_luma = ALIGN16(max_wd_luma);
2751 max_mb_rows = max_ht_luma / MB_SIZE;
2752 max_mb_cols = max_wd_luma / MB_SIZE;
2753 max_mb_cnt = max_mb_rows * max_mb_cols;
2754
Harinarayanan K K6cb67722015-06-19 14:44:42 +0530[diff] [blame]2755 /* profile / level info */
2756 level = ih264e_get_min_level(max_ht_luma, max_wd_luma);
2757
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2758 /* validate params */
2759 if ((level < MIN_LEVEL) || (level > MAX_LEVEL))
2760 {
2761 ps_op->s_ive_op.u4_error_code |= IH264E_CODEC_LEVEL_NOT_SUPPORTED;
2762 level = MAX_LEVEL;
2763 }
2764
2765 if (num_ref_frames > MAX_REF_CNT)
2766 {
2767 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED;
2768 num_ref_frames = MAX_REF_CNT;
2769 }
2770
2771 if (num_reorder_frames > MAX_REF_CNT)
2772 {
2773 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED;
2774 num_reorder_frames = MAX_REF_CNT;
2775 }
2776
2777 /* Set all memory records as persistent and alignment as 128 by default */
2778 ps_mem_rec = ps_mem_rec_base;
2779 for (i = 0; i < no_of_mem_rec; i++)
2780 {
2781 ps_mem_rec->u4_mem_alignment = 128;
2782 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2783 ps_mem_rec++;
2784 }
2785
2786 /************************************************************************
2787 * Request memory for h264 encoder handle *
2788 ***********************************************************************/
2789 ps_mem_rec = &ps_mem_rec_base[MEM_REC_IV_OBJ];
2790 {
2791 ps_mem_rec->u4_mem_size = sizeof(iv_obj_t);
2792 }
2793 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_IV_OBJ, ps_mem_rec->u4_mem_size);
2794
2795 /************************************************************************
2796 * Request memory for h264 encoder context *
2797 ***********************************************************************/
2798 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CODEC];
2799 {
2800 ps_mem_rec->u4_mem_size = sizeof(codec_t);
2801 }
2802 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CODEC, ps_mem_rec->u4_mem_size);
2803
2804 /************************************************************************
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame]2805 * Request memory for CABAC context *
2806 ***********************************************************************/
2807 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC];
2808 {
2809 ps_mem_rec->u4_mem_size = sizeof(cabac_ctxt_t);
2810 }
2811 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CABAC, ps_mem_rec->u4_mem_size);
2812
2813 /************************************************************************
2814 * Request memory for CABAC MB info *
2815 ***********************************************************************/
2816 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC_MB_INFO];
2817 {
2818 ps_mem_rec->u4_mem_size = ((max_mb_cols + 1) + 1)
2819 * sizeof(mb_info_ctxt_t);
2820 }
2821 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CABAC_MB_INFO, ps_mem_rec->u4_mem_size);
2822
2823
2824 /************************************************************************
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2825 * Request memory for entropy context *
2826 * In multi core encoding, each row is assumed to be launched on a *
2827 * thread. The rows below can only start after its neighbors are coded *
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame]2828 * The status of an mb coded/uncoded is signaled via entropy map. *
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2829 * 1. One word32 to store skip run cnt *
2830 * 2. mb entropy map (mb status entropy coded/uncoded). The size*
2831 * of the entropy map is max mb cols. Further allocate one *
2832 * more additional row to evade checking for row -1. *
2833 * 3. size of bit stream buffer to store bit stream ctxt. *
2834 * 4. Entropy coding is dependent on nnz coefficient count for *
2835 * the neighbor blocks. It is sufficient to maintain one row *
2836 * worth of nnz as entropy for lower row waits on entropy map*
2837 ************************************************************************/
2838 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY];
2839 {
2840 /* total size of the mem record */
2841 WORD32 total_size = 0;
2842
2843 /* size of skip mb run */
2844 total_size += sizeof(WORD32);
2845 total_size = ALIGN8(total_size);
2846
2847 /* size in bytes to store entropy status of an entire frame */
2848 total_size += (max_mb_cols * max_mb_rows);
2849 /* add an additional 1 row of bytes to evade the special case of row 0 */
2850 total_size += max_mb_cols;
2851 total_size = ALIGN128(total_size);
2852
2853 /* size of bit stream buffer */
2854 total_size += sizeof(bitstrm_t);
2855 total_size = ALIGN128(total_size);
2856
2857 /* top nnz luma */
2858 total_size += (max_mb_cols * 4 * sizeof(UWORD8));
2859 total_size = ALIGN128(total_size);
2860
2861 /* top nnz cbcr */
2862 total_size += (max_mb_cols * 4 * sizeof(UWORD8));
2863 total_size = ALIGN128(total_size);
2864
2865 /* total size per each proc ctxt */
2866 total_size *= MAX_CTXT_SETS;
2867
2868 ps_mem_rec->u4_mem_size = total_size;
2869 }
2870 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ENTROPY, ps_mem_rec->u4_mem_size);
2871
2872 /************************************************************************
2873 * The residue coefficients that needs to be entropy coded are packed *
2874 * at a buffer space by the proc threads. The entropy thread shall *
2875 * read from the buffer space, unpack them and encode the same. The *
2876 * buffer space required to pack a row of mbs are as follows. *
2877 * Assuming transform_8x8_flag is disabled, *
2878 * In the worst case, 1 mb contains 1 dc 4x4 luma sub block, followed *
2879 * by 16 ac 4x4 luma sub blocks, 2 dc chroma 2x2 sub blocks, followed *
2880 * by 8 ac 4x4 chroma sub blocks. *
2881 * For the sake of simplicity we assume that all sub blocks are of *
2882 * type 4x4. The packing of each 4x4 is depicted by the structure *
2883 * tu_sblk_coeff_data_t *
2884 ************************************************************************/
2885 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_COEFF_DATA];
2886 {
2887 /* temp var */
2888 WORD32 size = 0;
2889
2890 /* size of coeff data of 1 mb */
2891 size += sizeof(tu_sblk_coeff_data_t) * MAX_4x4_SUBBLKS;
2892
2893 /* size of coeff data of 1 row of mb's */
2894 size *= max_mb_cols;
2895
2896 /* align to avoid any false sharing across threads */
2897 size = ALIGN64(size);
2898
2899 /* size for one full frame */
2900 size *= max_mb_rows;
2901
2902 /* size of each proc buffer set (ping, pong) */
2903 size *= MAX_CTXT_SETS;
2904
2905 ps_mem_rec->u4_mem_size = size;
2906 }
2907 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MB_COEFF_DATA, ps_mem_rec->u4_mem_size);
2908
2909 /************************************************************************
2910 * while encoding an mb, the mb header data is signaled to the entropy*
2911 * thread by writing to a buffer space. the size of header data per mb *
2912 * is assumed to be 40 bytes *
2913 * TODO: revisit this inference *
2914 ************************************************************************/
2915 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_HEADER_DATA];
2916 {
2917 /* temp var */
2918 WORD32 size;
2919
2920 /* size per MB */
2921 size = 40;
2922
2923 /* size for 1 row of mbs */
2924 size = size * max_mb_cols;
2925
2926 /* align to avoid any false sharing across threads */
2927 size = ALIGN64(size);
2928
2929 /* size for one full frame */
2930 size *= max_mb_rows;
2931
2932 /* size of each proc buffer set (ping, pong) */
2933 size *= MAX_CTXT_SETS;
2934
2935 ps_mem_rec->u4_mem_size = size;
2936 }
2937 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MB_HEADER_DATA, ps_mem_rec->u4_mem_size);
2938
2939 /************************************************************************
2940 * Size for holding mv_buf_t for each MV Bank. *
2941 * Note this allocation is done for BUF_MGR_MAX_CNT instead of *
2942 * MAX_DPB_SIZE or max_dpb_size for following reasons *
2943 * max_dpb_size will be based on max_wd and max_ht *
2944 * For higher max_wd and max_ht this number will be smaller than *
2945 * MAX_DPB_SIZE But during actual initialization number of buffers *
2946 * allocated can be more. *
2947 * *
2948 * One extra MV Bank is needed to hold current pics MV bank. *
2949 * Since this is only a structure allocation and not actual buffer *
2950 * allocation, it is allocated for BUF_MGR_MAX_CNT entries *
2951 ************************************************************************/
2952 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBANK];
2953 {
2954 /* max luma samples */
2955 WORD32 max_luma_samples = 0;
2956
2957 /* determine max luma samples */
2958 for (i = 0; i < 16; i++)
2959 if (level ==(WORD32)gas_ih264_lvl_tbl[i].u4_level_idc)
2960 max_luma_samples = gas_ih264_lvl_tbl[i].u4_max_fs
2961 << (BLK_SIZE + BLK_SIZE);
2962
2963 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
2964
2965 /************************************************************************
2966 * Allocate for pu_map, enc_pu_t and pic_pu_idx for each MV bank *
2967 * Note: Number of luma samples is not max_wd * max_ht here, instead it *
2968 * is set to maximum number of luma samples allowed at the given level. *
2969 * This is done to ensure that any stream with width and height lesser *
2970 * than max_wd and max_ht is supported. Number of buffers required can *
2971 * be greater for lower width and heights at a given level and this *
2972 * increased number of buffers might require more memory than what *
2973 * max_wd and max_ht buffer would have required Also note one extra *
2974 * buffer is allocated to store current pictures MV bank. *
2975 ***********************************************************************/
2976
2977 ps_mem_rec->u4_mem_size += BUF_MGR_MAX_CNT * sizeof(mv_buf_t);
2978
2979 ps_mem_rec->u4_mem_size += (num_ref_frames + num_reorder_frames
2980 + MAX_CTXT_SETS)
2981 * ih264e_get_pic_mv_bank_size(max_luma_samples);
2982 }
2983 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MVBANK, ps_mem_rec->u4_mem_size);
2984
2985 /************************************************************************
2986 * While encoding inter slices, to compute the cost of encoding an mb *
2987 * with the mv's at hand, we employ the expression cost = sad + lambda *
2988 * x mv_bits. Here mv_bits is the total number of bits taken to represe*
2989 * nt the mv in the stream. The mv bits for all the possible mv are *
2990 * stored in the look up table. The mem record for this look up table *
2991 * is given below. *
2992 ************************************************************************/
2993 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBITS];
2994 {
2995 /* max srch range x */
2996 UWORD32 u4_srch_range_x = ps_ip->s_ive_ip.u4_max_srch_rng_x;
2997
2998 /* max srch range y */
2999 UWORD32 u4_srch_range_y = ps_ip->s_ive_ip.u4_max_srch_rng_y;
3000
3001 /* max srch range */
3002 UWORD32 u4_max_srch_range = MAX(u4_srch_range_x, u4_srch_range_y);
3003
3004 /* due to subpel */
3005 u4_max_srch_range <<= 2;
3006
3007 /* due to mv on either direction */
3008 u4_max_srch_range = (u4_max_srch_range << 1);
3009
3010 /* due to pred mv + zero */
3011 u4_max_srch_range = (u4_max_srch_range << 1) + 1;
3012
3013 u4_max_srch_range = ALIGN128(u4_max_srch_range);
3014
3015 ps_mem_rec->u4_mem_size = u4_max_srch_range;
3016 }
3017 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MVBITS, ps_mem_rec->u4_mem_size);
3018
3019 /************************************************************************
3020 * Request memory for SPS *
3021 ***********************************************************************/
3022 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SPS];
3023 {
3024 ps_mem_rec->u4_mem_size = MAX_SPS_CNT * sizeof(sps_t);
3025 }
3026 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SPS, ps_mem_rec->u4_mem_size);
3027
3028 /************************************************************************
3029 * Request memory for PPS *
3030 ***********************************************************************/
3031 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PPS];
3032 {
3033 ps_mem_rec->u4_mem_size = MAX_PPS_CNT * sizeof(pps_t);
3034 }
3035 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PPS, ps_mem_rec->u4_mem_size);
3036
3037 /************************************************************************
3038 * Request memory for Slice Header *
3039 ***********************************************************************/
3040 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_HDR];
3041 {
3042 ps_mem_rec->u4_mem_size = MAX_CTXT_SETS * MAX_SLICE_HDR_CNT
3043 * sizeof(slice_header_t);
3044 }
3045 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SLICE_HDR, ps_mem_rec->u4_mem_size);
3046
3047 /************************************************************************
3048 * Request memory for Adaptive Intra Refresh *
3049 ***********************************************************************/
3050 ps_mem_rec = &ps_mem_rec_base[MEM_REC_AIR_MAP];
3051 {
3052 /* total size of the mem record */
3053 WORD32 total_size = 0;
3054
3055 /* intra coded map */
3056 total_size += max_mb_cnt;
3057 total_size *= MAX_CTXT_SETS;
3058
3059 /* mb refresh map */
3060 total_size += sizeof(UWORD16) * max_mb_cnt;
3061
3062 /* alignment */
3063 total_size = ALIGN128(total_size);
3064
3065 ps_mem_rec->u4_mem_size = total_size;
3066 }
3067 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_AIR_MAP, ps_mem_rec->u4_mem_size);
3068
3069 /************************************************************************
3070 * In multi slice encoding, this memory record helps tracking the start*
3071 * of slice with reference to mb. *
3072 * MEM RECORD for holding *
3073 * 1. mb slice map *
3074 ************************************************************************/
3075 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_MAP];
3076 {
3077 /* total size of the mem record */
3078 WORD32 total_size = 0;
3079
3080 /* size in bytes to slice index of all mbs of a frame */
3081 total_size = ALIGN64(max_mb_cnt);
3082
Martin Storsjofc508f22015-05-24 01:26:35 +0300[diff] [blame]3083 /* ih264e_update_proc_ctxt can overread by 1 at the end */
3084 total_size += 1;
3085
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3086 /* total size per each proc ctxt */
3087 total_size *= MAX_CTXT_SETS;
3088 ps_mem_rec->u4_mem_size = total_size;
3089 }
3090 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SLICE_MAP, ps_mem_rec->u4_mem_size);
3091
3092 /************************************************************************
3093 * Request memory to hold thread handles for each processing thread *
3094 ************************************************************************/
3095 ps_mem_rec = &ps_mem_rec_base[MEM_REC_THREAD_HANDLE];
3096 {
3097 WORD32 handle_size = ithread_get_handle_size();
3098
3099 ps_mem_rec->u4_mem_size = MAX_PROCESS_THREADS * handle_size;
3100 }
3101 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_THREAD_HANDLE, ps_mem_rec->u4_mem_size);
3102
3103 /************************************************************************
3104 * Request memory to hold mutex for control calls *
3105 ************************************************************************/
3106 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CTL_MUTEX];
3107 {
3108 ps_mem_rec->u4_mem_size = ithread_get_mutex_lock_size();
3109 }
3110 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CTL_MUTEX, ps_mem_rec->u4_mem_size);
3111
3112 /************************************************************************
3113 * Request memory to hold mutex for entropy calls *
3114 ************************************************************************/
3115 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_MUTEX];
3116 {
3117 ps_mem_rec->u4_mem_size = ithread_get_mutex_lock_size();
3118 }
3119 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ENTROPY_MUTEX, ps_mem_rec->u4_mem_size);
3120
3121 /************************************************************************
3122 * Request memory to hold process jobs *
3123 ***********************************************************************/
3124 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_JOBQ];
3125 {
3126 /* One process job per row of MBs */
3127 /* Allocate for two pictures, so that wrap around can be handled easily */
Harinarayanan K K6cb67722015-06-19 14:44:42 +0530[diff] [blame]3128 WORD32 num_jobs = max_mb_rows * MAX_CTXT_SETS;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3129
3130 WORD32 job_queue_size = ih264_list_size(num_jobs, sizeof(job_t));
3131
3132 ps_mem_rec->u4_mem_size = job_queue_size;
3133 }
3134 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PROC_JOBQ, ps_mem_rec->u4_mem_size);
3135
3136 /************************************************************************
3137 * Request memory to hold entropy jobs *
3138 ***********************************************************************/
3139 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_JOBQ];
3140 {
3141 /* One process job per row of MBs */
3142 /* Allocate for two pictures, so that wrap around can be handled easily */
Harinarayanan K K6cb67722015-06-19 14:44:42 +0530[diff] [blame]3143 WORD32 num_jobs = max_mb_rows * MAX_CTXT_SETS;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3144
3145 WORD32 job_queue_size = ih264_list_size(num_jobs, sizeof(job_t));
3146
3147 ps_mem_rec->u4_mem_size = job_queue_size;
3148 }
3149 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ENTROPY_JOBQ, ps_mem_rec->u4_mem_size);
3150
3151 /************************************************************************
3152 * In multi core encoding, each row is assumed to be launched on a *
3153 * thread. The rows below can only start after its neighbors are coded *
3154 * The status of an mb coded/uncoded is signaled via proc map. *
3155 * MEM RECORD for holding *
3156 * 1. mb proc map (mb status core coded/uncoded) *
3157 ************************************************************************/
3158 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_MAP];
3159 {
3160 /* total size of the mem record */
3161 WORD32 total_size = 0;
3162
3163 /* size in bytes to mb core coding status of an entire frame */
3164 total_size = max_mb_cnt;
3165
3166 /* add an additional 1 row of bytes to evade the special case of row 0 */
3167 total_size += max_mb_cols;
3168
3169 /* total size per each proc ctxt */
3170 total_size *= MAX_CTXT_SETS;
3171 ps_mem_rec->u4_mem_size = total_size;
3172 }
3173 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PROC_MAP, ps_mem_rec->u4_mem_size);
3174
3175 /************************************************************************
3176 * mem record for holding a particular MB is deblocked or not *
3177 * 1. mb deblk map (mb status deblocked/not deblocked) *
3178 ************************************************************************/
3179 ps_mem_rec = &ps_mem_rec_base[MEM_REC_DBLK_MAP];
3180 {
3181 /* total size of the mem record */
3182 WORD32 total_size = 0;
3183
3184 /* size in bytes to mb core coding status of an entire frame */
3185 total_size = max_mb_cnt;
3186
3187 /* add an additional 1 row of bytes to evade the special case of row 0 */
3188 total_size += max_mb_cols;
3189
3190 total_size = ALIGN64(total_size);
3191
3192 /* total size per each proc ctxt */
3193 total_size *= MAX_CTXT_SETS;
3194 ps_mem_rec->u4_mem_size = total_size;
3195 }
3196 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_DBLK_MAP, ps_mem_rec->u4_mem_size);
3197
3198 /************************************************************************
3199 * mem record for holding a particular MB's me is done or not *
3200 * 1. mb me map *
3201 ************************************************************************/
3202 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ME_MAP];
3203 {
3204 /* total size of the mem record */
3205 WORD32 total_size = 0;
3206
3207 /* size in bytes to mb core coding status of an entire frame */
3208 total_size = max_mb_cnt;
3209
3210 /* add an additional 1 row of bytes to evade the special case of row 0 */
3211 total_size += max_mb_cols;
3212
3213 /* total size per each proc ctxt */
3214 total_size *= MAX_CTXT_SETS;
3215
3216 ps_mem_rec->u4_mem_size = total_size;
3217 }
3218 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ME_MAP, ps_mem_rec->u4_mem_size);
3219
3220 /************************************************************************
3221 * size for holding dpb manager context *
3222 ************************************************************************/
3223 ps_mem_rec = &ps_mem_rec_base[MEM_REC_DPB_MGR];
3224 {
3225 ps_mem_rec->u4_mem_size = sizeof(dpb_mgr_t);
3226 }
3227 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_DPB_MGR, ps_mem_rec->u4_mem_size);
3228
3229 /************************************************************************
3230 * luma or chroma core coding involves mb estimation, error computation*
3231 * between the estimated singnal and the actual signal, transform the *
3232 * error, quantize the error, then inverse transform and inverse quant *
3233 * ize the residue and add the result back to estimated signal. *
3234 * To perform all these, a set of temporary buffers are needed. *
3235 * MEM RECORD for holding scratch buffers *
3236 * 1. prediction buffer used during mb mode analysis *
3237 * 2 temp. reference buffer when intra 4x4 with rdopt on is *
3238 * enabled *
3239 * - when intra 4x4 is enabled, rdopt is on, to store the *
3240 * reconstructed values and use them later this temp. buffer *
3241 * is used. *
3242 * 3. prediction buffer used during intra mode analysis *
3243 * 4. prediction buffer used during intra 16x16 plane mode *
3244 * analysis
3245 * 5. prediction buffer used during intra chroma mode analysis *
3246 * 6. prediction buffer used during intra chroma 16x16 plane *
3247 * mode analysis
3248 * 7. forward transform output buffer *
3249 * - to store the error between estimated and the actual inp *
3250 * ut and to store the fwd transformed quantized output *
3251 * 8. forward transform output buffer *
3252 * - when intra 4x4 is enabled, rdopt is on, to store the *
3253 * fwd transform values and use them later this temp. buffer *
3254 * is used. *
3255 * 9. temporary buffer for inverse transform *
3256 * - temporary buffer used in inverse transform and inverse *
3257 * quantization *
3258 * A. Buffers for holding half_x , half_y and half_xy planes *
3259 ************************************************************************/
3260 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_SCRATCH];
3261 {
3262 WORD32 total_size = 0;
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame]3263 WORD32 i4_tmp_size;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3264
3265 /* size to hold prediction buffer */
3266 total_size += sizeof(UWORD8) * 16 * 16;
3267 total_size = ALIGN64(total_size);
3268
3269 /* size to hold recon for intra 4x4 buffer */
3270 total_size += sizeof(UWORD8) * 16 * 16;
3271 total_size = ALIGN64(total_size);
3272
3273 /* prediction buffer intra 16x16 */
3274 total_size += sizeof(UWORD8) * 16 * 16;
3275 total_size = ALIGN64(total_size);
3276
3277 /* prediction buffer intra 16x16 plane*/
3278 total_size += sizeof(UWORD8) * 16 * 16;
3279 total_size = ALIGN64(total_size);
3280
3281 /* prediction buffer intra chroma*/
3282 total_size += sizeof(UWORD8) * 16 * 8;
3283 total_size = ALIGN64(total_size);
3284
3285 /* prediction buffer intra chroma plane*/
3286 total_size += sizeof(UWORD8) * 16 * 8;
3287 total_size = ALIGN64(total_size);
3288
3289 /* size to hold fwd transform output */
3290 total_size += sizeof(WORD16) * SIZE_TRANS_BUFF;
3291 total_size = ALIGN64(total_size);
3292
3293 /* size to hold fwd transform output */
3294 total_size += sizeof(WORD16) * SIZE_TRANS_BUFF;
3295 total_size = ALIGN64(total_size);
3296
3297 /* size to hold temporary data during inverse transform */
3298 total_size += sizeof(WORD32) * SIZE_TMP_BUFF_ITRANS;
3299 total_size = ALIGN64(total_size);
3300
3301 /* Buffers for holding half_x , half_y and half_xy planes */
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame]3302 i4_tmp_size = sizeof(UWORD8) * (HP_BUFF_WD * HP_BUFF_HT);
3303 total_size += (ALIGN64(i4_tmp_size) * SUBPEL_BUFF_CNT);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3304
3305 /* Allocate for each process thread */
3306 total_size *= MAX_PROCESS_CTXT;
3307
3308 ps_mem_rec->u4_mem_size = total_size;
3309 }
3310 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PROC_SCRATCH, ps_mem_rec->u4_mem_size);
3311
3312 /************************************************************************
3313 * When transform_8x8_flag is disabled, the size of a sub block is *
3314 * 4x4 and when the transform_8x8_flag is enabled the size of the sub *
3315 * block is 8x8. The threshold matrix and the forward scaling list *
3316 * is of the size of the sub block. *
3317 * MEM RECORD for holding *
3318 * 1. quantization parameters for plane y, cb, cr *
3319 * - threshold matrix for quantization *
3320 * - forward weight matrix *
3321 * - satqd threshold matrix *
3322 ************************************************************************/
3323 ps_mem_rec = &ps_mem_rec_base[MEM_REC_QUANT_PARAM];
3324 {
3325 /* total size of the mem record */
3326 WORD32 total_size = 0;
3327
3328 /* quantization parameter list for planes y,cb and cr */
3329 total_size += ALIGN64(sizeof(quant_params_t)) * 3;
3330
3331 /* size of threshold matrix for quantization
3332 * (assuming the transform_8x8_flag is disabled).
3333 * for all 3 planes */
3334 total_size += ALIGN64(sizeof(WORD16) * 4 * 4) * 3;
3335
3336 /* size of forward weight matrix for quantization
3337 * (assuming the transform_8x8_flag is disabled).
3338 * for all 3 planes */
3339 total_size += ALIGN64(sizeof(WORD16) * 4 * 4) * 3;
3340
3341 /* Size for SATDQ threshold matrix for palnes y, cb and cr */
3342 total_size += ALIGN64(sizeof(UWORD16) * 9) * 3;
3343
3344 /* total size per each proc thread */
3345 total_size *= MAX_PROCESS_CTXT;
3346
3347 ps_mem_rec->u4_mem_size = total_size;
3348 }
3349 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_QUANT_PARAM, ps_mem_rec->u4_mem_size);
3350
3351 /************************************************************************
3352 * While computing blocking strength for the current mb, the csbp, mb *
3353 * type for the neighboring mbs are necessary. memtab for storing top *
3354 * row mbtype and csbp is evaluated here. *
3355 * *
3356 * when encoding intra 4x4 or intra 8x8 the submb types are estimated *
3357 * and sent. The estimation is dependent on neighbor mbs. For this *
3358 * store the top row sub mb types for intra mbs *
3359 * *
3360 * During motion vector prediction, the curr mb mv is predicted from *
3361 * neigbors left, top, top right and sometimes top left depending on *
3362 * the availability. The top and top right content is accessed from *
3363 * the memtab specified below. *
3364 ************************************************************************/
3365 ps_mem_rec = &ps_mem_rec_base[MEM_REC_TOP_ROW_SYN_INFO];
3366 {
3367 /* total size of the mem record */
3368 WORD32 total_size = 0;
3369
3370 /* size in bytes to store 1 row of mb_info_t */
3371 /* one additional mb, to avoid checking end of row condition */
3372 total_size += (max_mb_cols + 1) * sizeof(mb_info_t);
3373
3374 /* size in bytes to store 1 row of intra macroblock sub modes */
3375 total_size += max_mb_cols * sizeof(UWORD8) * 16;
3376
3377 /* size in bytes to store 1 row + 1 of enc_pu_t */
3378 /* one additional mb, to avoid checking end of row condition */
3379 total_size += (max_mb_cols + 1) * sizeof(enc_pu_t);
3380
3381 /* total size per proc ctxt */
3382 total_size = ALIGN128(total_size);
3383
3384 /* total size per each proc ctxt */
3385 total_size *= MAX_CTXT_SETS;
3386 ps_mem_rec->u4_mem_size = total_size;
3387 }
3388 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_TOP_ROW_SYN_INFO, ps_mem_rec->u4_mem_size);
3389
3390 /************************************************************************
3391 * When transform_8x8_flag is disabled, the mb is partitioned into *
3392 * 4 sub blocks. This corresponds to 1 vertical left edge and 1 *
3393 * vertical inner edge, 1 horizontal top edge and 1 horizontal *
3394 * inner edge per mb. Further, When transform_8x8_flag is enabled, *
3395 * the mb is partitioned in to 16 sub blocks. This corresponds to *
3396 * 1 vertical left edge and 3 vertical inner edges, 1 horizontal top *
3397 * edge and 3 horizontal inner edges per mb. *
3398 * MEM RECORD for holding *
3399 * 1. vertical edge blocking strength *
3400 * 2. horizontal edge blocking strength *
3401 * 3. mb qp *
3402 * all are frame level *
3403 ************************************************************************/
3404 ps_mem_rec = &ps_mem_rec_base[MEM_REC_BS_QP];
3405 {
3406 /* total size of the mem record */
3407 WORD32 total_size = 0;
3408
3409 /* size in bytes to store vertical edge bs, horizontal edge bs and qp of every mb*/
3410 WORD32 vert_bs_size, horz_bs_size, qp_size;
3411
3412 /* vertical edge bs = total number of vertical edges * number of bytes per each edge */
3413 /* total num of v edges = total mb * 4 (assuming transform_8x8_flag = 0),
3414 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */
3415 vert_bs_size = ALIGN64(max_mb_cnt * 4 * 4);
3416
3417 /* horizontal edge bs = total number of horizontal edges * number of bytes per each edge */
3418 /* total num of h edges = total mb * 4 (assuming transform_8x8_flag = 0),
3419 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */
3420 horz_bs_size = ALIGN64(max_mb_cnt * 4 * 4);
3421
3422 /* qp of each mb requires 1 byte */
3423 qp_size = ALIGN64(max_mb_cnt);
3424
3425 /* total size */
3426 total_size = vert_bs_size + horz_bs_size + qp_size;
3427
3428 /* total size per each proc ctxt */
3429 total_size *= MAX_CTXT_SETS;
3430
3431 ps_mem_rec->u4_mem_size = total_size;
3432 }
3433 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_BS_QP, ps_mem_rec->u4_mem_size);
3434
3435 /************************************************************************
3436 * size for holding dpb manager context *
3437 ************************************************************************/
3438 ps_mem_rec = &ps_mem_rec_base[MEM_REC_INP_PIC];
3439 {
3440 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
3441 }
3442 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_INP_PIC, ps_mem_rec->u4_mem_size);
3443
3444 /************************************************************************
3445 * size for holding dpb manager context *
3446 ************************************************************************/
3447 ps_mem_rec = &ps_mem_rec_base[MEM_REC_OUT];
3448 {
3449 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
3450 }
3451 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_OUT, ps_mem_rec->u4_mem_size);
3452
3453 /************************************************************************
3454 * Size for color space conversion *
3455 ************************************************************************/
3456 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CSC];
3457 {
3458 /* We need a total a memory for a single frame of 420 sp, ie
3459 * (wd * ht) for luma and (wd * ht / 2) for chroma*/
3460 ps_mem_rec->u4_mem_size = MAX_CTXT_SETS
3461 * ((3 * max_ht_luma * max_wd_luma) >> 1);
Harish Mahendrakar5cdb8882015-06-09 17:48:53 +0530[diff] [blame]3462 /* Allocate an extra row, since inverse transform functions for
3463 * chroma access(only read, not used) few extra bytes due to
3464 * interleaved input
3465 */
3466 ps_mem_rec->u4_mem_size += max_wd_luma;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3467 }
3468 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CSC, ps_mem_rec->u4_mem_size);
3469
3470 /************************************************************************
3471 * Size for holding pic_buf_t for each reference picture *
3472 * Note this allocation is done for BUF_MGR_MAX_CNT instead of *
3473 * MAX_DPB_SIZE or max_dpb_size for following reasons *
3474 * max_dpb_size will be based on max_wd and max_ht *
3475 * For higher max_wd and max_ht this number will be smaller than *
3476 * MAX_DPB_SIZE But during actual initialization number of buffers *
3477 * allocated can be more. *
3478 * *
3479 * Also to handle display depth application can allocate more than *
3480 * what codec asks for in case of non-shared mode *
3481 * Since this is only a structure allocation and not actual buffer *
3482 * allocation, it is allocated for BUF_MGR_MAX_CNT entries *
3483 ************************************************************************/
3484 ps_mem_rec = &ps_mem_rec_base[MEM_REC_REF_PIC];
3485 {
3486 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
3487 ps_mem_rec->u4_mem_size += BUF_MGR_MAX_CNT * sizeof(pic_buf_t);
3488
3489 /************************************************************************
3490 * Note: Number of luma samples is not max_wd * max_ht here, instead it *
3491 * is set to maximum number of luma samples allowed at the given level. *
3492 * This is done to ensure that any stream with width and height lesser *
3493 * than max_wd and max_ht is supported. Number of buffers required can *
3494 * be greater for lower width and heights at a given level and this *
3495 * increased number of buffers might require more memory than what *
3496 * max_wd and max_ht buffer would have required. Number of buffers is *
3497 * doubled in order to return one frame at a time instead of sending *
3498 * multiple outputs during dpb full case. Also note one extra buffer is *
3499 * allocted to store current picture. *
3500 * *
3501 * Half-pel planes for each reference buffer are allocated along with *
3502 * the reference buffer. So each reference buffer is 4 times the *
3503 * required size. This way buffer management for the half-pel planes is *
3504 * easier and while using the half-pel planes in MC, an offset can be *
3505 * used from a single pointer *
3506 ***********************************************************************/
3507 ps_mem_rec->u4_mem_size += HPEL_PLANES_CNT
3508 * ih264e_get_total_pic_buf_size(
3509 max_wd_luma * max_ht_luma, level,
3510 PAD_WD, PAD_HT, num_ref_frames,
3511 num_reorder_frames);
3512 }
3513 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_REF_PIC, ps_mem_rec->u4_mem_size);
3514
3515 /************************************************************************
3516 * Request memory to hold mem recs to be returned during retrieve call *
3517 ************************************************************************/
3518 ps_mem_rec = &ps_mem_rec_base[MEM_REC_BACKUP];
3519 {
3520 ps_mem_rec->u4_mem_size = MEM_REC_CNT * sizeof(iv_mem_rec_t);
3521 }
3522 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_BACKUP, ps_mem_rec->u4_mem_size);
3523
3524 /************************************************************************
3525 * size for memory required by NMB info structs and buffer for storing *
3526 * half pel plane *
3527 ************************************************************************/
3528 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_INFO_NMB];
3529 {
Harinarayanan K K6cb67722015-06-19 14:44:42 +0530[diff] [blame]3530 ps_mem_rec->u4_mem_size = MAX_PROCESS_CTXT * max_mb_cols *
Hamsalekha S42026062015-07-30 16:20:35 +0530[diff] [blame]3531 (sizeof(mb_info_nmb_t) + MB_SIZE * MB_SIZE
Harinarayanan K K6cb67722015-06-19 14:44:42 +0530[diff] [blame]3532 * sizeof(UWORD8));
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3533 }
3534 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MB_INFO_NMB, ps_mem_rec->u4_mem_size);
3535
3536 /************************************************************************
3537 * RC mem records *
3538 ************************************************************************/
3539 ps_mem_rec = &ps_mem_rec_base[MEM_REC_RC];
3540 {
3541 ih264e_get_rate_control_mem_tab(NULL, ps_mem_rec, FILL_MEMTAB);
3542 }
3543 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_RC, ps_mem_rec->u4_mem_size);
3544
3545 /* Each memtab size is aligned to next multiple of 128 bytes */
3546 /* This is to ensure all the memtabs start at different cache lines */
3547 ps_mem_rec = ps_mem_rec_base;
3548 for (i = 0; i < MEM_REC_CNT; i++)
3549 {
3550 ps_mem_rec->u4_mem_size = ALIGN128(ps_mem_rec->u4_mem_size);
3551 ps_mem_rec++;
3552 }
3553
3554 ps_op->s_ive_op.u4_num_mem_rec = MEM_REC_CNT;
3555
3556 DEBUG("Num mem recs in fill call : %d\n", ps_op->s_ive_op.u4_num_mem_rec);
3557
3558 return (status);
3559}
3560
3561/**
3562*******************************************************************************
3563*
3564* @brief
3565* Initializes from mem records passed to the codec
3566*
3567* @par Description:
3568* Initializes pointers based on mem records passed
3569*
3570* @param[in] ps_codec_obj
3571* Pointer to codec object at API level
3572*
3573* @param[in] pv_api_ip
3574* Pointer to input argument structure
3575*
3576* @param[out] pv_api_op
3577* Pointer to output argument structure
3578*
3579* @returns error status
3580*
3581* @remarks none
3582*
3583*******************************************************************************
3584*/
3585static WORD32 ih264e_init_mem_rec(iv_obj_t *ps_codec_obj,
3586 void *pv_api_ip,
3587 void *pv_api_op)
3588{
3589 /* api call I/O structures */
3590 ih264e_init_ip_t *ps_ip = pv_api_ip;
3591 ih264e_init_op_t *ps_op = pv_api_op;
3592
3593 /* mem records */
3594 iv_mem_rec_t *ps_mem_rec_base, *ps_mem_rec;
3595
3596 /* codec variables */
3597 codec_t * ps_codec;
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame]3598 cabac_ctxt_t *ps_cabac;
3599 mb_info_ctxt_t *ps_mb_map_ctxt_inc;
3600
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3601 cfg_params_t *ps_cfg;
3602
3603 /* frame dimensions */
3604 WORD32 max_wd_luma, max_ht_luma;
3605 WORD32 max_mb_rows, max_mb_cols, max_mb_cnt;
3606
3607 /* temp var */
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame]3608 WORD32 i, j;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3609 WORD32 status = IV_SUCCESS;
3610
3611 /* frame dimensions */
3612 max_ht_luma = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
3613 max_wd_luma = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
3614 max_mb_rows = max_ht_luma / MB_SIZE;
3615 max_mb_cols = max_wd_luma / MB_SIZE;
3616 max_mb_cnt = max_mb_rows * max_mb_cols;
3617
3618 /* mem records */
3619 ps_mem_rec_base = ps_ip->s_ive_ip.ps_mem_rec;
3620
3621 /* Init mem records */
3622 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CODEC];
3623 {
3624 ps_codec_obj->pv_codec_handle = ps_mem_rec->pv_base;
3625 ps_codec = (codec_t *) (ps_codec_obj->pv_codec_handle);
3626 }
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame]3627 /* Init mem records_cabac ctxt */
3628 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC];
3629 {
3630 ps_cabac = (cabac_ctxt_t *)(ps_mem_rec->pv_base);
3631 }
3632
3633 /* Init mem records mb info array for CABAC */
3634 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC_MB_INFO];
3635 {
3636 ps_mb_map_ctxt_inc = (mb_info_ctxt_t *)(ps_mem_rec->pv_base);
3637 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3638
3639 /* Note this memset can not be done in init() call, since init will called
3640 during reset as well. And calling this during reset will mean all pointers
3641 need to reinitialized */
3642 memset(ps_codec, 0, sizeof(codec_t));
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame]3643 memset(ps_cabac, 0, sizeof(cabac_ctxt_t));
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3644
3645 /* Set default Config Params */
3646 ps_cfg = &ps_codec->s_cfg;
3647 ih264e_set_default_params(ps_cfg);
3648
3649 /* Update config params as per input */
3650 ps_cfg->u4_max_wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
3651 ps_cfg->u4_max_ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
3652 ps_cfg->i4_wd_mbs = ps_cfg->u4_max_wd >> 4;
3653 ps_cfg->i4_ht_mbs = ps_cfg->u4_max_ht >> 4;
3654 ps_cfg->u4_max_ref_cnt = ps_ip->s_ive_ip.u4_max_ref_cnt;
3655 ps_cfg->u4_max_reorder_cnt = ps_ip->s_ive_ip.u4_max_reorder_cnt;
3656 ps_cfg->u4_max_level = ps_ip->s_ive_ip.u4_max_level;
3657 ps_cfg->e_inp_color_fmt = ps_ip->s_ive_ip.e_inp_color_fmt;
3658 ps_cfg->e_recon_color_fmt = ps_ip->s_ive_ip.e_recon_color_fmt;
3659 ps_cfg->u4_max_framerate = ps_ip->s_ive_ip.u4_max_framerate;
3660 ps_cfg->u4_max_bitrate = ps_ip->s_ive_ip.u4_max_bitrate;
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame]3661 ps_cfg->u4_num_bframes = ps_ip->s_ive_ip.u4_num_bframes;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3662 ps_cfg->e_content_type = ps_ip->s_ive_ip.e_content_type;
3663 ps_cfg->u4_max_srch_rng_x = ps_ip->s_ive_ip.u4_max_srch_rng_x;
3664 ps_cfg->u4_max_srch_rng_y = ps_ip->s_ive_ip.u4_max_srch_rng_y;
3665 ps_cfg->e_slice_mode = ps_ip->s_ive_ip.e_slice_mode;
3666 ps_cfg->u4_slice_param = ps_ip->s_ive_ip.u4_slice_param;
3667 ps_cfg->e_arch = ps_ip->s_ive_ip.e_arch;
3668 ps_cfg->e_soc = ps_ip->s_ive_ip.e_soc;
3669 ps_cfg->u4_enable_recon = ps_ip->s_ive_ip.u4_enable_recon;
3670 ps_cfg->e_rc_mode = ps_ip->s_ive_ip.e_rc_mode;
3671
3672 /* Validate params */
3673 if ((ps_ip->s_ive_ip.u4_max_level < MIN_LEVEL)
3674 || (ps_ip->s_ive_ip.u4_max_level > MAX_LEVEL))
3675 {
3676 ps_op->s_ive_op.u4_error_code |= IH264E_CODEC_LEVEL_NOT_SUPPORTED;
3677 ps_cfg->u4_max_level = DEFAULT_MAX_LEVEL;
3678 }
3679
3680 if (ps_ip->s_ive_ip.u4_max_ref_cnt > MAX_REF_CNT)
3681 {
3682 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED;
3683 ps_cfg->u4_max_ref_cnt = MAX_REF_CNT;
3684 }
3685
3686 if (ps_ip->s_ive_ip.u4_max_reorder_cnt > MAX_REF_CNT)
3687 {
3688 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED;
3689 ps_cfg->u4_max_reorder_cnt = MAX_REF_CNT;
3690 }
3691
3692 ps_mem_rec = &ps_mem_rec_base[MEM_REC_BACKUP];
3693 {
3694 ps_codec->ps_mem_rec_backup = (iv_mem_rec_t *) ps_mem_rec->pv_base;
3695
3696 memcpy(ps_codec->ps_mem_rec_backup, ps_mem_rec_base,
3697 MEM_REC_CNT * sizeof(iv_mem_rec_t));
3698 }
3699
3700 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY];
3701 {
3702 /* temp var */
3703 WORD32 size = 0, offset;
3704
3705 for (i = 0; i < MAX_PROCESS_CTXT; i++)
3706 {
Harinarayanan K K6cb67722015-06-19 14:44:42 +0530[diff] [blame]3707 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3708 {
3709 /* base ptr */
3710 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3711
3712 /* reset size */
3713 size = 0;
3714
3715 /* skip mb run */
3716 ps_codec->as_process[i].s_entropy.pi4_mb_skip_run =
3717 (void *) (pu1_buf + size);
3718 size += sizeof(WORD32);
3719 size = ALIGN8(size);
3720
3721 /* entropy map */
3722 ps_codec->as_process[i].s_entropy.pu1_entropy_map =
3723 (void *) (pu1_buf + size + max_mb_cols);
3724 /* size in bytes to store entropy status of an entire frame */
3725 size += (max_mb_cols * max_mb_rows);
3726 /* add an additional 1 row of bytes to evade the special case of row 0 */
3727 size += max_mb_cols;
3728 size = ALIGN128(size);
3729
3730 /* bit stream ptr */
3731 ps_codec->as_process[i].s_entropy.ps_bitstrm = (void *) (pu1_buf
3732 + size);
3733 size += sizeof(bitstrm_t);
3734 size = ALIGN128(size);
3735
3736 /* nnz luma */
3737 ps_codec->as_process[i].s_entropy.pu1_top_nnz_luma =
3738 (void *) (pu1_buf + size);
3739 size += (max_mb_cols * 4 * sizeof(UWORD8));
3740 size = ALIGN128(size);
3741
3742 /* nnz chroma */
3743 ps_codec->as_process[i].s_entropy.pu1_top_nnz_cbcr =
3744 (void *) (pu1_buf + size);
3745 size += (max_mb_cols * 4 * sizeof(UWORD8));
3746 size = ALIGN128(size);
3747 offset = size;
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame]3748 /* cabac Context */
3749 ps_codec->as_process[i].s_entropy.ps_cabac = ps_cabac;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3750 }
3751 else
3752 {
3753 /* base ptr */
3754 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3755
3756 /* reset size */
3757 size = offset;
3758
3759 /* skip mb run */
3760 ps_codec->as_process[i].s_entropy.pi4_mb_skip_run =
3761 (void *) (pu1_buf + size);
3762 size += sizeof(WORD32);
3763 size = ALIGN8(size);
3764
3765 /* entropy map */
3766 ps_codec->as_process[i].s_entropy.pu1_entropy_map =
3767 (void *) (pu1_buf + size + max_mb_cols);
3768 /* size in bytes to store entropy status of an entire frame */
3769 size += (max_mb_cols * max_mb_rows);
3770 /* add an additional 1 row of bytes to evade the special case of row 0 */
3771 size += max_mb_cols;
3772 size = ALIGN128(size);
3773
3774 /* bit stream ptr */
3775 ps_codec->as_process[i].s_entropy.ps_bitstrm = (void *) (pu1_buf
3776 + size);
3777 size += sizeof(bitstrm_t);
3778 size = ALIGN128(size);
3779
3780 /* nnz luma */
3781 ps_codec->as_process[i].s_entropy.pu1_top_nnz_luma =
3782 (void *) (pu1_buf + size);
3783 size += (max_mb_cols * 4 * sizeof(UWORD8));
3784 size = ALIGN128(size);
3785
3786 /* nnz chroma */
3787 ps_codec->as_process[i].s_entropy.pu1_top_nnz_cbcr =
3788 (void *) (pu1_buf + size);
3789 size += (max_mb_cols * 4 * sizeof(UWORD8));
3790 size = ALIGN128(size);
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame]3791 /* cabac Context */
3792 ps_codec->as_process[i].s_entropy.ps_cabac = ps_cabac;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3793 }
3794 }
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame]3795 ps_codec->as_process[0].s_entropy.ps_cabac->ps_mb_map_ctxt_inc_base =
3796 ps_mb_map_ctxt_inc;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3797 }
3798
3799 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_COEFF_DATA];
3800 {
3801 /* temp var */
3802 WORD32 size = 0, size_of_row;
3803 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3804
3805 /* size of coeff data of 1 mb */
3806 size += sizeof(tu_sblk_coeff_data_t) * MAX_4x4_SUBBLKS;
3807
3808 /* size of coeff data of 1 row of mb's */
3809 size *= max_mb_cols;
3810
3811 /* align to avoid false sharing */
3812 size = ALIGN64(size);
3813 size_of_row = size;
3814
3815 /* size for one full frame */
3816 size *= max_mb_rows;
3817
3818 ps_codec->u4_size_coeff_data = size_of_row;
3819
3820 for (i = 0; i < MAX_PROCESS_CTXT; i++)
3821 {
Harinarayanan K K6cb67722015-06-19 14:44:42 +0530[diff] [blame]3822 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3823 {
3824 ps_codec->as_process[i].pv_pic_mb_coeff_data = pu1_buf;
3825 ps_codec->as_process[i].s_entropy.pv_pic_mb_coeff_data =
3826 pu1_buf;
3827 }
3828 else
3829 {
3830 ps_codec->as_process[i].pv_pic_mb_coeff_data = pu1_buf + size;
3831 ps_codec->as_process[i].s_entropy.pv_pic_mb_coeff_data = pu1_buf
3832 + size;
3833 }
3834 }
3835 }
3836
3837 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_HEADER_DATA];
3838 {
3839 /* temp var */
3840 WORD32 size, size_of_row;
3841 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3842
3843 /* size of header data of 1 mb */
Harish Mahendrakarc7d9c912016-11-23 13:30:39 +0530[diff] [blame]3844 size = sizeof(mb_hdr_t);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3845
3846 /* size for 1 row of mbs */
3847 size = size * max_mb_cols;
3848
3849 /* align to avoid any false sharing across threads */
3850 size = ALIGN64(size);
3851 size_of_row = size;
3852
3853 /* size for one full frame */
3854 size *= max_mb_rows;
3855
3856 ps_codec->u4_size_header_data = size_of_row;
3857
3858 for (i = 0; i < MAX_PROCESS_CTXT; i++)
3859 {
Harinarayanan K K6cb67722015-06-19 14:44:42 +0530[diff] [blame]3860 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3861 {
3862 ps_codec->as_process[i].pv_pic_mb_header_data = pu1_buf;
3863 ps_codec->as_process[i].s_entropy.pv_pic_mb_header_data =
3864 pu1_buf;
3865 }
3866 else
3867 {
3868 ps_codec->as_process[i].pv_pic_mb_header_data = pu1_buf + size;
3869 ps_codec->as_process[i].s_entropy.pv_pic_mb_header_data =
3870 pu1_buf + size;
3871 }
3872 }
3873 }
3874
3875 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBANK];
3876 {
3877 /* size of buf mgr struct */
3878 WORD32 size = ih264_buf_mgr_size();
3879
3880 /* temp var */
3881 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3882
3883 /* mv buffer mgr */
3884 ps_codec->pv_mv_buf_mgr_base = pu1_buf;
3885
3886 /* mv bank */
3887 ps_codec->pv_mv_bank_buf_base = pu1_buf + size;
3888 ps_codec->i4_total_mv_bank_size = ps_mem_rec->u4_mem_size - size;
3889 }
3890
3891 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBITS];
3892 {
3893 /* max srch range x */
3894 UWORD32 u4_srch_range_x = ps_ip->s_ive_ip.u4_max_srch_rng_x;
3895
3896 /* max srch range y */
3897 UWORD32 u4_srch_range_y = ps_ip->s_ive_ip.u4_max_srch_rng_y;
3898
3899 /* max srch range */
3900 UWORD32 u4_max_srch_range = MAX(u4_srch_range_x, u4_srch_range_y);
3901
3902 /* temp var */
3903 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3904
3905 /* due to subpel */
3906 u4_max_srch_range <<= 2;
3907
3908// /* due to mv on either direction */
3909// u4_max_srch_range = (u4_max_srch_range << 1);
3910
3911 /* due to pred mv + zero */
3912 u4_max_srch_range = (u4_max_srch_range << 1) + 1;
3913
3914 for (i = 0; i < MAX_PROCESS_CTXT; i++)
3915 {
3916 /* me ctxt */
3917 me_ctxt_t *ps_mem_ctxt = &(ps_codec->as_process[i].s_me_ctxt);
3918
3919 /* init at zero mv */
3920 ps_mem_ctxt->pu1_mv_bits = pu1_buf + u4_max_srch_range;
3921 }
3922 }
3923
3924 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SPS];
3925 {
3926 ps_codec->ps_sps_base = (sps_t *) ps_mem_rec->pv_base;
3927 }
3928
3929 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PPS];
3930 {
3931 ps_codec->ps_pps_base = (pps_t *) ps_mem_rec->pv_base;
3932 }
3933
3934 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_HDR];
3935 {
3936 ps_codec->ps_slice_hdr_base = ps_mem_rec->pv_base;
3937
3938 for (i = 0; i < MAX_PROCESS_CTXT; i++)
3939 {
Harinarayanan K K6cb67722015-06-19 14:44:42 +0530[diff] [blame]3940 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3941 {
3942 ps_codec->as_process[i].ps_slice_hdr_base = ps_mem_rec->pv_base;
3943 }
3944 else
3945 {
3946 /* temp var */
3947 WORD32 size = MAX_SLICE_HDR_CNT * sizeof(slice_header_t);
3948 void *pv_buf = (UWORD8 *) ps_mem_rec->pv_base + size;
3949
3950 ps_codec->as_process[i].ps_slice_hdr_base = pv_buf;
3951 }
3952 }
3953 }
3954
3955 ps_mem_rec = &ps_mem_rec_base[MEM_REC_AIR_MAP];
3956 {
3957 /* temp var */
3958 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3959
3960 for (i = 0; i < MAX_PROCESS_CTXT; i++)
3961 {
Harinarayanan K K6cb67722015-06-19 14:44:42 +0530[diff] [blame]3962 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3963 {
3964 ps_codec->as_process[i].pu1_is_intra_coded = pu1_buf;
3965 }
3966 else
3967 {
3968 ps_codec->as_process[i].pu1_is_intra_coded = pu1_buf
3969 + max_mb_cnt;
3970 }
3971 }
3972
Harish Mahendrakar089f41d2016-02-09 11:47:19 +0530[diff] [blame]3973 ps_codec->pu2_intr_rfrsh_map = (UWORD16 *) (pu1_buf + max_mb_cnt * MAX_CTXT_SETS);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3974 }
3975
3976 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_MAP];
3977 {
3978 /* pointer to storage space */
3979 UWORD8 *pu1_buf_ping, *pu1_buf_pong;
3980
3981 /* init pointer */
3982 pu1_buf_ping = ps_mem_rec->pv_base;
3983 pu1_buf_pong = pu1_buf_ping + ALIGN64(max_mb_cnt);
3984
3985 for (i = 0; i < MAX_PROCESS_CTXT; i++)
3986 {
Harinarayanan K K6cb67722015-06-19 14:44:42 +0530[diff] [blame]3987 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3988 {
3989 ps_codec->as_process[i].pu1_slice_idx = pu1_buf_ping;
3990 }
3991 else
3992 {
3993 ps_codec->as_process[i].pu1_slice_idx = pu1_buf_pong;
3994 }
3995 }
3996 }
3997
3998 ps_mem_rec = &ps_mem_rec_base[MEM_REC_THREAD_HANDLE];
3999 {
4000 WORD32 handle_size = ithread_get_handle_size();
4001
4002 for (i = 0; i < MAX_PROCESS_THREADS; i++)
4003 {
4004 ps_codec->apv_proc_thread_handle[i] = (UWORD8 *) ps_mem_rec->pv_base
4005 + (i * handle_size);
4006 }
4007 }
4008
4009 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CTL_MUTEX];
4010 {
4011 ps_codec->pv_ctl_mutex = ps_mem_rec->pv_base;
4012 }
4013
4014 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_MUTEX];
4015 {
4016 ps_codec->pv_entropy_mutex = ps_mem_rec->pv_base;
4017 }
4018
4019 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_JOBQ];
4020 {
4021 ps_codec->pv_proc_jobq_buf = ps_mem_rec->pv_base;
4022 ps_codec->i4_proc_jobq_buf_size = ps_mem_rec->u4_mem_size;
4023 }
4024
4025 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_JOBQ];
4026 {
4027 ps_codec->pv_entropy_jobq_buf = ps_mem_rec->pv_base;
4028 ps_codec->i4_entropy_jobq_buf_size = ps_mem_rec->u4_mem_size;
4029 }
4030
4031 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_MAP];
4032 {
4033 /* pointer to storage space */
4034 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4035
4036 /* total size of the mem record */
4037 WORD32 total_size = 0;
4038
4039 /* size in bytes to mb core coding status of an entire frame */
4040 total_size = max_mb_cnt;
4041
4042 /* add an additional 1 row of bytes to evade the special case of row 0 */
4043 total_size += max_mb_cols;
4044
4045 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4046 {
Harinarayanan K K6cb67722015-06-19 14:44:42 +0530[diff] [blame]4047 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4048 {
4049 ps_codec->as_process[i].pu1_proc_map = pu1_buf + max_mb_cols;
4050 }
4051 else
4052 {
4053 ps_codec->as_process[i].pu1_proc_map = pu1_buf + total_size
4054 + max_mb_cols;
4055 }
4056 }
4057 }
4058
4059 ps_mem_rec = &ps_mem_rec_base[MEM_REC_DBLK_MAP];
4060 {
4061 /* pointer to storage space */
4062 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4063
4064 /* total size of the mem record */
4065 WORD32 total_size = 0;
4066
4067 /* size in bytes to mb core coding status of an entire frame */
4068 total_size = max_mb_cnt;
4069
4070 /* add an additional 1 row of bytes to evade the special case of row 0 */
4071 total_size += max_mb_cols;
4072
4073 /*Align the memory offsets*/
4074 total_size = ALIGN64(total_size);
4075
4076 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4077 {
Harinarayanan K K6cb67722015-06-19 14:44:42 +0530[diff] [blame]4078 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4079 {
4080 ps_codec->as_process[i].pu1_deblk_map = pu1_buf + max_mb_cols;
4081
4082 }
4083 else
4084 {
4085 ps_codec->as_process[i].pu1_deblk_map = pu1_buf + total_size
4086 + max_mb_cols;
4087
4088 }
4089 }
4090 }
4091
4092 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ME_MAP];
4093 {
4094 /* pointer to storage space */
4095 UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base;
4096
4097 /* total size of the mem record */
4098 WORD32 total_size = 0;
4099
4100 /* size in bytes to mb core coding status of an entire frame */
4101 total_size = max_mb_cnt;
4102
4103 /* add an additional 1 row of bytes to evade the special case of row 0 */
4104 total_size += max_mb_cols;
4105
4106 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4107 {
Harinarayanan K K6cb67722015-06-19 14:44:42 +0530[diff] [blame]4108 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4109 {
4110 ps_codec->as_process[i].pu1_me_map = pu1_buf + max_mb_cols;
4111 }
4112 else
4113 {
4114 ps_codec->as_process[i].pu1_me_map = pu1_buf + total_size
4115 + max_mb_cols;
4116 }
4117 }
4118 }
4119
4120 ps_mem_rec = &ps_mem_rec_base[MEM_REC_DPB_MGR];
4121 {
4122 ps_codec->pv_dpb_mgr = ps_mem_rec->pv_base;
4123 }
4124
4125 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_SCRATCH];
4126 {
4127 /* pointer to storage space */
4128 UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base;
4129
4130 /* size of pred buffer, fwd transform output, temp buffer for inv tra */
4131 WORD32 size_pred_luma, size_pred_chroma, size_fwd, size_inv, size_hp;
4132
4133 /* temp var */
4134 WORD32 size = 0;
4135
4136 /* size to hold intra/inter prediction buffer */
4137 size_pred_luma = sizeof(UWORD8) * 16 * 16;
4138 size_pred_chroma = sizeof(UWORD8) * 8 * 16;
4139
4140 /* size to hold fwd transform output */
4141 size_fwd = sizeof(WORD16) * SIZE_TRANS_BUFF;
4142
4143 /* size to hold temporary data during inverse transform */
4144 size_inv = sizeof(WORD32) * SIZE_TMP_BUFF_ITRANS;
4145
4146 /* size to hold half pel plane buffers */
4147 size_hp = sizeof(UWORD8) * (HP_BUFF_WD * HP_BUFF_HT);
4148
4149 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4150 {
4151 /* prediction buffer */
4152 ps_codec->as_process[i].pu1_pred_mb = (void *) (pu1_buf + size);
4153 ps_codec->as_process[i].i4_pred_strd = 16;
4154 size += size_pred_luma;
4155 size = ALIGN64(size);
4156
4157 /* prediction buffer */
4158 ps_codec->as_process[i].pu1_ref_mb_intra_4x4 = (void *) (pu1_buf
4159 + size);
4160 size += size_pred_luma;
4161 size = ALIGN64(size);
4162
4163 /* prediction buffer intra 16x16 */
4164 ps_codec->as_process[i].pu1_pred_mb_intra_16x16 = (void *) (pu1_buf
4165 + size);
4166 size += size_pred_luma;
4167 size = ALIGN64(size);
4168
4169 /* prediction buffer intra 16x16 plane*/
4170 ps_codec->as_process[i].pu1_pred_mb_intra_16x16_plane =
4171 (void *) (pu1_buf + size);
4172 size += size_pred_luma;
4173 size = ALIGN64(size);
4174
4175 /* prediction buffer intra chroma*/
4176 ps_codec->as_process[i].pu1_pred_mb_intra_chroma = (void *) (pu1_buf
4177 + size);
4178 size += size_pred_chroma;
4179 size = ALIGN64(size);
4180
4181 /* prediction buffer intra chroma plane*/
4182 ps_codec->as_process[i].pu1_pred_mb_intra_chroma_plane =
4183 (void *) (pu1_buf + size);
4184 size += size_pred_chroma;
4185 size = ALIGN64(size);
4186
4187 /* Fwd transform output */
4188 ps_codec->as_process[i].pi2_res_buf = (void *) (pu1_buf + size);
4189 ps_codec->as_process[i].i4_res_strd = 16;
4190 size += size_fwd;
4191 size = ALIGN64(size);
4192
4193 /* Fwd transform output */
4194 ps_codec->as_process[i].pi2_res_buf_intra_4x4 = (void *) (pu1_buf
4195 + size);
4196 size += size_fwd;
4197 size = ALIGN64(size);
4198
4199 /* scratch buffer used during inverse transform */
4200 ps_codec->as_process[i].pv_scratch_buff = (void *) (pu1_buf + size);
4201 size += size_inv;
4202 size = ALIGN64(size);
4203
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame]4204 for (j = 0; j < SUBPEL_BUFF_CNT; j++)
4205 {
4206 ps_codec->as_process[i].apu1_subpel_buffs[j] = (pu1_buf + size);
4207 size += ALIGN64(size_hp);
4208 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4209 }
4210 }
4211
4212 ps_mem_rec = &ps_mem_rec_base[MEM_REC_QUANT_PARAM];
4213 {
4214 /* pointer to storage space */
4215 UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base;
4216
4217 /* size of qp, threshold matrix, fwd scaling list for one plane */
4218 WORD32 size_quant_param, size_thres_mat, size_fwd_weight_mat,
4219 size_satqd_weight_mat;
4220
4221 /* temp var */
4222 WORD32 total_size = 0;
4223
4224 /* size of quantization parameter list of 1 plane */
4225 size_quant_param = ALIGN64(sizeof(quant_params_t));
4226
4227 /* size of threshold matrix for quantization
4228 * (assuming the transform_8x8_flag is disabled).
4229 * for 1 plane */
4230 size_thres_mat = ALIGN64(sizeof(WORD16) * 4 * 4);
4231
4232 /* size of forward weight matrix for quantization
4233 * (assuming the transform_8x8_flag is disabled).
4234 * for 1 plane */
4235 size_fwd_weight_mat = ALIGN64(sizeof(WORD16) * 4 * 4);
4236
4237 /* size of SATQD matrix*/
4238 size_satqd_weight_mat = ALIGN64(sizeof(UWORD16) * 9);
4239
4240 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4241 {
4242 quant_params_t **ps_qp_params = ps_codec->as_process[i].ps_qp_params;
4243
4244 /* quantization param structure */
4245 ps_qp_params[0] = (quant_params_t *) (pu1_buf + total_size);
4246 total_size = total_size + size_quant_param;
4247 ps_qp_params[1] = (quant_params_t *) (pu1_buf + total_size);
4248 total_size = total_size + size_quant_param;
4249 ps_qp_params[2] = (quant_params_t *) (pu1_buf + total_size);
4250 total_size = total_size + size_quant_param;
4251
4252 /* threshold matrix for quantization */
4253 ps_qp_params[0]->pu2_thres_mat = (void *) (pu1_buf + total_size);
4254 total_size = total_size + size_thres_mat;
4255 ps_qp_params[1]->pu2_thres_mat = (void *) (pu1_buf + total_size);
4256 total_size = total_size + size_thres_mat;
4257 ps_qp_params[2]->pu2_thres_mat = (void *) (pu1_buf + total_size);
4258 total_size = total_size + size_thres_mat;
4259
4260 /* fwd weight matrix */
4261 ps_qp_params[0]->pu2_weigh_mat = (void *) (pu1_buf + total_size);
4262 total_size = total_size + size_fwd_weight_mat;
4263 ps_qp_params[1]->pu2_weigh_mat = (void *) (pu1_buf + total_size);
4264 total_size = total_size + size_fwd_weight_mat;
4265 ps_qp_params[2]->pu2_weigh_mat = (void *) (pu1_buf + total_size);
4266 total_size = total_size + size_fwd_weight_mat;
4267
4268 /* threshold matrix for SATQD */
4269 ps_qp_params[0]->pu2_sad_thrsh = (void *) (pu1_buf + total_size);
4270 total_size = total_size + size_satqd_weight_mat;
4271 ps_qp_params[1]->pu2_sad_thrsh = (void *) (pu1_buf + total_size);
4272 total_size = total_size + size_satqd_weight_mat;
4273 ps_qp_params[2]->pu2_sad_thrsh = (void *) (pu1_buf + total_size);
4274 total_size = total_size + size_satqd_weight_mat;
4275
4276 total_size = ALIGN128(total_size);
4277 }
4278 }
4279
4280 ps_mem_rec = &ps_mem_rec_base[MEM_REC_TOP_ROW_SYN_INFO];
4281 {
4282 /* total size of the mem record */
4283 WORD32 total_size = 0, size_csbp, size_intra_modes, size_mv;
4284
4285 /* pointer to buffer */
4286 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4287
4288 /* size in bytes to store 1 row of mb_info_t */
4289 /* one additional mb, to avoid checking end of row condition */
4290 size_csbp = (max_mb_cols + 1) * sizeof(mb_info_t);
4291
4292 /* size in bytes to store 1 row of intra macroblock sub modes */
4293 size_intra_modes = max_mb_cols * sizeof(UWORD8) * 16;
4294
4295 /* size in bytes to store 1 row + 1 of enc_pu_t */
4296 /* one additional mb, to avoid checking end of row condition */
4297 size_mv = (max_mb_cols + 1) * sizeof(enc_pu_t);
4298
4299 /* total size per proc ctxt */
4300 total_size = size_csbp + size_intra_modes + size_mv;
4301
4302 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4303 {
Harinarayanan K K6cb67722015-06-19 14:44:42 +0530[diff] [blame]4304 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4305 {
4306 ps_codec->as_process[i].ps_top_row_mb_syntax_ele_base =
4307 (mb_info_t *) pu1_buf;
4308 ps_codec->as_process[i].pu1_top_mb_intra_modes_base = pu1_buf
4309 + size_csbp;
4310 ps_codec->as_process[i].ps_top_row_pu_base =
4311 (enc_pu_t *) (pu1_buf + size_csbp
4312 + size_intra_modes);
4313 }
4314 else
4315 {
4316 ps_codec->as_process[i].ps_top_row_mb_syntax_ele_base =
4317 (mb_info_t *) (pu1_buf + total_size);
4318 ps_codec->as_process[i].pu1_top_mb_intra_modes_base = pu1_buf
4319 + total_size + size_csbp;
4320 ps_codec->as_process[i].ps_top_row_pu_base =
4321 (enc_pu_t *) (pu1_buf + total_size + size_csbp
4322 + size_intra_modes);
4323 }
4324 }
4325 }
4326
4327 ps_mem_rec = &ps_mem_rec_base[MEM_REC_BS_QP];
4328 {
4329 UWORD8 *pu1_buf_ping, *pu1_buf_pong;
4330
4331 /* total size of the mem record */
4332 WORD32 total_size = 0;
4333
4334 /* size in bytes to store vertical edge bs, horizontal edge bs and qp of every mb*/
4335 WORD32 vert_bs_size, horz_bs_size, qp_size;
4336
4337 /* vertical edge bs = total number of vertical edges * number of bytes per each edge */
4338 /* total num of v edges = total mb * 4 (assuming transform_8x8_flag = 0),
4339 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */
4340 vert_bs_size = ALIGN64(max_mb_cnt * 4 * 4);
4341
4342 /* horizontal edge bs = total number of horizontal edges * number of bytes per each edge */
4343 /* total num of h edges = total mb * 4 (assuming transform_8x8_flag = 0),
4344 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */
4345 horz_bs_size = ALIGN64(max_mb_cnt * 4 * 4);
4346
4347 /* qp of each mb requires 1 byte */
4348 qp_size = ALIGN64(max_mb_cnt);
4349
4350 /* total size */
4351 total_size = vert_bs_size + horz_bs_size + qp_size;
4352
4353 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4354 {
Harinarayanan K K6cb67722015-06-19 14:44:42 +0530[diff] [blame]4355 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4356 {
4357 pu1_buf_ping = (UWORD8 *) ps_mem_rec->pv_base;
4358
4359 /* vertical edge bs storage space */
4360 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_vert_bs =
4361 (UWORD32 *) pu1_buf_ping;
4362 pu1_buf_ping += vert_bs_size;
4363
4364 /* horizontal edge bs storage space */
4365 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_horz_bs =
4366 (UWORD32 *) pu1_buf_ping;
4367 pu1_buf_ping += horz_bs_size;
4368
4369 /* qp */
4370 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu1_pic_qp =
4371 (UWORD8 *) pu1_buf_ping;
4372 pu1_buf_ping += qp_size;
4373 }
4374 else
4375 {
4376 pu1_buf_pong = (UWORD8 *) ps_mem_rec->pv_base;
4377 pu1_buf_pong += total_size;
4378
4379 /* vertical edge bs storage space */
4380 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_vert_bs =
4381 (UWORD32 *) pu1_buf_pong;
4382 pu1_buf_pong += vert_bs_size;
4383
4384 /* horizontal edge bs storage space */
4385 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_horz_bs =
4386 (UWORD32 *) pu1_buf_pong;
4387 pu1_buf_pong += horz_bs_size;
4388
4389 /* qp */
4390 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu1_pic_qp =
4391 (UWORD8 *) pu1_buf_pong;
4392 pu1_buf_pong += qp_size;
4393 }
4394 }
4395 }
4396
4397 ps_mem_rec = &ps_mem_rec_base[MEM_REC_INP_PIC];
4398 {
4399 ps_codec->pv_inp_buf_mgr_base = ps_mem_rec->pv_base;
4400 }
4401
4402 ps_mem_rec = &ps_mem_rec_base[MEM_REC_OUT];
4403 {
4404 ps_codec->pv_out_buf_mgr_base = ps_mem_rec->pv_base;
4405 }
4406
4407 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CSC];
4408 {
4409 ps_codec->pu1_y_csc_buf_base = ps_mem_rec->pv_base;
4410 ps_codec->pu1_uv_csc_buf_base = (UWORD8 *) ps_mem_rec->pv_base
4411 + (max_ht_luma * max_wd_luma);
4412 }
4413
4414 ps_mem_rec = &ps_mem_rec_base[MEM_REC_REF_PIC];
4415 {
4416 /* size of buf mgr struct */
4417 WORD32 size = ih264_buf_mgr_size();
4418
4419 /* temp var */
4420 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4421
4422 /* pic buffer mgr */
4423 ps_codec->pv_ref_buf_mgr_base = pu1_buf;
4424
4425 /* picture bank */
4426 ps_codec->pv_pic_buf_base = pu1_buf + size;
4427 ps_codec->i4_total_pic_buf_size = ps_mem_rec->u4_mem_size - size;
4428 }
4429
4430 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_INFO_NMB];
4431 {
4432 /* temp var */
4433 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4434
4435 /* size of nmb ctxt */
Harinarayanan K K6cb67722015-06-19 14:44:42 +0530[diff] [blame]4436 WORD32 size = max_mb_cols * sizeof(mb_info_nmb_t);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4437
Harinarayanan K K6cb67722015-06-19 14:44:42 +0530[diff] [blame]4438 WORD32 nmb_cntr, subpel_buf_size;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4439
4440 /* init nmb info structure pointer in all proc ctxts */
4441 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4442 {
4443 ps_codec->as_process[i].ps_nmb_info = (mb_info_nmb_t *) (pu1_buf);
4444
4445 pu1_buf += size;
4446 }
4447
4448 subpel_buf_size = MB_SIZE * MB_SIZE * sizeof(UWORD8);
4449
4450 /* adjusting pointers for nmb halfpel buffer */
4451 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4452 {
4453 mb_info_nmb_t* ps_mb_info_nmb =
4454 &ps_codec->as_process[i].ps_nmb_info[0];
4455
Harinarayanan K K6cb67722015-06-19 14:44:42 +0530[diff] [blame]4456 for (nmb_cntr = 0; nmb_cntr < max_mb_cols; nmb_cntr++)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4457 {
4458 ps_mb_info_nmb[nmb_cntr].pu1_best_sub_pel_buf = pu1_buf;
4459
4460 pu1_buf = pu1_buf + subpel_buf_size;
4461
4462 ps_mb_info_nmb[nmb_cntr].u4_bst_spel_buf_strd = MB_SIZE;
4463 }
4464 }
4465 }
4466
4467 ps_mem_rec = &ps_mem_rec_base[MEM_REC_RC];
4468 {
4469 ih264e_get_rate_control_mem_tab(&ps_codec->s_rate_control, ps_mem_rec,
4470 USE_BASE);
4471 }
4472
4473 /* init codec ctxt */
4474 status = ih264e_init(ps_codec);
4475
4476 return status;
4477}
4478
4479/**
4480*******************************************************************************
4481*
4482* @brief
4483* Retrieves mem records passed to the codec
4484*
4485* @par Description:
4486* Retrieves mem recs passed during init
4487*
4488* @param[in] ps_codec_obj
4489* Pointer to codec object at API level
4490*
4491* @param[in] pv_api_ip
4492* Pointer to input argument structure
4493*
4494* @param[out] pv_api_op
4495* Pointer to output argument structure
4496*
4497* @returns error status
4498*
4499* @remarks none
4500*
4501*******************************************************************************
4502*/
4503static WORD32 ih264e_retrieve_memrec(iv_obj_t *ps_codec_obj,
4504 void *pv_api_ip,
4505 void *pv_api_op)
4506{
4507 /* codec ctxt */
4508 codec_t *ps_codec = (codec_t *) ps_codec_obj->pv_codec_handle;
4509
4510 /* ctrl call I/O structures */
4511 ih264e_retrieve_mem_rec_ip_t *ps_ip = pv_api_ip;
4512 ih264e_retrieve_mem_rec_op_t *ps_op = pv_api_op;
4513
4514 if (ps_codec->i4_init_done != 1)
4515 {
4516 ps_op->s_ive_op.u4_error_code |= 1 << IVE_FATALERROR;
4517 ps_op->s_ive_op.u4_error_code |= IH264E_INIT_NOT_DONE;
4518 return IV_FAIL;
4519 }
4520
4521 /* join threads upon at end of sequence */
4522 ih264e_join_threads(ps_codec);
4523
4524 /* collect list of memory records used by the encoder library */
4525 memcpy(ps_ip->s_ive_ip.ps_mem_rec, ps_codec->ps_mem_rec_backup,
4526 MEM_REC_CNT * (sizeof(iv_mem_rec_t)));
4527 ps_op->s_ive_op.u4_num_mem_rec_filled = MEM_REC_CNT;
4528
4529 /* clean up mutex memory */
4530 ih264_list_free(ps_codec->pv_entropy_jobq);
4531 ih264_list_free(ps_codec->pv_proc_jobq);
4532 ithread_mutex_destroy(ps_codec->pv_ctl_mutex);
4533 ithread_mutex_destroy(ps_codec->pv_entropy_mutex);
4534
4535
4536 ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_mv_buf_mgr);
4537 ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_ref_buf_mgr);
4538 ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_inp_buf_mgr);
4539 ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_out_buf_mgr);
4540
4541 return IV_SUCCESS;
4542}
4543
4544/**
4545*******************************************************************************
4546*
4547* @brief
4548* Sets the encoder in flush mode.
4549*
4550* @par Description:
4551* Sets the encoder in flush mode
4552*
4553* @param[in] ps_codec_obj
4554* Pointer to codec object at API level
4555*
4556* @param[in] pv_api_ip
4557* Pointer to input argument structure
4558*
4559* @param[out] pv_api_op
4560* Pointer to output argument structure
4561*
4562* @returns error status
4563*
4564* @remarks This call has no real effect on encoder
4565*
4566*******************************************************************************
4567*/
4568static WORD32 ih264e_set_flush_mode(iv_obj_t *ps_codec_obj,
4569 void *pv_api_ip,
4570 void *pv_api_op)
4571{
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4572 /* codec ctxt */
4573 codec_t *ps_codec = (codec_t *) ps_codec_obj->pv_codec_handle;
4574
4575 /* ctrl call I/O structures */
4576 ih264e_ctl_flush_op_t *ps_ctl_op = pv_api_op;
4577
Martin Storsjocc872412015-06-13 00:35:01 +0300[diff] [blame]4578 UNUSED(pv_api_ip);
4579
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4580 ps_ctl_op->s_ive_op.u4_error_code = 0;
4581
4582 /* signal flush frame control call */
4583 ps_codec->i4_flush_mode = 1;
4584
4585 return IV_SUCCESS;
4586}
4587
4588/**
4589*******************************************************************************
4590*
4591* @brief
4592* Gets encoder buffer requirements
4593*
4594* @par Description:
4595* Gets the encoder buffer requirements. Basing on max width and max height
4596* configuration settings, this routine, computes the sizes of necessary input,
4597* output buffers returns this info to callee.
4598*
4599* @param[in] ps_codec_obj
4600* Pointer to codec object at API level
4601*
4602* @param[in] pv_api_ip
4603* Pointer to input argument structure
4604*
4605* @param[out] pv_api_op
4606* Pointer to output argument structure
4607*
4608* @returns error status
4609*
4610* @remarks none
4611*
4612*******************************************************************************
4613*/
4614static WORD32 ih264e_get_buf_info(iv_obj_t *ps_codec_obj,
4615 void *pv_api_ip,
4616 void *pv_api_op)
4617{
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4618 /* ctrl call I/O structures */
4619 ih264e_ctl_getbufinfo_ip_t *ps_ip = pv_api_ip;
4620 ih264e_ctl_getbufinfo_op_t *ps_op = pv_api_op;
4621
4622 /* temp var */
4623 WORD32 wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
4624 WORD32 ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
4625 WORD32 i;
4626
Martin Storsjocc872412015-06-13 00:35:01 +0300[diff] [blame]4627 UNUSED(ps_codec_obj);
4628
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4629 ps_op->s_ive_op.u4_error_code = 0;
4630
4631 /* Number of components in input buffers required for codec &
4632 * Minimum sizes of each component in input buffer required */
4633 if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420P)
4634 {
4635 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_420_COMP;
4636
4637 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht;
4638 ps_op->s_ive_op.au4_min_in_buf_size[1] = (wd >> 1) * (ht >> 1);
4639 ps_op->s_ive_op.au4_min_in_buf_size[2] = (wd >> 1) * (ht >> 1);
4640 }
4641 else if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_422ILE)
4642 {
4643 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_422ILE_COMP;
4644
4645 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 2;
4646 ps_op->s_ive_op.au4_min_in_buf_size[1] =
4647 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
4648 }
4649 else if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_RGB_565)
4650 {
4651 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_RGB565_COMP;
4652
4653 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 2;
4654 ps_op->s_ive_op.au4_min_in_buf_size[1] =
4655 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
4656 }
4657 else if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_RGBA_8888)
4658 {
4659 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_RGBA8888_COMP;
4660
4661 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 4;
4662 ps_op->s_ive_op.au4_min_in_buf_size[1] =
4663 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
4664 }
4665 else if ((ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420SP_UV)
4666 || (ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420SP_VU))
4667 {
4668 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_420SP_COMP;
4669
4670 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht;
4671 ps_op->s_ive_op.au4_min_in_buf_size[1] = wd * (ht >> 1);
4672 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
4673 }
4674
4675 /* Number of components in output buffers required for codec &
4676 * Minimum sizes of each component in output buffer required */
4677 ps_op->s_ive_op.u4_out_comp_cnt = MIN_BITS_BUFS_COMP;
4678
4679 for (i = 0; i < (WORD32) ps_op->s_ive_op.u4_out_comp_cnt; i++)
4680 {
Harinarayanan K Kd2d469e2015-06-19 14:45:44 +0530[diff] [blame]4681 ps_op->s_ive_op.au4_min_out_buf_size[i] = MAX(((wd * ht * 3) >> 1), MIN_STREAM_SIZE);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4682 }
4683
4684 ps_op->s_ive_op.u4_min_inp_bufs = MIN_INP_BUFS;
4685 ps_op->s_ive_op.u4_min_out_bufs = MIN_OUT_BUFS;
4686
4687 return IV_SUCCESS;
4688}
4689
4690/**
4691*******************************************************************************
4692*
4693* @brief
4694* Sets the picture dimensions
4695*
4696* @par Description:
4697* Sets width, height, display width, display height and strides
4698*
4699* @param[in] pv_api_ip
4700* Pointer to input argument structure
4701*
4702* @param[out] pv_api_op
4703* Pointer to output argument structure
4704*
4705* @param[out] ps_cfg
4706* Pointer to config structure to be updated
4707*
4708* @returns error status
4709*
4710* @remarks none
4711*
4712*******************************************************************************
4713*/
4714static IV_STATUS_T ih264e_set_dimensions(void *pv_api_ip,
4715 void *pv_api_op,
4716 cfg_params_t *ps_cfg)
4717{
4718 /* ctrl call I/O structures */
4719 ih264e_ctl_set_dimensions_ip_t *ps_ip = pv_api_ip;
4720 ih264e_ctl_set_dimensions_op_t *ps_op = pv_api_op;
4721
4722 ps_op->s_ive_op.u4_error_code = 0;
4723
4724 ps_cfg->u4_wd = ALIGN16(ps_ip->s_ive_ip.u4_wd);
4725 ps_cfg->u4_ht = ALIGN16(ps_ip->s_ive_ip.u4_ht);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4726 ps_cfg->i4_wd_mbs = ps_cfg->u4_wd >> 4;
4727 ps_cfg->i4_ht_mbs = ps_cfg->u4_ht >> 4;
4728 ps_cfg->u4_disp_wd = ps_ip->s_ive_ip.u4_wd;
4729 ps_cfg->u4_disp_ht = ps_ip->s_ive_ip.u4_ht;
4730
4731 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4732 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4733
4734 return IV_SUCCESS;
4735}
4736
4737/**
4738*******************************************************************************
4739*
4740* @brief
4741* Sets source and target frame rates
4742*
4743* @par Description:
4744* Sets source and target frame rates
4745*
4746* @param[in] pv_api_ip
4747* Pointer to input argument structure
4748*
4749* @param[out] pv_api_op
4750* Pointer to output argument structure
4751*
4752* @param[out] ps_cfg
4753* Pointer to config structure to be updated
4754*
4755* @returns error status
4756*
4757* @remarks none
4758*
4759*******************************************************************************
4760*/
4761static IV_STATUS_T ih264e_set_frame_rate(void *pv_api_ip,
4762 void *pv_api_op,
4763 cfg_params_t *ps_cfg)
4764{
4765 /* ctrl call I/O structures */
4766 ih264e_ctl_set_frame_rate_ip_t *ps_ip = pv_api_ip;
4767 ih264e_ctl_set_frame_rate_op_t *ps_op = pv_api_op;
4768
4769 ps_op->s_ive_op.u4_error_code = 0;
4770
4771 ps_cfg->u4_src_frame_rate = ps_ip->s_ive_ip.u4_src_frame_rate;
4772 ps_cfg->u4_tgt_frame_rate = ps_ip->s_ive_ip.u4_tgt_frame_rate;
4773
4774 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4775 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4776
4777 return IV_SUCCESS;
4778}
4779
4780/**
4781*******************************************************************************
4782*
4783* @brief
4784* Sets target bit rate
4785*
4786* @par Description:
4787* Sets target bit rate
4788*
4789* @param[in] pv_api_ip
4790* Pointer to input argument structure
4791*
4792* @param[out] pv_api_op
4793* Pointer to output argument structure
4794*
4795* @param[out] ps_cfg
4796* Pointer to config structure to be updated
4797*
4798* @returns error status
4799*
4800* @remarks none
4801*
4802*******************************************************************************
4803*/
4804static IV_STATUS_T ih264e_set_bit_rate(void *pv_api_ip,
4805 void *pv_api_op,
4806 cfg_params_t *ps_cfg)
4807{
4808 /* ctrl call I/O structures */
4809 ih264e_ctl_set_bitrate_ip_t *ps_ip = pv_api_ip;
4810 ih264e_ctl_set_bitrate_op_t *ps_op = pv_api_op;
4811
4812 ps_op->s_ive_op.u4_error_code = 0;
4813
4814 ps_cfg->u4_target_bitrate = ps_ip->s_ive_ip.u4_target_bitrate;
4815
4816 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4817 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4818
4819 return IV_SUCCESS;
4820}
4821
4822/**
4823*******************************************************************************
4824*
4825* @brief
4826* Sets frame type
4827*
4828* @par Description:
4829* Sets frame type
4830*
4831* @param[in] pv_api_ip
4832* Pointer to input argument structure
4833*
4834* @param[out] pv_api_op
4835* Pointer to output argument structure
4836*
4837* @param[out] ps_cfg
4838* Pointer to config structure to be updated
4839*
4840* @returns error status
4841*
4842* @remarks not a sticky tag
4843*
4844*******************************************************************************
4845*/
4846static IV_STATUS_T ih264e_set_frame_type(void *pv_api_ip,
4847 void *pv_api_op,
4848 cfg_params_t *ps_cfg)
4849{
4850 /* ctrl call I/O structures */
4851 ih264e_ctl_set_frame_type_ip_t *ps_ip = pv_api_ip;
4852 ih264e_ctl_set_frame_type_op_t *ps_op = pv_api_op;
4853
4854 ps_op->s_ive_op.u4_error_code = 0;
4855
4856 ps_cfg->e_frame_type = ps_ip->s_ive_ip.e_frame_type;
4857
4858 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4859 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4860
4861 return IV_SUCCESS;
4862}
4863
4864/**
4865*******************************************************************************
4866*
4867* @brief
4868* Sets quantization params
4869*
4870* @par Description:
4871* Sets the max, min and default qp for I frame, P frame and B frame
4872*
4873* @param[in] pv_api_ip
4874* Pointer to input argument structure
4875*
4876* @param[out] pv_api_op
4877* Pointer to output argument structure
4878*
4879* @param[out] ps_cfg
4880* Pointer to config structure to be updated
4881*
4882* @returns error status
4883*
4884* @remarks none
4885*
4886*******************************************************************************
4887*/
4888static IV_STATUS_T ih264e_set_qp(void *pv_api_ip,
4889 void *pv_api_op,
4890 cfg_params_t *ps_cfg)
4891{
4892 /* ctrl call I/O structures */
4893 ih264e_ctl_set_qp_ip_t *ps_set_qp_ip = pv_api_ip;
4894 ih264e_ctl_set_qp_op_t *ps_set_qp_op = pv_api_op;
4895
4896 ps_set_qp_op->s_ive_op.u4_error_code = 0;
4897
4898 ps_cfg->u4_i_qp_max = ps_set_qp_ip->s_ive_ip.u4_i_qp_max;
4899 ps_cfg->u4_i_qp_min = ps_set_qp_ip->s_ive_ip.u4_i_qp_min;
4900 ps_cfg->u4_i_qp = ps_set_qp_ip->s_ive_ip.u4_i_qp;
4901 ps_cfg->u4_p_qp_max = ps_set_qp_ip->s_ive_ip.u4_p_qp_max;
4902 ps_cfg->u4_p_qp_min = ps_set_qp_ip->s_ive_ip.u4_p_qp_min;
4903 ps_cfg->u4_p_qp = ps_set_qp_ip->s_ive_ip.u4_p_qp;
4904 ps_cfg->u4_b_qp_max = ps_set_qp_ip->s_ive_ip.u4_b_qp_max;
4905 ps_cfg->u4_b_qp_min = ps_set_qp_ip->s_ive_ip.u4_b_qp_min;
4906 ps_cfg->u4_b_qp = ps_set_qp_ip->s_ive_ip.u4_b_qp;
4907
4908 ps_cfg->u4_timestamp_high = ps_set_qp_ip->s_ive_ip.u4_timestamp_high;
4909 ps_cfg->u4_timestamp_low = ps_set_qp_ip->s_ive_ip.u4_timestamp_low;
4910
4911 return IV_SUCCESS;
4912}
4913
4914/**
4915*******************************************************************************
4916*
4917* @brief
4918* Sets encoding mode
4919*
4920* @par Description:
4921* Sets encoding mode
4922*
4923* @param[in] pv_api_ip
4924* Pointer to input argument structure
4925*
4926* @param[out] pv_api_op
4927* Pointer to output argument structure
4928*
4929* @param[out] ps_cfg
4930* Pointer to config structure to be updated
4931*
4932* @returns error status
4933*
4934* @remarks none
4935*
4936*******************************************************************************
4937*/
4938static IV_STATUS_T ih264e_set_enc_mode(void *pv_api_ip,
4939 void *pv_api_op,
4940 cfg_params_t *ps_cfg)
4941{
4942 /* ctrl call I/O structures */
4943 ih264e_ctl_set_enc_mode_ip_t *ps_ip = pv_api_ip;
4944 ih264e_ctl_set_enc_mode_op_t *ps_op = pv_api_op;
4945
4946 ps_op->s_ive_op.u4_error_code = 0;
4947
4948 ps_cfg->e_enc_mode = ps_ip->s_ive_ip.e_enc_mode;
4949
4950 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4951 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4952
4953 return IV_SUCCESS;
4954}
4955
4956/**
4957*******************************************************************************
4958*
4959* @brief
4960* Sets vbv parameters
4961*
4962* @par Description:
4963* Sets vbv parameters
4964*
4965* @param[in] pv_api_ip
4966* Pointer to input argument structure
4967*
4968* @param[out] pv_api_op
4969* Pointer to output argument structure
4970*
4971* @param[out] ps_cfg
4972* Pointer to config structure to be updated
4973*
4974* @returns error status
4975*
4976* @remarks none
4977*
4978*******************************************************************************
4979*/
4980static IV_STATUS_T ih264e_set_vbv_params(void *pv_api_ip,
4981 void *pv_api_op,
4982 cfg_params_t *ps_cfg)
4983{
4984 /* ctrl call I/O structures */
4985 ih264e_ctl_set_vbv_params_ip_t *ps_ip = pv_api_ip;
4986 ih264e_ctl_set_vbv_params_op_t *ps_op = pv_api_op;
4987
4988 ps_op->s_ive_op.u4_error_code = 0;
4989
4990 ps_cfg->u4_vbv_buf_size = ps_ip->s_ive_ip.u4_vbv_buf_size;
4991 ps_cfg->u4_vbv_buffer_delay = ps_ip->s_ive_ip.u4_vbv_buffer_delay;
4992
4993 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4994 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4995
4996 return IV_SUCCESS;
4997}
4998
4999/**
5000*******************************************************************************
5001*
5002* @brief
5003* Sets AIR parameters
5004*
5005* @par Description:
5006* Sets AIR parameters
5007*
5008* @param[in] pv_api_ip
5009* Pointer to input argument structure
5010*
5011* @param[out] pv_api_op
5012* Pointer to output argument structure
5013*
5014* @param[out] ps_cfg
5015* Pointer to config structure to be updated
5016*
5017* @returns error status
5018*
5019* @remarks none
5020*
5021*******************************************************************************
5022*/
5023static IV_STATUS_T ih264_set_air_params(void *pv_api_ip,
5024 void *pv_api_op,
5025 cfg_params_t *ps_cfg)
5026{
5027 /* ctrl call I/O structures */
5028 ih264e_ctl_set_air_params_ip_t *ps_ip = pv_api_ip;
5029 ih264e_ctl_set_air_params_op_t *ps_op = pv_api_op;
5030
5031 ps_op->s_ive_op.u4_error_code = 0;
5032
5033 ps_cfg->e_air_mode = ps_ip->s_ive_ip.e_air_mode;
5034 ps_cfg->u4_air_refresh_period = ps_ip->s_ive_ip.u4_air_refresh_period;
5035
5036 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5037 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5038
5039 return IV_SUCCESS;
5040}
5041
5042/**
5043*******************************************************************************
5044*
5045* @brief
5046* Sets motion estimation parameters
5047*
5048* @par Description:
5049* Sets motion estimation parameters
5050*
5051* @param[in] pv_api_ip
5052* Pointer to input argument structure
5053*
5054* @param[out] pv_api_op
5055* Pointer to output argument structure
5056*
5057* @param[out] ps_cfg
5058* Pointer to config structure to be updated
5059*
5060* @returns error status
5061*
5062* @remarks none
5063*
5064*******************************************************************************
5065*/
5066static IV_STATUS_T ih264_set_me_params(void *pv_api_ip,
5067 void *pv_api_op,
5068 cfg_params_t *ps_cfg)
5069{
5070 /* ctrl call I/O structures */
5071 ih264e_ctl_set_me_params_ip_t *ps_ip = pv_api_ip;
5072 ih264e_ctl_set_me_params_op_t *ps_op = pv_api_op;
5073
5074 ps_op->s_ive_op.u4_error_code = 0;
5075
5076 ps_cfg->u4_enable_hpel = ps_ip->s_ive_ip.u4_enable_hpel;
5077 ps_cfg->u4_enable_qpel = ps_ip->s_ive_ip.u4_enable_qpel;
5078 ps_cfg->u4_enable_fast_sad = ps_ip->s_ive_ip.u4_enable_fast_sad;
5079 ps_cfg->u4_enable_alt_ref = ps_ip->s_ive_ip.u4_enable_alt_ref;
5080 ps_cfg->u4_srch_rng_x = ps_ip->s_ive_ip.u4_srch_rng_x;
5081 ps_cfg->u4_srch_rng_y = ps_ip->s_ive_ip.u4_srch_rng_y;
5082 ps_cfg->u4_me_speed_preset = ps_ip->s_ive_ip.u4_me_speed_preset;
5083
5084 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5085 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5086
5087 return IV_SUCCESS;
5088}
5089
5090/**
5091*******************************************************************************
5092*
5093* @brief
5094* Sets Intra/Inter Prediction estimation parameters
5095*
5096* @par Description:
5097* Sets Intra/Inter Prediction estimation parameters
5098*
5099* @param[in] pv_api_ip
5100* Pointer to input argument structure
5101*
5102* @param[out] pv_api_op
5103* Pointer to output argument structure
5104*
5105* @param[out] ps_cfg
5106* Pointer to config structure to be updated
5107*
5108* @returns error status
5109*
5110* @remarks none
5111*
5112*******************************************************************************
5113*/
5114static IV_STATUS_T ih264_set_ipe_params(void *pv_api_ip,
5115 void *pv_api_op,
5116 cfg_params_t *ps_cfg)
5117{
5118 /* ctrl call I/O structures */
5119 ih264e_ctl_set_ipe_params_ip_t *ps_ip = pv_api_ip;
5120 ih264e_ctl_set_ipe_params_op_t *ps_op = pv_api_op;
5121
5122 ps_op->s_ive_op.u4_error_code = 0;
5123
5124 ps_cfg->u4_enable_intra_4x4 = ps_ip->s_ive_ip.u4_enable_intra_4x4;
5125 ps_cfg->u4_enc_speed_preset = ps_ip->s_ive_ip.u4_enc_speed_preset;
5126
Doney Alexdfe686a2016-02-24 12:00:03 +0530[diff] [blame]5127 ps_cfg->u4_constrained_intra_pred = ps_ip->s_ive_ip.u4_constrained_intra_pred;
5128
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]5129 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5130 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5131
5132 return IV_SUCCESS;
5133}
5134
5135/**
5136*******************************************************************************
5137*
5138* @brief
5139* Sets GOP parameters
5140*
5141* @par Description:
5142* Sets GOP parameters
5143*
5144* @param[in] pv_api_ip
5145* Pointer to input argument structure
5146*
5147* @param[out] pv_api_op
5148* Pointer to output argument structure
5149*
5150* @param[out] ps_cfg
5151* Pointer to config structure to be updated
5152*
5153* @returns error status
5154*
5155* @remarks none
5156*
5157*******************************************************************************
5158*/
5159static IV_STATUS_T ih264_set_gop_params(void *pv_api_ip,
5160 void *pv_api_op,
5161 cfg_params_t *ps_cfg)
5162{
5163 /* ctrl call I/O structures */
5164 ih264e_ctl_set_gop_params_ip_t *ps_ip = pv_api_ip;
5165 ih264e_ctl_set_gop_params_op_t *ps_op = pv_api_op;
5166
5167 ps_op->s_ive_op.u4_error_code = 0;
5168
5169 ps_cfg->u4_i_frm_interval = ps_ip->s_ive_ip.u4_i_frm_interval;
5170 ps_cfg->u4_idr_frm_interval = ps_ip->s_ive_ip.u4_idr_frm_interval;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]5171
5172 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5173 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5174
5175 return IV_SUCCESS;
5176}
5177
5178/**
5179*******************************************************************************
5180*
5181* @brief
5182* Sets profile parameters
5183*
5184* @par Description:
5185* Sets profile parameters
5186*
5187* @param[in] pv_api_ip
5188* Pointer to input argument structure
5189*
5190* @param[out] pv_api_op
5191* Pointer to output argument structure
5192*
5193* @param[out] ps_cfg
5194* Pointer to config structure to be updated
5195*
5196* @returns error status
5197*
5198* @remarks none
5199*
5200*******************************************************************************
5201*/
5202static IV_STATUS_T ih264_set_profile_params(void *pv_api_ip,
5203 void *pv_api_op,
5204 cfg_params_t *ps_cfg)
5205{
5206 /* ctrl call I/O structures */
5207 ih264e_ctl_set_profile_params_ip_t *ps_ip = pv_api_ip;
5208 ih264e_ctl_set_profile_params_op_t *ps_op = pv_api_op;
5209
5210 ps_op->s_ive_op.u4_error_code = 0;
5211
5212 ps_cfg->e_profile = ps_ip->s_ive_ip.e_profile;
5213
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame]5214 ps_cfg->u4_entropy_coding_mode = ps_ip->s_ive_ip.u4_entropy_coding_mode;
5215
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]5216 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5217 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5218
5219 return IV_SUCCESS;
5220}
5221
5222/**
5223*******************************************************************************
5224*
5225* @brief
5226* Sets disable deblock level
5227*
5228* @par Description:
5229* Sets disable deblock level. Level 0 means no disabling and level 4 means
5230* disable completely. 1, 2, 3 are intermediate levels that control amount
5231* of deblocking done.
5232*
5233* @param[in] ps_codec_obj
5234* Pointer to codec object at API level
5235*
5236* @param[in] pv_api_ip
5237* Pointer to input argument structure
5238*
5239* @param[out] pv_api_op
5240* Pointer to output argument structure
5241*
5242* @returns error status
5243*
5244* @remarks none
5245*
5246*******************************************************************************
5247*/
5248static WORD32 ih264_set_deblock_params(void *pv_api_ip,
5249 void *pv_api_op,
5250 cfg_params_t *ps_cfg)
5251{
5252 /* ctrl call I/O structures */
5253 ih264e_ctl_set_deblock_params_ip_t *ps_ip = pv_api_ip;
5254 ih264e_ctl_set_deblock_params_op_t *ps_op = pv_api_op;
5255
5256 ps_op->s_ive_op.u4_error_code = 0;
5257
5258 ps_cfg->u4_disable_deblock_level = ps_ip->s_ive_ip.u4_disable_deblock_level;
5259
5260 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5261 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5262
5263 return IV_SUCCESS;
5264}
Doney Alex983e1ae2016-03-30 17:31:26 +0530[diff] [blame]5265/**
5266 *******************************************************************************
5267 *
5268 * @brief
5269 * Sets vui params
5270 *
5271 * @par Description:
5272 * Video usability information
5273 *
5274 * @param[in] pv_api_ip
5275 * Pointer to input argument structure
5276 *
5277 * @param[out] pv_api_op
5278 * Pointer to output argument structure
5279 *
5280 * @param[out] ps_cfg
5281 * Pointer to config structure to be updated
5282 *
5283 * @returns error status
5284 *
5285 * @remarks none
5286 *
5287 *******************************************************************************
5288 */
5289static WORD32 ih264e_set_vui_params(void *pv_api_ip,
5290 void *pv_api_op,
5291 cfg_params_t *ps_cfg)
5292{
5293 /* ctrl call I/O structures */
5294 ih264e_vui_ip_t *ps_ip = pv_api_ip;
5295 ih264e_vui_op_t *ps_op = pv_api_op;
5296 vui_t *ps_vui = &ps_cfg->s_vui;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]5297
Doney Alex983e1ae2016-03-30 17:31:26 +0530[diff] [blame]5298 ps_op->u4_error_code = 0;
5299
5300 ps_vui->u1_aspect_ratio_info_present_flag =
5301 ps_ip->u1_aspect_ratio_info_present_flag;
5302 ps_vui->u1_aspect_ratio_idc = ps_ip->u1_aspect_ratio_idc;
5303 ps_vui->u2_sar_width = ps_ip->u2_sar_width;
5304 ps_vui->u2_sar_height = ps_ip->u2_sar_height;
5305 ps_vui->u1_overscan_info_present_flag =
5306 ps_ip->u1_overscan_info_present_flag;
5307 ps_vui->u1_overscan_appropriate_flag = ps_ip->u1_overscan_appropriate_flag;
5308 ps_vui->u1_video_signal_type_present_flag =
5309 ps_ip->u1_video_signal_type_present_flag;
5310 ps_vui->u1_video_format = ps_ip->u1_video_format;
5311 ps_vui->u1_video_full_range_flag = ps_ip->u1_video_full_range_flag;
5312 ps_vui->u1_colour_description_present_flag =
5313 ps_ip->u1_colour_description_present_flag;
5314 ps_vui->u1_colour_primaries = ps_ip->u1_colour_primaries;
5315 ps_vui->u1_transfer_characteristics = ps_ip->u1_transfer_characteristics;
5316 ps_vui->u1_matrix_coefficients = ps_ip->u1_matrix_coefficients;
5317 ps_vui->u1_chroma_loc_info_present_flag =
5318 ps_ip->u1_chroma_loc_info_present_flag;
5319 ps_vui->u1_chroma_sample_loc_type_top_field =
5320 ps_ip->u1_chroma_sample_loc_type_top_field;
5321 ps_vui->u1_chroma_sample_loc_type_bottom_field =
5322 ps_ip->u1_chroma_sample_loc_type_bottom_field;
5323 ps_vui->u1_vui_timing_info_present_flag =
5324 ps_ip->u1_vui_timing_info_present_flag;
5325 ps_vui->u4_vui_num_units_in_tick = ps_ip->u4_vui_num_units_in_tick;
5326 ps_vui->u4_vui_time_scale = ps_ip->u4_vui_time_scale;
5327 ps_vui->u1_fixed_frame_rate_flag = ps_ip->u1_fixed_frame_rate_flag;
5328 ps_vui->u1_nal_hrd_parameters_present_flag =
5329 ps_ip->u1_nal_hrd_parameters_present_flag;
5330 ps_vui->u1_vcl_hrd_parameters_present_flag =
5331 ps_ip->u1_vcl_hrd_parameters_present_flag;
5332 ps_vui->u1_low_delay_hrd_flag = ps_ip->u1_low_delay_hrd_flag;
5333 ps_vui->u1_pic_struct_present_flag = ps_ip->u1_pic_struct_present_flag;
5334 ps_vui->u1_bitstream_restriction_flag =
5335 ps_ip->u1_bitstream_restriction_flag;
5336 ps_vui->u1_motion_vectors_over_pic_boundaries_flag =
5337 ps_ip->u1_motion_vectors_over_pic_boundaries_flag;
5338 ps_vui->u1_max_bytes_per_pic_denom = ps_ip->u1_max_bytes_per_pic_denom;
5339 ps_vui->u1_max_bits_per_mb_denom = ps_ip->u1_max_bits_per_mb_denom;
5340 ps_vui->u1_log2_max_mv_length_horizontal =
5341 ps_ip->u1_log2_max_mv_length_horizontal;
5342 ps_vui->u1_log2_max_mv_length_vertical =
5343 ps_ip->u1_log2_max_mv_length_vertical;
5344 ps_vui->u1_num_reorder_frames = ps_ip->u1_num_reorder_frames;
5345 ps_vui->u1_max_dec_frame_buffering = ps_ip->u1_max_dec_frame_buffering;
5346
5347 return IV_SUCCESS;
5348}
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]5349/**
5350*******************************************************************************
5351*
5352* @brief
5353* Sets number of cores
5354*
5355* @par Description:
5356* Sets number of cores
5357*
5358* @param[in] ps_codec_obj
5359* Pointer to codec object at API level
5360*
5361* @param[in] pv_api_ip
5362* Pointer to input argument structure
5363*
5364* @param[out] pv_api_op
5365* Pointer to output argument structure
5366*
5367* @returns error status
5368*
5369* @remarks The number of encoder threads is limited to MAX_PROCESS_THREADS
5370*
5371*******************************************************************************
5372*/
5373static WORD32 ih264e_set_num_cores(void *pv_api_ip,
5374 void *pv_api_op,
5375 cfg_params_t *ps_cfg)
5376{
5377 /* ctrl call I/O structures */
5378 ih264e_ctl_set_num_cores_ip_t *ps_ip = pv_api_ip;
5379 ih264e_ctl_set_num_cores_op_t *ps_op = pv_api_op;
5380
5381 ps_op->s_ive_op.u4_error_code = 0;
5382
5383 ps_cfg->u4_num_cores = MIN(ps_ip->s_ive_ip.u4_num_cores, MAX_PROCESS_THREADS);
5384
5385 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5386 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5387
5388 return IV_SUCCESS;
5389}
5390
5391/**
5392*******************************************************************************
5393*
5394* @brief
5395* Resets encoder state
5396*
5397* @par Description:
5398* Resets encoder state by calling ih264e_init()
5399*
5400* @param[in] ps_codec_obj
5401* Pointer to codec object at API level
5402*
5403* @param[in] pv_api_ip
5404* Pointer to input argument structure
5405*
5406* @param[out] pv_api_op
5407* Pointer to output argument structure
5408*
5409* @returns error status
5410*
5411* @remarks none
5412*
5413*******************************************************************************
5414*/
5415static WORD32 ih264e_reset(iv_obj_t *ps_codec_obj,
5416 void *pv_api_ip,
5417 void *pv_api_op)
5418{
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]5419 /* codec ctxt */
5420 codec_t * ps_codec = (codec_t *) (ps_codec_obj->pv_codec_handle);
5421
5422 /* ctrl call I/O structures */
5423 ih264e_ctl_reset_op_t *ps_op = pv_api_op;
5424
Martin Storsjocc872412015-06-13 00:35:01 +0300[diff] [blame]5425 UNUSED(pv_api_ip);
5426
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]5427 ps_op->s_ive_op.u4_error_code = 0;
5428
5429 if (ps_codec != NULL)
5430 {
5431 ih264e_init(ps_codec);
5432 }
5433 else
5434 {
5435 ps_op->s_ive_op.u4_error_code = IH264E_INIT_NOT_DONE;
5436 }
5437
5438 return IV_SUCCESS;
5439}
5440
5441/**
5442*******************************************************************************
5443*
5444* @brief
5445* Codec control call
5446*
5447* @par Description:
5448* Codec control call which in turn calls appropriate calls based on sub-command
5449*
5450* @param[in] ps_codec_obj
5451* Pointer to codec object at API level
5452*
5453* @param[in] pv_api_ip
5454* Pointer to input argument structure
5455*
5456* @param[out] pv_api_op
5457* Pointer to output argument structure
5458*
5459* @returns error status
5460*
5461* @remarks none
5462*
5463*******************************************************************************
5464*/
5465static WORD32 ih264e_ctl(iv_obj_t *ps_codec_obj,
5466 void *pv_api_ip,
5467 void *pv_api_op)
5468{
5469 /* codec ctxt */
5470 codec_t *ps_codec = (codec_t *) ps_codec_obj->pv_codec_handle;
5471
5472 /* ctrl call I/O structures */
5473 ih264e_ctl_setdefault_ip_t *ps_ctl_ip = pv_api_ip;
5474 ih264e_ctl_setdefault_op_t *ps_ctl_op = pv_api_op;
5475
5476 /* ctrl call sub cmd */
5477 IVE_CONTROL_API_COMMAND_TYPE_T sub_cmd = ps_ctl_ip->s_ive_ip.e_sub_cmd;
5478
5479 /* error status */
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame]5480 IV_STATUS_T ret = IV_SUCCESS;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]5481
5482 /* temp var */
5483 WORD32 i;
5484 cfg_params_t *ps_cfg = NULL;
5485
5486 /* control call is for configuring encoding params, this is not to be called
5487 * before a successful init call */
5488 if (ps_codec->i4_init_done != 1)
5489 {
5490 ps_ctl_op->s_ive_op.u4_error_code |= 1 << IVE_FATALERROR;
5491 ps_ctl_op->s_ive_op.u4_error_code |= IH264E_INIT_NOT_DONE;
5492 return IV_FAIL;
5493 }
5494
5495 /* make it thread safe */
5496 ithread_mutex_lock(ps_codec->pv_ctl_mutex);
5497
5498 /* find a free config param set to hold current parameters */
5499 for (i = 0; i < MAX_ACTIVE_CONFIG_PARAMS; i++)
5500 {
5501 if (0 == ps_codec->as_cfg[i].u4_is_valid)
5502 {
5503 ps_cfg = &ps_codec->as_cfg[i];
5504 break;
5505 }
5506 }
5507
5508 /* If all are invalid, then start overwriting from the head config params */
5509 if (NULL == ps_cfg)
5510 {
5511 ps_cfg = &ps_codec->as_cfg[0];
5512 }
5513
5514 ps_cfg->u4_is_valid = 1;
5515
5516 ps_cfg->e_cmd = sub_cmd;
5517
5518 switch (sub_cmd)
5519 {
5520 case IVE_CMD_CTL_SET_DIMENSIONS:
5521 ret = ih264e_set_dimensions(pv_api_ip, pv_api_op, ps_cfg);
5522 break;
5523
5524 case IVE_CMD_CTL_SET_FRAMERATE:
5525 ret = ih264e_set_frame_rate(pv_api_ip, pv_api_op, ps_cfg);
5526 break;
5527
5528 case IVE_CMD_CTL_SET_BITRATE:
5529 ret = ih264e_set_bit_rate(pv_api_ip, pv_api_op, ps_cfg);
5530 break;
5531
5532 case IVE_CMD_CTL_SET_FRAMETYPE:
5533 ret = ih264e_set_frame_type(pv_api_ip, pv_api_op, ps_cfg);
5534 break;
5535
5536 case IVE_CMD_CTL_SET_QP:
5537 ret = ih264e_set_qp(pv_api_ip, pv_api_op, ps_cfg);
5538 break;
5539
5540 case IVE_CMD_CTL_SET_ENC_MODE:
5541 ret = ih264e_set_enc_mode(pv_api_ip, pv_api_op, ps_cfg);
5542 break;
5543
5544 case IVE_CMD_CTL_SET_VBV_PARAMS:
5545 ret = ih264e_set_vbv_params(pv_api_ip, pv_api_op, ps_cfg);
5546 break;
5547
5548 case IVE_CMD_CTL_SET_AIR_PARAMS:
5549 ret = ih264_set_air_params(pv_api_ip, pv_api_op, ps_cfg);
5550 break;
5551
5552 case IVE_CMD_CTL_SET_ME_PARAMS:
5553 ret = ih264_set_me_params(pv_api_ip, pv_api_op, ps_cfg);
5554 break;
5555
5556 case IVE_CMD_CTL_SET_IPE_PARAMS:
5557 ret = ih264_set_ipe_params(pv_api_ip, pv_api_op, ps_cfg);
5558 break;
5559
5560 case IVE_CMD_CTL_SET_GOP_PARAMS:
5561 ret = ih264_set_gop_params(pv_api_ip, pv_api_op, ps_cfg);
5562 break;
5563
5564 case IVE_CMD_CTL_SET_PROFILE_PARAMS:
5565 ret = ih264_set_profile_params(pv_api_ip, pv_api_op, ps_cfg);
5566 break;
5567
5568 case IVE_CMD_CTL_SET_DEBLOCK_PARAMS:
5569 ret = ih264_set_deblock_params(pv_api_ip, pv_api_op, ps_cfg);
5570 break;
5571
Doney Alex983e1ae2016-03-30 17:31:26 +0530[diff] [blame]5572 case IVE_CMD_CTL_SET_VUI_PARAMS:
5573 ret = ih264e_set_vui_params(pv_api_ip, pv_api_op, ps_cfg);
5574 break;
5575
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]5576 case IVE_CMD_CTL_RESET:
5577
5578 /* invalidate config param struct as it is being served right away */
5579 ps_codec->as_cfg[i].u4_is_valid = 0;
5580
5581 ret = ih264e_reset(ps_codec_obj, pv_api_ip, pv_api_op);
5582 break;
5583
5584 case IVE_CMD_CTL_SETDEFAULT:
5585 {
5586 /* ctrl call I/O structures */
5587 ih264e_ctl_setdefault_op_t *ps_op = pv_api_op;
5588
5589 /* invalidate config param struct as it is being served right away */
5590 ps_codec->as_cfg[i].u4_is_valid = 0;
5591
5592 /* error status */
5593 ret = ih264e_set_default_params(ps_cfg);
5594
5595 ps_op->s_ive_op.u4_error_code = ret;
5596
5597 break;
5598 }
5599
5600 case IVE_CMD_CTL_FLUSH:
5601
5602 /* invalidate config param struct as it is being served right away */
5603 ps_codec->as_cfg[i].u4_is_valid = 0;
5604
5605 ret = ih264e_set_flush_mode(ps_codec_obj, pv_api_ip, pv_api_op);
5606 break;
5607
5608 case IVE_CMD_CTL_GETBUFINFO:
5609
5610 /* invalidate config param struct as it is being served right away */
5611 ps_codec->as_cfg[i].u4_is_valid = 0;
5612
5613 ret = ih264e_get_buf_info(ps_codec_obj, pv_api_ip, pv_api_op);
5614 break;
5615
5616 case IVE_CMD_CTL_GETVERSION:
5617 {
5618 /* ctrl call I/O structures */
5619 ih264e_ctl_getversioninfo_ip_t *ps_ip = pv_api_ip;
5620 ih264e_ctl_getversioninfo_op_t *ps_op = pv_api_op;
5621
5622 /* invalidate config param struct as it is being served right away */
5623 ps_codec->as_cfg[i].u4_is_valid = 0;
5624
5625 /* error status */
5626 ps_op->s_ive_op.u4_error_code = IV_SUCCESS;
5627
5628 if (ps_ip->s_ive_ip.u4_version_bufsize <= 0)
5629 {
5630 ps_op->s_ive_op.u4_error_code =
5631 IH264E_CXA_VERS_BUF_INSUFFICIENT;
5632 ret = IV_FAIL;
5633 }
5634 else
5635 {
5636 ret = ih264e_get_version((CHAR *) ps_ip->s_ive_ip.pu1_version,
5637 ps_ip->s_ive_ip.u4_version_bufsize);
5638
5639 if (ret != IV_SUCCESS)
5640 {
5641 ps_op->s_ive_op.u4_error_code =
5642 IH264E_CXA_VERS_BUF_INSUFFICIENT;
5643 ret = IV_FAIL;
5644 }
5645 }
5646 break;
5647 }
5648
5649 case IVE_CMD_CTL_SET_NUM_CORES:
5650 ret = ih264e_set_num_cores(pv_api_ip, pv_api_op, ps_cfg);
5651 break;
5652
5653 default:
5654 /* invalidate config param struct as it is being served right away */
5655 ps_codec->as_cfg[i].u4_is_valid = 0;
5656
5657 DEBUG("Warning !! unrecognized control api command \n");
5658 break;
5659 }
5660
5661 ithread_mutex_unlock(ps_codec->pv_ctl_mutex);
5662
5663 return ret;
5664}
5665
5666/**
5667*******************************************************************************
5668*
5669* @brief
5670* Codec entry point function. All the function calls to the codec are done
5671* using this function with different values specified in command
5672*
5673* @par Description:
5674* Arguments are tested for validity and then based on the command
5675* appropriate function is called
5676*
5677* @param[in] ps_handle
5678* API level handle for codec
5679*
5680* @param[in] pv_api_ip
5681* Input argument structure
5682*
5683* @param[out] pv_api_op
5684* Output argument structure
5685*
5686* @returns error_status
5687*
5688* @remarks
5689*
5690*******************************************************************************
5691*/
5692IV_STATUS_T ih264e_api_function(iv_obj_t *ps_handle,
5693 void *pv_api_ip,
5694 void *pv_api_op)
5695{
5696 /* api command */
5697 WORD32 command = IV_CMD_NA;
5698
5699 /* error status */
5700 IV_STATUS_T e_status;
5701 WORD32 ret;
5702
5703 /* tmp var */
5704 WORD32 *pu4_ptr_cmd = (WORD32 *) pv_api_ip;
5705
5706 /* validate input / output structures */
5707 e_status = api_check_struct_sanity(ps_handle, pv_api_ip, pv_api_op);
5708
5709 if (e_status != IV_SUCCESS)
5710 {
5711 DEBUG("error code = %d\n", *((UWORD32 *)pv_api_op + 1));
5712 return IV_FAIL;
5713 }
5714
5715 pu4_ptr_cmd++;
5716
5717 command = *pu4_ptr_cmd;
5718
5719 switch (command)
5720 {
5721 case IV_CMD_GET_NUM_MEM_REC:
5722 ret = ih264e_get_num_rec(pv_api_ip, pv_api_op);
5723 break;
5724
5725 case IV_CMD_FILL_NUM_MEM_REC:
5726 ret = ih264e_fill_num_mem_rec(pv_api_ip, pv_api_op);
5727 break;
5728
5729 case IV_CMD_INIT:
5730 ret = ih264e_init_mem_rec(ps_handle, pv_api_ip, pv_api_op);
5731 break;
5732
5733 case IV_CMD_RETRIEVE_MEMREC:
5734 ret = ih264e_retrieve_memrec(ps_handle, pv_api_ip, pv_api_op);
5735 break;
5736
5737 case IVE_CMD_VIDEO_CTL:
5738 ret = ih264e_ctl(ps_handle, pv_api_ip, pv_api_op);
5739 break;
5740
5741 case IVE_CMD_VIDEO_ENCODE:
5742 ret = ih264e_encode(ps_handle, pv_api_ip, pv_api_op);
5743 break;
5744
5745 default:
5746 ret = IV_FAIL;
5747 break;
5748 }
5749
5750 return (IV_STATUS_T) ret;
5751}