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Eric Anholtc4857422008-06-03 10:20:49 -07001/*
Eric Anholtc9ce2ed2012-03-09 16:08:23 -08002 * Copyright © 2008-2012 Intel Corporation
Eric Anholtc4857422008-06-03 10:20:49 -07003 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28/**
29 * @file intel_bufmgr.h
30 *
31 * Public definitions of Intel-specific bufmgr functions.
32 */
33
Eric Anholt738e36a2008-09-05 10:35:32 +010034#ifndef INTEL_BUFMGR_H
35#define INTEL_BUFMGR_H
Eric Anholtc4857422008-06-03 10:20:49 -070036
Eric Anholtea33a232012-01-03 13:05:57 -080037#include <stdio.h>
Eric Anholt738e36a2008-09-05 10:35:32 +010038#include <stdint.h>
Eric Anholt4db16a92011-10-11 15:59:03 -070039#include <stdio.h>
Eric Anholtc4857422008-06-03 10:20:49 -070040
Tapani Pällif1468e82015-08-07 10:37:57 +030041#if defined(__cplusplus)
42extern "C" {
43#endif
44
Chris Wilson1443bea2010-11-25 16:59:20 +000045struct drm_clip_rect;
46
Eric Anholt4b982642008-10-30 09:33:07 -070047typedef struct _drm_intel_bufmgr drm_intel_bufmgr;
Ben Widawskyb3b123d2012-01-13 11:31:31 -080048typedef struct _drm_intel_context drm_intel_context;
Eric Anholt4b982642008-10-30 09:33:07 -070049typedef struct _drm_intel_bo drm_intel_bo;
Eric Anholt738e36a2008-09-05 10:35:32 +010050
Eric Anholt4b982642008-10-30 09:33:07 -070051struct _drm_intel_bo {
Eric Anholtd70d6052009-10-06 12:40:42 -070052 /**
53 * Size in bytes of the buffer object.
54 *
55 * The size may be larger than the size originally requested for the
56 * allocation, such as being aligned to page size.
57 */
58 unsigned long size;
Jesse Barnes276c07d2008-11-13 13:52:04 -080059
Eric Anholtd70d6052009-10-06 12:40:42 -070060 /**
61 * Alignment requirement for object
62 *
63 * Used for GTT mapping & pinning the object.
64 */
65 unsigned long align;
Eric Anholt738e36a2008-09-05 10:35:32 +010066
Eric Anholtd70d6052009-10-06 12:40:42 -070067 /**
Kenneth Graunkeedf17db2014-01-13 14:14:36 -080068 * Deprecated field containing (possibly the low 32-bits of) the last
69 * seen virtual card address. Use offset64 instead.
Eric Anholtd70d6052009-10-06 12:40:42 -070070 */
71 unsigned long offset;
Jesse Barnes731cd552008-12-17 10:09:49 -080072
Eric Anholtd70d6052009-10-06 12:40:42 -070073 /**
74 * Virtual address for accessing the buffer data. Only valid while
75 * mapped.
76 */
Eric Anholt23287f02010-08-26 15:39:28 -070077#ifdef __cplusplus
78 void *virt;
79#else
Eric Anholtd70d6052009-10-06 12:40:42 -070080 void *virtual;
Eric Anholt23287f02010-08-26 15:39:28 -070081#endif
Eric Anholtd70d6052009-10-06 12:40:42 -070082
83 /** Buffer manager context associated with this buffer object */
84 drm_intel_bufmgr *bufmgr;
85
86 /**
87 * MM-specific handle for accessing object
88 */
89 int handle;
Kenneth Graunkeedf17db2014-01-13 14:14:36 -080090
91 /**
92 * Last seen card virtual address (offset from the beginning of the
93 * aperture) for the object. This should be used to fill relocation
94 * entries when calling drm_intel_bo_emit_reloc()
95 */
96 uint64_t offset64;
Eric Anholtc4857422008-06-03 10:20:49 -070097};
98
Eric Anholt4db16a92011-10-11 15:59:03 -070099enum aub_dump_bmp_format {
100 AUB_DUMP_BMP_FORMAT_8BIT = 1,
101 AUB_DUMP_BMP_FORMAT_ARGB_4444 = 4,
102 AUB_DUMP_BMP_FORMAT_ARGB_0888 = 6,
103 AUB_DUMP_BMP_FORMAT_ARGB_8888 = 7,
104};
105
Paul Berryda02f722012-05-04 12:41:00 -0700106typedef struct _drm_intel_aub_annotation {
107 uint32_t type;
108 uint32_t subtype;
109 uint32_t ending_offset;
110} drm_intel_aub_annotation;
111
Jesse Barnes3a7dfcd2009-10-06 14:34:06 -0700112#define BO_ALLOC_FOR_RENDER (1<<0)
113
Eric Anholt4b982642008-10-30 09:33:07 -0700114drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
115 unsigned long size, unsigned int alignment);
Eric Anholt72abe982009-02-18 13:06:35 -0800116drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
117 const char *name,
118 unsigned long size,
119 unsigned int alignment);
Tvrtko Ursulinae8edc72014-06-19 15:52:03 +0100120drm_intel_bo *drm_intel_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
121 const char *name,
122 void *addr, uint32_t tiling_mode,
123 uint32_t stride, unsigned long size,
124 unsigned long flags);
Jesse Barnes3a7dfcd2009-10-06 14:34:06 -0700125drm_intel_bo *drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr,
126 const char *name,
127 int x, int y, int cpp,
128 uint32_t *tiling_mode,
129 unsigned long *pitch,
130 unsigned long flags);
Eric Anholt4b982642008-10-30 09:33:07 -0700131void drm_intel_bo_reference(drm_intel_bo *bo);
132void drm_intel_bo_unreference(drm_intel_bo *bo);
133int drm_intel_bo_map(drm_intel_bo *bo, int write_enable);
134int drm_intel_bo_unmap(drm_intel_bo *bo);
Eric Anholt738e36a2008-09-05 10:35:32 +0100135
Eric Anholt4b982642008-10-30 09:33:07 -0700136int drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
Eric Anholtd70d6052009-10-06 12:40:42 -0700137 unsigned long size, const void *data);
Eric Anholt4b982642008-10-30 09:33:07 -0700138int drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
Eric Anholtd70d6052009-10-06 12:40:42 -0700139 unsigned long size, void *data);
Eric Anholt4b982642008-10-30 09:33:07 -0700140void drm_intel_bo_wait_rendering(drm_intel_bo *bo);
Eric Anholt738e36a2008-09-05 10:35:32 +0100141
Eric Anholt4b982642008-10-30 09:33:07 -0700142void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug);
143void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr);
144int drm_intel_bo_exec(drm_intel_bo *bo, int used,
Chris Wilson1443bea2010-11-25 16:59:20 +0000145 struct drm_clip_rect *cliprects, int num_cliprects, int DR4);
Zou Nan hai66375fd2010-06-02 10:07:37 +0800146int drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
Chris Wilson1443bea2010-11-25 16:59:20 +0000147 struct drm_clip_rect *cliprects, int num_cliprects, int DR4,
Chris Wilson0184bb12010-12-19 13:01:15 +0000148 unsigned int flags);
Eric Anholtd70d6052009-10-06 12:40:42 -0700149int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count);
Eric Anholt738e36a2008-09-05 10:35:32 +0100150
Eric Anholt4b982642008-10-30 09:33:07 -0700151int drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
152 drm_intel_bo *target_bo, uint32_t target_offset,
153 uint32_t read_domains, uint32_t write_domain);
Jesse Barnesb5096402009-09-15 11:02:58 -0700154int drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
155 drm_intel_bo *target_bo,
156 uint32_t target_offset,
157 uint32_t read_domains, uint32_t write_domain);
Eric Anholt4b982642008-10-30 09:33:07 -0700158int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment);
159int drm_intel_bo_unpin(drm_intel_bo *bo);
Eric Anholtd70d6052009-10-06 12:40:42 -0700160int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
Eric Anholt4b982642008-10-30 09:33:07 -0700161 uint32_t stride);
Eric Anholtd70d6052009-10-06 12:40:42 -0700162int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
163 uint32_t * swizzle_mode);
164int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name);
Eric Anholt8214a652009-08-27 18:32:07 -0700165int drm_intel_bo_busy(drm_intel_bo *bo);
Chris Wilson83a35b62009-11-11 13:04:38 +0000166int drm_intel_bo_madvise(drm_intel_bo *bo, int madv);
Eric Anholt738e36a2008-09-05 10:35:32 +0100167
Keith Packard5b5ce302009-05-11 13:42:12 -0700168int drm_intel_bo_disable_reuse(drm_intel_bo *bo);
Chris Wilson07e75892010-05-11 08:54:06 +0100169int drm_intel_bo_is_reusable(drm_intel_bo *bo);
Eric Anholt769b1052009-10-01 19:09:26 -0700170int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo);
Keith Packard5b5ce302009-05-11 13:42:12 -0700171
Eric Anholt4b982642008-10-30 09:33:07 -0700172/* drm_intel_bufmgr_gem.c */
173drm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size);
174drm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
175 const char *name,
176 unsigned int handle);
177void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr);
Jesse Barnesb5096402009-09-15 11:02:58 -0700178void drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr);
Chris Wilsone4b60f22011-12-05 21:29:05 +0000179void drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr,
180 int limit);
Eric Anholt99c73372012-02-10 04:12:15 -0800181int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo);
Jesse Barnes276c07d2008-11-13 13:52:04 -0800182int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo);
Jesse Barnese2d7dfb2009-03-26 16:43:00 -0700183int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo);
Eric Anholt99c73372012-02-10 04:12:15 -0800184
Eric Anholt515cea62011-10-21 18:48:20 -0700185int drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo);
186void drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start);
Eric Anholt6fb1ad72008-11-13 11:44:22 -0800187void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable);
Eric Anholtc4857422008-06-03 10:20:49 -0700188
Damien Lespiaufbd106a2013-02-20 12:11:49 +0000189void
190drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
191 const char *filename);
Eric Anholt4db16a92011-10-11 15:59:03 -0700192void drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable);
193void drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
194 int x1, int y1, int width, int height,
195 enum aub_dump_bmp_format format,
196 int pitch, int offset);
Paul Berryda02f722012-05-04 12:41:00 -0700197void
198drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
199 drm_intel_aub_annotation *annotations,
200 unsigned count);
Eric Anholt4db16a92011-10-11 15:59:03 -0700201
Carl Worthafd245d2009-04-29 14:43:55 -0700202int drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id);
203
Chris Wilson9d776032011-06-04 12:47:19 +0100204int drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total);
Kenneth Graunke6e642db2011-10-11 14:38:34 -0700205int drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr);
Ben Widawsky971c0802012-06-05 11:30:48 -0700206int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns);
Chris Wilson9d776032011-06-04 12:47:19 +0100207
Ben Widawsky3ed38712012-03-18 18:28:28 -0700208drm_intel_context *drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr);
209void drm_intel_gem_context_destroy(drm_intel_context *ctx);
210int drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
211 int used, unsigned int flags);
212
Dave Airlieff65de92012-07-15 00:22:46 +0000213int drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd);
214drm_intel_bo *drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr,
215 int prime_fd, int size);
216
Eric Anholt4b982642008-10-30 09:33:07 -0700217/* drm_intel_bufmgr_fake.c */
218drm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd,
219 unsigned long low_offset,
220 void *low_virtual,
221 unsigned long size,
Eric Anholtd70d6052009-10-06 12:40:42 -0700222 volatile unsigned int
223 *last_dispatch);
Eric Anholt4b982642008-10-30 09:33:07 -0700224void drm_intel_bufmgr_fake_set_last_dispatch(drm_intel_bufmgr *bufmgr,
Eric Anholtd70d6052009-10-06 12:40:42 -0700225 volatile unsigned int
226 *last_dispatch);
Eric Anholt4b982642008-10-30 09:33:07 -0700227void drm_intel_bufmgr_fake_set_exec_callback(drm_intel_bufmgr *bufmgr,
Eric Anholtd70d6052009-10-06 12:40:42 -0700228 int (*exec) (drm_intel_bo *bo,
229 unsigned int used,
230 void *priv),
Eric Anholt4b982642008-10-30 09:33:07 -0700231 void *priv);
232void drm_intel_bufmgr_fake_set_fence_callback(drm_intel_bufmgr *bufmgr,
Eric Anholtd70d6052009-10-06 12:40:42 -0700233 unsigned int (*emit) (void *priv),
234 void (*wait) (unsigned int fence,
235 void *priv),
Eric Anholt4b982642008-10-30 09:33:07 -0700236 void *priv);
237drm_intel_bo *drm_intel_bo_fake_alloc_static(drm_intel_bufmgr *bufmgr,
238 const char *name,
Eric Anholtd70d6052009-10-06 12:40:42 -0700239 unsigned long offset,
Eric Anholt23287f02010-08-26 15:39:28 -0700240 unsigned long size, void *virt);
Eric Anholt4b982642008-10-30 09:33:07 -0700241void drm_intel_bo_fake_disable_backing_store(drm_intel_bo *bo,
Eric Anholtd70d6052009-10-06 12:40:42 -0700242 void (*invalidate_cb) (drm_intel_bo
243 * bo,
244 void *ptr),
Eric Anholt4b982642008-10-30 09:33:07 -0700245 void *ptr);
Eric Anholt738e36a2008-09-05 10:35:32 +0100246
Eric Anholt4b982642008-10-30 09:33:07 -0700247void drm_intel_bufmgr_fake_contended_lock_take(drm_intel_bufmgr *bufmgr);
248void drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr);
249
Eric Anholt71066ab2011-12-20 13:06:16 -0800250struct drm_intel_decode *drm_intel_decode_context_alloc(uint32_t devid);
251void drm_intel_decode_context_free(struct drm_intel_decode *ctx);
252void drm_intel_decode_set_batch_pointer(struct drm_intel_decode *ctx,
253 void *data, uint32_t hw_offset,
254 int count);
255void drm_intel_decode_set_dump_past_end(struct drm_intel_decode *ctx,
256 int dump_past_end);
257void drm_intel_decode_set_head_tail(struct drm_intel_decode *ctx,
258 uint32_t head, uint32_t tail);
Eric Anholtea33a232012-01-03 13:05:57 -0800259void drm_intel_decode_set_output_file(struct drm_intel_decode *ctx, FILE *out);
Eric Anholt71066ab2011-12-20 13:06:16 -0800260void drm_intel_decode(struct drm_intel_decode *ctx);
261
Eric Anholt2607dad2012-08-01 16:43:16 -0700262int drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
263 uint32_t offset,
264 uint64_t *result);
Eric Anholt71066ab2011-12-20 13:06:16 -0800265
Ian Romanick5a41b022013-11-15 10:24:43 -0800266int drm_intel_get_reset_stats(drm_intel_context *ctx,
267 uint32_t *reset_count,
268 uint32_t *active,
269 uint32_t *pending);
270
Jeff McGeed556e062015-03-09 16:13:03 -0700271int drm_intel_get_subslice_total(int fd, unsigned int *subslice_total);
272int drm_intel_get_eu_total(int fd, unsigned int *eu_total);
273
Eric Anholt4b982642008-10-30 09:33:07 -0700274/** @{ Compatibility defines to keep old code building despite the symbol rename
275 * from dri_* to drm_intel_*
276 */
277#define dri_bo drm_intel_bo
278#define dri_bufmgr drm_intel_bufmgr
279#define dri_bo_alloc drm_intel_bo_alloc
280#define dri_bo_reference drm_intel_bo_reference
281#define dri_bo_unreference drm_intel_bo_unreference
282#define dri_bo_map drm_intel_bo_map
283#define dri_bo_unmap drm_intel_bo_unmap
284#define dri_bo_subdata drm_intel_bo_subdata
285#define dri_bo_get_subdata drm_intel_bo_get_subdata
286#define dri_bo_wait_rendering drm_intel_bo_wait_rendering
287#define dri_bufmgr_set_debug drm_intel_bufmgr_set_debug
288#define dri_bufmgr_destroy drm_intel_bufmgr_destroy
289#define dri_bo_exec drm_intel_bo_exec
290#define dri_bufmgr_check_aperture_space drm_intel_bufmgr_check_aperture_space
291#define dri_bo_emit_reloc(reloc_bo, read, write, target_offset, \
292 reloc_offset, target_bo) \
293 drm_intel_bo_emit_reloc(reloc_bo, reloc_offset, \
Eric Anholtd70d6052009-10-06 12:40:42 -0700294 target_bo, target_offset, \
295 read, write);
Eric Anholt4b982642008-10-30 09:33:07 -0700296#define dri_bo_pin drm_intel_bo_pin
297#define dri_bo_unpin drm_intel_bo_unpin
298#define dri_bo_get_tiling drm_intel_bo_get_tiling
299#define dri_bo_set_tiling(bo, mode) drm_intel_bo_set_tiling(bo, mode, 0)
300#define dri_bo_flink drm_intel_bo_flink
301#define intel_bufmgr_gem_init drm_intel_bufmgr_gem_init
302#define intel_bo_gem_create_from_name drm_intel_bo_gem_create_from_name
303#define intel_bufmgr_gem_enable_reuse drm_intel_bufmgr_gem_enable_reuse
304#define intel_bufmgr_fake_init drm_intel_bufmgr_fake_init
305#define intel_bufmgr_fake_set_last_dispatch drm_intel_bufmgr_fake_set_last_dispatch
306#define intel_bufmgr_fake_set_exec_callback drm_intel_bufmgr_fake_set_exec_callback
307#define intel_bufmgr_fake_set_fence_callback drm_intel_bufmgr_fake_set_fence_callback
308#define intel_bo_fake_alloc_static drm_intel_bo_fake_alloc_static
309#define intel_bo_fake_disable_backing_store drm_intel_bo_fake_disable_backing_store
310#define intel_bufmgr_fake_contended_lock_take drm_intel_bufmgr_fake_contended_lock_take
311#define intel_bufmgr_fake_evict_all drm_intel_bufmgr_fake_evict_all
312
313/** @{ */
Eric Anholtc4857422008-06-03 10:20:49 -0700314
Tapani Pällif1468e82015-08-07 10:37:57 +0300315#if defined(__cplusplus)
316}
317#endif
318
Eric Anholt738e36a2008-09-05 10:35:32 +0100319#endif /* INTEL_BUFMGR_H */