Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 1 | //===-- EmulateInstruction.h ------------------------------------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | |
Greg Clayton | 17f5afe | 2011-02-05 02:56:16 +0000 | [diff] [blame] | 10 | #include "lldb/Core/EmulateInstruction.h" |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 11 | |
Greg Clayton | 888a733 | 2011-04-26 04:39:08 +0000 | [diff] [blame^] | 12 | #include "lldb/Core/Address.h" |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 13 | #include "lldb/Core/DataBufferHeap.h" |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 14 | #include "lldb/Core/DataExtractor.h" |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 15 | #include "lldb/Core/Error.h" |
Greg Clayton | 52fd984 | 2011-02-02 02:24:04 +0000 | [diff] [blame] | 16 | #include "lldb/Core/PluginManager.h" |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 17 | #include "lldb/Core/StreamString.h" |
Greg Clayton | cd54803 | 2011-02-01 01:31:41 +0000 | [diff] [blame] | 18 | #include "lldb/Host/Endian.h" |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 19 | #include "lldb/Target/Process.h" |
| 20 | #include "lldb/Target/RegisterContext.h" |
Greg Clayton | 888a733 | 2011-04-26 04:39:08 +0000 | [diff] [blame^] | 21 | #include "lldb/Target/Target.h" |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 22 | #include "lldb/Target/Thread.h" |
| 23 | |
| 24 | #include "Plugins/Instruction/ARM/EmulateInstructionARM.h" |
| 25 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 26 | using namespace lldb; |
| 27 | using namespace lldb_private; |
| 28 | |
Greg Clayton | 52fd984 | 2011-02-02 02:24:04 +0000 | [diff] [blame] | 29 | EmulateInstruction* |
Greg Clayton | 888a733 | 2011-04-26 04:39:08 +0000 | [diff] [blame^] | 30 | EmulateInstruction::FindPlugin (const ArchSpec &arch, InstructionType supported_inst_type, const char *plugin_name) |
Greg Clayton | 52fd984 | 2011-02-02 02:24:04 +0000 | [diff] [blame] | 31 | { |
| 32 | EmulateInstructionCreateInstance create_callback = NULL; |
| 33 | if (plugin_name) |
| 34 | { |
| 35 | create_callback = PluginManager::GetEmulateInstructionCreateCallbackForPluginName (plugin_name); |
| 36 | if (create_callback) |
| 37 | { |
Greg Clayton | 888a733 | 2011-04-26 04:39:08 +0000 | [diff] [blame^] | 38 | EmulateInstruction *emulate_insn_ptr = create_callback(arch, supported_inst_type); |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 39 | if (emulate_insn_ptr) |
| 40 | return emulate_insn_ptr; |
Greg Clayton | 52fd984 | 2011-02-02 02:24:04 +0000 | [diff] [blame] | 41 | } |
| 42 | } |
| 43 | else |
| 44 | { |
| 45 | for (uint32_t idx = 0; (create_callback = PluginManager::GetEmulateInstructionCreateCallbackAtIndex(idx)) != NULL; ++idx) |
| 46 | { |
Greg Clayton | 888a733 | 2011-04-26 04:39:08 +0000 | [diff] [blame^] | 47 | EmulateInstruction *emulate_insn_ptr = create_callback(arch, supported_inst_type); |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 48 | if (emulate_insn_ptr) |
| 49 | return emulate_insn_ptr; |
Greg Clayton | 52fd984 | 2011-02-02 02:24:04 +0000 | [diff] [blame] | 50 | } |
| 51 | } |
| 52 | return NULL; |
| 53 | } |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 54 | |
Greg Clayton | 888a733 | 2011-04-26 04:39:08 +0000 | [diff] [blame^] | 55 | EmulateInstruction::EmulateInstruction (const ArchSpec &arch) : |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 56 | m_arch (arch), |
| 57 | m_baton (NULL), |
| 58 | m_read_mem_callback (&ReadMemoryDefault), |
| 59 | m_write_mem_callback (&WriteMemoryDefault), |
| 60 | m_read_reg_callback (&ReadRegisterDefault), |
| 61 | m_write_reg_callback (&WriteRegisterDefault), |
Greg Clayton | 888a733 | 2011-04-26 04:39:08 +0000 | [diff] [blame^] | 62 | m_opcode_pc (LLDB_INVALID_ADDRESS) |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 63 | { |
| 64 | ::memset (&m_opcode, 0, sizeof (m_opcode)); |
| 65 | } |
| 66 | |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 67 | uint64_t |
| 68 | EmulateInstruction::ReadRegisterUnsigned (uint32_t reg_kind, uint32_t reg_num, uint64_t fail_value, bool *success_ptr) |
| 69 | { |
| 70 | uint64_t uval64 = 0; |
Greg Clayton | 888a733 | 2011-04-26 04:39:08 +0000 | [diff] [blame^] | 71 | bool success = m_read_reg_callback (this, m_baton, reg_kind, reg_num, uval64); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 72 | if (success_ptr) |
| 73 | *success_ptr = success; |
| 74 | if (!success) |
| 75 | uval64 = fail_value; |
| 76 | return uval64; |
| 77 | } |
| 78 | |
| 79 | bool |
| 80 | EmulateInstruction::WriteRegisterUnsigned (const Context &context, uint32_t reg_kind, uint32_t reg_num, uint64_t reg_value) |
| 81 | { |
Greg Clayton | 888a733 | 2011-04-26 04:39:08 +0000 | [diff] [blame^] | 82 | return m_write_reg_callback (this, m_baton, context, reg_kind, reg_num, reg_value); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 83 | } |
| 84 | |
| 85 | uint64_t |
| 86 | EmulateInstruction::ReadMemoryUnsigned (const Context &context, lldb::addr_t addr, size_t byte_size, uint64_t fail_value, bool *success_ptr) |
| 87 | { |
| 88 | uint64_t uval64 = 0; |
| 89 | bool success = false; |
| 90 | if (byte_size <= 8) |
| 91 | { |
| 92 | uint8_t buf[sizeof(uint64_t)]; |
Greg Clayton | 888a733 | 2011-04-26 04:39:08 +0000 | [diff] [blame^] | 93 | size_t bytes_read = m_read_mem_callback (this, m_baton, context, addr, buf, byte_size); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 94 | if (bytes_read == byte_size) |
| 95 | { |
| 96 | uint32_t offset = 0; |
Greg Clayton | 888a733 | 2011-04-26 04:39:08 +0000 | [diff] [blame^] | 97 | DataExtractor data (buf, byte_size, GetByteOrder(), GetAddressByteSize()); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 98 | uval64 = data.GetMaxU64 (&offset, byte_size); |
| 99 | success = true; |
| 100 | } |
| 101 | } |
| 102 | |
| 103 | if (success_ptr) |
| 104 | *success_ptr = success; |
| 105 | |
| 106 | if (!success) |
| 107 | uval64 = fail_value; |
| 108 | return uval64; |
| 109 | } |
| 110 | |
| 111 | |
| 112 | bool |
| 113 | EmulateInstruction::WriteMemoryUnsigned (const Context &context, |
| 114 | lldb::addr_t addr, |
| 115 | uint64_t uval, |
| 116 | size_t uval_byte_size) |
| 117 | { |
| 118 | StreamString strm(Stream::eBinary, GetAddressByteSize(), GetByteOrder()); |
| 119 | strm.PutMaxHex64 (uval, uval_byte_size); |
| 120 | |
Greg Clayton | 888a733 | 2011-04-26 04:39:08 +0000 | [diff] [blame^] | 121 | size_t bytes_written = m_write_mem_callback (this, m_baton, context, addr, strm.GetData(), uval_byte_size); |
Greg Clayton | 64c8443 | 2011-01-21 22:02:52 +0000 | [diff] [blame] | 122 | if (bytes_written == uval_byte_size) |
| 123 | return true; |
| 124 | return false; |
| 125 | } |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 126 | |
| 127 | |
| 128 | void |
| 129 | EmulateInstruction::SetBaton (void *baton) |
| 130 | { |
| 131 | m_baton = baton; |
| 132 | } |
| 133 | |
| 134 | void |
| 135 | EmulateInstruction::SetCallbacks (ReadMemory read_mem_callback, |
| 136 | WriteMemory write_mem_callback, |
| 137 | ReadRegister read_reg_callback, |
| 138 | WriteRegister write_reg_callback) |
| 139 | { |
| 140 | m_read_mem_callback = read_mem_callback; |
| 141 | m_write_mem_callback = write_mem_callback; |
| 142 | m_read_reg_callback = read_reg_callback; |
| 143 | m_write_reg_callback = write_reg_callback; |
| 144 | } |
| 145 | |
| 146 | void |
| 147 | EmulateInstruction::SetReadMemCallback (ReadMemory read_mem_callback) |
| 148 | { |
| 149 | m_read_mem_callback = read_mem_callback; |
| 150 | } |
| 151 | |
| 152 | |
| 153 | void |
| 154 | EmulateInstruction::SetWriteMemCallback (WriteMemory write_mem_callback) |
| 155 | { |
| 156 | m_write_mem_callback = write_mem_callback; |
| 157 | } |
| 158 | |
| 159 | |
| 160 | void |
| 161 | EmulateInstruction::SetReadRegCallback (ReadRegister read_reg_callback) |
| 162 | { |
| 163 | m_read_reg_callback = read_reg_callback; |
| 164 | } |
| 165 | |
| 166 | |
| 167 | void |
| 168 | EmulateInstruction::SetWriteRegCallback (WriteRegister write_reg_callback) |
| 169 | { |
| 170 | m_write_reg_callback = write_reg_callback; |
| 171 | } |
| 172 | |
| 173 | |
| 174 | |
| 175 | // |
| 176 | // Read & Write Memory and Registers callback functions. |
| 177 | // |
| 178 | |
| 179 | size_t |
Greg Clayton | 888a733 | 2011-04-26 04:39:08 +0000 | [diff] [blame^] | 180 | EmulateInstruction::ReadMemoryFrame (EmulateInstruction *instruction, |
| 181 | void *baton, |
Caroline Tice | ea69d6d | 2011-04-05 20:18:48 +0000 | [diff] [blame] | 182 | const Context &context, |
| 183 | lldb::addr_t addr, |
| 184 | void *dst, |
| 185 | size_t length) |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 186 | { |
Caroline Tice | ea69d6d | 2011-04-05 20:18:48 +0000 | [diff] [blame] | 187 | if (!baton) |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 188 | return 0; |
| 189 | |
Caroline Tice | ea69d6d | 2011-04-05 20:18:48 +0000 | [diff] [blame] | 190 | |
| 191 | StackFrame *frame = (StackFrame *) baton; |
| 192 | |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 193 | DataBufferSP data_sp (new DataBufferHeap (length, '\0')); |
| 194 | Error error; |
| 195 | |
Caroline Tice | ea69d6d | 2011-04-05 20:18:48 +0000 | [diff] [blame] | 196 | size_t bytes_read = frame->GetThread().GetProcess().ReadMemory (addr, data_sp->GetBytes(), data_sp->GetByteSize(), |
| 197 | error); |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 198 | |
| 199 | if (bytes_read > 0) |
| 200 | ((DataBufferHeap *) data_sp.get())->CopyData (dst, length); |
| 201 | |
| 202 | return bytes_read; |
| 203 | } |
| 204 | |
| 205 | size_t |
Greg Clayton | 888a733 | 2011-04-26 04:39:08 +0000 | [diff] [blame^] | 206 | EmulateInstruction::WriteMemoryFrame (EmulateInstruction *instruction, |
| 207 | void *baton, |
Caroline Tice | ea69d6d | 2011-04-05 20:18:48 +0000 | [diff] [blame] | 208 | const Context &context, |
| 209 | lldb::addr_t addr, |
| 210 | const void *dst, |
| 211 | size_t length) |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 212 | { |
Caroline Tice | ea69d6d | 2011-04-05 20:18:48 +0000 | [diff] [blame] | 213 | if (!baton) |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 214 | return 0; |
| 215 | |
Caroline Tice | ea69d6d | 2011-04-05 20:18:48 +0000 | [diff] [blame] | 216 | StackFrame *frame = (StackFrame *) baton; |
| 217 | |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 218 | lldb::DataBufferSP data_sp (new DataBufferHeap (dst, length)); |
| 219 | if (data_sp) |
| 220 | { |
| 221 | length = data_sp->GetByteSize(); |
| 222 | if (length > 0) |
| 223 | { |
| 224 | Error error; |
Caroline Tice | ea69d6d | 2011-04-05 20:18:48 +0000 | [diff] [blame] | 225 | size_t bytes_written = frame->GetThread().GetProcess().WriteMemory (addr, data_sp->GetBytes(), length, |
| 226 | error); |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 227 | |
| 228 | return bytes_written; |
| 229 | } |
| 230 | } |
| 231 | |
| 232 | return 0; |
| 233 | } |
| 234 | |
| 235 | bool |
Greg Clayton | 888a733 | 2011-04-26 04:39:08 +0000 | [diff] [blame^] | 236 | EmulateInstruction::ReadRegisterFrame (EmulateInstruction *instruction, |
| 237 | void *baton, |
Caroline Tice | ea69d6d | 2011-04-05 20:18:48 +0000 | [diff] [blame] | 238 | uint32_t reg_kind, |
| 239 | uint32_t reg_num, |
| 240 | uint64_t ®_value) |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 241 | { |
Caroline Tice | ea69d6d | 2011-04-05 20:18:48 +0000 | [diff] [blame] | 242 | if (!baton) |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 243 | return false; |
| 244 | |
Caroline Tice | ea69d6d | 2011-04-05 20:18:48 +0000 | [diff] [blame] | 245 | StackFrame *frame = (StackFrame *) baton; |
| 246 | RegisterContext *reg_context = frame->GetRegisterContext().get(); |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 247 | Scalar value; |
| 248 | |
Caroline Tice | 21f0d4b | 2011-04-06 23:30:18 +0000 | [diff] [blame] | 249 | uint32_t internal_reg_num = reg_context->ConvertRegisterKindToRegisterNumber (reg_kind, reg_num); |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 250 | |
Caroline Tice | 21f0d4b | 2011-04-06 23:30:18 +0000 | [diff] [blame] | 251 | if (internal_reg_num == LLDB_INVALID_REGNUM) |
| 252 | return false; |
| 253 | |
| 254 | if (reg_context->ReadRegisterValue (internal_reg_num, value)) |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 255 | { |
| 256 | reg_value = value.GetRawBits64 (0); |
| 257 | return true; |
| 258 | } |
| 259 | |
| 260 | return false; |
| 261 | } |
| 262 | |
| 263 | bool |
Greg Clayton | 888a733 | 2011-04-26 04:39:08 +0000 | [diff] [blame^] | 264 | EmulateInstruction::WriteRegisterFrame (EmulateInstruction *instruction, |
| 265 | void *baton, |
Caroline Tice | ea69d6d | 2011-04-05 20:18:48 +0000 | [diff] [blame] | 266 | const Context &context, |
| 267 | uint32_t reg_kind, |
| 268 | uint32_t reg_num, |
| 269 | uint64_t reg_value) |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 270 | { |
Caroline Tice | ea69d6d | 2011-04-05 20:18:48 +0000 | [diff] [blame] | 271 | if (!baton) |
| 272 | return false; |
| 273 | |
| 274 | StackFrame *frame = (StackFrame *) baton; |
| 275 | RegisterContext *reg_context = frame->GetRegisterContext().get(); |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 276 | Scalar value (reg_value); |
| 277 | |
Caroline Tice | 21f0d4b | 2011-04-06 23:30:18 +0000 | [diff] [blame] | 278 | uint32_t internal_reg_num = reg_context->ConvertRegisterKindToRegisterNumber (reg_kind, reg_num); |
| 279 | if (internal_reg_num != LLDB_INVALID_REGNUM) |
| 280 | return reg_context->WriteRegisterValue (internal_reg_num, value); |
| 281 | else |
| 282 | return false; |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 283 | } |
| 284 | |
| 285 | size_t |
Greg Clayton | 888a733 | 2011-04-26 04:39:08 +0000 | [diff] [blame^] | 286 | EmulateInstruction::ReadMemoryDefault (EmulateInstruction *instruction, |
| 287 | void *baton, |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 288 | const Context &context, |
| 289 | lldb::addr_t addr, |
| 290 | void *dst, |
| 291 | size_t length) |
| 292 | { |
| 293 | PrintContext ("Read from memory", context); |
Greg Clayton | f15996e | 2011-04-07 22:46:35 +0000 | [diff] [blame] | 294 | fprintf (stdout, " Read from Memory (address = %p, length = %d)\n",(void *) addr, (uint32_t) length); |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 295 | |
| 296 | *((uint64_t *) dst) = 0xdeadbeef; |
| 297 | return length; |
| 298 | } |
| 299 | |
| 300 | size_t |
Greg Clayton | 888a733 | 2011-04-26 04:39:08 +0000 | [diff] [blame^] | 301 | EmulateInstruction::WriteMemoryDefault (EmulateInstruction *instruction, |
| 302 | void *baton, |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 303 | const Context &context, |
| 304 | lldb::addr_t addr, |
| 305 | const void *dst, |
| 306 | size_t length) |
| 307 | { |
| 308 | PrintContext ("Write to memory", context); |
Greg Clayton | f15996e | 2011-04-07 22:46:35 +0000 | [diff] [blame] | 309 | fprintf (stdout, " Write to Memory (address = %p, length = %d)\n", (void *) addr, (uint32_t) length); |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 310 | return length; |
| 311 | } |
| 312 | |
| 313 | bool |
Greg Clayton | 888a733 | 2011-04-26 04:39:08 +0000 | [diff] [blame^] | 314 | EmulateInstruction::ReadRegisterDefault (EmulateInstruction *instruction, |
| 315 | void *baton, |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 316 | uint32_t reg_kind, |
| 317 | uint32_t reg_num, |
| 318 | uint64_t ®_value) |
| 319 | { |
| 320 | std::string reg_name; |
| 321 | TranslateRegister (reg_kind, reg_num, reg_name); |
| 322 | fprintf (stdout, " Read Register (%s)\n", reg_name.c_str()); |
| 323 | |
| 324 | reg_value = 24; |
| 325 | return true; |
| 326 | } |
| 327 | |
| 328 | bool |
Greg Clayton | 888a733 | 2011-04-26 04:39:08 +0000 | [diff] [blame^] | 329 | EmulateInstruction::WriteRegisterDefault (EmulateInstruction *instruction, |
| 330 | void *baton, |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 331 | const Context &context, |
| 332 | uint32_t reg_kind, |
| 333 | uint32_t reg_num, |
| 334 | uint64_t reg_value) |
| 335 | { |
| 336 | PrintContext ("Write to register", context); |
| 337 | std::string reg_name; |
| 338 | TranslateRegister (reg_kind, reg_num, reg_name); |
| 339 | fprintf (stdout, " Write to Register (%s), value = 0x%llx\n", reg_name.c_str(), reg_value); |
| 340 | return true; |
| 341 | } |
| 342 | |
| 343 | void |
| 344 | EmulateInstruction::PrintContext (const char *context_type, const Context &context) |
| 345 | { |
| 346 | switch (context.type) |
| 347 | { |
| 348 | case eContextReadOpcode: |
| 349 | fprintf (stdout, " %s context: Reading an Opcode\n", context_type); |
| 350 | break; |
| 351 | |
| 352 | case eContextImmediate: |
| 353 | fprintf (stdout, " %s context: Immediate\n", context_type); |
| 354 | break; |
| 355 | |
| 356 | case eContextPushRegisterOnStack: |
| 357 | fprintf (stdout, " %s context: Pushing a register onto the stack.\n", context_type); |
| 358 | break; |
| 359 | |
| 360 | case eContextPopRegisterOffStack: |
| 361 | fprintf (stdout, " %s context: Popping a register off the stack.\n", context_type); |
| 362 | break; |
| 363 | |
| 364 | case eContextAdjustStackPointer: |
| 365 | fprintf (stdout, " %s context: Adjusting the stack pointer.\n", context_type); |
| 366 | break; |
| 367 | |
| 368 | case eContextAdjustBaseRegister: |
| 369 | fprintf (stdout, " %s context: Adjusting (writing value back to) a base register.\n", context_type); |
| 370 | break; |
| 371 | |
| 372 | case eContextRegisterPlusOffset: |
| 373 | fprintf (stdout, " %s context: Register plus offset\n", context_type); |
| 374 | break; |
| 375 | |
| 376 | case eContextRegisterStore: |
| 377 | fprintf (stdout, " %s context: Storing a register.\n", context_type); |
| 378 | break; |
| 379 | |
| 380 | case eContextRegisterLoad: |
| 381 | fprintf (stdout, " %s context: Loading a register.\n", context_type); |
| 382 | break; |
| 383 | |
| 384 | case eContextRelativeBranchImmediate: |
| 385 | fprintf (stdout, " %s context: Relative branch immediate\n", context_type); |
| 386 | break; |
| 387 | |
| 388 | case eContextAbsoluteBranchRegister: |
| 389 | fprintf (stdout, " %s context: Absolute branch register\n", context_type); |
| 390 | break; |
| 391 | |
| 392 | case eContextSupervisorCall: |
| 393 | fprintf (stdout, " %s context: Performing a supervisor call.\n", context_type); |
| 394 | break; |
| 395 | |
| 396 | case eContextTableBranchReadMemory: |
| 397 | fprintf (stdout, " %s context: Table branch read memory\n", context_type); |
| 398 | break; |
| 399 | |
| 400 | case eContextWriteRegisterRandomBits: |
| 401 | fprintf (stdout, " %s context: Write random bits to a register\n", context_type); |
| 402 | break; |
| 403 | |
| 404 | case eContextWriteMemoryRandomBits: |
| 405 | fprintf (stdout, " %s context: Write random bits to a memory address\n", context_type); |
| 406 | break; |
| 407 | |
| 408 | case eContextMultiplication: |
| 409 | fprintf (stdout, " %s context: Performing a multiplication\n", context_type); |
| 410 | break; |
| 411 | |
| 412 | case eContextAddition: |
| 413 | fprintf (stdout, " %s context: Performing an addition\n", context_type); |
| 414 | break; |
| 415 | |
| 416 | case eContextReturnFromException: |
| 417 | fprintf (stdout, " %s context: Returning from an exception\n", context_type); |
| 418 | break; |
| 419 | |
| 420 | default: |
| 421 | fprintf (stdout, " %s context: Unrecognized context.\n", context_type); |
| 422 | break; |
| 423 | } |
| 424 | |
| 425 | switch (context.info_type) |
| 426 | { |
| 427 | case eInfoTypeRegisterPlusOffset: |
| 428 | { |
| 429 | std::string reg_name; |
| 430 | TranslateRegister (context.info.RegisterPlusOffset.reg.kind, |
| 431 | context.info.RegisterPlusOffset.reg.num, |
| 432 | reg_name); |
| 433 | fprintf (stdout, " Info type: Register plus offset (%s +/- %lld)\n", reg_name.c_str(), |
| 434 | context.info.RegisterPlusOffset.signed_offset); |
| 435 | } |
| 436 | break; |
| 437 | case eInfoTypeRegisterPlusIndirectOffset: |
| 438 | { |
| 439 | std::string base_reg_name; |
| 440 | std::string offset_reg_name; |
| 441 | TranslateRegister (context.info.RegisterPlusIndirectOffset.base_reg.kind, |
| 442 | context.info.RegisterPlusIndirectOffset.base_reg.num, |
| 443 | base_reg_name); |
| 444 | TranslateRegister (context.info.RegisterPlusIndirectOffset.offset_reg.kind, |
| 445 | context.info.RegisterPlusIndirectOffset.offset_reg.num, |
| 446 | offset_reg_name); |
| 447 | fprintf (stdout, " Info type: Register plus indirect offset (%s +/- %s)\n", |
| 448 | base_reg_name.c_str(), |
| 449 | offset_reg_name.c_str()); |
| 450 | } |
| 451 | break; |
| 452 | case eInfoTypeRegisterToRegisterPlusOffset: |
| 453 | { |
| 454 | std::string base_reg_name; |
| 455 | std::string data_reg_name; |
| 456 | TranslateRegister (context.info.RegisterToRegisterPlusOffset.base_reg.kind, |
| 457 | context.info.RegisterToRegisterPlusOffset.base_reg.num, |
| 458 | base_reg_name); |
| 459 | TranslateRegister (context.info.RegisterToRegisterPlusOffset.data_reg.kind, |
| 460 | context.info.RegisterToRegisterPlusOffset.data_reg.num, |
| 461 | data_reg_name); |
| 462 | fprintf (stdout, " Info type: Register plus offset (%s +/- %lld) and data register (%s)\n", |
| 463 | base_reg_name.c_str(), context.info.RegisterToRegisterPlusOffset.offset, |
| 464 | data_reg_name.c_str()); |
| 465 | } |
| 466 | break; |
| 467 | case eInfoTypeRegisterToRegisterPlusIndirectOffset: |
| 468 | { |
| 469 | std::string base_reg_name; |
| 470 | std::string offset_reg_name; |
| 471 | std::string data_reg_name; |
| 472 | TranslateRegister (context.info.RegisterToRegisterPlusIndirectOffset.base_reg.kind, |
| 473 | context.info.RegisterToRegisterPlusIndirectOffset.base_reg.num, |
| 474 | base_reg_name); |
| 475 | TranslateRegister (context.info.RegisterToRegisterPlusIndirectOffset.offset_reg.kind, |
| 476 | context.info.RegisterToRegisterPlusIndirectOffset.offset_reg.num, |
| 477 | offset_reg_name); |
| 478 | TranslateRegister (context.info.RegisterToRegisterPlusIndirectOffset.data_reg.kind, |
| 479 | context.info.RegisterToRegisterPlusIndirectOffset.data_reg.num, |
| 480 | data_reg_name); |
| 481 | fprintf (stdout, " Info type: Register plus indirect offset (%s +/- %s) and data register (%s)\n", |
| 482 | base_reg_name.c_str(), offset_reg_name.c_str(), data_reg_name.c_str()); |
| 483 | } |
| 484 | break; |
| 485 | |
| 486 | case eInfoTypeRegisterRegisterOperands: |
| 487 | { |
| 488 | std::string op1_reg_name; |
| 489 | std::string op2_reg_name; |
| 490 | TranslateRegister (context.info.RegisterRegisterOperands.operand1.kind, |
| 491 | context.info.RegisterRegisterOperands.operand1.num, |
| 492 | op1_reg_name); |
| 493 | TranslateRegister (context.info.RegisterRegisterOperands.operand2.kind, |
| 494 | context.info.RegisterRegisterOperands.operand2.num, |
| 495 | op2_reg_name); |
| 496 | fprintf (stdout, " Info type: Register operands for binary op (%s, %s)\n", |
| 497 | op1_reg_name.c_str(), |
| 498 | op2_reg_name.c_str()); |
| 499 | } |
| 500 | break; |
| 501 | case eInfoTypeOffset: |
| 502 | fprintf (stdout, " Info type: signed offset (%lld)\n", context.info.signed_offset); |
| 503 | break; |
| 504 | |
| 505 | case eInfoTypeRegister: |
| 506 | { |
| 507 | std::string reg_name; |
| 508 | TranslateRegister (context.info.reg.kind, context.info.reg.num, reg_name); |
| 509 | fprintf (stdout, " Info type: Register (%s)\n", reg_name.c_str()); |
| 510 | } |
| 511 | break; |
| 512 | |
| 513 | case eInfoTypeImmediate: |
| 514 | fprintf (stdout, " Info type: Immediate (%lld)\n", context.info.immediate); |
| 515 | break; |
| 516 | |
| 517 | case eInfoTypeImmediateSigned: |
| 518 | fprintf (stdout, " Info type: Signed immediate (%lld)\n", context.info.signed_immediate); |
| 519 | break; |
| 520 | |
| 521 | case eInfoTypeAddress: |
| 522 | fprintf (stdout, " Info type: Address (%p)\n", (void *) context.info.address); |
| 523 | break; |
| 524 | |
| 525 | case eInfoTypeModeAndImmediate: |
| 526 | { |
| 527 | std::string mode_name; |
| 528 | |
| 529 | if (context.info.ModeAndImmediate.mode == EmulateInstructionARM::eModeARM) |
| 530 | mode_name = "ARM"; |
| 531 | else if (context.info.ModeAndImmediate.mode == EmulateInstructionARM::eModeThumb) |
| 532 | mode_name = "Thumb"; |
| 533 | else |
| 534 | mode_name = "Unknown mode"; |
| 535 | |
| 536 | fprintf (stdout, " Info type: Mode (%s) and immediate (%d)\n", mode_name.c_str(), |
| 537 | context.info.ModeAndImmediate.data_value); |
| 538 | } |
| 539 | break; |
| 540 | |
| 541 | case eInfoTypeModeAndImmediateSigned: |
| 542 | { |
| 543 | std::string mode_name; |
| 544 | |
| 545 | if (context.info.ModeAndImmediateSigned.mode == EmulateInstructionARM::eModeARM) |
| 546 | mode_name = "ARM"; |
| 547 | else if (context.info.ModeAndImmediateSigned.mode == EmulateInstructionARM::eModeThumb) |
| 548 | mode_name = "Thumb"; |
| 549 | else |
| 550 | mode_name = "Unknown mode"; |
| 551 | |
| 552 | fprintf (stdout, " Info type: Mode (%s) and signed immediate (%d)\n", mode_name.c_str(), |
| 553 | context.info.ModeAndImmediateSigned.signed_data_value); |
| 554 | } |
| 555 | break; |
| 556 | |
| 557 | case eInfoTypeMode: |
| 558 | { |
| 559 | std::string mode_name; |
| 560 | |
| 561 | if (context.info.mode == EmulateInstructionARM::eModeARM) |
| 562 | mode_name = "ARM"; |
| 563 | else if (context.info.mode == EmulateInstructionARM::eModeThumb) |
| 564 | mode_name = "Thumb"; |
| 565 | else |
| 566 | mode_name = "Unknown mode"; |
| 567 | |
| 568 | fprintf (stdout, " Info type: Mode (%s)\n", mode_name.c_str()); |
| 569 | } |
| 570 | break; |
| 571 | |
| 572 | case eInfoTypeNoArgs: |
| 573 | fprintf (stdout, " Info type: no arguments\n"); |
| 574 | break; |
| 575 | |
| 576 | default: |
| 577 | break; |
| 578 | } |
| 579 | } |
| 580 | |
Greg Clayton | 888a733 | 2011-04-26 04:39:08 +0000 | [diff] [blame^] | 581 | bool |
| 582 | EmulateInstruction::SetInstruction (const Opcode &opcode, const Address &inst_addr, Target *target) |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 583 | { |
Greg Clayton | 888a733 | 2011-04-26 04:39:08 +0000 | [diff] [blame^] | 584 | m_opcode = opcode; |
| 585 | m_opcode_pc = LLDB_INVALID_ADDRESS; |
| 586 | if (inst_addr.IsValid()) |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 587 | { |
Greg Clayton | 888a733 | 2011-04-26 04:39:08 +0000 | [diff] [blame^] | 588 | if (target) |
| 589 | m_opcode_pc = inst_addr.GetLoadAddress (target); |
| 590 | if (m_opcode_pc == LLDB_INVALID_ADDRESS) |
| 591 | m_opcode_pc = inst_addr.GetFileAddress (); |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 592 | } |
Greg Clayton | 888a733 | 2011-04-26 04:39:08 +0000 | [diff] [blame^] | 593 | return true; |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 594 | } |
| 595 | |
| 596 | |
Greg Clayton | 888a733 | 2011-04-26 04:39:08 +0000 | [diff] [blame^] | 597 | const char * |
| 598 | EmulateInstruction::TranslateRegister (uint32_t kind, uint32_t num, std::string &name) |
| 599 | { |
| 600 | if (kind == eRegisterKindGeneric) |
| 601 | { |
| 602 | switch (num) |
| 603 | { |
| 604 | case LLDB_REGNUM_GENERIC_PC: name = "pc"; break; |
| 605 | case LLDB_REGNUM_GENERIC_SP: name = "sp"; break; |
| 606 | case LLDB_REGNUM_GENERIC_FP: name = "fp"; break; |
| 607 | case LLDB_REGNUM_GENERIC_RA: name = "ra"; break; |
| 608 | case LLDB_REGNUM_GENERIC_FLAGS: name = "flags"; break; |
| 609 | default: name.clear(); break; |
| 610 | } |
| 611 | if (!name.empty()) |
| 612 | return name.c_str(); |
| 613 | } |
| 614 | const char *kind_cstr = NULL; |
| 615 | |
| 616 | switch (kind) |
| 617 | { |
| 618 | case eRegisterKindGCC: // the register numbers seen in eh_frame |
| 619 | kind_cstr = "gcc"; |
| 620 | break; |
| 621 | |
| 622 | case eRegisterKindDWARF: // the register numbers seen DWARF |
| 623 | kind_cstr = "dwarf"; |
| 624 | break; |
| 625 | |
| 626 | case eRegisterKindGeneric: // insn ptr reg, stack ptr reg, etc not specific to any particular target |
| 627 | kind_cstr = "generic"; |
| 628 | break; |
| 629 | |
| 630 | case eRegisterKindGDB: // the register numbers gdb uses (matches stabs numbers?) |
| 631 | kind_cstr = "gdb"; |
| 632 | break; |
| 633 | |
| 634 | case eRegisterKindLLDB: // lldb's internal register numbers |
| 635 | kind_cstr = "lldb"; |
| 636 | break; |
| 637 | } |
| 638 | |
| 639 | |
| 640 | StreamString sstr; |
| 641 | sstr.Printf ("%s(%u)", kind_cstr, num); |
| 642 | name.swap (sstr.GetString()); |
| 643 | return name.c_str(); |
| 644 | } |
| 645 | |
Caroline Tice | 080bf61 | 2011-04-05 18:46:00 +0000 | [diff] [blame] | 646 | |