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Chris Lattner1c08c712005-01-07 07:47:53 +00001//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
Misha Brukmanedf128a2005-04-21 22:36:52 +00002//
Chris Lattner1c08c712005-01-07 07:47:53 +00003// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
Misha Brukmanedf128a2005-04-21 22:36:52 +00007//
Chris Lattner1c08c712005-01-07 07:47:53 +00008//===----------------------------------------------------------------------===//
9//
10// This implements the SelectionDAGISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "isel"
15#include "llvm/CodeGen/SelectionDAGISel.h"
Evan Chenga9c20912006-01-21 02:32:06 +000016#include "llvm/CodeGen/ScheduleDAG.h"
Chris Lattneradf6a962005-05-13 18:50:42 +000017#include "llvm/CallingConv.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000018#include "llvm/Constants.h"
19#include "llvm/DerivedTypes.h"
20#include "llvm/Function.h"
Chris Lattner36ce6912005-11-29 06:21:05 +000021#include "llvm/GlobalVariable.h"
Chris Lattnerce7518c2006-01-26 22:24:51 +000022#include "llvm/InlineAsm.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000023#include "llvm/Instructions.h"
24#include "llvm/Intrinsics.h"
Jim Laskey43970fe2006-03-23 18:06:46 +000025#include "llvm/IntrinsicInst.h"
Chris Lattnerb1a5a5c2005-11-16 07:22:30 +000026#include "llvm/CodeGen/IntrinsicLowering.h"
Jim Laskeyb2efb852006-01-04 22:28:25 +000027#include "llvm/CodeGen/MachineDebugInfo.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000028#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
Nate Begeman37efe672006-04-22 18:53:45 +000030#include "llvm/CodeGen/MachineJumpTableInfo.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000031#include "llvm/CodeGen/MachineInstrBuilder.h"
Jim Laskeyeb577ba2006-08-02 12:30:23 +000032#include "llvm/CodeGen/SchedulerRegistry.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000033#include "llvm/CodeGen/SelectionDAG.h"
34#include "llvm/CodeGen/SSARegMap.h"
Chris Lattnerfa577022005-09-13 19:30:54 +000035#include "llvm/Target/MRegisterInfo.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000036#include "llvm/Target/TargetData.h"
37#include "llvm/Target/TargetFrameInfo.h"
38#include "llvm/Target/TargetInstrInfo.h"
39#include "llvm/Target/TargetLowering.h"
40#include "llvm/Target/TargetMachine.h"
Vladimir Prus12472912006-05-23 13:43:15 +000041#include "llvm/Target/TargetOptions.h"
Chris Lattner495a0b52005-08-17 06:37:43 +000042#include "llvm/Transforms/Utils/BasicBlockUtils.h"
Chris Lattner7c0104b2005-11-09 04:45:33 +000043#include "llvm/Support/MathExtras.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000044#include "llvm/Support/Debug.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000045#include "llvm/Support/Compiler.h"
Chris Lattner1c08c712005-01-07 07:47:53 +000046#include <map>
Chris Lattner4e4b5762006-02-01 18:59:47 +000047#include <set>
Chris Lattner1c08c712005-01-07 07:47:53 +000048#include <iostream>
Jeff Cohen7e881032006-02-24 02:52:40 +000049#include <algorithm>
Chris Lattner1c08c712005-01-07 07:47:53 +000050using namespace llvm;
51
Chris Lattnerda8abb02005-09-01 18:44:10 +000052#ifndef NDEBUG
Chris Lattner7944d9d2005-01-12 03:41:21 +000053static cl::opt<bool>
Evan Chenga9c20912006-01-21 02:32:06 +000054ViewISelDAGs("view-isel-dags", cl::Hidden,
55 cl::desc("Pop up a window to show isel dags as they are selected"));
56static cl::opt<bool>
57ViewSchedDAGs("view-sched-dags", cl::Hidden,
58 cl::desc("Pop up a window to show sched dags as they are processed"));
Chris Lattner7944d9d2005-01-12 03:41:21 +000059#else
Chris Lattner5e46a192006-04-02 03:07:27 +000060static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
Chris Lattner7944d9d2005-01-12 03:41:21 +000061#endif
62
Jim Laskeyeb577ba2006-08-02 12:30:23 +000063
64//===---------------------------------------------------------------------===//
65///
66/// RegisterScheduler class - Track the registration of instruction schedulers.
67///
68//===---------------------------------------------------------------------===//
69MachinePassRegistry RegisterScheduler::Registry;
70
71//===---------------------------------------------------------------------===//
72///
73/// ISHeuristic command line option for instruction schedulers.
74///
75//===---------------------------------------------------------------------===//
Evan Cheng4ef10862006-01-23 07:01:07 +000076namespace {
Jim Laskeyeb577ba2006-08-02 12:30:23 +000077 cl::opt<RegisterScheduler::FunctionPassCtor, false,
78 RegisterPassParser<RegisterScheduler> >
Jim Laskey13ec7022006-08-01 14:21:23 +000079 ISHeuristic("sched",
Chris Lattner3700f902006-08-03 00:18:59 +000080 cl::init(&createDefaultScheduler),
Jim Laskey13ec7022006-08-01 14:21:23 +000081 cl::desc("Instruction schedulers available:"));
82
Jim Laskey9ff542f2006-08-01 18:29:48 +000083 static RegisterScheduler
Jim Laskey9373beb2006-08-01 19:14:14 +000084 defaultListDAGScheduler("default", " Best scheduler for the target",
85 createDefaultScheduler);
Evan Cheng4ef10862006-01-23 07:01:07 +000086} // namespace
87
Chris Lattner864635a2006-02-22 22:37:12 +000088namespace {
89 /// RegsForValue - This struct represents the physical registers that a
90 /// particular value is assigned and the type information about the value.
91 /// This is needed because values can be promoted into larger registers and
92 /// expanded into multiple smaller registers than the value.
Chris Lattner95255282006-06-28 23:17:24 +000093 struct VISIBILITY_HIDDEN RegsForValue {
Chris Lattner864635a2006-02-22 22:37:12 +000094 /// Regs - This list hold the register (for legal and promoted values)
95 /// or register set (for expanded values) that the value should be assigned
96 /// to.
97 std::vector<unsigned> Regs;
98
99 /// RegVT - The value type of each register.
100 ///
101 MVT::ValueType RegVT;
102
103 /// ValueVT - The value type of the LLVM value, which may be promoted from
104 /// RegVT or made from merging the two expanded parts.
105 MVT::ValueType ValueVT;
106
107 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
108
109 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
110 : RegVT(regvt), ValueVT(valuevt) {
111 Regs.push_back(Reg);
112 }
113 RegsForValue(const std::vector<unsigned> &regs,
114 MVT::ValueType regvt, MVT::ValueType valuevt)
115 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
116 }
117
118 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
119 /// this value and returns the result as a ValueVT value. This uses
120 /// Chain/Flag as the input and updates them for the output Chain/Flag.
121 SDOperand getCopyFromRegs(SelectionDAG &DAG,
Chris Lattner9f6637d2006-02-23 20:06:57 +0000122 SDOperand &Chain, SDOperand &Flag) const;
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +0000123
124 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
125 /// specified value into the registers specified by this object. This uses
126 /// Chain/Flag as the input and updates them for the output Chain/Flag.
127 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
Evan Chenga8441262006-06-15 08:11:54 +0000128 SDOperand &Chain, SDOperand &Flag,
129 MVT::ValueType PtrVT) const;
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +0000130
131 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
132 /// operand list. This adds the code marker and includes the number of
133 /// values added into it.
134 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
Chris Lattner9f6637d2006-02-23 20:06:57 +0000135 std::vector<SDOperand> &Ops) const;
Chris Lattner864635a2006-02-22 22:37:12 +0000136 };
137}
Evan Cheng4ef10862006-01-23 07:01:07 +0000138
Chris Lattner1c08c712005-01-07 07:47:53 +0000139namespace llvm {
140 //===--------------------------------------------------------------------===//
Jim Laskey9373beb2006-08-01 19:14:14 +0000141 /// createDefaultScheduler - This creates an instruction scheduler appropriate
142 /// for the target.
143 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
144 SelectionDAG *DAG,
145 MachineBasicBlock *BB) {
146 TargetLowering &TLI = IS->getTargetLowering();
147
148 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
149 return createTDListDAGScheduler(IS, DAG, BB);
150 } else {
151 assert(TLI.getSchedulingPreference() ==
152 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
153 return createBURRListDAGScheduler(IS, DAG, BB);
154 }
155 }
156
157
158 //===--------------------------------------------------------------------===//
Chris Lattner1c08c712005-01-07 07:47:53 +0000159 /// FunctionLoweringInfo - This contains information that is global to a
160 /// function that is used when lowering a region of the function.
Chris Lattnerf26bc8e2005-01-08 19:52:31 +0000161 class FunctionLoweringInfo {
162 public:
Chris Lattner1c08c712005-01-07 07:47:53 +0000163 TargetLowering &TLI;
164 Function &Fn;
165 MachineFunction &MF;
166 SSARegMap *RegMap;
167
168 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
169
170 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
171 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
172
173 /// ValueMap - Since we emit code for the function a basic block at a time,
174 /// we must remember which virtual registers hold the values for
175 /// cross-basic-block values.
176 std::map<const Value*, unsigned> ValueMap;
177
178 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
179 /// the entry block. This allows the allocas to be efficiently referenced
180 /// anywhere in the function.
181 std::map<const AllocaInst*, int> StaticAllocaMap;
182
183 unsigned MakeReg(MVT::ValueType VT) {
184 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
185 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000186
Chris Lattner3c384492006-03-16 19:51:18 +0000187 unsigned CreateRegForValue(const Value *V);
188
Chris Lattner1c08c712005-01-07 07:47:53 +0000189 unsigned InitializeRegForValue(const Value *V) {
190 unsigned &R = ValueMap[V];
191 assert(R == 0 && "Already initialized this value register!");
192 return R = CreateRegForValue(V);
193 }
194 };
195}
196
197/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
Nate Begemanf15485a2006-03-27 01:32:24 +0000198/// PHI nodes or outside of the basic block that defines it, or used by a
199/// switch instruction, which may expand to multiple basic blocks.
Chris Lattner1c08c712005-01-07 07:47:53 +0000200static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
201 if (isa<PHINode>(I)) return true;
202 BasicBlock *BB = I->getParent();
203 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
Nate Begemanf15485a2006-03-27 01:32:24 +0000204 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
205 isa<SwitchInst>(*UI))
Chris Lattner1c08c712005-01-07 07:47:53 +0000206 return true;
207 return false;
208}
209
Chris Lattnerbf209482005-10-30 19:42:35 +0000210/// isOnlyUsedInEntryBlock - If the specified argument is only used in the
Nate Begemanf15485a2006-03-27 01:32:24 +0000211/// entry block, return true. This includes arguments used by switches, since
212/// the switch may expand into multiple basic blocks.
Chris Lattnerbf209482005-10-30 19:42:35 +0000213static bool isOnlyUsedInEntryBlock(Argument *A) {
214 BasicBlock *Entry = A->getParent()->begin();
215 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
Nate Begemanf15485a2006-03-27 01:32:24 +0000216 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
Chris Lattnerbf209482005-10-30 19:42:35 +0000217 return false; // Use not in entry block.
218 return true;
219}
220
Chris Lattner1c08c712005-01-07 07:47:53 +0000221FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
Misha Brukmanedf128a2005-04-21 22:36:52 +0000222 Function &fn, MachineFunction &mf)
Chris Lattner1c08c712005-01-07 07:47:53 +0000223 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
224
Chris Lattnerbf209482005-10-30 19:42:35 +0000225 // Create a vreg for each argument register that is not dead and is used
226 // outside of the entry block for the function.
227 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
228 AI != E; ++AI)
229 if (!isOnlyUsedInEntryBlock(AI))
230 InitializeRegForValue(AI);
231
Chris Lattner1c08c712005-01-07 07:47:53 +0000232 // Initialize the mapping of values to registers. This is only set up for
233 // instruction values that are used outside of the block that defines
234 // them.
Jeff Cohen2aeaf4e2005-10-01 03:57:14 +0000235 Function::iterator BB = Fn.begin(), EB = Fn.end();
Chris Lattner1c08c712005-01-07 07:47:53 +0000236 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
237 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
238 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(AI->getArraySize())) {
239 const Type *Ty = AI->getAllocatedType();
Owen Andersona69571c2006-05-03 01:29:57 +0000240 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
Nate Begemanae232e72005-11-06 09:00:38 +0000241 unsigned Align =
Owen Andersona69571c2006-05-03 01:29:57 +0000242 std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
Nate Begemanae232e72005-11-06 09:00:38 +0000243 AI->getAlignment());
Chris Lattnera8217e32005-05-13 23:14:17 +0000244
245 // If the alignment of the value is smaller than the size of the value,
246 // and if the size of the value is particularly small (<= 8 bytes),
247 // round up to the size of the value for potentially better performance.
248 //
249 // FIXME: This could be made better with a preferred alignment hook in
250 // TargetData. It serves primarily to 8-byte align doubles for X86.
251 if (Align < TySize && TySize <= 8) Align = TySize;
Chris Lattner2dfa8192005-10-18 22:11:42 +0000252 TySize *= CUI->getValue(); // Get total allocated size.
Chris Lattnerd222f6a2005-10-18 22:14:06 +0000253 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
Chris Lattner1c08c712005-01-07 07:47:53 +0000254 StaticAllocaMap[AI] =
Chris Lattnerf26bc8e2005-01-08 19:52:31 +0000255 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
Chris Lattner1c08c712005-01-07 07:47:53 +0000256 }
257
Jeff Cohen2aeaf4e2005-10-01 03:57:14 +0000258 for (; BB != EB; ++BB)
259 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
Chris Lattner1c08c712005-01-07 07:47:53 +0000260 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
261 if (!isa<AllocaInst>(I) ||
262 !StaticAllocaMap.count(cast<AllocaInst>(I)))
263 InitializeRegForValue(I);
264
265 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
266 // also creates the initial PHI MachineInstrs, though none of the input
267 // operands are populated.
Jeff Cohen2aeaf4e2005-10-01 03:57:14 +0000268 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
Chris Lattner1c08c712005-01-07 07:47:53 +0000269 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
270 MBBMap[BB] = MBB;
271 MF.getBasicBlockList().push_back(MBB);
272
273 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
274 // appropriate.
275 PHINode *PN;
276 for (BasicBlock::iterator I = BB->begin();
Chris Lattnerf44fd882005-01-07 21:34:19 +0000277 (PN = dyn_cast<PHINode>(I)); ++I)
278 if (!PN->use_empty()) {
Chris Lattner70c2a612006-03-31 02:06:56 +0000279 MVT::ValueType VT = TLI.getValueType(PN->getType());
280 unsigned NumElements;
281 if (VT != MVT::Vector)
282 NumElements = TLI.getNumElements(VT);
283 else {
284 MVT::ValueType VT1,VT2;
285 NumElements =
286 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
287 VT1, VT2);
288 }
Chris Lattnerf44fd882005-01-07 21:34:19 +0000289 unsigned PHIReg = ValueMap[PN];
290 assert(PHIReg &&"PHI node does not have an assigned virtual register!");
291 for (unsigned i = 0; i != NumElements; ++i)
292 BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
293 }
Chris Lattner1c08c712005-01-07 07:47:53 +0000294 }
295}
296
Chris Lattner3c384492006-03-16 19:51:18 +0000297/// CreateRegForValue - Allocate the appropriate number of virtual registers of
298/// the correctly promoted or expanded types. Assign these registers
299/// consecutive vreg numbers and return the first assigned number.
300unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
301 MVT::ValueType VT = TLI.getValueType(V->getType());
302
303 // The number of multiples of registers that we need, to, e.g., split up
304 // a <2 x int64> -> 4 x i32 registers.
305 unsigned NumVectorRegs = 1;
306
307 // If this is a packed type, figure out what type it will decompose into
308 // and how many of the elements it will use.
309 if (VT == MVT::Vector) {
310 const PackedType *PTy = cast<PackedType>(V->getType());
311 unsigned NumElts = PTy->getNumElements();
312 MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
313
314 // Divide the input until we get to a supported size. This will always
315 // end with a scalar if the target doesn't support vectors.
316 while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
317 NumElts >>= 1;
318 NumVectorRegs <<= 1;
319 }
Chris Lattner6cb70042006-03-16 23:05:19 +0000320 if (NumElts == 1)
321 VT = EltTy;
322 else
323 VT = getVectorType(EltTy, NumElts);
Chris Lattner3c384492006-03-16 19:51:18 +0000324 }
325
326 // The common case is that we will only create one register for this
327 // value. If we have that case, create and return the virtual register.
328 unsigned NV = TLI.getNumElements(VT);
329 if (NV == 1) {
330 // If we are promoting this value, pick the next largest supported type.
331 MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
332 unsigned Reg = MakeReg(PromotedType);
333 // If this is a vector of supported or promoted types (e.g. 4 x i16),
334 // create all of the registers.
335 for (unsigned i = 1; i != NumVectorRegs; ++i)
336 MakeReg(PromotedType);
337 return Reg;
338 }
339
340 // If this value is represented with multiple target registers, make sure
341 // to create enough consecutive registers of the right (smaller) type.
342 unsigned NT = VT-1; // Find the type to use.
343 while (TLI.getNumElements((MVT::ValueType)NT) != 1)
344 --NT;
345
346 unsigned R = MakeReg((MVT::ValueType)NT);
347 for (unsigned i = 1; i != NV*NumVectorRegs; ++i)
348 MakeReg((MVT::ValueType)NT);
349 return R;
350}
Chris Lattner1c08c712005-01-07 07:47:53 +0000351
352//===----------------------------------------------------------------------===//
353/// SelectionDAGLowering - This is the common target-independent lowering
354/// implementation that is parameterized by a TargetLowering object.
355/// Also, targets can overload any lowering method.
356///
357namespace llvm {
358class SelectionDAGLowering {
359 MachineBasicBlock *CurMBB;
360
361 std::map<const Value*, SDOperand> NodeMap;
362
Chris Lattnerd3948112005-01-17 22:19:26 +0000363 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
364 /// them up and then emit token factor nodes when possible. This allows us to
365 /// get simple disambiguation between loads without worrying about alias
366 /// analysis.
367 std::vector<SDOperand> PendingLoads;
368
Nate Begemanf15485a2006-03-27 01:32:24 +0000369 /// Case - A pair of values to record the Value for a switch case, and the
370 /// case's target basic block.
371 typedef std::pair<Constant*, MachineBasicBlock*> Case;
372 typedef std::vector<Case>::iterator CaseItr;
373 typedef std::pair<CaseItr, CaseItr> CaseRange;
374
375 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
376 /// of conditional branches.
377 struct CaseRec {
378 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
379 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
380
381 /// CaseBB - The MBB in which to emit the compare and branch
382 MachineBasicBlock *CaseBB;
383 /// LT, GE - If nonzero, we know the current case value must be less-than or
384 /// greater-than-or-equal-to these Constants.
385 Constant *LT;
386 Constant *GE;
387 /// Range - A pair of iterators representing the range of case values to be
388 /// processed at this point in the binary search tree.
389 CaseRange Range;
390 };
391
392 /// The comparison function for sorting Case values.
393 struct CaseCmp {
394 bool operator () (const Case& C1, const Case& C2) {
395 if (const ConstantUInt* U1 = dyn_cast<const ConstantUInt>(C1.first))
396 return U1->getValue() < cast<const ConstantUInt>(C2.first)->getValue();
397
398 const ConstantSInt* S1 = dyn_cast<const ConstantSInt>(C1.first);
399 return S1->getValue() < cast<const ConstantSInt>(C2.first)->getValue();
400 }
401 };
402
Chris Lattner1c08c712005-01-07 07:47:53 +0000403public:
404 // TLI - This is information that describes the available target features we
405 // need for lowering. This indicates when operations are unavailable,
406 // implemented with a libcall, etc.
407 TargetLowering &TLI;
408 SelectionDAG &DAG;
Owen Andersona69571c2006-05-03 01:29:57 +0000409 const TargetData *TD;
Chris Lattner1c08c712005-01-07 07:47:53 +0000410
Nate Begemanf15485a2006-03-27 01:32:24 +0000411 /// SwitchCases - Vector of CaseBlock structures used to communicate
412 /// SwitchInst code generation information.
413 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
Nate Begeman37efe672006-04-22 18:53:45 +0000414 SelectionDAGISel::JumpTable JT;
Nate Begemanf15485a2006-03-27 01:32:24 +0000415
Chris Lattner1c08c712005-01-07 07:47:53 +0000416 /// FuncInfo - Information about the function as a whole.
417 ///
418 FunctionLoweringInfo &FuncInfo;
419
420 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
Misha Brukmanedf128a2005-04-21 22:36:52 +0000421 FunctionLoweringInfo &funcinfo)
Chris Lattner1c08c712005-01-07 07:47:53 +0000422 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
Nate Begeman9453eea2006-04-23 06:26:20 +0000423 JT(0,0,0,0), FuncInfo(funcinfo) {
Chris Lattner1c08c712005-01-07 07:47:53 +0000424 }
425
Chris Lattnera651cf62005-01-17 19:43:36 +0000426 /// getRoot - Return the current virtual root of the Selection DAG.
427 ///
428 SDOperand getRoot() {
Chris Lattnerd3948112005-01-17 22:19:26 +0000429 if (PendingLoads.empty())
430 return DAG.getRoot();
Misha Brukmanedf128a2005-04-21 22:36:52 +0000431
Chris Lattnerd3948112005-01-17 22:19:26 +0000432 if (PendingLoads.size() == 1) {
433 SDOperand Root = PendingLoads[0];
434 DAG.setRoot(Root);
435 PendingLoads.clear();
436 return Root;
437 }
438
439 // Otherwise, we have to make a token factor node.
Chris Lattnerbd564bf2006-08-08 02:23:42 +0000440 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
441 &PendingLoads[0], PendingLoads.size());
Chris Lattnerd3948112005-01-17 22:19:26 +0000442 PendingLoads.clear();
443 DAG.setRoot(Root);
444 return Root;
Chris Lattnera651cf62005-01-17 19:43:36 +0000445 }
446
Chris Lattner1c08c712005-01-07 07:47:53 +0000447 void visit(Instruction &I) { visit(I.getOpcode(), I); }
448
449 void visit(unsigned Opcode, User &I) {
450 switch (Opcode) {
451 default: assert(0 && "Unknown instruction type encountered!");
452 abort();
453 // Build the switch statement using the Instruction.def file.
454#define HANDLE_INST(NUM, OPCODE, CLASS) \
455 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
456#include "llvm/Instruction.def"
457 }
458 }
459
460 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
461
Chris Lattner28b5b1c2006-03-15 22:19:46 +0000462 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
Evan Cheng466685d2006-10-09 20:57:25 +0000463 const Value *SV, SDOperand Root,
Chris Lattner28b5b1c2006-03-15 22:19:46 +0000464 bool isVolatile);
Chris Lattner1c08c712005-01-07 07:47:53 +0000465
466 SDOperand getIntPtrConstant(uint64_t Val) {
467 return DAG.getConstant(Val, TLI.getPointerTy());
468 }
469
Chris Lattner199862b2006-03-16 19:57:50 +0000470 SDOperand getValue(const Value *V);
Chris Lattner1c08c712005-01-07 07:47:53 +0000471
472 const SDOperand &setValue(const Value *V, SDOperand NewN) {
473 SDOperand &N = NodeMap[V];
474 assert(N.Val == 0 && "Already set a value for this node!");
475 return N = NewN;
476 }
Chris Lattner4e4b5762006-02-01 18:59:47 +0000477
Chris Lattner864635a2006-02-22 22:37:12 +0000478 RegsForValue GetRegistersForValue(const std::string &ConstrCode,
479 MVT::ValueType VT,
480 bool OutReg, bool InReg,
481 std::set<unsigned> &OutputRegs,
482 std::set<unsigned> &InputRegs);
Nate Begemanf15485a2006-03-27 01:32:24 +0000483
Chris Lattner1c08c712005-01-07 07:47:53 +0000484 // Terminator instructions.
485 void visitRet(ReturnInst &I);
486 void visitBr(BranchInst &I);
Nate Begemanf15485a2006-03-27 01:32:24 +0000487 void visitSwitch(SwitchInst &I);
Chris Lattner1c08c712005-01-07 07:47:53 +0000488 void visitUnreachable(UnreachableInst &I) { /* noop */ }
489
Nate Begemanf15485a2006-03-27 01:32:24 +0000490 // Helper for visitSwitch
491 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
Nate Begeman37efe672006-04-22 18:53:45 +0000492 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
Nate Begemanf15485a2006-03-27 01:32:24 +0000493
Chris Lattner1c08c712005-01-07 07:47:53 +0000494 // These all get lowered before this pass.
Chris Lattner1c08c712005-01-07 07:47:53 +0000495 void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); }
496 void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
497
Nate Begeman5fbb5d22005-11-19 00:36:38 +0000498 void visitBinary(User &I, unsigned IntOp, unsigned FPOp, unsigned VecOp);
Nate Begemane21ea612005-11-18 07:42:56 +0000499 void visitShift(User &I, unsigned Opcode);
Nate Begeman5fbb5d22005-11-19 00:36:38 +0000500 void visitAdd(User &I) {
501 visitBinary(I, ISD::ADD, ISD::FADD, ISD::VADD);
Chris Lattner01b3d732005-09-28 22:28:18 +0000502 }
Chris Lattnerb9fccc42005-04-02 05:04:50 +0000503 void visitSub(User &I);
Nate Begeman5fbb5d22005-11-19 00:36:38 +0000504 void visitMul(User &I) {
505 visitBinary(I, ISD::MUL, ISD::FMUL, ISD::VMUL);
Chris Lattner01b3d732005-09-28 22:28:18 +0000506 }
Chris Lattner1c08c712005-01-07 07:47:53 +0000507 void visitDiv(User &I) {
Chris Lattner01b3d732005-09-28 22:28:18 +0000508 const Type *Ty = I.getType();
Evan Cheng3e1ce5a2006-03-03 07:01:07 +0000509 visitBinary(I,
510 Ty->isSigned() ? ISD::SDIV : ISD::UDIV, ISD::FDIV,
511 Ty->isSigned() ? ISD::VSDIV : ISD::VUDIV);
Chris Lattner1c08c712005-01-07 07:47:53 +0000512 }
513 void visitRem(User &I) {
Chris Lattner01b3d732005-09-28 22:28:18 +0000514 const Type *Ty = I.getType();
Nate Begeman5fbb5d22005-11-19 00:36:38 +0000515 visitBinary(I, Ty->isSigned() ? ISD::SREM : ISD::UREM, ISD::FREM, 0);
Chris Lattner1c08c712005-01-07 07:47:53 +0000516 }
Evan Cheng3e1ce5a2006-03-03 07:01:07 +0000517 void visitAnd(User &I) { visitBinary(I, ISD::AND, 0, ISD::VAND); }
518 void visitOr (User &I) { visitBinary(I, ISD::OR, 0, ISD::VOR); }
519 void visitXor(User &I) { visitBinary(I, ISD::XOR, 0, ISD::VXOR); }
Nate Begemane21ea612005-11-18 07:42:56 +0000520 void visitShl(User &I) { visitShift(I, ISD::SHL); }
521 void visitShr(User &I) {
522 visitShift(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);
Chris Lattner1c08c712005-01-07 07:47:53 +0000523 }
524
Evan Chengf6f95812006-05-23 06:40:47 +0000525 void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc,
526 ISD::CondCode FPOpc);
527 void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ,
528 ISD::SETOEQ); }
529 void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE,
530 ISD::SETUNE); }
531 void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE,
532 ISD::SETOLE); }
533 void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE,
534 ISD::SETOGE); }
535 void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT,
536 ISD::SETOLT); }
537 void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT,
538 ISD::SETOGT); }
Chris Lattner1c08c712005-01-07 07:47:53 +0000539
Chris Lattner2bbd8102006-03-29 00:11:43 +0000540 void visitExtractElement(User &I);
541 void visitInsertElement(User &I);
Chris Lattner3e104b12006-04-08 04:15:24 +0000542 void visitShuffleVector(User &I);
Chris Lattnerc7029802006-03-18 01:44:44 +0000543
Chris Lattner1c08c712005-01-07 07:47:53 +0000544 void visitGetElementPtr(User &I);
545 void visitCast(User &I);
546 void visitSelect(User &I);
Chris Lattner1c08c712005-01-07 07:47:53 +0000547
548 void visitMalloc(MallocInst &I);
549 void visitFree(FreeInst &I);
550 void visitAlloca(AllocaInst &I);
551 void visitLoad(LoadInst &I);
552 void visitStore(StoreInst &I);
553 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
554 void visitCall(CallInst &I);
Chris Lattnerce7518c2006-01-26 22:24:51 +0000555 void visitInlineAsm(CallInst &I);
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +0000556 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
Chris Lattner0eade312006-03-24 02:22:33 +0000557 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
Chris Lattner1c08c712005-01-07 07:47:53 +0000558
Chris Lattner1c08c712005-01-07 07:47:53 +0000559 void visitVAStart(CallInst &I);
Chris Lattner1c08c712005-01-07 07:47:53 +0000560 void visitVAArg(VAArgInst &I);
561 void visitVAEnd(CallInst &I);
562 void visitVACopy(CallInst &I);
Chris Lattner39ae3622005-01-09 00:00:49 +0000563 void visitFrameReturnAddress(CallInst &I, bool isFrameAddress);
Chris Lattner1c08c712005-01-07 07:47:53 +0000564
Chris Lattner7041ee32005-01-11 05:56:49 +0000565 void visitMemIntrinsic(CallInst &I, unsigned Op);
Chris Lattner1c08c712005-01-07 07:47:53 +0000566
567 void visitUserOp1(Instruction &I) {
568 assert(0 && "UserOp1 should not exist at instruction selection time!");
569 abort();
570 }
571 void visitUserOp2(Instruction &I) {
572 assert(0 && "UserOp2 should not exist at instruction selection time!");
573 abort();
574 }
575};
576} // end namespace llvm
577
Chris Lattner199862b2006-03-16 19:57:50 +0000578SDOperand SelectionDAGLowering::getValue(const Value *V) {
579 SDOperand &N = NodeMap[V];
580 if (N.Val) return N;
581
582 const Type *VTy = V->getType();
583 MVT::ValueType VT = TLI.getValueType(VTy);
584 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
585 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
586 visit(CE->getOpcode(), *CE);
587 assert(N.Val && "visit didn't populate the ValueMap!");
588 return N;
589 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
590 return N = DAG.getGlobalAddress(GV, VT);
591 } else if (isa<ConstantPointerNull>(C)) {
592 return N = DAG.getConstant(0, TLI.getPointerTy());
593 } else if (isa<UndefValue>(C)) {
Chris Lattner23d564c2006-03-19 00:20:20 +0000594 if (!isa<PackedType>(VTy))
595 return N = DAG.getNode(ISD::UNDEF, VT);
596
Chris Lattnerb2827b02006-03-19 00:52:58 +0000597 // Create a VBUILD_VECTOR of undef nodes.
Chris Lattner23d564c2006-03-19 00:20:20 +0000598 const PackedType *PTy = cast<PackedType>(VTy);
599 unsigned NumElements = PTy->getNumElements();
600 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
601
Chris Lattnerbd564bf2006-08-08 02:23:42 +0000602 SmallVector<SDOperand, 8> Ops;
Chris Lattner23d564c2006-03-19 00:20:20 +0000603 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
604
605 // Create a VConstant node with generic Vector type.
606 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
607 Ops.push_back(DAG.getValueType(PVT));
Chris Lattnerbd564bf2006-08-08 02:23:42 +0000608 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
609 &Ops[0], Ops.size());
Chris Lattner199862b2006-03-16 19:57:50 +0000610 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
611 return N = DAG.getConstantFP(CFP->getValue(), VT);
612 } else if (const PackedType *PTy = dyn_cast<PackedType>(VTy)) {
613 unsigned NumElements = PTy->getNumElements();
614 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
Chris Lattner199862b2006-03-16 19:57:50 +0000615
616 // Now that we know the number and type of the elements, push a
617 // Constant or ConstantFP node onto the ops list for each element of
618 // the packed constant.
Chris Lattnerbd564bf2006-08-08 02:23:42 +0000619 SmallVector<SDOperand, 8> Ops;
Chris Lattner199862b2006-03-16 19:57:50 +0000620 if (ConstantPacked *CP = dyn_cast<ConstantPacked>(C)) {
Chris Lattner2bbd8102006-03-29 00:11:43 +0000621 for (unsigned i = 0; i != NumElements; ++i)
622 Ops.push_back(getValue(CP->getOperand(i)));
Chris Lattner199862b2006-03-16 19:57:50 +0000623 } else {
624 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!");
625 SDOperand Op;
626 if (MVT::isFloatingPoint(PVT))
627 Op = DAG.getConstantFP(0, PVT);
628 else
629 Op = DAG.getConstant(0, PVT);
630 Ops.assign(NumElements, Op);
631 }
632
Chris Lattnerb2827b02006-03-19 00:52:58 +0000633 // Create a VBUILD_VECTOR node with generic Vector type.
Chris Lattner23d564c2006-03-19 00:20:20 +0000634 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
635 Ops.push_back(DAG.getValueType(PVT));
Chris Lattnerbd564bf2006-08-08 02:23:42 +0000636 return N = DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector,&Ops[0],Ops.size());
Chris Lattner199862b2006-03-16 19:57:50 +0000637 } else {
638 // Canonicalize all constant ints to be unsigned.
639 return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT);
640 }
641 }
642
643 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
644 std::map<const AllocaInst*, int>::iterator SI =
645 FuncInfo.StaticAllocaMap.find(AI);
646 if (SI != FuncInfo.StaticAllocaMap.end())
647 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
648 }
649
650 std::map<const Value*, unsigned>::const_iterator VMI =
651 FuncInfo.ValueMap.find(V);
652 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
653
654 unsigned InReg = VMI->second;
655
656 // If this type is not legal, make it so now.
Chris Lattner70c2a612006-03-31 02:06:56 +0000657 if (VT != MVT::Vector) {
658 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
Chris Lattner199862b2006-03-16 19:57:50 +0000659
Chris Lattner70c2a612006-03-31 02:06:56 +0000660 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
661 if (DestVT < VT) {
662 // Source must be expanded. This input value is actually coming from the
663 // register pair VMI->second and VMI->second+1.
664 N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
665 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
666 } else if (DestVT > VT) { // Promotion case
Chris Lattner199862b2006-03-16 19:57:50 +0000667 if (MVT::isFloatingPoint(VT))
668 N = DAG.getNode(ISD::FP_ROUND, VT, N);
669 else
670 N = DAG.getNode(ISD::TRUNCATE, VT, N);
671 }
Chris Lattner70c2a612006-03-31 02:06:56 +0000672 } else {
673 // Otherwise, if this is a vector, make it available as a generic vector
674 // here.
675 MVT::ValueType PTyElementVT, PTyLegalElementVT;
Chris Lattner2e2ef952006-04-05 06:54:42 +0000676 const PackedType *PTy = cast<PackedType>(VTy);
677 unsigned NE = TLI.getPackedTypeBreakdown(PTy, PTyElementVT,
Chris Lattner70c2a612006-03-31 02:06:56 +0000678 PTyLegalElementVT);
679
680 // Build a VBUILD_VECTOR with the input registers.
Chris Lattnerbd564bf2006-08-08 02:23:42 +0000681 SmallVector<SDOperand, 8> Ops;
Chris Lattner70c2a612006-03-31 02:06:56 +0000682 if (PTyElementVT == PTyLegalElementVT) {
683 // If the value types are legal, just VBUILD the CopyFromReg nodes.
684 for (unsigned i = 0; i != NE; ++i)
685 Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
686 PTyElementVT));
687 } else if (PTyElementVT < PTyLegalElementVT) {
688 // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate.
689 for (unsigned i = 0; i != NE; ++i) {
690 SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
691 PTyElementVT);
692 if (MVT::isFloatingPoint(PTyElementVT))
693 Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op);
694 else
695 Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op);
696 Ops.push_back(Op);
697 }
698 } else {
699 // If the register was expanded, use BUILD_PAIR.
700 assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!");
701 for (unsigned i = 0; i != NE/2; ++i) {
702 SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
703 PTyElementVT);
704 SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
705 PTyElementVT);
706 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1));
707 }
708 }
709
710 Ops.push_back(DAG.getConstant(NE, MVT::i32));
711 Ops.push_back(DAG.getValueType(PTyLegalElementVT));
Chris Lattnerbd564bf2006-08-08 02:23:42 +0000712 N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
Chris Lattner2e2ef952006-04-05 06:54:42 +0000713
714 // Finally, use a VBIT_CONVERT to make this available as the appropriate
715 // vector type.
716 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
717 DAG.getConstant(PTy->getNumElements(),
718 MVT::i32),
719 DAG.getValueType(TLI.getValueType(PTy->getElementType())));
Chris Lattner199862b2006-03-16 19:57:50 +0000720 }
721
722 return N;
723}
724
725
Chris Lattner1c08c712005-01-07 07:47:53 +0000726void SelectionDAGLowering::visitRet(ReturnInst &I) {
727 if (I.getNumOperands() == 0) {
Chris Lattnera651cf62005-01-17 19:43:36 +0000728 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
Chris Lattner1c08c712005-01-07 07:47:53 +0000729 return;
730 }
Chris Lattnerbd564bf2006-08-08 02:23:42 +0000731 SmallVector<SDOperand, 8> NewValues;
Nate Begemanee625572006-01-27 21:09:22 +0000732 NewValues.push_back(getRoot());
733 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
734 SDOperand RetOp = getValue(I.getOperand(i));
Evan Cheng8e7d0562006-05-26 23:09:09 +0000735 bool isSigned = I.getOperand(i)->getType()->isSigned();
Nate Begemanee625572006-01-27 21:09:22 +0000736
737 // If this is an integer return value, we need to promote it ourselves to
738 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather
739 // than sign/zero.
Evan Cheng8e7d0562006-05-26 23:09:09 +0000740 // FIXME: C calling convention requires the return type to be promoted to
741 // at least 32-bit. But this is not necessary for non-C calling conventions.
Nate Begemanee625572006-01-27 21:09:22 +0000742 if (MVT::isInteger(RetOp.getValueType()) &&
743 RetOp.getValueType() < MVT::i64) {
744 MVT::ValueType TmpVT;
745 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
746 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
747 else
748 TmpVT = MVT::i32;
Chris Lattner1c08c712005-01-07 07:47:53 +0000749
Evan Cheng8e7d0562006-05-26 23:09:09 +0000750 if (isSigned)
Nate Begemanee625572006-01-27 21:09:22 +0000751 RetOp = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, RetOp);
752 else
753 RetOp = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, RetOp);
754 }
755 NewValues.push_back(RetOp);
Evan Cheng8e7d0562006-05-26 23:09:09 +0000756 NewValues.push_back(DAG.getConstant(isSigned, MVT::i32));
Chris Lattner1c08c712005-01-07 07:47:53 +0000757 }
Chris Lattnerbd564bf2006-08-08 02:23:42 +0000758 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
759 &NewValues[0], NewValues.size()));
Chris Lattner1c08c712005-01-07 07:47:53 +0000760}
761
762void SelectionDAGLowering::visitBr(BranchInst &I) {
763 // Update machine-CFG edges.
764 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
Nate Begemanf15485a2006-03-27 01:32:24 +0000765 CurMBB->addSuccessor(Succ0MBB);
Chris Lattner1c08c712005-01-07 07:47:53 +0000766
767 // Figure out which block is immediately after the current one.
768 MachineBasicBlock *NextBlock = 0;
769 MachineFunction::iterator BBI = CurMBB;
770 if (++BBI != CurMBB->getParent()->end())
771 NextBlock = BBI;
772
773 if (I.isUnconditional()) {
774 // If this is not a fall-through branch, emit the branch.
775 if (Succ0MBB != NextBlock)
Chris Lattnera651cf62005-01-17 19:43:36 +0000776 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
Misha Brukmandedf2bd2005-04-22 04:01:18 +0000777 DAG.getBasicBlock(Succ0MBB)));
Chris Lattner1c08c712005-01-07 07:47:53 +0000778 } else {
779 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
Nate Begemanf15485a2006-03-27 01:32:24 +0000780 CurMBB->addSuccessor(Succ1MBB);
Chris Lattner1c08c712005-01-07 07:47:53 +0000781
782 SDOperand Cond = getValue(I.getCondition());
Chris Lattner1c08c712005-01-07 07:47:53 +0000783 if (Succ1MBB == NextBlock) {
784 // If the condition is false, fall through. This means we should branch
785 // if the condition is true to Succ #0.
Chris Lattnera651cf62005-01-17 19:43:36 +0000786 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
Misha Brukmandedf2bd2005-04-22 04:01:18 +0000787 Cond, DAG.getBasicBlock(Succ0MBB)));
Chris Lattner1c08c712005-01-07 07:47:53 +0000788 } else if (Succ0MBB == NextBlock) {
789 // If the condition is true, fall through. This means we should branch if
790 // the condition is false to Succ #1. Invert the condition first.
791 SDOperand True = DAG.getConstant(1, Cond.getValueType());
792 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
Chris Lattnera651cf62005-01-17 19:43:36 +0000793 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
Misha Brukmandedf2bd2005-04-22 04:01:18 +0000794 Cond, DAG.getBasicBlock(Succ1MBB)));
Chris Lattner1c08c712005-01-07 07:47:53 +0000795 } else {
Chris Lattnere7ccd4a2005-04-09 03:30:29 +0000796 std::vector<SDOperand> Ops;
797 Ops.push_back(getRoot());
Evan Cheng298ebf22006-02-16 08:27:56 +0000798 // If the false case is the current basic block, then this is a self
799 // loop. We do not want to emit "Loop: ... brcond Out; br Loop", as it
800 // adds an extra instruction in the loop. Instead, invert the
801 // condition and emit "Loop: ... br!cond Loop; br Out.
802 if (CurMBB == Succ1MBB) {
803 std::swap(Succ0MBB, Succ1MBB);
804 SDOperand True = DAG.getConstant(1, Cond.getValueType());
805 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
806 }
Nate Begeman81e80972006-03-17 01:40:33 +0000807 SDOperand True = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
808 DAG.getBasicBlock(Succ0MBB));
809 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, True,
810 DAG.getBasicBlock(Succ1MBB)));
Chris Lattner1c08c712005-01-07 07:47:53 +0000811 }
812 }
813}
814
Nate Begemanf15485a2006-03-27 01:32:24 +0000815/// visitSwitchCase - Emits the necessary code to represent a single node in
816/// the binary search tree resulting from lowering a switch instruction.
817void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
818 SDOperand SwitchOp = getValue(CB.SwitchV);
819 SDOperand CaseOp = getValue(CB.CaseC);
820 SDOperand Cond = DAG.getSetCC(MVT::i1, SwitchOp, CaseOp, CB.CC);
821
822 // Set NextBlock to be the MBB immediately after the current one, if any.
823 // This is used to avoid emitting unnecessary branches to the next block.
824 MachineBasicBlock *NextBlock = 0;
825 MachineFunction::iterator BBI = CurMBB;
826 if (++BBI != CurMBB->getParent()->end())
827 NextBlock = BBI;
828
829 // If the lhs block is the next block, invert the condition so that we can
830 // fall through to the lhs instead of the rhs block.
831 if (CB.LHSBB == NextBlock) {
832 std::swap(CB.LHSBB, CB.RHSBB);
833 SDOperand True = DAG.getConstant(1, Cond.getValueType());
834 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
835 }
836 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
837 DAG.getBasicBlock(CB.LHSBB));
838 if (CB.RHSBB == NextBlock)
839 DAG.setRoot(BrCond);
840 else
841 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
842 DAG.getBasicBlock(CB.RHSBB)));
843 // Update successor info
844 CurMBB->addSuccessor(CB.LHSBB);
845 CurMBB->addSuccessor(CB.RHSBB);
846}
847
Nate Begeman37efe672006-04-22 18:53:45 +0000848void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
Nate Begeman37efe672006-04-22 18:53:45 +0000849 // Emit the code for the jump table
850 MVT::ValueType PTy = TLI.getPointerTy();
Evan Cheng8825a482006-08-01 01:03:13 +0000851 assert((PTy == MVT::i32 || PTy == MVT::i64) &&
852 "Jump table entries are 32-bit values");
Evan Cheng2ae5b872006-09-24 05:22:38 +0000853 bool isPIC = TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_;
Evan Cheng8825a482006-08-01 01:03:13 +0000854 // PIC jump table entries are 32-bit values.
Evan Cheng2ae5b872006-09-24 05:22:38 +0000855 unsigned EntrySize = isPIC ? 4 : MVT::getSizeInBits(PTy)/8;
Nate Begeman37efe672006-04-22 18:53:45 +0000856 SDOperand Copy = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
857 SDOperand IDX = DAG.getNode(ISD::MUL, PTy, Copy,
Evan Cheng8825a482006-08-01 01:03:13 +0000858 DAG.getConstant(EntrySize, PTy));
Nate Begeman2f1ae882006-07-27 01:13:04 +0000859 SDOperand TAB = DAG.getJumpTable(JT.JTI,PTy);
860 SDOperand ADD = DAG.getNode(ISD::ADD, PTy, IDX, TAB);
Evan Cheng2ae5b872006-09-24 05:22:38 +0000861 SDOperand LD = DAG.getLoad(isPIC ? MVT::i32 : PTy, Copy.getValue(1), ADD,
Evan Cheng466685d2006-10-09 20:57:25 +0000862 NULL, 0);
Evan Cheng2ae5b872006-09-24 05:22:38 +0000863 if (isPIC) {
Andrew Lenharth16113432006-09-26 20:02:30 +0000864 // For Pic, the sequence is:
865 // BRIND(load(Jumptable + index) + RelocBase)
866 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha
Andrew Lenharth82c3d8f2006-10-11 04:29:42 +0000867 SDOperand Reloc;
868 if (TLI.usesGlobalOffsetTable())
869 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy);
870 else
871 Reloc = TAB;
Evan Cheng8825a482006-08-01 01:03:13 +0000872 ADD = DAG.getNode(ISD::ADD, PTy,
Andrew Lenharthbeec30e2006-09-24 19:45:58 +0000873 ((PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD), Reloc);
Nate Begeman2f1ae882006-07-27 01:13:04 +0000874 DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), ADD));
875 } else {
876 DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD));
877 }
Nate Begeman37efe672006-04-22 18:53:45 +0000878}
879
Nate Begemanf15485a2006-03-27 01:32:24 +0000880void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
881 // Figure out which block is immediately after the current one.
882 MachineBasicBlock *NextBlock = 0;
883 MachineFunction::iterator BBI = CurMBB;
884 if (++BBI != CurMBB->getParent()->end())
885 NextBlock = BBI;
886
887 // If there is only the default destination, branch to it if it is not the
888 // next basic block. Otherwise, just fall through.
889 if (I.getNumOperands() == 2) {
890 // Update machine-CFG edges.
891 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[I.getDefaultDest()];
892 // If this is not a fall-through branch, emit the branch.
893 if (DefaultMBB != NextBlock)
894 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
895 DAG.getBasicBlock(DefaultMBB)));
Chris Lattnera3bb86d2006-06-12 18:25:29 +0000896 CurMBB->addSuccessor(DefaultMBB);
Nate Begemanf15485a2006-03-27 01:32:24 +0000897 return;
898 }
899
900 // If there are any non-default case statements, create a vector of Cases
901 // representing each one, and sort the vector so that we can efficiently
902 // create a binary search tree from them.
903 std::vector<Case> Cases;
904 for (unsigned i = 1; i < I.getNumSuccessors(); ++i) {
905 MachineBasicBlock *SMBB = FuncInfo.MBBMap[I.getSuccessor(i)];
906 Cases.push_back(Case(I.getSuccessorValue(i), SMBB));
907 }
908 std::sort(Cases.begin(), Cases.end(), CaseCmp());
909
910 // Get the Value to be switched on and default basic blocks, which will be
911 // inserted into CaseBlock records, representing basic blocks in the binary
912 // search tree.
913 Value *SV = I.getOperand(0);
914 MachineBasicBlock *Default = FuncInfo.MBBMap[I.getDefaultDest()];
Nate Begeman37efe672006-04-22 18:53:45 +0000915
916 // Get the MachineFunction which holds the current MBB. This is used during
917 // emission of jump tables, and when inserting any additional MBBs necessary
918 // to represent the switch.
Nate Begemanf15485a2006-03-27 01:32:24 +0000919 MachineFunction *CurMF = CurMBB->getParent();
920 const BasicBlock *LLVMBB = CurMBB->getBasicBlock();
Nate Begeman37efe672006-04-22 18:53:45 +0000921
Nate Begeman17c275f2006-05-08 16:51:36 +0000922 // If the switch has more than 5 blocks, and at least 31.25% dense, and the
923 // target supports indirect branches, then emit a jump table rather than
924 // lowering the switch to a binary tree of conditional branches.
Nate Begeman9453eea2006-04-23 06:26:20 +0000925 if (TLI.isOperationLegal(ISD::BRIND, TLI.getPointerTy()) &&
Nate Begemanf4360a42006-05-03 03:48:02 +0000926 Cases.size() > 5) {
Nate Begeman37efe672006-04-22 18:53:45 +0000927 uint64_t First = cast<ConstantIntegral>(Cases.front().first)->getRawValue();
928 uint64_t Last = cast<ConstantIntegral>(Cases.back().first)->getRawValue();
Nate Begemanf4360a42006-05-03 03:48:02 +0000929 double Density = (double)Cases.size() / (double)((Last - First) + 1ULL);
930
Nate Begeman17c275f2006-05-08 16:51:36 +0000931 if (Density >= 0.3125) {
Nate Begeman37efe672006-04-22 18:53:45 +0000932 // Create a new basic block to hold the code for loading the address
933 // of the jump table, and jumping to it. Update successor information;
934 // we will either branch to the default case for the switch, or the jump
935 // table.
936 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
937 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
938 CurMBB->addSuccessor(Default);
939 CurMBB->addSuccessor(JumpTableBB);
940
941 // Subtract the lowest switch case value from the value being switched on
942 // and conditional branch to default mbb if the result is greater than the
943 // difference between smallest and largest cases.
944 SDOperand SwitchOp = getValue(SV);
945 MVT::ValueType VT = SwitchOp.getValueType();
946 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
947 DAG.getConstant(First, VT));
948
949 // The SDNode we just created, which holds the value being switched on
950 // minus the the smallest case value, needs to be copied to a virtual
951 // register so it can be used as an index into the jump table in a
952 // subsequent basic block. This value may be smaller or larger than the
953 // target's pointer type, and therefore require extension or truncating.
954 if (VT > TLI.getPointerTy())
955 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
956 else
957 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
958 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
959 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
960
961 // Emit the range check for the jump table, and branch to the default
962 // block for the switch statement if the value being switched on exceeds
963 // the largest case in the switch.
964 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
965 DAG.getConstant(Last-First,VT), ISD::SETUGT);
966 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
967 DAG.getBasicBlock(Default)));
968
Nate Begemanf4360a42006-05-03 03:48:02 +0000969 // Build a vector of destination BBs, corresponding to each target
970 // of the jump table. If the value of the jump table slot corresponds to
971 // a case statement, push the case's BB onto the vector, otherwise, push
972 // the default BB.
Nate Begeman37efe672006-04-22 18:53:45 +0000973 std::vector<MachineBasicBlock*> DestBBs;
Nate Begemanf4360a42006-05-03 03:48:02 +0000974 uint64_t TEI = First;
975 for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++TEI) {
976 if (cast<ConstantIntegral>(ii->first)->getRawValue() == TEI) {
977 DestBBs.push_back(ii->second);
Nate Begemanf4360a42006-05-03 03:48:02 +0000978 ++ii;
979 } else {
980 DestBBs.push_back(Default);
Nate Begemanf4360a42006-05-03 03:48:02 +0000981 }
Nate Begeman37efe672006-04-22 18:53:45 +0000982 }
Nate Begemanf4360a42006-05-03 03:48:02 +0000983
984 // Update successor info
Chris Lattnerc66764c2006-09-10 06:36:57 +0000985 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
986 E = DestBBs.end(); I != E; ++I)
987 JumpTableBB->addSuccessor(*I);
Nate Begemanf4360a42006-05-03 03:48:02 +0000988
989 // Create a jump table index for this jump table, or return an existing
990 // one.
Nate Begeman37efe672006-04-22 18:53:45 +0000991 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
992
993 // Set the jump table information so that we can codegen it as a second
994 // MachineBasicBlock
995 JT.Reg = JumpTableReg;
996 JT.JTI = JTI;
997 JT.MBB = JumpTableBB;
Nate Begeman9453eea2006-04-23 06:26:20 +0000998 JT.Default = Default;
Nate Begeman37efe672006-04-22 18:53:45 +0000999 return;
1000 }
1001 }
Nate Begemanf15485a2006-03-27 01:32:24 +00001002
1003 // Push the initial CaseRec onto the worklist
1004 std::vector<CaseRec> CaseVec;
1005 CaseVec.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
1006
1007 while (!CaseVec.empty()) {
1008 // Grab a record representing a case range to process off the worklist
1009 CaseRec CR = CaseVec.back();
1010 CaseVec.pop_back();
1011
1012 // Size is the number of Cases represented by this range. If Size is 1,
1013 // then we are processing a leaf of the binary search tree. Otherwise,
1014 // we need to pick a pivot, and push left and right ranges onto the
1015 // worklist.
1016 unsigned Size = CR.Range.second - CR.Range.first;
1017
1018 if (Size == 1) {
1019 // Create a CaseBlock record representing a conditional branch to
1020 // the Case's target mbb if the value being switched on SV is equal
1021 // to C. Otherwise, branch to default.
1022 Constant *C = CR.Range.first->first;
1023 MachineBasicBlock *Target = CR.Range.first->second;
1024 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, C, Target, Default,
1025 CR.CaseBB);
1026 // If the MBB representing the leaf node is the current MBB, then just
1027 // call visitSwitchCase to emit the code into the current block.
1028 // Otherwise, push the CaseBlock onto the vector to be later processed
1029 // by SDISel, and insert the node's MBB before the next MBB.
1030 if (CR.CaseBB == CurMBB)
1031 visitSwitchCase(CB);
1032 else {
1033 SwitchCases.push_back(CB);
1034 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
1035 }
1036 } else {
1037 // split case range at pivot
1038 CaseItr Pivot = CR.Range.first + (Size / 2);
1039 CaseRange LHSR(CR.Range.first, Pivot);
1040 CaseRange RHSR(Pivot, CR.Range.second);
1041 Constant *C = Pivot->first;
1042 MachineBasicBlock *RHSBB = 0, *LHSBB = 0;
1043 // We know that we branch to the LHS if the Value being switched on is
1044 // less than the Pivot value, C. We use this to optimize our binary
1045 // tree a bit, by recognizing that if SV is greater than or equal to the
1046 // LHS's Case Value, and that Case Value is exactly one less than the
1047 // Pivot's Value, then we can branch directly to the LHS's Target,
1048 // rather than creating a leaf node for it.
1049 if ((LHSR.second - LHSR.first) == 1 &&
1050 LHSR.first->first == CR.GE &&
1051 cast<ConstantIntegral>(C)->getRawValue() ==
1052 (cast<ConstantIntegral>(CR.GE)->getRawValue() + 1ULL)) {
1053 LHSBB = LHSR.first->second;
1054 } else {
1055 LHSBB = new MachineBasicBlock(LLVMBB);
1056 CaseVec.push_back(CaseRec(LHSBB,C,CR.GE,LHSR));
1057 }
1058 // Similar to the optimization above, if the Value being switched on is
1059 // known to be less than the Constant CR.LT, and the current Case Value
1060 // is CR.LT - 1, then we can branch directly to the target block for
1061 // the current Case Value, rather than emitting a RHS leaf node for it.
1062 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1063 cast<ConstantIntegral>(RHSR.first->first)->getRawValue() ==
1064 (cast<ConstantIntegral>(CR.LT)->getRawValue() - 1ULL)) {
1065 RHSBB = RHSR.first->second;
1066 } else {
1067 RHSBB = new MachineBasicBlock(LLVMBB);
1068 CaseVec.push_back(CaseRec(RHSBB,CR.LT,C,RHSR));
1069 }
1070 // Create a CaseBlock record representing a conditional branch to
1071 // the LHS node if the value being switched on SV is less than C.
1072 // Otherwise, branch to LHS.
1073 ISD::CondCode CC = C->getType()->isSigned() ? ISD::SETLT : ISD::SETULT;
1074 SelectionDAGISel::CaseBlock CB(CC, SV, C, LHSBB, RHSBB, CR.CaseBB);
1075 if (CR.CaseBB == CurMBB)
1076 visitSwitchCase(CB);
1077 else {
1078 SwitchCases.push_back(CB);
1079 CurMF->getBasicBlockList().insert(BBI, CR.CaseBB);
1080 }
1081 }
1082 }
1083}
1084
Chris Lattnerb9fccc42005-04-02 05:04:50 +00001085void SelectionDAGLowering::visitSub(User &I) {
1086 // -0.0 - X --> fneg
Chris Lattner01b3d732005-09-28 22:28:18 +00001087 if (I.getType()->isFloatingPoint()) {
1088 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
1089 if (CFP->isExactlyValue(-0.0)) {
1090 SDOperand Op2 = getValue(I.getOperand(1));
1091 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
1092 return;
1093 }
Chris Lattner01b3d732005-09-28 22:28:18 +00001094 }
Nate Begeman5fbb5d22005-11-19 00:36:38 +00001095 visitBinary(I, ISD::SUB, ISD::FSUB, ISD::VSUB);
Chris Lattnerb9fccc42005-04-02 05:04:50 +00001096}
1097
Nate Begeman5fbb5d22005-11-19 00:36:38 +00001098void SelectionDAGLowering::visitBinary(User &I, unsigned IntOp, unsigned FPOp,
1099 unsigned VecOp) {
1100 const Type *Ty = I.getType();
Chris Lattner1c08c712005-01-07 07:47:53 +00001101 SDOperand Op1 = getValue(I.getOperand(0));
1102 SDOperand Op2 = getValue(I.getOperand(1));
Chris Lattner2c49f272005-01-19 22:31:21 +00001103
Chris Lattnerb67eb912005-11-19 18:40:42 +00001104 if (Ty->isIntegral()) {
Nate Begeman5fbb5d22005-11-19 00:36:38 +00001105 setValue(&I, DAG.getNode(IntOp, Op1.getValueType(), Op1, Op2));
1106 } else if (Ty->isFloatingPoint()) {
1107 setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2));
1108 } else {
1109 const PackedType *PTy = cast<PackedType>(Ty);
Chris Lattnerc7029802006-03-18 01:44:44 +00001110 SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
1111 SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
1112 setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ));
Nate Begeman5fbb5d22005-11-19 00:36:38 +00001113 }
Nate Begemane21ea612005-11-18 07:42:56 +00001114}
Chris Lattner2c49f272005-01-19 22:31:21 +00001115
Nate Begemane21ea612005-11-18 07:42:56 +00001116void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
1117 SDOperand Op1 = getValue(I.getOperand(0));
1118 SDOperand Op2 = getValue(I.getOperand(1));
1119
1120 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
1121
Chris Lattner1c08c712005-01-07 07:47:53 +00001122 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
1123}
1124
1125void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode,
Evan Chengf6f95812006-05-23 06:40:47 +00001126 ISD::CondCode UnsignedOpcode,
1127 ISD::CondCode FPOpcode) {
Chris Lattner1c08c712005-01-07 07:47:53 +00001128 SDOperand Op1 = getValue(I.getOperand(0));
1129 SDOperand Op2 = getValue(I.getOperand(1));
1130 ISD::CondCode Opcode = SignedOpcode;
Evan Cheng80235d52006-05-23 18:18:46 +00001131 if (!FiniteOnlyFPMath() && I.getOperand(0)->getType()->isFloatingPoint())
Evan Chengf6f95812006-05-23 06:40:47 +00001132 Opcode = FPOpcode;
1133 else if (I.getOperand(0)->getType()->isUnsigned())
Chris Lattner1c08c712005-01-07 07:47:53 +00001134 Opcode = UnsignedOpcode;
Chris Lattner7cf7e3f2005-08-09 20:20:18 +00001135 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
Chris Lattner1c08c712005-01-07 07:47:53 +00001136}
1137
1138void SelectionDAGLowering::visitSelect(User &I) {
1139 SDOperand Cond = getValue(I.getOperand(0));
1140 SDOperand TrueVal = getValue(I.getOperand(1));
1141 SDOperand FalseVal = getValue(I.getOperand(2));
Chris Lattnerb22e35a2006-04-08 22:22:57 +00001142 if (!isa<PackedType>(I.getType())) {
1143 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
1144 TrueVal, FalseVal));
1145 } else {
1146 setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal,
1147 *(TrueVal.Val->op_end()-2),
1148 *(TrueVal.Val->op_end()-1)));
1149 }
Chris Lattner1c08c712005-01-07 07:47:53 +00001150}
1151
1152void SelectionDAGLowering::visitCast(User &I) {
1153 SDOperand N = getValue(I.getOperand(0));
Chris Lattnere25ca692006-03-22 20:09:35 +00001154 MVT::ValueType SrcVT = N.getValueType();
Chris Lattner28b5b1c2006-03-15 22:19:46 +00001155 MVT::ValueType DestVT = TLI.getValueType(I.getType());
Chris Lattner1c08c712005-01-07 07:47:53 +00001156
Chris Lattnere25ca692006-03-22 20:09:35 +00001157 if (DestVT == MVT::Vector) {
1158 // This is a cast to a vector from something else. This is always a bit
1159 // convert. Get information about the input vector.
1160 const PackedType *DestTy = cast<PackedType>(I.getType());
1161 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1162 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N,
1163 DAG.getConstant(DestTy->getNumElements(),MVT::i32),
1164 DAG.getValueType(EltVT)));
1165 } else if (SrcVT == DestVT) {
Chris Lattner1c08c712005-01-07 07:47:53 +00001166 setValue(&I, N); // noop cast.
Chris Lattner28b5b1c2006-03-15 22:19:46 +00001167 } else if (DestVT == MVT::i1) {
Chris Lattneref311aa2005-05-09 22:17:13 +00001168 // Cast to bool is a comparison against zero, not truncation to zero.
Chris Lattner28b5b1c2006-03-15 22:19:46 +00001169 SDOperand Zero = isInteger(SrcVT) ? DAG.getConstant(0, N.getValueType()) :
Chris Lattneref311aa2005-05-09 22:17:13 +00001170 DAG.getConstantFP(0.0, N.getValueType());
Chris Lattner7cf7e3f2005-08-09 20:20:18 +00001171 setValue(&I, DAG.getSetCC(MVT::i1, N, Zero, ISD::SETNE));
Chris Lattner28b5b1c2006-03-15 22:19:46 +00001172 } else if (isInteger(SrcVT)) {
1173 if (isInteger(DestVT)) { // Int -> Int cast
1174 if (DestVT < SrcVT) // Truncating cast?
1175 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
Chris Lattnerae0aacb2005-01-08 08:08:56 +00001176 else if (I.getOperand(0)->getType()->isSigned())
Chris Lattner28b5b1c2006-03-15 22:19:46 +00001177 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
Chris Lattnerae0aacb2005-01-08 08:08:56 +00001178 else
Chris Lattner28b5b1c2006-03-15 22:19:46 +00001179 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
Chris Lattner7e358902006-03-22 22:20:49 +00001180 } else if (isFloatingPoint(DestVT)) { // Int -> FP cast
Chris Lattnerae0aacb2005-01-08 08:08:56 +00001181 if (I.getOperand(0)->getType()->isSigned())
Chris Lattner28b5b1c2006-03-15 22:19:46 +00001182 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
Chris Lattnerae0aacb2005-01-08 08:08:56 +00001183 else
Chris Lattner28b5b1c2006-03-15 22:19:46 +00001184 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
Chris Lattnere25ca692006-03-22 20:09:35 +00001185 } else {
1186 assert(0 && "Unknown cast!");
Chris Lattnerae0aacb2005-01-08 08:08:56 +00001187 }
Chris Lattner28b5b1c2006-03-15 22:19:46 +00001188 } else if (isFloatingPoint(SrcVT)) {
1189 if (isFloatingPoint(DestVT)) { // FP -> FP cast
1190 if (DestVT < SrcVT) // Rounding cast?
1191 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
Chris Lattnerae0aacb2005-01-08 08:08:56 +00001192 else
Chris Lattner28b5b1c2006-03-15 22:19:46 +00001193 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
Chris Lattnere25ca692006-03-22 20:09:35 +00001194 } else if (isInteger(DestVT)) { // FP -> Int cast.
Chris Lattnerae0aacb2005-01-08 08:08:56 +00001195 if (I.getType()->isSigned())
Chris Lattner28b5b1c2006-03-15 22:19:46 +00001196 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
Chris Lattnerae0aacb2005-01-08 08:08:56 +00001197 else
Chris Lattner28b5b1c2006-03-15 22:19:46 +00001198 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
Chris Lattnere25ca692006-03-22 20:09:35 +00001199 } else {
1200 assert(0 && "Unknown cast!");
Chris Lattner28b5b1c2006-03-15 22:19:46 +00001201 }
1202 } else {
Chris Lattnere25ca692006-03-22 20:09:35 +00001203 assert(SrcVT == MVT::Vector && "Unknown cast!");
1204 assert(DestVT != MVT::Vector && "Casts to vector already handled!");
1205 // This is a cast from a vector to something else. This is always a bit
1206 // convert. Get information about the input vector.
1207 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N));
Chris Lattner1c08c712005-01-07 07:47:53 +00001208 }
1209}
1210
Chris Lattner2bbd8102006-03-29 00:11:43 +00001211void SelectionDAGLowering::visitInsertElement(User &I) {
Chris Lattnerc7029802006-03-18 01:44:44 +00001212 SDOperand InVec = getValue(I.getOperand(0));
1213 SDOperand InVal = getValue(I.getOperand(1));
1214 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1215 getValue(I.getOperand(2)));
1216
Chris Lattner2332b9f2006-03-19 01:17:20 +00001217 SDOperand Num = *(InVec.Val->op_end()-2);
1218 SDOperand Typ = *(InVec.Val->op_end()-1);
1219 setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector,
1220 InVec, InVal, InIdx, Num, Typ));
Chris Lattnerc7029802006-03-18 01:44:44 +00001221}
1222
Chris Lattner2bbd8102006-03-29 00:11:43 +00001223void SelectionDAGLowering::visitExtractElement(User &I) {
Chris Lattner384504c2006-03-21 20:44:12 +00001224 SDOperand InVec = getValue(I.getOperand(0));
1225 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1226 getValue(I.getOperand(1)));
1227 SDOperand Typ = *(InVec.Val->op_end()-1);
1228 setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT,
1229 TLI.getValueType(I.getType()), InVec, InIdx));
1230}
Chris Lattnerc7029802006-03-18 01:44:44 +00001231
Chris Lattner3e104b12006-04-08 04:15:24 +00001232void SelectionDAGLowering::visitShuffleVector(User &I) {
1233 SDOperand V1 = getValue(I.getOperand(0));
1234 SDOperand V2 = getValue(I.getOperand(1));
1235 SDOperand Mask = getValue(I.getOperand(2));
1236
1237 SDOperand Num = *(V1.Val->op_end()-2);
1238 SDOperand Typ = *(V2.Val->op_end()-1);
1239 setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
1240 V1, V2, Mask, Num, Typ));
1241}
1242
1243
Chris Lattner1c08c712005-01-07 07:47:53 +00001244void SelectionDAGLowering::visitGetElementPtr(User &I) {
1245 SDOperand N = getValue(I.getOperand(0));
1246 const Type *Ty = I.getOperand(0)->getType();
Chris Lattner1c08c712005-01-07 07:47:53 +00001247
1248 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
1249 OI != E; ++OI) {
1250 Value *Idx = *OI;
Chris Lattnerc88d8e92005-12-05 07:10:48 +00001251 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
Chris Lattner1c08c712005-01-07 07:47:53 +00001252 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
1253 if (Field) {
1254 // N = N + Offset
Owen Andersona69571c2006-05-03 01:29:57 +00001255 uint64_t Offset = TD->getStructLayout(StTy)->MemberOffsets[Field];
Chris Lattner1c08c712005-01-07 07:47:53 +00001256 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
Misha Brukmandedf2bd2005-04-22 04:01:18 +00001257 getIntPtrConstant(Offset));
Chris Lattner1c08c712005-01-07 07:47:53 +00001258 }
1259 Ty = StTy->getElementType(Field);
1260 } else {
1261 Ty = cast<SequentialType>(Ty)->getElementType();
Chris Lattner7cc47772005-01-07 21:56:57 +00001262
Chris Lattner7c0104b2005-11-09 04:45:33 +00001263 // If this is a constant subscript, handle it quickly.
1264 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
1265 if (CI->getRawValue() == 0) continue;
Chris Lattner7cc47772005-01-07 21:56:57 +00001266
Chris Lattner7c0104b2005-11-09 04:45:33 +00001267 uint64_t Offs;
1268 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
Owen Andersona69571c2006-05-03 01:29:57 +00001269 Offs = (int64_t)TD->getTypeSize(Ty)*CSI->getValue();
Chris Lattner7c0104b2005-11-09 04:45:33 +00001270 else
Owen Andersona69571c2006-05-03 01:29:57 +00001271 Offs = TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
Chris Lattner7c0104b2005-11-09 04:45:33 +00001272 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
1273 continue;
Chris Lattner1c08c712005-01-07 07:47:53 +00001274 }
Chris Lattner7c0104b2005-11-09 04:45:33 +00001275
1276 // N = N + Idx * ElementSize;
Owen Andersona69571c2006-05-03 01:29:57 +00001277 uint64_t ElementSize = TD->getTypeSize(Ty);
Chris Lattner7c0104b2005-11-09 04:45:33 +00001278 SDOperand IdxN = getValue(Idx);
1279
1280 // If the index is smaller or larger than intptr_t, truncate or extend
1281 // it.
1282 if (IdxN.getValueType() < N.getValueType()) {
1283 if (Idx->getType()->isSigned())
1284 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
1285 else
1286 IdxN = DAG.getNode(ISD::ZERO_EXTEND, N.getValueType(), IdxN);
1287 } else if (IdxN.getValueType() > N.getValueType())
1288 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
1289
1290 // If this is a multiply by a power of two, turn it into a shl
1291 // immediately. This is a very common case.
1292 if (isPowerOf2_64(ElementSize)) {
1293 unsigned Amt = Log2_64(ElementSize);
1294 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
Chris Lattner6b2d6962005-11-09 16:50:40 +00001295 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
Chris Lattner7c0104b2005-11-09 04:45:33 +00001296 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1297 continue;
1298 }
1299
1300 SDOperand Scale = getIntPtrConstant(ElementSize);
1301 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
1302 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
Chris Lattner1c08c712005-01-07 07:47:53 +00001303 }
1304 }
1305 setValue(&I, N);
1306}
1307
1308void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
1309 // If this is a fixed sized alloca in the entry block of the function,
1310 // allocate it statically on the stack.
1311 if (FuncInfo.StaticAllocaMap.count(&I))
1312 return; // getValue will auto-populate this.
1313
1314 const Type *Ty = I.getAllocatedType();
Owen Andersona69571c2006-05-03 01:29:57 +00001315 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
1316 unsigned Align = std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
Nate Begemanae232e72005-11-06 09:00:38 +00001317 I.getAlignment());
Chris Lattner1c08c712005-01-07 07:47:53 +00001318
1319 SDOperand AllocSize = getValue(I.getArraySize());
Chris Lattner68cd65e2005-01-22 23:04:37 +00001320 MVT::ValueType IntPtr = TLI.getPointerTy();
1321 if (IntPtr < AllocSize.getValueType())
1322 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
1323 else if (IntPtr > AllocSize.getValueType())
1324 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
Chris Lattner1c08c712005-01-07 07:47:53 +00001325
Chris Lattner68cd65e2005-01-22 23:04:37 +00001326 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
Chris Lattner1c08c712005-01-07 07:47:53 +00001327 getIntPtrConstant(TySize));
1328
1329 // Handle alignment. If the requested alignment is less than or equal to the
1330 // stack alignment, ignore it and round the size of the allocation up to the
1331 // stack alignment size. If the size is greater than the stack alignment, we
1332 // note this in the DYNAMIC_STACKALLOC node.
1333 unsigned StackAlign =
1334 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1335 if (Align <= StackAlign) {
1336 Align = 0;
1337 // Add SA-1 to the size.
1338 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
1339 getIntPtrConstant(StackAlign-1));
1340 // Mask out the low bits for alignment purposes.
1341 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
1342 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
1343 }
1344
Chris Lattnerbd564bf2006-08-08 02:23:42 +00001345 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) };
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00001346 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
1347 MVT::Other);
1348 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
Chris Lattner1c08c712005-01-07 07:47:53 +00001349 DAG.setRoot(setValue(&I, DSA).getValue(1));
1350
1351 // Inform the Frame Information that we have just allocated a variable-sized
1352 // object.
1353 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
1354}
1355
Chris Lattner1c08c712005-01-07 07:47:53 +00001356void SelectionDAGLowering::visitLoad(LoadInst &I) {
1357 SDOperand Ptr = getValue(I.getOperand(0));
Misha Brukmanedf128a2005-04-21 22:36:52 +00001358
Chris Lattnerd3948112005-01-17 22:19:26 +00001359 SDOperand Root;
1360 if (I.isVolatile())
1361 Root = getRoot();
1362 else {
1363 // Do not serialize non-volatile loads against each other.
1364 Root = DAG.getRoot();
1365 }
Chris Lattner28b5b1c2006-03-15 22:19:46 +00001366
Evan Cheng466685d2006-10-09 20:57:25 +00001367 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
Chris Lattner28b5b1c2006-03-15 22:19:46 +00001368 Root, I.isVolatile()));
1369}
1370
1371SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
Evan Cheng466685d2006-10-09 20:57:25 +00001372 const Value *SV, SDOperand Root,
Chris Lattner28b5b1c2006-03-15 22:19:46 +00001373 bool isVolatile) {
Nate Begeman5fbb5d22005-11-19 00:36:38 +00001374 SDOperand L;
Nate Begeman8cfa57b2005-12-06 06:18:55 +00001375 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
Nate Begeman4ef3b812005-11-22 01:29:36 +00001376 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
Evan Cheng466685d2006-10-09 20:57:25 +00001377 L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr,
1378 DAG.getSrcValue(SV));
Nate Begeman5fbb5d22005-11-19 00:36:38 +00001379 } else {
Evan Cheng466685d2006-10-09 20:57:25 +00001380 L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, isVolatile);
Nate Begeman5fbb5d22005-11-19 00:36:38 +00001381 }
Chris Lattnerd3948112005-01-17 22:19:26 +00001382
Chris Lattner28b5b1c2006-03-15 22:19:46 +00001383 if (isVolatile)
Chris Lattnerd3948112005-01-17 22:19:26 +00001384 DAG.setRoot(L.getValue(1));
1385 else
1386 PendingLoads.push_back(L.getValue(1));
Chris Lattner28b5b1c2006-03-15 22:19:46 +00001387
1388 return L;
Chris Lattner1c08c712005-01-07 07:47:53 +00001389}
1390
1391
1392void SelectionDAGLowering::visitStore(StoreInst &I) {
1393 Value *SrcV = I.getOperand(0);
1394 SDOperand Src = getValue(SrcV);
1395 SDOperand Ptr = getValue(I.getOperand(1));
Evan Cheng786225a2006-10-05 23:01:46 +00001396 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr,
1397 DAG.getSrcValue(I.getOperand(1))));
Chris Lattner1c08c712005-01-07 07:47:53 +00001398}
1399
Chris Lattner0eade312006-03-24 02:22:33 +00001400/// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
1401/// access memory and has no other side effects at all.
1402static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) {
1403#define GET_NO_MEMORY_INTRINSICS
1404#include "llvm/Intrinsics.gen"
1405#undef GET_NO_MEMORY_INTRINSICS
1406 return false;
1407}
1408
Chris Lattnere58a7802006-04-02 03:41:14 +00001409// IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
1410// have any side-effects or if it only reads memory.
1411static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
1412#define GET_SIDE_EFFECT_INFO
1413#include "llvm/Intrinsics.gen"
1414#undef GET_SIDE_EFFECT_INFO
1415 return false;
1416}
1417
Chris Lattner0eade312006-03-24 02:22:33 +00001418/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
1419/// node.
1420void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
1421 unsigned Intrinsic) {
Chris Lattner7255a542006-03-24 22:49:42 +00001422 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic);
Chris Lattnere58a7802006-04-02 03:41:14 +00001423 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
Chris Lattner0eade312006-03-24 02:22:33 +00001424
1425 // Build the operand list.
Chris Lattnerbd564bf2006-08-08 02:23:42 +00001426 SmallVector<SDOperand, 8> Ops;
Chris Lattnere58a7802006-04-02 03:41:14 +00001427 if (HasChain) { // If this intrinsic has side-effects, chainify it.
1428 if (OnlyLoad) {
1429 // We don't need to serialize loads against other loads.
1430 Ops.push_back(DAG.getRoot());
1431 } else {
1432 Ops.push_back(getRoot());
1433 }
1434 }
Chris Lattner0eade312006-03-24 02:22:33 +00001435
1436 // Add the intrinsic ID as an integer operand.
1437 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
1438
1439 // Add all operands of the call to the operand list.
1440 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1441 SDOperand Op = getValue(I.getOperand(i));
1442
1443 // If this is a vector type, force it to the right packed type.
1444 if (Op.getValueType() == MVT::Vector) {
1445 const PackedType *OpTy = cast<PackedType>(I.getOperand(i)->getType());
1446 MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType());
1447
1448 MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements());
1449 assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?");
1450 Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op);
1451 }
1452
1453 assert(TLI.isTypeLegal(Op.getValueType()) &&
1454 "Intrinsic uses a non-legal type?");
1455 Ops.push_back(Op);
1456 }
1457
1458 std::vector<MVT::ValueType> VTs;
1459 if (I.getType() != Type::VoidTy) {
1460 MVT::ValueType VT = TLI.getValueType(I.getType());
1461 if (VT == MVT::Vector) {
1462 const PackedType *DestTy = cast<PackedType>(I.getType());
1463 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1464
1465 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
1466 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
1467 }
1468
1469 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
1470 VTs.push_back(VT);
1471 }
1472 if (HasChain)
1473 VTs.push_back(MVT::Other);
1474
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00001475 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
1476
Chris Lattner0eade312006-03-24 02:22:33 +00001477 // Create the node.
Chris Lattner48b61a72006-03-28 00:40:33 +00001478 SDOperand Result;
1479 if (!HasChain)
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00001480 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
1481 &Ops[0], Ops.size());
Chris Lattner48b61a72006-03-28 00:40:33 +00001482 else if (I.getType() != Type::VoidTy)
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00001483 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
1484 &Ops[0], Ops.size());
Chris Lattner48b61a72006-03-28 00:40:33 +00001485 else
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00001486 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
1487 &Ops[0], Ops.size());
Chris Lattner48b61a72006-03-28 00:40:33 +00001488
Chris Lattnere58a7802006-04-02 03:41:14 +00001489 if (HasChain) {
1490 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
1491 if (OnlyLoad)
1492 PendingLoads.push_back(Chain);
1493 else
1494 DAG.setRoot(Chain);
1495 }
Chris Lattner0eade312006-03-24 02:22:33 +00001496 if (I.getType() != Type::VoidTy) {
1497 if (const PackedType *PTy = dyn_cast<PackedType>(I.getType())) {
1498 MVT::ValueType EVT = TLI.getValueType(PTy->getElementType());
1499 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
1500 DAG.getConstant(PTy->getNumElements(), MVT::i32),
1501 DAG.getValueType(EVT));
1502 }
1503 setValue(&I, Result);
1504 }
1505}
1506
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00001507/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
1508/// we want to emit this as a call to a named external function, return the name
1509/// otherwise lower it and return null.
1510const char *
1511SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
1512 switch (Intrinsic) {
Chris Lattner0eade312006-03-24 02:22:33 +00001513 default:
1514 // By default, turn this into a target intrinsic node.
1515 visitTargetIntrinsic(I, Intrinsic);
1516 return 0;
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00001517 case Intrinsic::vastart: visitVAStart(I); return 0;
1518 case Intrinsic::vaend: visitVAEnd(I); return 0;
1519 case Intrinsic::vacopy: visitVACopy(I); return 0;
1520 case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return 0;
1521 case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return 0;
1522 case Intrinsic::setjmp:
1523 return "_setjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1524 break;
1525 case Intrinsic::longjmp:
1526 return "_longjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1527 break;
Chris Lattner03dd4652006-03-03 00:00:25 +00001528 case Intrinsic::memcpy_i32:
1529 case Intrinsic::memcpy_i64:
1530 visitMemIntrinsic(I, ISD::MEMCPY);
1531 return 0;
1532 case Intrinsic::memset_i32:
1533 case Intrinsic::memset_i64:
1534 visitMemIntrinsic(I, ISD::MEMSET);
1535 return 0;
1536 case Intrinsic::memmove_i32:
1537 case Intrinsic::memmove_i64:
1538 visitMemIntrinsic(I, ISD::MEMMOVE);
1539 return 0;
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00001540
Chris Lattner86cb6432005-12-13 17:40:33 +00001541 case Intrinsic::dbg_stoppoint: {
Jim Laskeyce72b172006-02-11 01:01:30 +00001542 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
Jim Laskey43970fe2006-03-23 18:06:46 +00001543 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
Jim Laskeyfbcf23c2006-03-26 22:46:27 +00001544 if (DebugInfo && SPI.getContext() && DebugInfo->Verify(SPI.getContext())) {
Chris Lattnerbd564bf2006-08-08 02:23:42 +00001545 SDOperand Ops[5];
Chris Lattner36ce6912005-11-29 06:21:05 +00001546
Chris Lattnerbd564bf2006-08-08 02:23:42 +00001547 Ops[0] = getRoot();
1548 Ops[1] = getValue(SPI.getLineValue());
1549 Ops[2] = getValue(SPI.getColumnValue());
Chris Lattner36ce6912005-11-29 06:21:05 +00001550
Jim Laskey43970fe2006-03-23 18:06:46 +00001551 DebugInfoDesc *DD = DebugInfo->getDescFor(SPI.getContext());
Jim Laskeyce72b172006-02-11 01:01:30 +00001552 assert(DD && "Not a debug information descriptor");
Jim Laskey43970fe2006-03-23 18:06:46 +00001553 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
1554
Chris Lattnerbd564bf2006-08-08 02:23:42 +00001555 Ops[3] = DAG.getString(CompileUnit->getFileName());
1556 Ops[4] = DAG.getString(CompileUnit->getDirectory());
Jim Laskeyce72b172006-02-11 01:01:30 +00001557
Chris Lattnerbd564bf2006-08-08 02:23:42 +00001558 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
Chris Lattner86cb6432005-12-13 17:40:33 +00001559 }
Jim Laskey43970fe2006-03-23 18:06:46 +00001560
Chris Lattnerb1a5a5c2005-11-16 07:22:30 +00001561 return 0;
Chris Lattner36ce6912005-11-29 06:21:05 +00001562 }
Jim Laskey43970fe2006-03-23 18:06:46 +00001563 case Intrinsic::dbg_region_start: {
1564 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1565 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
Jim Laskeyfbcf23c2006-03-26 22:46:27 +00001566 if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) {
Jim Laskey43970fe2006-03-23 18:06:46 +00001567 unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext());
Chris Lattnerbd564bf2006-08-08 02:23:42 +00001568 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, getRoot(),
1569 DAG.getConstant(LabelID, MVT::i32)));
Jim Laskey43970fe2006-03-23 18:06:46 +00001570 }
1571
Chris Lattnerb1a5a5c2005-11-16 07:22:30 +00001572 return 0;
Jim Laskey43970fe2006-03-23 18:06:46 +00001573 }
1574 case Intrinsic::dbg_region_end: {
1575 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1576 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
Jim Laskeyfbcf23c2006-03-26 22:46:27 +00001577 if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) {
Jim Laskey43970fe2006-03-23 18:06:46 +00001578 unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext());
Chris Lattnerbd564bf2006-08-08 02:23:42 +00001579 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
1580 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
Jim Laskey43970fe2006-03-23 18:06:46 +00001581 }
1582
Chris Lattnerb1a5a5c2005-11-16 07:22:30 +00001583 return 0;
Jim Laskey43970fe2006-03-23 18:06:46 +00001584 }
1585 case Intrinsic::dbg_func_start: {
1586 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1587 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
Jim Laskeyfbcf23c2006-03-26 22:46:27 +00001588 if (DebugInfo && FSI.getSubprogram() &&
1589 DebugInfo->Verify(FSI.getSubprogram())) {
Jim Laskey43970fe2006-03-23 18:06:46 +00001590 unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram());
Chris Lattnerbd564bf2006-08-08 02:23:42 +00001591 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
1592 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
Jim Laskey43970fe2006-03-23 18:06:46 +00001593 }
1594
Chris Lattnerb1a5a5c2005-11-16 07:22:30 +00001595 return 0;
Jim Laskey43970fe2006-03-23 18:06:46 +00001596 }
1597 case Intrinsic::dbg_declare: {
1598 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1599 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
Jim Laskeybf7637d2006-03-28 13:45:20 +00001600 if (DebugInfo && DI.getVariable() && DebugInfo->Verify(DI.getVariable())) {
Jim Laskey0892cee2006-03-24 09:50:27 +00001601 SDOperand AddressOp = getValue(DI.getAddress());
Chris Lattnerbd564bf2006-08-08 02:23:42 +00001602 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp))
Jim Laskey43970fe2006-03-23 18:06:46 +00001603 DebugInfo->RecordVariable(DI.getVariable(), FI->getIndex());
Jim Laskey43970fe2006-03-23 18:06:46 +00001604 }
1605
1606 return 0;
1607 }
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00001608
Reid Spencer0b118202006-01-16 21:12:35 +00001609 case Intrinsic::isunordered_f32:
1610 case Intrinsic::isunordered_f64:
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00001611 setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)),
1612 getValue(I.getOperand(2)), ISD::SETUO));
1613 return 0;
1614
Reid Spencer0b118202006-01-16 21:12:35 +00001615 case Intrinsic::sqrt_f32:
1616 case Intrinsic::sqrt_f64:
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00001617 setValue(&I, DAG.getNode(ISD::FSQRT,
1618 getValue(I.getOperand(1)).getValueType(),
1619 getValue(I.getOperand(1))));
1620 return 0;
Chris Lattner6ddf8ed2006-09-09 06:03:30 +00001621 case Intrinsic::powi_f32:
1622 case Intrinsic::powi_f64:
1623 setValue(&I, DAG.getNode(ISD::FPOWI,
1624 getValue(I.getOperand(1)).getValueType(),
1625 getValue(I.getOperand(1)),
1626 getValue(I.getOperand(2))));
1627 return 0;
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00001628 case Intrinsic::pcmarker: {
1629 SDOperand Tmp = getValue(I.getOperand(1));
1630 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
1631 return 0;
1632 }
Andrew Lenharth8b91c772005-11-11 22:48:54 +00001633 case Intrinsic::readcyclecounter: {
Chris Lattnerbd564bf2006-08-08 02:23:42 +00001634 SDOperand Op = getRoot();
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00001635 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
1636 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
1637 &Op, 1);
Andrew Lenharth8b91c772005-11-11 22:48:54 +00001638 setValue(&I, Tmp);
1639 DAG.setRoot(Tmp.getValue(1));
Andrew Lenharth51b8d542005-11-11 16:47:30 +00001640 return 0;
Andrew Lenharth8b91c772005-11-11 22:48:54 +00001641 }
Nate Begemand88fc032006-01-14 03:14:10 +00001642 case Intrinsic::bswap_i16:
Nate Begemand88fc032006-01-14 03:14:10 +00001643 case Intrinsic::bswap_i32:
Nate Begemand88fc032006-01-14 03:14:10 +00001644 case Intrinsic::bswap_i64:
1645 setValue(&I, DAG.getNode(ISD::BSWAP,
1646 getValue(I.getOperand(1)).getValueType(),
1647 getValue(I.getOperand(1))));
1648 return 0;
Reid Spencer0b118202006-01-16 21:12:35 +00001649 case Intrinsic::cttz_i8:
1650 case Intrinsic::cttz_i16:
1651 case Intrinsic::cttz_i32:
1652 case Intrinsic::cttz_i64:
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00001653 setValue(&I, DAG.getNode(ISD::CTTZ,
1654 getValue(I.getOperand(1)).getValueType(),
1655 getValue(I.getOperand(1))));
1656 return 0;
Reid Spencer0b118202006-01-16 21:12:35 +00001657 case Intrinsic::ctlz_i8:
1658 case Intrinsic::ctlz_i16:
1659 case Intrinsic::ctlz_i32:
1660 case Intrinsic::ctlz_i64:
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00001661 setValue(&I, DAG.getNode(ISD::CTLZ,
1662 getValue(I.getOperand(1)).getValueType(),
1663 getValue(I.getOperand(1))));
1664 return 0;
Reid Spencer0b118202006-01-16 21:12:35 +00001665 case Intrinsic::ctpop_i8:
1666 case Intrinsic::ctpop_i16:
1667 case Intrinsic::ctpop_i32:
1668 case Intrinsic::ctpop_i64:
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00001669 setValue(&I, DAG.getNode(ISD::CTPOP,
1670 getValue(I.getOperand(1)).getValueType(),
1671 getValue(I.getOperand(1))));
1672 return 0;
Chris Lattner140d53c2006-01-13 02:50:02 +00001673 case Intrinsic::stacksave: {
Chris Lattnerbd564bf2006-08-08 02:23:42 +00001674 SDOperand Op = getRoot();
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00001675 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
1676 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
Chris Lattner140d53c2006-01-13 02:50:02 +00001677 setValue(&I, Tmp);
1678 DAG.setRoot(Tmp.getValue(1));
1679 return 0;
1680 }
Chris Lattner39a17dd2006-01-23 05:22:07 +00001681 case Intrinsic::stackrestore: {
1682 SDOperand Tmp = getValue(I.getOperand(1));
1683 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
Chris Lattner140d53c2006-01-13 02:50:02 +00001684 return 0;
Chris Lattner39a17dd2006-01-23 05:22:07 +00001685 }
Chris Lattnerac22c832005-12-12 22:51:16 +00001686 case Intrinsic::prefetch:
1687 // FIXME: Currently discarding prefetches.
1688 return 0;
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00001689 }
1690}
1691
1692
Chris Lattner1c08c712005-01-07 07:47:53 +00001693void SelectionDAGLowering::visitCall(CallInst &I) {
Chris Lattner64e14b12005-01-08 22:48:57 +00001694 const char *RenameFn = 0;
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00001695 if (Function *F = I.getCalledFunction()) {
Chris Lattnerc0f18152005-04-02 05:26:53 +00001696 if (F->isExternal())
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00001697 if (unsigned IID = F->getIntrinsicID()) {
1698 RenameFn = visitIntrinsicCall(I, IID);
1699 if (!RenameFn)
1700 return;
1701 } else { // Not an LLVM intrinsic.
1702 const std::string &Name = F->getName();
Chris Lattnera09f8482006-03-05 05:09:38 +00001703 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) {
1704 if (I.getNumOperands() == 3 && // Basic sanity checks.
1705 I.getOperand(1)->getType()->isFloatingPoint() &&
1706 I.getType() == I.getOperand(1)->getType() &&
1707 I.getType() == I.getOperand(2)->getType()) {
1708 SDOperand LHS = getValue(I.getOperand(1));
1709 SDOperand RHS = getValue(I.getOperand(2));
1710 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
1711 LHS, RHS));
1712 return;
1713 }
1714 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) {
Chris Lattnerc0f18152005-04-02 05:26:53 +00001715 if (I.getNumOperands() == 2 && // Basic sanity checks.
1716 I.getOperand(1)->getType()->isFloatingPoint() &&
1717 I.getType() == I.getOperand(1)->getType()) {
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00001718 SDOperand Tmp = getValue(I.getOperand(1));
Chris Lattnerc0f18152005-04-02 05:26:53 +00001719 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
1720 return;
1721 }
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00001722 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) {
Chris Lattnerf76e7dc2005-04-30 04:43:14 +00001723 if (I.getNumOperands() == 2 && // Basic sanity checks.
1724 I.getOperand(1)->getType()->isFloatingPoint() &&
Chris Lattner06a248c92006-02-14 05:39:35 +00001725 I.getType() == I.getOperand(1)->getType()) {
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00001726 SDOperand Tmp = getValue(I.getOperand(1));
Chris Lattnerf76e7dc2005-04-30 04:43:14 +00001727 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
1728 return;
1729 }
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00001730 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) {
Chris Lattnerf76e7dc2005-04-30 04:43:14 +00001731 if (I.getNumOperands() == 2 && // Basic sanity checks.
1732 I.getOperand(1)->getType()->isFloatingPoint() &&
Chris Lattner06a248c92006-02-14 05:39:35 +00001733 I.getType() == I.getOperand(1)->getType()) {
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00001734 SDOperand Tmp = getValue(I.getOperand(1));
Chris Lattnerf76e7dc2005-04-30 04:43:14 +00001735 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
1736 return;
1737 }
1738 }
Chris Lattner1ca85d52005-05-14 13:56:55 +00001739 }
Chris Lattnerce7518c2006-01-26 22:24:51 +00001740 } else if (isa<InlineAsm>(I.getOperand(0))) {
1741 visitInlineAsm(I);
1742 return;
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00001743 }
Misha Brukmanedf128a2005-04-21 22:36:52 +00001744
Chris Lattner64e14b12005-01-08 22:48:57 +00001745 SDOperand Callee;
1746 if (!RenameFn)
1747 Callee = getValue(I.getOperand(0));
1748 else
1749 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
Chris Lattner1c08c712005-01-07 07:47:53 +00001750 std::vector<std::pair<SDOperand, const Type*> > Args;
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00001751 Args.reserve(I.getNumOperands());
Chris Lattner1c08c712005-01-07 07:47:53 +00001752 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1753 Value *Arg = I.getOperand(i);
1754 SDOperand ArgNode = getValue(Arg);
1755 Args.push_back(std::make_pair(ArgNode, Arg->getType()));
1756 }
Misha Brukmanedf128a2005-04-21 22:36:52 +00001757
Nate Begeman8e21e712005-03-26 01:29:23 +00001758 const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType());
1759 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
Misha Brukmanedf128a2005-04-21 22:36:52 +00001760
Chris Lattnercf5734d2005-01-08 19:26:18 +00001761 std::pair<SDOperand,SDOperand> Result =
Chris Lattner9092fa32005-05-12 19:56:57 +00001762 TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), I.getCallingConv(),
Chris Lattneradf6a962005-05-13 18:50:42 +00001763 I.isTailCall(), Callee, Args, DAG);
Chris Lattner1c08c712005-01-07 07:47:53 +00001764 if (I.getType() != Type::VoidTy)
Chris Lattnercf5734d2005-01-08 19:26:18 +00001765 setValue(&I, Result.first);
1766 DAG.setRoot(Result.second);
Chris Lattner1c08c712005-01-07 07:47:53 +00001767}
1768
Chris Lattner864635a2006-02-22 22:37:12 +00001769SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
Chris Lattner9f6637d2006-02-23 20:06:57 +00001770 SDOperand &Chain, SDOperand &Flag)const{
Chris Lattner864635a2006-02-22 22:37:12 +00001771 SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag);
1772 Chain = Val.getValue(1);
1773 Flag = Val.getValue(2);
1774
1775 // If the result was expanded, copy from the top part.
1776 if (Regs.size() > 1) {
1777 assert(Regs.size() == 2 &&
1778 "Cannot expand to more than 2 elts yet!");
1779 SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag);
Evan Cheng693163e2006-10-04 22:23:53 +00001780 Chain = Hi.getValue(1);
1781 Flag = Hi.getValue(2);
Chris Lattner9f6637d2006-02-23 20:06:57 +00001782 if (DAG.getTargetLoweringInfo().isLittleEndian())
1783 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
1784 else
1785 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val);
Chris Lattner864635a2006-02-22 22:37:12 +00001786 }
Chris Lattner4e4b5762006-02-01 18:59:47 +00001787
Chris Lattnercf752aa2006-06-08 18:22:48 +00001788 // Otherwise, if the return value was promoted or extended, truncate it to the
Chris Lattner864635a2006-02-22 22:37:12 +00001789 // appropriate type.
1790 if (RegVT == ValueVT)
1791 return Val;
1792
Chris Lattnercf752aa2006-06-08 18:22:48 +00001793 if (MVT::isInteger(RegVT)) {
1794 if (ValueVT < RegVT)
1795 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
1796 else
1797 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
1798 } else {
Chris Lattner864635a2006-02-22 22:37:12 +00001799 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
Chris Lattnercf752aa2006-06-08 18:22:48 +00001800 }
Chris Lattner864635a2006-02-22 22:37:12 +00001801}
1802
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00001803/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
1804/// specified value into the registers specified by this object. This uses
1805/// Chain/Flag as the input and updates them for the output Chain/Flag.
1806void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
Evan Chenga8441262006-06-15 08:11:54 +00001807 SDOperand &Chain, SDOperand &Flag,
1808 MVT::ValueType PtrVT) const {
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00001809 if (Regs.size() == 1) {
1810 // If there is a single register and the types differ, this must be
1811 // a promotion.
1812 if (RegVT != ValueVT) {
Chris Lattner0c48fd42006-06-08 18:27:11 +00001813 if (MVT::isInteger(RegVT)) {
1814 if (RegVT < ValueVT)
1815 Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val);
1816 else
1817 Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
1818 } else
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00001819 Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
1820 }
1821 Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
1822 Flag = Chain.getValue(1);
1823 } else {
Chris Lattner9f6637d2006-02-23 20:06:57 +00001824 std::vector<unsigned> R(Regs);
1825 if (!DAG.getTargetLoweringInfo().isLittleEndian())
1826 std::reverse(R.begin(), R.end());
1827
1828 for (unsigned i = 0, e = R.size(); i != e; ++i) {
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00001829 SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val,
Evan Chenga8441262006-06-15 08:11:54 +00001830 DAG.getConstant(i, PtrVT));
Chris Lattner9f6637d2006-02-23 20:06:57 +00001831 Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag);
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00001832 Flag = Chain.getValue(1);
1833 }
1834 }
1835}
Chris Lattner864635a2006-02-22 22:37:12 +00001836
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00001837/// AddInlineAsmOperands - Add this value to the specified inlineasm node
1838/// operand list. This adds the code marker and includes the number of
1839/// values added into it.
1840void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
Chris Lattner9f6637d2006-02-23 20:06:57 +00001841 std::vector<SDOperand> &Ops) const {
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00001842 Ops.push_back(DAG.getConstant(Code | (Regs.size() << 3), MVT::i32));
1843 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
1844 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
1845}
Chris Lattner864635a2006-02-22 22:37:12 +00001846
1847/// isAllocatableRegister - If the specified register is safe to allocate,
1848/// i.e. it isn't a stack pointer or some other special register, return the
1849/// register class for the register. Otherwise, return null.
1850static const TargetRegisterClass *
Chris Lattner9b6fb5d2006-02-22 23:09:03 +00001851isAllocatableRegister(unsigned Reg, MachineFunction &MF,
1852 const TargetLowering &TLI, const MRegisterInfo *MRI) {
Chris Lattnerf8814cf2006-04-02 00:24:45 +00001853 MVT::ValueType FoundVT = MVT::Other;
1854 const TargetRegisterClass *FoundRC = 0;
Chris Lattner9b6fb5d2006-02-22 23:09:03 +00001855 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
1856 E = MRI->regclass_end(); RCI != E; ++RCI) {
Chris Lattnerf8814cf2006-04-02 00:24:45 +00001857 MVT::ValueType ThisVT = MVT::Other;
1858
Chris Lattner9b6fb5d2006-02-22 23:09:03 +00001859 const TargetRegisterClass *RC = *RCI;
1860 // If none of the the value types for this register class are valid, we
1861 // can't use it. For example, 64-bit reg classes on 32-bit targets.
Chris Lattner9b6fb5d2006-02-22 23:09:03 +00001862 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1863 I != E; ++I) {
1864 if (TLI.isTypeLegal(*I)) {
Chris Lattnerf8814cf2006-04-02 00:24:45 +00001865 // If we have already found this register in a different register class,
1866 // choose the one with the largest VT specified. For example, on
1867 // PowerPC, we favor f64 register classes over f32.
1868 if (FoundVT == MVT::Other ||
1869 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
1870 ThisVT = *I;
1871 break;
1872 }
Chris Lattner9b6fb5d2006-02-22 23:09:03 +00001873 }
1874 }
1875
Chris Lattnerf8814cf2006-04-02 00:24:45 +00001876 if (ThisVT == MVT::Other) continue;
Chris Lattner9b6fb5d2006-02-22 23:09:03 +00001877
Chris Lattner864635a2006-02-22 22:37:12 +00001878 // NOTE: This isn't ideal. In particular, this might allocate the
1879 // frame pointer in functions that need it (due to them not being taken
1880 // out of allocation, because a variable sized allocation hasn't been seen
1881 // yet). This is a slight code pessimization, but should still work.
Chris Lattner9b6fb5d2006-02-22 23:09:03 +00001882 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
1883 E = RC->allocation_order_end(MF); I != E; ++I)
Chris Lattnerf8814cf2006-04-02 00:24:45 +00001884 if (*I == Reg) {
1885 // We found a matching register class. Keep looking at others in case
1886 // we find one with larger registers that this physreg is also in.
1887 FoundRC = RC;
1888 FoundVT = ThisVT;
1889 break;
1890 }
Chris Lattner4e4b5762006-02-01 18:59:47 +00001891 }
Chris Lattnerf8814cf2006-04-02 00:24:45 +00001892 return FoundRC;
Chris Lattner864635a2006-02-22 22:37:12 +00001893}
1894
1895RegsForValue SelectionDAGLowering::
1896GetRegistersForValue(const std::string &ConstrCode,
1897 MVT::ValueType VT, bool isOutReg, bool isInReg,
1898 std::set<unsigned> &OutputRegs,
1899 std::set<unsigned> &InputRegs) {
1900 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
1901 TLI.getRegForInlineAsmConstraint(ConstrCode, VT);
1902 std::vector<unsigned> Regs;
1903
1904 unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1;
1905 MVT::ValueType RegVT;
1906 MVT::ValueType ValueVT = VT;
1907
1908 if (PhysReg.first) {
1909 if (VT == MVT::Other)
1910 ValueVT = *PhysReg.second->vt_begin();
Chris Lattnercf752aa2006-06-08 18:22:48 +00001911
1912 // Get the actual register value type. This is important, because the user
1913 // may have asked for (e.g.) the AX register in i32 type. We need to
1914 // remember that AX is actually i16 to get the right extension.
1915 RegVT = *PhysReg.second->vt_begin();
Chris Lattner864635a2006-02-22 22:37:12 +00001916
1917 // This is a explicit reference to a physical register.
1918 Regs.push_back(PhysReg.first);
1919
1920 // If this is an expanded reference, add the rest of the regs to Regs.
1921 if (NumRegs != 1) {
Chris Lattner864635a2006-02-22 22:37:12 +00001922 TargetRegisterClass::iterator I = PhysReg.second->begin();
1923 TargetRegisterClass::iterator E = PhysReg.second->end();
1924 for (; *I != PhysReg.first; ++I)
1925 assert(I != E && "Didn't find reg!");
1926
1927 // Already added the first reg.
1928 --NumRegs; ++I;
1929 for (; NumRegs; --NumRegs, ++I) {
1930 assert(I != E && "Ran out of registers to allocate!");
1931 Regs.push_back(*I);
1932 }
1933 }
1934 return RegsForValue(Regs, RegVT, ValueVT);
1935 }
1936
1937 // This is a reference to a register class. Allocate NumRegs consecutive,
1938 // available, registers from the class.
1939 std::vector<unsigned> RegClassRegs =
1940 TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
1941
1942 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
1943 MachineFunction &MF = *CurMBB->getParent();
1944 unsigned NumAllocated = 0;
1945 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
1946 unsigned Reg = RegClassRegs[i];
1947 // See if this register is available.
1948 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
1949 (isInReg && InputRegs.count(Reg))) { // Already used.
1950 // Make sure we find consecutive registers.
1951 NumAllocated = 0;
1952 continue;
1953 }
1954
1955 // Check to see if this register is allocatable (i.e. don't give out the
1956 // stack pointer).
Chris Lattner9b6fb5d2006-02-22 23:09:03 +00001957 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
Chris Lattner864635a2006-02-22 22:37:12 +00001958 if (!RC) {
1959 // Make sure we find consecutive registers.
1960 NumAllocated = 0;
1961 continue;
1962 }
1963
1964 // Okay, this register is good, we can use it.
1965 ++NumAllocated;
1966
1967 // If we allocated enough consecutive
1968 if (NumAllocated == NumRegs) {
1969 unsigned RegStart = (i-NumAllocated)+1;
1970 unsigned RegEnd = i+1;
1971 // Mark all of the allocated registers used.
1972 for (unsigned i = RegStart; i != RegEnd; ++i) {
1973 unsigned Reg = RegClassRegs[i];
1974 Regs.push_back(Reg);
1975 if (isOutReg) OutputRegs.insert(Reg); // Mark reg used.
1976 if (isInReg) InputRegs.insert(Reg); // Mark reg used.
1977 }
1978
1979 return RegsForValue(Regs, *RC->vt_begin(), VT);
1980 }
1981 }
1982
1983 // Otherwise, we couldn't allocate enough registers for this.
1984 return RegsForValue();
Chris Lattner4e4b5762006-02-01 18:59:47 +00001985}
1986
Chris Lattner864635a2006-02-22 22:37:12 +00001987
Chris Lattnerce7518c2006-01-26 22:24:51 +00001988/// visitInlineAsm - Handle a call to an InlineAsm object.
1989///
1990void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
1991 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0));
1992
1993 SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
1994 MVT::Other);
1995
1996 // Note, we treat inline asms both with and without side-effects as the same.
1997 // If an inline asm doesn't have side effects and doesn't access memory, we
1998 // could not choose to not chain it.
1999 bool hasSideEffects = IA->hasSideEffects();
2000
Chris Lattner2cc2f662006-02-01 01:28:23 +00002001 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
Chris Lattner1efa40f2006-02-22 00:56:39 +00002002 std::vector<MVT::ValueType> ConstraintVTs;
Chris Lattnerce7518c2006-01-26 22:24:51 +00002003
2004 /// AsmNodeOperands - A list of pairs. The first element is a register, the
2005 /// second is a bitfield where bit #0 is set if it is a use and bit #1 is set
2006 /// if it is a def of that register.
2007 std::vector<SDOperand> AsmNodeOperands;
2008 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
2009 AsmNodeOperands.push_back(AsmStr);
2010
2011 SDOperand Chain = getRoot();
2012 SDOperand Flag;
2013
Chris Lattner4e4b5762006-02-01 18:59:47 +00002014 // We fully assign registers here at isel time. This is not optimal, but
2015 // should work. For register classes that correspond to LLVM classes, we
2016 // could let the LLVM RA do its thing, but we currently don't. Do a prepass
2017 // over the constraints, collecting fixed registers that we know we can't use.
2018 std::set<unsigned> OutputRegs, InputRegs;
Chris Lattner1efa40f2006-02-22 00:56:39 +00002019 unsigned OpNum = 1;
Chris Lattner4e4b5762006-02-01 18:59:47 +00002020 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2021 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2022 std::string &ConstraintCode = Constraints[i].Codes[0];
Chris Lattner2223aea2006-02-02 00:25:23 +00002023
Chris Lattner1efa40f2006-02-22 00:56:39 +00002024 MVT::ValueType OpVT;
2025
2026 // Compute the value type for each operand and add it to ConstraintVTs.
2027 switch (Constraints[i].Type) {
2028 case InlineAsm::isOutput:
2029 if (!Constraints[i].isIndirectOutput) {
2030 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2031 OpVT = TLI.getValueType(I.getType());
2032 } else {
Chris Lattner22873462006-02-27 23:45:39 +00002033 const Type *OpTy = I.getOperand(OpNum)->getType();
Chris Lattner1efa40f2006-02-22 00:56:39 +00002034 OpVT = TLI.getValueType(cast<PointerType>(OpTy)->getElementType());
2035 OpNum++; // Consumes a call operand.
2036 }
2037 break;
2038 case InlineAsm::isInput:
2039 OpVT = TLI.getValueType(I.getOperand(OpNum)->getType());
2040 OpNum++; // Consumes a call operand.
2041 break;
2042 case InlineAsm::isClobber:
2043 OpVT = MVT::Other;
2044 break;
2045 }
2046
2047 ConstraintVTs.push_back(OpVT);
2048
Chris Lattner864635a2006-02-22 22:37:12 +00002049 if (TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT).first == 0)
2050 continue; // Not assigned a fixed reg.
Chris Lattner1efa40f2006-02-22 00:56:39 +00002051
Chris Lattner864635a2006-02-22 22:37:12 +00002052 // Build a list of regs that this operand uses. This always has a single
2053 // element for promoted/expanded operands.
2054 RegsForValue Regs = GetRegistersForValue(ConstraintCode, OpVT,
2055 false, false,
2056 OutputRegs, InputRegs);
Chris Lattner4e4b5762006-02-01 18:59:47 +00002057
2058 switch (Constraints[i].Type) {
2059 case InlineAsm::isOutput:
2060 // We can't assign any other output to this register.
Chris Lattner864635a2006-02-22 22:37:12 +00002061 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
Chris Lattner4e4b5762006-02-01 18:59:47 +00002062 // If this is an early-clobber output, it cannot be assigned to the same
2063 // value as the input reg.
Chris Lattner2223aea2006-02-02 00:25:23 +00002064 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
Chris Lattner864635a2006-02-22 22:37:12 +00002065 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
Chris Lattner4e4b5762006-02-01 18:59:47 +00002066 break;
Chris Lattner1efa40f2006-02-22 00:56:39 +00002067 case InlineAsm::isInput:
2068 // We can't assign any other input to this register.
Chris Lattner864635a2006-02-22 22:37:12 +00002069 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
Chris Lattner1efa40f2006-02-22 00:56:39 +00002070 break;
Chris Lattner4e4b5762006-02-01 18:59:47 +00002071 case InlineAsm::isClobber:
2072 // Clobbered regs cannot be used as inputs or outputs.
Chris Lattner864635a2006-02-22 22:37:12 +00002073 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2074 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
Chris Lattner4e4b5762006-02-01 18:59:47 +00002075 break;
Chris Lattner4e4b5762006-02-01 18:59:47 +00002076 }
2077 }
Chris Lattner2cc2f662006-02-01 01:28:23 +00002078
Chris Lattner0f0b7d42006-02-21 23:12:12 +00002079 // Loop over all of the inputs, copying the operand values into the
2080 // appropriate registers and processing the output regs.
Chris Lattner864635a2006-02-22 22:37:12 +00002081 RegsForValue RetValRegs;
2082 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
Chris Lattner1efa40f2006-02-22 00:56:39 +00002083 OpNum = 1;
Chris Lattner0f0b7d42006-02-21 23:12:12 +00002084
Chris Lattner6656dd12006-01-31 02:03:41 +00002085 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
Chris Lattner2cc2f662006-02-01 01:28:23 +00002086 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2087 std::string &ConstraintCode = Constraints[i].Codes[0];
Chris Lattner1efa40f2006-02-22 00:56:39 +00002088
Chris Lattner2cc2f662006-02-01 01:28:23 +00002089 switch (Constraints[i].Type) {
2090 case InlineAsm::isOutput: {
Chris Lattner22873462006-02-27 23:45:39 +00002091 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2092 if (ConstraintCode.size() == 1) // not a physreg name.
2093 CTy = TLI.getConstraintType(ConstraintCode[0]);
2094
2095 if (CTy == TargetLowering::C_Memory) {
2096 // Memory output.
2097 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2098
2099 // Check that the operand (the address to store to) isn't a float.
2100 if (!MVT::isInteger(InOperandVal.getValueType()))
2101 assert(0 && "MATCH FAIL!");
2102
2103 if (!Constraints[i].isIndirectOutput)
2104 assert(0 && "MATCH FAIL!");
2105
2106 OpNum++; // Consumes a call operand.
2107
2108 // Extend/truncate to the right pointer type if needed.
2109 MVT::ValueType PtrType = TLI.getPointerTy();
2110 if (InOperandVal.getValueType() < PtrType)
2111 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2112 else if (InOperandVal.getValueType() > PtrType)
2113 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2114
2115 // Add information to the INLINEASM node to know about this output.
2116 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2117 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2118 AsmNodeOperands.push_back(InOperandVal);
2119 break;
2120 }
2121
2122 // Otherwise, this is a register output.
2123 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2124
Chris Lattner864635a2006-02-22 22:37:12 +00002125 // If this is an early-clobber output, or if there is an input
2126 // constraint that matches this, we need to reserve the input register
2127 // so no other inputs allocate to it.
2128 bool UsesInputRegister = false;
2129 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2130 UsesInputRegister = true;
2131
2132 // Copy the output from the appropriate register. Find a register that
Chris Lattner1efa40f2006-02-22 00:56:39 +00002133 // we can use.
Chris Lattner864635a2006-02-22 22:37:12 +00002134 RegsForValue Regs =
2135 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2136 true, UsesInputRegister,
2137 OutputRegs, InputRegs);
2138 assert(!Regs.Regs.empty() && "Couldn't allocate output reg!");
Chris Lattner1efa40f2006-02-22 00:56:39 +00002139
Chris Lattner2cc2f662006-02-01 01:28:23 +00002140 if (!Constraints[i].isIndirectOutput) {
Chris Lattner864635a2006-02-22 22:37:12 +00002141 assert(RetValRegs.Regs.empty() &&
Chris Lattner2cc2f662006-02-01 01:28:23 +00002142 "Cannot have multiple output constraints yet!");
Chris Lattner2cc2f662006-02-01 01:28:23 +00002143 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
Chris Lattner864635a2006-02-22 22:37:12 +00002144 RetValRegs = Regs;
Chris Lattner2cc2f662006-02-01 01:28:23 +00002145 } else {
Chris Lattner22873462006-02-27 23:45:39 +00002146 IndirectStoresToEmit.push_back(std::make_pair(Regs,
2147 I.getOperand(OpNum)));
Chris Lattner2cc2f662006-02-01 01:28:23 +00002148 OpNum++; // Consumes a call operand.
2149 }
Chris Lattner6656dd12006-01-31 02:03:41 +00002150
2151 // Add information to the INLINEASM node to know that this register is
2152 // set.
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00002153 Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands);
Chris Lattner6656dd12006-01-31 02:03:41 +00002154 break;
2155 }
2156 case InlineAsm::isInput: {
Chris Lattner22873462006-02-27 23:45:39 +00002157 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
Chris Lattner4e4b5762006-02-01 18:59:47 +00002158 OpNum++; // Consumes a call operand.
Chris Lattner3d81fee2006-02-04 02:16:44 +00002159
Chris Lattner2223aea2006-02-02 00:25:23 +00002160 if (isdigit(ConstraintCode[0])) { // Matching constraint?
2161 // If this is required to match an output register we have already set,
2162 // just use its register.
2163 unsigned OperandNo = atoi(ConstraintCode.c_str());
Chris Lattner3d81fee2006-02-04 02:16:44 +00002164
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00002165 // Scan until we find the definition we already emitted of this operand.
2166 // When we find it, create a RegsForValue operand.
2167 unsigned CurOp = 2; // The first operand.
2168 for (; OperandNo; --OperandNo) {
2169 // Advance to the next operand.
2170 unsigned NumOps =
2171 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
Chris Lattnera15cf702006-07-20 19:02:21 +00002172 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
2173 (NumOps & 7) == 4 /*MEM*/) &&
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00002174 "Skipped past definitions?");
2175 CurOp += (NumOps>>3)+1;
2176 }
2177
2178 unsigned NumOps =
2179 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2180 assert((NumOps & 7) == 2 /*REGDEF*/ &&
2181 "Skipped past definitions?");
2182
2183 // Add NumOps>>3 registers to MatchedRegs.
2184 RegsForValue MatchedRegs;
2185 MatchedRegs.ValueVT = InOperandVal.getValueType();
2186 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
2187 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
2188 unsigned Reg=cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
2189 MatchedRegs.Regs.push_back(Reg);
2190 }
2191
2192 // Use the produced MatchedRegs object to
Evan Chenga8441262006-06-15 08:11:54 +00002193 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag,
2194 TLI.getPointerTy());
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00002195 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00002196 break;
Chris Lattner2223aea2006-02-02 00:25:23 +00002197 }
Chris Lattner87bc3bd2006-02-24 01:11:24 +00002198
2199 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2200 if (ConstraintCode.size() == 1) // not a physreg name.
2201 CTy = TLI.getConstraintType(ConstraintCode[0]);
2202
2203 if (CTy == TargetLowering::C_Other) {
2204 if (!TLI.isOperandValidForConstraint(InOperandVal, ConstraintCode[0]))
2205 assert(0 && "MATCH FAIL!");
2206
2207 // Add information to the INLINEASM node to know about this input.
2208 unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
2209 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2210 AsmNodeOperands.push_back(InOperandVal);
2211 break;
2212 } else if (CTy == TargetLowering::C_Memory) {
2213 // Memory input.
2214
2215 // Check that the operand isn't a float.
2216 if (!MVT::isInteger(InOperandVal.getValueType()))
2217 assert(0 && "MATCH FAIL!");
2218
2219 // Extend/truncate to the right pointer type if needed.
2220 MVT::ValueType PtrType = TLI.getPointerTy();
2221 if (InOperandVal.getValueType() < PtrType)
2222 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2223 else if (InOperandVal.getValueType() > PtrType)
2224 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2225
2226 // Add information to the INLINEASM node to know about this input.
2227 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2228 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2229 AsmNodeOperands.push_back(InOperandVal);
2230 break;
2231 }
2232
2233 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2234
2235 // Copy the input into the appropriate registers.
2236 RegsForValue InRegs =
2237 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2238 false, true, OutputRegs, InputRegs);
2239 // FIXME: should be match fail.
2240 assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!");
2241
Evan Chenga8441262006-06-15 08:11:54 +00002242 InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, TLI.getPointerTy());
Chris Lattner87bc3bd2006-02-24 01:11:24 +00002243
2244 InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands);
Chris Lattner6656dd12006-01-31 02:03:41 +00002245 break;
2246 }
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00002247 case InlineAsm::isClobber: {
2248 RegsForValue ClobberedRegs =
2249 GetRegistersForValue(ConstraintCode, MVT::Other, false, false,
2250 OutputRegs, InputRegs);
2251 // Add the clobbered value to the operand list, so that the register
2252 // allocator is aware that the physreg got clobbered.
2253 if (!ClobberedRegs.Regs.empty())
2254 ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands);
Chris Lattner6656dd12006-01-31 02:03:41 +00002255 break;
2256 }
Chris Lattnerc3a9f8d2006-02-23 19:21:04 +00002257 }
Chris Lattner6656dd12006-01-31 02:03:41 +00002258 }
Chris Lattnerce7518c2006-01-26 22:24:51 +00002259
2260 // Finish up input operands.
2261 AsmNodeOperands[0] = Chain;
2262 if (Flag.Val) AsmNodeOperands.push_back(Flag);
2263
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00002264 Chain = DAG.getNode(ISD::INLINEASM,
2265 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002266 &AsmNodeOperands[0], AsmNodeOperands.size());
Chris Lattnerce7518c2006-01-26 22:24:51 +00002267 Flag = Chain.getValue(1);
2268
Chris Lattner6656dd12006-01-31 02:03:41 +00002269 // If this asm returns a register value, copy the result from that register
2270 // and set it as the value of the call.
Chris Lattner864635a2006-02-22 22:37:12 +00002271 if (!RetValRegs.Regs.empty())
2272 setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag));
Chris Lattnerce7518c2006-01-26 22:24:51 +00002273
Chris Lattner6656dd12006-01-31 02:03:41 +00002274 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
2275
2276 // Process indirect outputs, first output all of the flagged copies out of
2277 // physregs.
2278 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
Chris Lattner864635a2006-02-22 22:37:12 +00002279 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
Chris Lattner6656dd12006-01-31 02:03:41 +00002280 Value *Ptr = IndirectStoresToEmit[i].second;
Chris Lattner864635a2006-02-22 22:37:12 +00002281 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag);
2282 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
Chris Lattner6656dd12006-01-31 02:03:41 +00002283 }
2284
2285 // Emit the non-flagged stores from the physregs.
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002286 SmallVector<SDOperand, 8> OutChains;
Chris Lattner6656dd12006-01-31 02:03:41 +00002287 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
Evan Cheng786225a2006-10-05 23:01:46 +00002288 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
Chris Lattner6656dd12006-01-31 02:03:41 +00002289 getValue(StoresToEmit[i].second),
2290 DAG.getSrcValue(StoresToEmit[i].second)));
2291 if (!OutChains.empty())
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002292 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2293 &OutChains[0], OutChains.size());
Chris Lattnerce7518c2006-01-26 22:24:51 +00002294 DAG.setRoot(Chain);
2295}
2296
2297
Chris Lattner1c08c712005-01-07 07:47:53 +00002298void SelectionDAGLowering::visitMalloc(MallocInst &I) {
2299 SDOperand Src = getValue(I.getOperand(0));
2300
2301 MVT::ValueType IntPtr = TLI.getPointerTy();
Chris Lattner68cd65e2005-01-22 23:04:37 +00002302
2303 if (IntPtr < Src.getValueType())
2304 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
2305 else if (IntPtr > Src.getValueType())
2306 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
Chris Lattner1c08c712005-01-07 07:47:53 +00002307
2308 // Scale the source by the type size.
Owen Andersona69571c2006-05-03 01:29:57 +00002309 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType());
Chris Lattner1c08c712005-01-07 07:47:53 +00002310 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
2311 Src, getIntPtrConstant(ElementSize));
2312
2313 std::vector<std::pair<SDOperand, const Type*> > Args;
Owen Andersona69571c2006-05-03 01:29:57 +00002314 Args.push_back(std::make_pair(Src, TLI.getTargetData()->getIntPtrType()));
Chris Lattnercf5734d2005-01-08 19:26:18 +00002315
2316 std::pair<SDOperand,SDOperand> Result =
Chris Lattneradf6a962005-05-13 18:50:42 +00002317 TLI.LowerCallTo(getRoot(), I.getType(), false, CallingConv::C, true,
Chris Lattnercf5734d2005-01-08 19:26:18 +00002318 DAG.getExternalSymbol("malloc", IntPtr),
2319 Args, DAG);
2320 setValue(&I, Result.first); // Pointers always fit in registers
2321 DAG.setRoot(Result.second);
Chris Lattner1c08c712005-01-07 07:47:53 +00002322}
2323
2324void SelectionDAGLowering::visitFree(FreeInst &I) {
2325 std::vector<std::pair<SDOperand, const Type*> > Args;
2326 Args.push_back(std::make_pair(getValue(I.getOperand(0)),
Owen Andersona69571c2006-05-03 01:29:57 +00002327 TLI.getTargetData()->getIntPtrType()));
Chris Lattner1c08c712005-01-07 07:47:53 +00002328 MVT::ValueType IntPtr = TLI.getPointerTy();
Chris Lattnercf5734d2005-01-08 19:26:18 +00002329 std::pair<SDOperand,SDOperand> Result =
Chris Lattneradf6a962005-05-13 18:50:42 +00002330 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, CallingConv::C, true,
Chris Lattnercf5734d2005-01-08 19:26:18 +00002331 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
2332 DAG.setRoot(Result.second);
Chris Lattner1c08c712005-01-07 07:47:53 +00002333}
2334
Chris Lattner025c39b2005-08-26 20:54:47 +00002335// InsertAtEndOfBasicBlock - This method should be implemented by targets that
2336// mark instructions with the 'usesCustomDAGSchedInserter' flag. These
2337// instructions are special in various ways, which require special support to
2338// insert. The specified MachineInstr is created but not inserted into any
2339// basic blocks, and the scheduler passes ownership of it to this method.
2340MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2341 MachineBasicBlock *MBB) {
2342 std::cerr << "If a target marks an instruction with "
2343 "'usesCustomDAGSchedInserter', it must implement "
2344 "TargetLowering::InsertAtEndOfBasicBlock!\n";
2345 abort();
2346 return 0;
2347}
2348
Chris Lattner39ae3622005-01-09 00:00:49 +00002349void SelectionDAGLowering::visitVAStart(CallInst &I) {
Nate Begemanacc398c2006-01-25 18:21:52 +00002350 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
2351 getValue(I.getOperand(1)),
2352 DAG.getSrcValue(I.getOperand(1))));
Chris Lattner39ae3622005-01-09 00:00:49 +00002353}
2354
2355void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
Nate Begemanacc398c2006-01-25 18:21:52 +00002356 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
2357 getValue(I.getOperand(0)),
2358 DAG.getSrcValue(I.getOperand(0)));
2359 setValue(&I, V);
2360 DAG.setRoot(V.getValue(1));
Chris Lattner1c08c712005-01-07 07:47:53 +00002361}
2362
2363void SelectionDAGLowering::visitVAEnd(CallInst &I) {
Nate Begemanacc398c2006-01-25 18:21:52 +00002364 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
2365 getValue(I.getOperand(1)),
2366 DAG.getSrcValue(I.getOperand(1))));
Chris Lattner1c08c712005-01-07 07:47:53 +00002367}
2368
2369void SelectionDAGLowering::visitVACopy(CallInst &I) {
Nate Begemanacc398c2006-01-25 18:21:52 +00002370 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
2371 getValue(I.getOperand(1)),
2372 getValue(I.getOperand(2)),
2373 DAG.getSrcValue(I.getOperand(1)),
2374 DAG.getSrcValue(I.getOperand(2))));
Chris Lattner1c08c712005-01-07 07:47:53 +00002375}
2376
Chris Lattnerfdfded52006-04-12 16:20:43 +00002377/// TargetLowering::LowerArguments - This is the default LowerArguments
2378/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
Chris Lattnerf4ec8172006-05-16 22:53:20 +00002379/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
2380/// integrated into SDISel.
Chris Lattnerfdfded52006-04-12 16:20:43 +00002381std::vector<SDOperand>
2382TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
2383 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
2384 std::vector<SDOperand> Ops;
Chris Lattner8c0c10c2006-05-16 06:45:34 +00002385 Ops.push_back(DAG.getRoot());
Chris Lattnerfdfded52006-04-12 16:20:43 +00002386 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
2387 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
2388
2389 // Add one result value for each formal argument.
2390 std::vector<MVT::ValueType> RetVals;
2391 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2392 MVT::ValueType VT = getValueType(I->getType());
2393
2394 switch (getTypeAction(VT)) {
2395 default: assert(0 && "Unknown type action!");
2396 case Legal:
2397 RetVals.push_back(VT);
2398 break;
2399 case Promote:
2400 RetVals.push_back(getTypeToTransformTo(VT));
2401 break;
2402 case Expand:
2403 if (VT != MVT::Vector) {
2404 // If this is a large integer, it needs to be broken up into small
2405 // integers. Figure out what the destination type is and how many small
2406 // integers it turns into.
2407 MVT::ValueType NVT = getTypeToTransformTo(VT);
2408 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2409 for (unsigned i = 0; i != NumVals; ++i)
2410 RetVals.push_back(NVT);
2411 } else {
2412 // Otherwise, this is a vector type. We only support legal vectors
2413 // right now.
2414 unsigned NumElems = cast<PackedType>(I->getType())->getNumElements();
2415 const Type *EltTy = cast<PackedType>(I->getType())->getElementType();
Evan Chengf7179bb2006-04-27 08:29:42 +00002416
Chris Lattnerfdfded52006-04-12 16:20:43 +00002417 // Figure out if there is a Packed type corresponding to this Vector
2418 // type. If so, convert to the packed type.
2419 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2420 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2421 RetVals.push_back(TVT);
2422 } else {
2423 assert(0 && "Don't support illegal by-val vector arguments yet!");
2424 }
2425 }
2426 break;
2427 }
2428 }
Evan Cheng3b0d2862006-04-25 23:03:35 +00002429
Chris Lattner8c0c10c2006-05-16 06:45:34 +00002430 RetVals.push_back(MVT::Other);
Chris Lattnerfdfded52006-04-12 16:20:43 +00002431
2432 // Create the node.
Chris Lattnerf9f37fc2006-08-14 23:53:35 +00002433 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
2434 DAG.getNodeValueTypes(RetVals), RetVals.size(),
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002435 &Ops[0], Ops.size()).Val;
Chris Lattner8c0c10c2006-05-16 06:45:34 +00002436
2437 DAG.setRoot(SDOperand(Result, Result->getNumValues()-1));
Chris Lattnerfdfded52006-04-12 16:20:43 +00002438
2439 // Set up the return result vector.
2440 Ops.clear();
2441 unsigned i = 0;
2442 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2443 MVT::ValueType VT = getValueType(I->getType());
2444
2445 switch (getTypeAction(VT)) {
2446 default: assert(0 && "Unknown type action!");
2447 case Legal:
2448 Ops.push_back(SDOperand(Result, i++));
2449 break;
2450 case Promote: {
2451 SDOperand Op(Result, i++);
2452 if (MVT::isInteger(VT)) {
2453 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
2454 : ISD::AssertZext;
2455 Op = DAG.getNode(AssertOp, Op.getValueType(), Op, DAG.getValueType(VT));
2456 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2457 } else {
2458 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2459 Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
2460 }
2461 Ops.push_back(Op);
2462 break;
2463 }
2464 case Expand:
2465 if (VT != MVT::Vector) {
2466 // If this is a large integer, it needs to be reassembled from small
2467 // integers. Figure out what the source elt type is and how many small
2468 // integers it is.
2469 MVT::ValueType NVT = getTypeToTransformTo(VT);
2470 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2471 if (NumVals == 2) {
2472 SDOperand Lo = SDOperand(Result, i++);
2473 SDOperand Hi = SDOperand(Result, i++);
2474
2475 if (!isLittleEndian())
2476 std::swap(Lo, Hi);
2477
2478 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi));
2479 } else {
2480 // Value scalarized into many values. Unimp for now.
2481 assert(0 && "Cannot expand i64 -> i16 yet!");
2482 }
2483 } else {
2484 // Otherwise, this is a vector type. We only support legal vectors
2485 // right now.
Evan Cheng020c41f2006-04-28 05:25:15 +00002486 const PackedType *PTy = cast<PackedType>(I->getType());
2487 unsigned NumElems = PTy->getNumElements();
2488 const Type *EltTy = PTy->getElementType();
Evan Chengf7179bb2006-04-27 08:29:42 +00002489
Chris Lattnerfdfded52006-04-12 16:20:43 +00002490 // Figure out if there is a Packed type corresponding to this Vector
2491 // type. If so, convert to the packed type.
2492 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
Chris Lattnerd202ca42006-05-17 20:49:36 +00002493 if (TVT != MVT::Other && isTypeLegal(TVT)) {
Evan Cheng020c41f2006-04-28 05:25:15 +00002494 SDOperand N = SDOperand(Result, i++);
2495 // Handle copies from generic vectors to registers.
Chris Lattnerd202ca42006-05-17 20:49:36 +00002496 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
2497 DAG.getConstant(NumElems, MVT::i32),
2498 DAG.getValueType(getValueType(EltTy)));
2499 Ops.push_back(N);
2500 } else {
Chris Lattnerfdfded52006-04-12 16:20:43 +00002501 assert(0 && "Don't support illegal by-val vector arguments yet!");
Chris Lattnerda098e72006-05-16 23:39:44 +00002502 abort();
Chris Lattnerfdfded52006-04-12 16:20:43 +00002503 }
2504 }
2505 break;
2506 }
2507 }
2508 return Ops;
2509}
2510
Chris Lattnerf4ec8172006-05-16 22:53:20 +00002511
2512/// TargetLowering::LowerCallTo - This is the default LowerCallTo
2513/// implementation, which just inserts an ISD::CALL node, which is later custom
2514/// lowered by the target to something concrete. FIXME: When all targets are
2515/// migrated to using ISD::CALL, this hook should be integrated into SDISel.
2516std::pair<SDOperand, SDOperand>
2517TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
2518 unsigned CallingConv, bool isTailCall,
2519 SDOperand Callee,
2520 ArgListTy &Args, SelectionDAG &DAG) {
Chris Lattnerbe384162006-08-16 22:57:46 +00002521 SmallVector<SDOperand, 32> Ops;
Chris Lattnerf4ec8172006-05-16 22:53:20 +00002522 Ops.push_back(Chain); // Op#0 - Chain
2523 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
2524 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
2525 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
2526 Ops.push_back(Callee);
2527
2528 // Handle all of the outgoing arguments.
2529 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
2530 MVT::ValueType VT = getValueType(Args[i].second);
2531 SDOperand Op = Args[i].first;
Evan Chengf6d62c22006-05-25 00:55:32 +00002532 bool isSigned = Args[i].second->isSigned();
Chris Lattnerf4ec8172006-05-16 22:53:20 +00002533 switch (getTypeAction(VT)) {
2534 default: assert(0 && "Unknown type action!");
2535 case Legal:
2536 Ops.push_back(Op);
Evan Chengd61c4822006-05-26 23:13:20 +00002537 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
Chris Lattnerf4ec8172006-05-16 22:53:20 +00002538 break;
2539 case Promote:
2540 if (MVT::isInteger(VT)) {
Evan Chengf6d62c22006-05-25 00:55:32 +00002541 unsigned ExtOp = isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
Chris Lattnerf4ec8172006-05-16 22:53:20 +00002542 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
2543 } else {
2544 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2545 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
2546 }
2547 Ops.push_back(Op);
Evan Chengd61c4822006-05-26 23:13:20 +00002548 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
Chris Lattnerf4ec8172006-05-16 22:53:20 +00002549 break;
2550 case Expand:
2551 if (VT != MVT::Vector) {
2552 // If this is a large integer, it needs to be broken down into small
2553 // integers. Figure out what the source elt type is and how many small
2554 // integers it is.
2555 MVT::ValueType NVT = getTypeToTransformTo(VT);
2556 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2557 if (NumVals == 2) {
2558 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
2559 DAG.getConstant(0, getPointerTy()));
2560 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
2561 DAG.getConstant(1, getPointerTy()));
2562 if (!isLittleEndian())
2563 std::swap(Lo, Hi);
2564
2565 Ops.push_back(Lo);
Evan Chengd61c4822006-05-26 23:13:20 +00002566 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
Chris Lattnerf4ec8172006-05-16 22:53:20 +00002567 Ops.push_back(Hi);
Evan Chengd61c4822006-05-26 23:13:20 +00002568 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
Chris Lattnerf4ec8172006-05-16 22:53:20 +00002569 } else {
2570 // Value scalarized into many values. Unimp for now.
2571 assert(0 && "Cannot expand i64 -> i16 yet!");
2572 }
2573 } else {
Chris Lattnerda098e72006-05-16 23:39:44 +00002574 // Otherwise, this is a vector type. We only support legal vectors
2575 // right now.
2576 const PackedType *PTy = cast<PackedType>(Args[i].second);
2577 unsigned NumElems = PTy->getNumElements();
2578 const Type *EltTy = PTy->getElementType();
2579
2580 // Figure out if there is a Packed type corresponding to this Vector
2581 // type. If so, convert to the packed type.
2582 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
Chris Lattner1b8daae2006-05-17 20:43:21 +00002583 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2584 // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type.
2585 Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op);
2586 Ops.push_back(Op);
Evan Chengd61c4822006-05-26 23:13:20 +00002587 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
Chris Lattner1b8daae2006-05-17 20:43:21 +00002588 } else {
Chris Lattnerda098e72006-05-16 23:39:44 +00002589 assert(0 && "Don't support illegal by-val vector call args yet!");
2590 abort();
2591 }
Chris Lattnerf4ec8172006-05-16 22:53:20 +00002592 }
2593 break;
2594 }
2595 }
2596
2597 // Figure out the result value types.
Chris Lattnerbe384162006-08-16 22:57:46 +00002598 SmallVector<MVT::ValueType, 4> RetTys;
Chris Lattnerf4ec8172006-05-16 22:53:20 +00002599
2600 if (RetTy != Type::VoidTy) {
2601 MVT::ValueType VT = getValueType(RetTy);
2602 switch (getTypeAction(VT)) {
2603 default: assert(0 && "Unknown type action!");
2604 case Legal:
2605 RetTys.push_back(VT);
2606 break;
2607 case Promote:
2608 RetTys.push_back(getTypeToTransformTo(VT));
2609 break;
2610 case Expand:
2611 if (VT != MVT::Vector) {
2612 // If this is a large integer, it needs to be reassembled from small
2613 // integers. Figure out what the source elt type is and how many small
2614 // integers it is.
2615 MVT::ValueType NVT = getTypeToTransformTo(VT);
2616 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2617 for (unsigned i = 0; i != NumVals; ++i)
2618 RetTys.push_back(NVT);
2619 } else {
Chris Lattnerda098e72006-05-16 23:39:44 +00002620 // Otherwise, this is a vector type. We only support legal vectors
2621 // right now.
2622 const PackedType *PTy = cast<PackedType>(RetTy);
2623 unsigned NumElems = PTy->getNumElements();
2624 const Type *EltTy = PTy->getElementType();
2625
2626 // Figure out if there is a Packed type corresponding to this Vector
2627 // type. If so, convert to the packed type.
2628 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2629 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2630 RetTys.push_back(TVT);
2631 } else {
2632 assert(0 && "Don't support illegal by-val vector call results yet!");
2633 abort();
2634 }
Chris Lattnerf4ec8172006-05-16 22:53:20 +00002635 }
2636 }
2637 }
2638
2639 RetTys.push_back(MVT::Other); // Always has a chain.
2640
2641 // Finally, create the CALL node.
Chris Lattnerbe384162006-08-16 22:57:46 +00002642 SDOperand Res = DAG.getNode(ISD::CALL,
2643 DAG.getVTList(&RetTys[0], RetTys.size()),
2644 &Ops[0], Ops.size());
Chris Lattnerf4ec8172006-05-16 22:53:20 +00002645
2646 // This returns a pair of operands. The first element is the
2647 // return value for the function (if RetTy is not VoidTy). The second
2648 // element is the outgoing token chain.
2649 SDOperand ResVal;
2650 if (RetTys.size() != 1) {
2651 MVT::ValueType VT = getValueType(RetTy);
2652 if (RetTys.size() == 2) {
2653 ResVal = Res;
2654
2655 // If this value was promoted, truncate it down.
2656 if (ResVal.getValueType() != VT) {
Chris Lattnerda098e72006-05-16 23:39:44 +00002657 if (VT == MVT::Vector) {
2658 // Insert a VBITCONVERT to convert from the packed result type to the
2659 // MVT::Vector type.
2660 unsigned NumElems = cast<PackedType>(RetTy)->getNumElements();
2661 const Type *EltTy = cast<PackedType>(RetTy)->getElementType();
2662
2663 // Figure out if there is a Packed type corresponding to this Vector
2664 // type. If so, convert to the packed type.
2665 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2666 if (TVT != MVT::Other && isTypeLegal(TVT)) {
Chris Lattnerda098e72006-05-16 23:39:44 +00002667 // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a
2668 // "N x PTyElementVT" MVT::Vector type.
2669 ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal,
Chris Lattnerd202ca42006-05-17 20:49:36 +00002670 DAG.getConstant(NumElems, MVT::i32),
2671 DAG.getValueType(getValueType(EltTy)));
Chris Lattnerda098e72006-05-16 23:39:44 +00002672 } else {
2673 abort();
2674 }
2675 } else if (MVT::isInteger(VT)) {
Chris Lattnerf4ec8172006-05-16 22:53:20 +00002676 unsigned AssertOp = RetTy->isSigned() ?
2677 ISD::AssertSext : ISD::AssertZext;
2678 ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal,
2679 DAG.getValueType(VT));
2680 ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal);
2681 } else {
2682 assert(MVT::isFloatingPoint(VT));
2683 ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal);
2684 }
2685 }
2686 } else if (RetTys.size() == 3) {
2687 ResVal = DAG.getNode(ISD::BUILD_PAIR, VT,
2688 Res.getValue(0), Res.getValue(1));
2689
2690 } else {
2691 assert(0 && "Case not handled yet!");
2692 }
2693 }
2694
2695 return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1));
2696}
2697
2698
2699
Chris Lattner39ae3622005-01-09 00:00:49 +00002700// It is always conservatively correct for llvm.returnaddress and
2701// llvm.frameaddress to return 0.
Chris Lattnerf4ec8172006-05-16 22:53:20 +00002702//
2703// FIXME: Change this to insert a FRAMEADDR/RETURNADDR node, and have that be
2704// expanded to 0 if the target wants.
Chris Lattner39ae3622005-01-09 00:00:49 +00002705std::pair<SDOperand, SDOperand>
2706TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain,
2707 unsigned Depth, SelectionDAG &DAG) {
2708 return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain);
Chris Lattner1c08c712005-01-07 07:47:53 +00002709}
2710
Chris Lattner50381b62005-05-14 05:50:48 +00002711SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
Chris Lattner171453a2005-01-16 07:28:41 +00002712 assert(0 && "LowerOperation not implemented for this target!");
2713 abort();
Misha Brukmand3f03e42005-02-17 21:39:27 +00002714 return SDOperand();
Chris Lattner171453a2005-01-16 07:28:41 +00002715}
2716
Nate Begeman0aed7842006-01-28 03:14:31 +00002717SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
2718 SelectionDAG &DAG) {
2719 assert(0 && "CustomPromoteOperation not implemented for this target!");
2720 abort();
2721 return SDOperand();
2722}
2723
Chris Lattner39ae3622005-01-09 00:00:49 +00002724void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) {
2725 unsigned Depth = (unsigned)cast<ConstantUInt>(I.getOperand(1))->getValue();
2726 std::pair<SDOperand,SDOperand> Result =
Chris Lattnera651cf62005-01-17 19:43:36 +00002727 TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG);
Chris Lattner39ae3622005-01-09 00:00:49 +00002728 setValue(&I, Result.first);
2729 DAG.setRoot(Result.second);
Chris Lattner1c08c712005-01-07 07:47:53 +00002730}
2731
Evan Cheng74d0aa92006-02-15 21:59:04 +00002732/// getMemsetValue - Vectorized representation of the memset value
Evan Cheng1db92f92006-02-14 08:22:34 +00002733/// operand.
2734static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
Evan Chenga47876d2006-02-15 22:12:35 +00002735 SelectionDAG &DAG) {
Evan Cheng1db92f92006-02-14 08:22:34 +00002736 MVT::ValueType CurVT = VT;
2737 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
2738 uint64_t Val = C->getValue() & 255;
2739 unsigned Shift = 8;
2740 while (CurVT != MVT::i8) {
2741 Val = (Val << Shift) | Val;
2742 Shift <<= 1;
2743 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
Evan Cheng1db92f92006-02-14 08:22:34 +00002744 }
2745 return DAG.getConstant(Val, VT);
2746 } else {
2747 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
2748 unsigned Shift = 8;
2749 while (CurVT != MVT::i8) {
2750 Value =
2751 DAG.getNode(ISD::OR, VT,
2752 DAG.getNode(ISD::SHL, VT, Value,
2753 DAG.getConstant(Shift, MVT::i8)), Value);
2754 Shift <<= 1;
2755 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
Evan Cheng1db92f92006-02-14 08:22:34 +00002756 }
2757
2758 return Value;
2759 }
2760}
2761
Evan Cheng74d0aa92006-02-15 21:59:04 +00002762/// getMemsetStringVal - Similar to getMemsetValue. Except this is only
2763/// used when a memcpy is turned into a memset when the source is a constant
2764/// string ptr.
2765static SDOperand getMemsetStringVal(MVT::ValueType VT,
2766 SelectionDAG &DAG, TargetLowering &TLI,
2767 std::string &Str, unsigned Offset) {
2768 MVT::ValueType CurVT = VT;
2769 uint64_t Val = 0;
2770 unsigned MSB = getSizeInBits(VT) / 8;
2771 if (TLI.isLittleEndian())
2772 Offset = Offset + MSB - 1;
2773 for (unsigned i = 0; i != MSB; ++i) {
2774 Val = (Val << 8) | Str[Offset];
2775 Offset += TLI.isLittleEndian() ? -1 : 1;
2776 }
2777 return DAG.getConstant(Val, VT);
2778}
2779
Evan Cheng1db92f92006-02-14 08:22:34 +00002780/// getMemBasePlusOffset - Returns base and offset node for the
2781static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
2782 SelectionDAG &DAG, TargetLowering &TLI) {
2783 MVT::ValueType VT = Base.getValueType();
2784 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
2785}
2786
Evan Chengc4f8eee2006-02-14 20:12:38 +00002787/// MeetsMaxMemopRequirement - Determines if the number of memory ops required
Evan Cheng80e89d72006-02-14 09:11:59 +00002788/// to replace the memset / memcpy is below the threshold. It also returns the
2789/// types of the sequence of memory ops to perform memset / memcpy.
Evan Chengc4f8eee2006-02-14 20:12:38 +00002790static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
2791 unsigned Limit, uint64_t Size,
2792 unsigned Align, TargetLowering &TLI) {
Evan Cheng1db92f92006-02-14 08:22:34 +00002793 MVT::ValueType VT;
2794
2795 if (TLI.allowsUnalignedMemoryAccesses()) {
2796 VT = MVT::i64;
2797 } else {
2798 switch (Align & 7) {
2799 case 0:
2800 VT = MVT::i64;
2801 break;
2802 case 4:
2803 VT = MVT::i32;
2804 break;
2805 case 2:
2806 VT = MVT::i16;
2807 break;
2808 default:
2809 VT = MVT::i8;
2810 break;
2811 }
2812 }
2813
Evan Cheng80e89d72006-02-14 09:11:59 +00002814 MVT::ValueType LVT = MVT::i64;
2815 while (!TLI.isTypeLegal(LVT))
2816 LVT = (MVT::ValueType)((unsigned)LVT - 1);
2817 assert(MVT::isInteger(LVT));
Evan Cheng1db92f92006-02-14 08:22:34 +00002818
Evan Cheng80e89d72006-02-14 09:11:59 +00002819 if (VT > LVT)
2820 VT = LVT;
2821
Evan Chengdea72452006-02-14 23:05:54 +00002822 unsigned NumMemOps = 0;
Evan Cheng1db92f92006-02-14 08:22:34 +00002823 while (Size != 0) {
2824 unsigned VTSize = getSizeInBits(VT) / 8;
2825 while (VTSize > Size) {
2826 VT = (MVT::ValueType)((unsigned)VT - 1);
Evan Cheng1db92f92006-02-14 08:22:34 +00002827 VTSize >>= 1;
2828 }
Evan Cheng80e89d72006-02-14 09:11:59 +00002829 assert(MVT::isInteger(VT));
2830
2831 if (++NumMemOps > Limit)
2832 return false;
Evan Cheng1db92f92006-02-14 08:22:34 +00002833 MemOps.push_back(VT);
2834 Size -= VTSize;
2835 }
Evan Cheng80e89d72006-02-14 09:11:59 +00002836
2837 return true;
Evan Cheng1db92f92006-02-14 08:22:34 +00002838}
2839
Chris Lattner7041ee32005-01-11 05:56:49 +00002840void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
Evan Cheng1db92f92006-02-14 08:22:34 +00002841 SDOperand Op1 = getValue(I.getOperand(1));
2842 SDOperand Op2 = getValue(I.getOperand(2));
2843 SDOperand Op3 = getValue(I.getOperand(3));
2844 SDOperand Op4 = getValue(I.getOperand(4));
2845 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
2846 if (Align == 0) Align = 1;
2847
2848 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
2849 std::vector<MVT::ValueType> MemOps;
Evan Cheng1db92f92006-02-14 08:22:34 +00002850
2851 // Expand memset / memcpy to a series of load / store ops
2852 // if the size operand falls below a certain threshold.
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002853 SmallVector<SDOperand, 8> OutChains;
Evan Cheng1db92f92006-02-14 08:22:34 +00002854 switch (Op) {
Evan Chengac940ab2006-02-14 19:45:56 +00002855 default: break; // Do nothing for now.
Evan Cheng1db92f92006-02-14 08:22:34 +00002856 case ISD::MEMSET: {
Evan Chengc4f8eee2006-02-14 20:12:38 +00002857 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
2858 Size->getValue(), Align, TLI)) {
Evan Cheng80e89d72006-02-14 09:11:59 +00002859 unsigned NumMemOps = MemOps.size();
Evan Cheng1db92f92006-02-14 08:22:34 +00002860 unsigned Offset = 0;
2861 for (unsigned i = 0; i < NumMemOps; i++) {
2862 MVT::ValueType VT = MemOps[i];
2863 unsigned VTSize = getSizeInBits(VT) / 8;
Evan Chenga47876d2006-02-15 22:12:35 +00002864 SDOperand Value = getMemsetValue(Op2, VT, DAG);
Evan Cheng786225a2006-10-05 23:01:46 +00002865 SDOperand Store = DAG.getStore(getRoot(), Value,
Chris Lattner864635a2006-02-22 22:37:12 +00002866 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
2867 DAG.getSrcValue(I.getOperand(1), Offset));
Evan Chengc080d6f2006-02-15 01:54:51 +00002868 OutChains.push_back(Store);
Evan Cheng1db92f92006-02-14 08:22:34 +00002869 Offset += VTSize;
2870 }
Evan Cheng1db92f92006-02-14 08:22:34 +00002871 }
Evan Chengc080d6f2006-02-15 01:54:51 +00002872 break;
Evan Cheng1db92f92006-02-14 08:22:34 +00002873 }
Evan Chengc080d6f2006-02-15 01:54:51 +00002874 case ISD::MEMCPY: {
2875 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
2876 Size->getValue(), Align, TLI)) {
2877 unsigned NumMemOps = MemOps.size();
Evan Chengcffbb512006-02-16 23:11:42 +00002878 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
Evan Cheng74d0aa92006-02-15 21:59:04 +00002879 GlobalAddressSDNode *G = NULL;
2880 std::string Str;
Evan Chengcffbb512006-02-16 23:11:42 +00002881 bool CopyFromStr = false;
Evan Cheng74d0aa92006-02-15 21:59:04 +00002882
2883 if (Op2.getOpcode() == ISD::GlobalAddress)
2884 G = cast<GlobalAddressSDNode>(Op2);
2885 else if (Op2.getOpcode() == ISD::ADD &&
2886 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
2887 Op2.getOperand(1).getOpcode() == ISD::Constant) {
2888 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
Evan Chengcffbb512006-02-16 23:11:42 +00002889 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
Evan Cheng74d0aa92006-02-15 21:59:04 +00002890 }
2891 if (G) {
2892 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
Evan Chengcffbb512006-02-16 23:11:42 +00002893 if (GV) {
Evan Cheng09371032006-03-10 23:52:03 +00002894 Str = GV->getStringValue(false);
Evan Chengcffbb512006-02-16 23:11:42 +00002895 if (!Str.empty()) {
2896 CopyFromStr = true;
2897 SrcOff += SrcDelta;
2898 }
2899 }
Evan Cheng74d0aa92006-02-15 21:59:04 +00002900 }
2901
Evan Chengc080d6f2006-02-15 01:54:51 +00002902 for (unsigned i = 0; i < NumMemOps; i++) {
2903 MVT::ValueType VT = MemOps[i];
2904 unsigned VTSize = getSizeInBits(VT) / 8;
Evan Cheng74d0aa92006-02-15 21:59:04 +00002905 SDOperand Value, Chain, Store;
2906
Evan Chengcffbb512006-02-16 23:11:42 +00002907 if (CopyFromStr) {
Evan Cheng74d0aa92006-02-15 21:59:04 +00002908 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
2909 Chain = getRoot();
2910 Store =
Evan Cheng786225a2006-10-05 23:01:46 +00002911 DAG.getStore(Chain, Value,
2912 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
2913 DAG.getSrcValue(I.getOperand(1), DstOff));
Evan Cheng74d0aa92006-02-15 21:59:04 +00002914 } else {
2915 Value = DAG.getLoad(VT, getRoot(),
2916 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
Evan Cheng466685d2006-10-09 20:57:25 +00002917 I.getOperand(2), SrcOff);
Evan Cheng74d0aa92006-02-15 21:59:04 +00002918 Chain = Value.getValue(1);
2919 Store =
Evan Cheng786225a2006-10-05 23:01:46 +00002920 DAG.getStore(Chain, Value,
2921 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
2922 DAG.getSrcValue(I.getOperand(1), DstOff));
Evan Cheng74d0aa92006-02-15 21:59:04 +00002923 }
Evan Chengc080d6f2006-02-15 01:54:51 +00002924 OutChains.push_back(Store);
Evan Cheng74d0aa92006-02-15 21:59:04 +00002925 SrcOff += VTSize;
2926 DstOff += VTSize;
Evan Chengc080d6f2006-02-15 01:54:51 +00002927 }
2928 }
2929 break;
2930 }
2931 }
2932
2933 if (!OutChains.empty()) {
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002934 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
2935 &OutChains[0], OutChains.size()));
Evan Chengc080d6f2006-02-15 01:54:51 +00002936 return;
Evan Cheng1db92f92006-02-14 08:22:34 +00002937 }
2938 }
2939
Chris Lattnerbd564bf2006-08-08 02:23:42 +00002940 DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4));
Chris Lattner1c08c712005-01-07 07:47:53 +00002941}
2942
Chris Lattner7041ee32005-01-11 05:56:49 +00002943//===----------------------------------------------------------------------===//
2944// SelectionDAGISel code
2945//===----------------------------------------------------------------------===//
Chris Lattner1c08c712005-01-07 07:47:53 +00002946
2947unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
2948 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
2949}
2950
Chris Lattner495a0b52005-08-17 06:37:43 +00002951void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
Chris Lattner36b708f2005-08-18 17:35:14 +00002952 // FIXME: we only modify the CFG to split critical edges. This
2953 // updates dom and loop info.
Chris Lattner495a0b52005-08-17 06:37:43 +00002954}
Chris Lattner1c08c712005-01-07 07:47:53 +00002955
Chris Lattnerc88d8e92005-12-05 07:10:48 +00002956
Chris Lattner90323642006-05-05 21:17:49 +00002957/// OptimizeNoopCopyExpression - We have determined that the specified cast
2958/// instruction is a noop copy (e.g. it's casting from one pointer type to
2959/// another, int->uint, or int->sbyte on PPC.
2960///
2961/// Return true if any changes are made.
2962static bool OptimizeNoopCopyExpression(CastInst *CI) {
2963 BasicBlock *DefBB = CI->getParent();
2964
2965 /// InsertedCasts - Only insert a cast in each block once.
2966 std::map<BasicBlock*, CastInst*> InsertedCasts;
2967
2968 bool MadeChange = false;
2969 for (Value::use_iterator UI = CI->use_begin(), E = CI->use_end();
2970 UI != E; ) {
2971 Use &TheUse = UI.getUse();
2972 Instruction *User = cast<Instruction>(*UI);
2973
2974 // Figure out which BB this cast is used in. For PHI's this is the
2975 // appropriate predecessor block.
2976 BasicBlock *UserBB = User->getParent();
2977 if (PHINode *PN = dyn_cast<PHINode>(User)) {
2978 unsigned OpVal = UI.getOperandNo()/2;
2979 UserBB = PN->getIncomingBlock(OpVal);
2980 }
2981
2982 // Preincrement use iterator so we don't invalidate it.
2983 ++UI;
2984
2985 // If this user is in the same block as the cast, don't change the cast.
2986 if (UserBB == DefBB) continue;
2987
2988 // If we have already inserted a cast into this block, use it.
2989 CastInst *&InsertedCast = InsertedCasts[UserBB];
2990
2991 if (!InsertedCast) {
2992 BasicBlock::iterator InsertPt = UserBB->begin();
2993 while (isa<PHINode>(InsertPt)) ++InsertPt;
2994
2995 InsertedCast =
2996 new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
2997 MadeChange = true;
2998 }
2999
3000 // Replace a use of the cast with a use of the new casat.
3001 TheUse = InsertedCast;
3002 }
3003
3004 // If we removed all uses, nuke the cast.
3005 if (CI->use_empty())
3006 CI->eraseFromParent();
3007
3008 return MadeChange;
3009}
3010
Chris Lattnerc88d8e92005-12-05 07:10:48 +00003011/// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset,
3012/// casting to the type of GEPI.
Chris Lattnerf0df8822006-05-06 09:10:37 +00003013static Instruction *InsertGEPComputeCode(Instruction *&V, BasicBlock *BB,
3014 Instruction *GEPI, Value *Ptr,
3015 Value *PtrOffset) {
Chris Lattnerc88d8e92005-12-05 07:10:48 +00003016 if (V) return V; // Already computed.
3017
3018 BasicBlock::iterator InsertPt;
3019 if (BB == GEPI->getParent()) {
3020 // If insert into the GEP's block, insert right after the GEP.
3021 InsertPt = GEPI;
3022 ++InsertPt;
3023 } else {
3024 // Otherwise, insert at the top of BB, after any PHI nodes
3025 InsertPt = BB->begin();
3026 while (isa<PHINode>(InsertPt)) ++InsertPt;
3027 }
3028
Chris Lattnerc78b0b72005-12-08 08:00:12 +00003029 // If Ptr is itself a cast, but in some other BB, emit a copy of the cast into
3030 // BB so that there is only one value live across basic blocks (the cast
3031 // operand).
3032 if (CastInst *CI = dyn_cast<CastInst>(Ptr))
3033 if (CI->getParent() != BB && isa<PointerType>(CI->getOperand(0)->getType()))
3034 Ptr = new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
3035
Chris Lattnerc88d8e92005-12-05 07:10:48 +00003036 // Add the offset, cast it to the right type.
3037 Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt);
Chris Lattnerf0df8822006-05-06 09:10:37 +00003038 return V = new CastInst(Ptr, GEPI->getType(), "", InsertPt);
Chris Lattnerc88d8e92005-12-05 07:10:48 +00003039}
3040
Chris Lattner90323642006-05-05 21:17:49 +00003041/// ReplaceUsesOfGEPInst - Replace all uses of RepPtr with inserted code to
3042/// compute its value. The RepPtr value can be computed with Ptr+PtrOffset. One
3043/// trivial way of doing this would be to evaluate Ptr+PtrOffset in RepPtr's
3044/// block, then ReplaceAllUsesWith'ing everything. However, we would prefer to
3045/// sink PtrOffset into user blocks where doing so will likely allow us to fold
3046/// the constant add into a load or store instruction. Additionally, if a user
3047/// is a pointer-pointer cast, we look through it to find its users.
3048static void ReplaceUsesOfGEPInst(Instruction *RepPtr, Value *Ptr,
3049 Constant *PtrOffset, BasicBlock *DefBB,
3050 GetElementPtrInst *GEPI,
Chris Lattnerf0df8822006-05-06 09:10:37 +00003051 std::map<BasicBlock*,Instruction*> &InsertedExprs) {
Chris Lattner90323642006-05-05 21:17:49 +00003052 while (!RepPtr->use_empty()) {
3053 Instruction *User = cast<Instruction>(RepPtr->use_back());
Chris Lattner7e598092006-05-05 01:04:50 +00003054
Chris Lattner90323642006-05-05 21:17:49 +00003055 // If the user is a Pointer-Pointer cast, recurse.
3056 if (isa<CastInst>(User) && isa<PointerType>(User->getType())) {
3057 ReplaceUsesOfGEPInst(User, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
Chris Lattner7e598092006-05-05 01:04:50 +00003058
Chris Lattner90323642006-05-05 21:17:49 +00003059 // Drop the use of RepPtr. The cast is dead. Don't delete it now, else we
3060 // could invalidate an iterator.
3061 User->setOperand(0, UndefValue::get(RepPtr->getType()));
3062 continue;
Chris Lattner7e598092006-05-05 01:04:50 +00003063 }
3064
Chris Lattner90323642006-05-05 21:17:49 +00003065 // If this is a load of the pointer, or a store through the pointer, emit
3066 // the increment into the load/store block.
Chris Lattnerf0df8822006-05-06 09:10:37 +00003067 Instruction *NewVal;
Chris Lattner90323642006-05-05 21:17:49 +00003068 if (isa<LoadInst>(User) ||
3069 (isa<StoreInst>(User) && User->getOperand(0) != RepPtr)) {
3070 NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()],
3071 User->getParent(), GEPI,
3072 Ptr, PtrOffset);
3073 } else {
3074 // If this use is not foldable into the addressing mode, use a version
3075 // emitted in the GEP block.
3076 NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI,
3077 Ptr, PtrOffset);
3078 }
3079
Chris Lattnerf0df8822006-05-06 09:10:37 +00003080 if (GEPI->getType() != RepPtr->getType()) {
3081 BasicBlock::iterator IP = NewVal;
3082 ++IP;
3083 NewVal = new CastInst(NewVal, RepPtr->getType(), "", IP);
3084 }
Chris Lattner90323642006-05-05 21:17:49 +00003085 User->replaceUsesOfWith(RepPtr, NewVal);
Chris Lattner7e598092006-05-05 01:04:50 +00003086 }
3087}
Chris Lattnerc88d8e92005-12-05 07:10:48 +00003088
Chris Lattner90323642006-05-05 21:17:49 +00003089
Chris Lattnerc88d8e92005-12-05 07:10:48 +00003090/// OptimizeGEPExpression - Since we are doing basic-block-at-a-time instruction
3091/// selection, we want to be a bit careful about some things. In particular, if
3092/// we have a GEP instruction that is used in a different block than it is
3093/// defined, the addressing expression of the GEP cannot be folded into loads or
3094/// stores that use it. In this case, decompose the GEP and move constant
3095/// indices into blocks that use it.
Chris Lattner90323642006-05-05 21:17:49 +00003096static bool OptimizeGEPExpression(GetElementPtrInst *GEPI,
Owen Andersona69571c2006-05-03 01:29:57 +00003097 const TargetData *TD) {
Chris Lattnerc88d8e92005-12-05 07:10:48 +00003098 // If this GEP is only used inside the block it is defined in, there is no
3099 // need to rewrite it.
3100 bool isUsedOutsideDefBB = false;
3101 BasicBlock *DefBB = GEPI->getParent();
3102 for (Value::use_iterator UI = GEPI->use_begin(), E = GEPI->use_end();
3103 UI != E; ++UI) {
3104 if (cast<Instruction>(*UI)->getParent() != DefBB) {
3105 isUsedOutsideDefBB = true;
3106 break;
3107 }
3108 }
Chris Lattner90323642006-05-05 21:17:49 +00003109 if (!isUsedOutsideDefBB) return false;
Chris Lattnerc88d8e92005-12-05 07:10:48 +00003110
3111 // If this GEP has no non-zero constant indices, there is nothing we can do,
3112 // ignore it.
3113 bool hasConstantIndex = false;
Chris Lattner90323642006-05-05 21:17:49 +00003114 bool hasVariableIndex = false;
Chris Lattnerc88d8e92005-12-05 07:10:48 +00003115 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3116 E = GEPI->op_end(); OI != E; ++OI) {
Chris Lattner90323642006-05-05 21:17:49 +00003117 if (ConstantInt *CI = dyn_cast<ConstantInt>(*OI)) {
Chris Lattnerc88d8e92005-12-05 07:10:48 +00003118 if (CI->getRawValue()) {
3119 hasConstantIndex = true;
3120 break;
3121 }
Chris Lattner90323642006-05-05 21:17:49 +00003122 } else {
3123 hasVariableIndex = true;
3124 }
Chris Lattnerc88d8e92005-12-05 07:10:48 +00003125 }
Chris Lattner90323642006-05-05 21:17:49 +00003126
3127 // If this is a "GEP X, 0, 0, 0", turn this into a cast.
3128 if (!hasConstantIndex && !hasVariableIndex) {
3129 Value *NC = new CastInst(GEPI->getOperand(0), GEPI->getType(),
3130 GEPI->getName(), GEPI);
3131 GEPI->replaceAllUsesWith(NC);
3132 GEPI->eraseFromParent();
3133 return true;
3134 }
3135
Chris Lattner3802c252005-12-11 09:05:13 +00003136 // If this is a GEP &Alloca, 0, 0, forward subst the frame index into uses.
Chris Lattner90323642006-05-05 21:17:49 +00003137 if (!hasConstantIndex && !isa<AllocaInst>(GEPI->getOperand(0)))
3138 return false;
Chris Lattnerc88d8e92005-12-05 07:10:48 +00003139
3140 // Otherwise, decompose the GEP instruction into multiplies and adds. Sum the
3141 // constant offset (which we now know is non-zero) and deal with it later.
3142 uint64_t ConstantOffset = 0;
Owen Andersona69571c2006-05-03 01:29:57 +00003143 const Type *UIntPtrTy = TD->getIntPtrType();
Chris Lattnerc88d8e92005-12-05 07:10:48 +00003144 Value *Ptr = new CastInst(GEPI->getOperand(0), UIntPtrTy, "", GEPI);
3145 const Type *Ty = GEPI->getOperand(0)->getType();
3146
3147 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3148 E = GEPI->op_end(); OI != E; ++OI) {
3149 Value *Idx = *OI;
3150 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
3151 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
3152 if (Field)
Owen Andersona69571c2006-05-03 01:29:57 +00003153 ConstantOffset += TD->getStructLayout(StTy)->MemberOffsets[Field];
Chris Lattnerc88d8e92005-12-05 07:10:48 +00003154 Ty = StTy->getElementType(Field);
3155 } else {
3156 Ty = cast<SequentialType>(Ty)->getElementType();
3157
3158 // Handle constant subscripts.
3159 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3160 if (CI->getRawValue() == 0) continue;
3161
3162 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
Owen Andersona69571c2006-05-03 01:29:57 +00003163 ConstantOffset += (int64_t)TD->getTypeSize(Ty)*CSI->getValue();
Chris Lattnerc88d8e92005-12-05 07:10:48 +00003164 else
Owen Andersona69571c2006-05-03 01:29:57 +00003165 ConstantOffset+=TD->getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
Chris Lattnerc88d8e92005-12-05 07:10:48 +00003166 continue;
3167 }
3168
3169 // Ptr = Ptr + Idx * ElementSize;
3170
3171 // Cast Idx to UIntPtrTy if needed.
3172 Idx = new CastInst(Idx, UIntPtrTy, "", GEPI);
3173
Owen Andersona69571c2006-05-03 01:29:57 +00003174 uint64_t ElementSize = TD->getTypeSize(Ty);
Chris Lattnerc88d8e92005-12-05 07:10:48 +00003175 // Mask off bits that should not be set.
3176 ElementSize &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3177 Constant *SizeCst = ConstantUInt::get(UIntPtrTy, ElementSize);
3178
3179 // Multiply by the element size and add to the base.
3180 Idx = BinaryOperator::createMul(Idx, SizeCst, "", GEPI);
3181 Ptr = BinaryOperator::createAdd(Ptr, Idx, "", GEPI);
3182 }
3183 }
3184
3185 // Make sure that the offset fits in uintptr_t.
3186 ConstantOffset &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3187 Constant *PtrOffset = ConstantUInt::get(UIntPtrTy, ConstantOffset);
3188
3189 // Okay, we have now emitted all of the variable index parts to the BB that
3190 // the GEP is defined in. Loop over all of the using instructions, inserting
3191 // an "add Ptr, ConstantOffset" into each block that uses it and update the
Chris Lattnerc78b0b72005-12-08 08:00:12 +00003192 // instruction to use the newly computed value, making GEPI dead. When the
3193 // user is a load or store instruction address, we emit the add into the user
3194 // block, otherwise we use a canonical version right next to the gep (these
3195 // won't be foldable as addresses, so we might as well share the computation).
3196
Chris Lattnerf0df8822006-05-06 09:10:37 +00003197 std::map<BasicBlock*,Instruction*> InsertedExprs;
Chris Lattner90323642006-05-05 21:17:49 +00003198 ReplaceUsesOfGEPInst(GEPI, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
Chris Lattnerc88d8e92005-12-05 07:10:48 +00003199
3200 // Finally, the GEP is dead, remove it.
3201 GEPI->eraseFromParent();
Chris Lattner90323642006-05-05 21:17:49 +00003202
3203 return true;
Chris Lattnerc88d8e92005-12-05 07:10:48 +00003204}
3205
Chris Lattner57f9a432006-09-28 06:17:10 +00003206/// SplitCritEdgesForPHIConstants - If this block has any PHI nodes with
3207/// constant operands, and if any of the edges feeding the PHI node are
3208/// critical, split them so that the assignments of a constant to a register
3209/// will not be executed on a path that isn't relevant.
3210void SelectionDAGISel::SplitCritEdgesForPHIConstants(BasicBlock *BB) {
Chris Lattner75548062006-10-11 03:58:02 +00003211 // The most common case is that this is a PHI node with two incoming
3212 // successors handle this case efficiently, because it is simple.
3213 PHINode *PN = cast<PHINode>(BB->begin());
3214 if (PN->getNumIncomingValues() == 2) {
3215 // If neither edge is critical, we never need to split.
3216 if (PN->getIncomingBlock(0)->getTerminator()->getNumSuccessors() == 1 &&
3217 PN->getIncomingBlock(1)->getTerminator()->getNumSuccessors() == 1)
3218 return;
3219
3220 BasicBlock::iterator BBI = BB->begin();
3221 while ((PN = dyn_cast<PHINode>(BBI++))) {
3222 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
3223 if (isa<Constant>(PN->getIncomingValue(i)))
3224 SplitCriticalEdge(PN->getIncomingBlock(i), BB);
3225 }
3226 return;
3227 }
3228
3229 // Otherwise, things are a bit trickier.
3230
3231 // BE SMART HERE.
3232
Chris Lattner57f9a432006-09-28 06:17:10 +00003233 BasicBlock::iterator BBI = BB->begin();
3234 while ((PN = dyn_cast<PHINode>(BBI++))) {
3235 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
3236 if (isa<Constant>(PN->getIncomingValue(i)))
3237 SplitCriticalEdge(PN->getIncomingBlock(i), BB);
3238 }
3239}
3240
3241
Chris Lattner1c08c712005-01-07 07:47:53 +00003242bool SelectionDAGISel::runOnFunction(Function &Fn) {
3243 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
3244 RegMap = MF.getSSARegMap();
3245 DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n");
3246
Chris Lattnerc88d8e92005-12-05 07:10:48 +00003247 // First, split all critical edges for PHI nodes with incoming values that are
3248 // constants, this way the load of the constant into a vreg will not be placed
3249 // into MBBs that are used some other way.
3250 //
Chris Lattner7e598092006-05-05 01:04:50 +00003251 // In this pass we also look for GEP and cast instructions that are used
3252 // across basic blocks and rewrite them to improve basic-block-at-a-time
3253 // selection.
3254 //
Chris Lattnerc88d8e92005-12-05 07:10:48 +00003255 //
Chris Lattner90323642006-05-05 21:17:49 +00003256 bool MadeChange = true;
3257 while (MadeChange) {
3258 MadeChange = false;
Chris Lattner36b708f2005-08-18 17:35:14 +00003259 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
Chris Lattner57f9a432006-09-28 06:17:10 +00003260 // If this block has any PHI nodes with constant operands, and if any of the
3261 // edges feeding the PHI node are critical, split them.
3262 if (isa<PHINode>(BB->begin()))
3263 SplitCritEdgesForPHIConstants(BB);
Chris Lattnerc88d8e92005-12-05 07:10:48 +00003264
Chris Lattner57f9a432006-09-28 06:17:10 +00003265 for (BasicBlock::iterator BBI = BB->begin(), E = BB->end(); BBI != E; ) {
Chris Lattner7e598092006-05-05 01:04:50 +00003266 Instruction *I = BBI++;
3267 if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(I)) {
Chris Lattner90323642006-05-05 21:17:49 +00003268 MadeChange |= OptimizeGEPExpression(GEPI, TLI.getTargetData());
Chris Lattner7e598092006-05-05 01:04:50 +00003269 } else if (CastInst *CI = dyn_cast<CastInst>(I)) {
Chris Lattnerc970f062006-09-13 06:02:42 +00003270 // If the source of the cast is a constant, then this should have
3271 // already been constant folded. The only reason NOT to constant fold
3272 // it is if something (e.g. LSR) was careful to place the constant
3273 // evaluation in a block other than then one that uses it (e.g. to hoist
3274 // the address of globals out of a loop). If this is the case, we don't
3275 // want to forward-subst the cast.
3276 if (isa<Constant>(CI->getOperand(0)))
3277 continue;
3278
Chris Lattner7e598092006-05-05 01:04:50 +00003279 // If this is a noop copy, sink it into user blocks to reduce the number
3280 // of virtual registers that must be created and coallesced.
3281 MVT::ValueType SrcVT = TLI.getValueType(CI->getOperand(0)->getType());
3282 MVT::ValueType DstVT = TLI.getValueType(CI->getType());
3283
3284 // This is an fp<->int conversion?
3285 if (MVT::isInteger(SrcVT) != MVT::isInteger(DstVT))
3286 continue;
3287
3288 // If this is an extension, it will be a zero or sign extension, which
3289 // isn't a noop.
3290 if (SrcVT < DstVT) continue;
3291
3292 // If these values will be promoted, find out what they will be promoted
3293 // to. This helps us consider truncates on PPC as noop copies when they
3294 // are.
3295 if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote)
3296 SrcVT = TLI.getTypeToTransformTo(SrcVT);
3297 if (TLI.getTypeAction(DstVT) == TargetLowering::Promote)
3298 DstVT = TLI.getTypeToTransformTo(DstVT);
3299
3300 // If, after promotion, these are the same types, this is a noop copy.
3301 if (SrcVT == DstVT)
Chris Lattner90323642006-05-05 21:17:49 +00003302 MadeChange |= OptimizeNoopCopyExpression(CI);
Chris Lattner7e598092006-05-05 01:04:50 +00003303 }
3304 }
Chris Lattner36b708f2005-08-18 17:35:14 +00003305 }
Chris Lattner90323642006-05-05 21:17:49 +00003306 }
Chris Lattnerc9ea6fd2005-11-09 19:44:01 +00003307
Chris Lattner1c08c712005-01-07 07:47:53 +00003308 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
3309
3310 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
3311 SelectBasicBlock(I, MF, FuncInfo);
Misha Brukmanedf128a2005-04-21 22:36:52 +00003312
Chris Lattner1c08c712005-01-07 07:47:53 +00003313 return true;
3314}
3315
3316
Chris Lattnerddb870b2005-01-13 17:59:43 +00003317SDOperand SelectionDAGISel::
3318CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
Chris Lattnerf1fdaca2005-01-11 22:03:46 +00003319 SDOperand Op = SDL.getValue(V);
Chris Lattner18c2f132005-01-13 20:50:02 +00003320 assert((Op.getOpcode() != ISD::CopyFromReg ||
Chris Lattnerd5d0f9b2005-08-16 21:55:35 +00003321 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
Chris Lattner18c2f132005-01-13 20:50:02 +00003322 "Copy from a reg to the same reg!");
Chris Lattnerd5d0f9b2005-08-16 21:55:35 +00003323
3324 // If this type is not legal, we must make sure to not create an invalid
3325 // register use.
3326 MVT::ValueType SrcVT = Op.getValueType();
3327 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT);
3328 SelectionDAG &DAG = SDL.DAG;
3329 if (SrcVT == DestVT) {
3330 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
Chris Lattner1c6191f2006-03-21 19:20:37 +00003331 } else if (SrcVT == MVT::Vector) {
Chris Lattner70c2a612006-03-31 02:06:56 +00003332 // Handle copies from generic vectors to registers.
3333 MVT::ValueType PTyElementVT, PTyLegalElementVT;
3334 unsigned NE = TLI.getPackedTypeBreakdown(cast<PackedType>(V->getType()),
3335 PTyElementVT, PTyLegalElementVT);
Chris Lattner1c6191f2006-03-21 19:20:37 +00003336
Chris Lattner70c2a612006-03-31 02:06:56 +00003337 // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT"
3338 // MVT::Vector type.
3339 Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op,
3340 DAG.getConstant(NE, MVT::i32),
3341 DAG.getValueType(PTyElementVT));
Chris Lattner1c6191f2006-03-21 19:20:37 +00003342
Chris Lattner70c2a612006-03-31 02:06:56 +00003343 // Loop over all of the elements of the resultant vector,
3344 // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then
3345 // copying them into output registers.
Chris Lattnerbd564bf2006-08-08 02:23:42 +00003346 SmallVector<SDOperand, 8> OutChains;
Chris Lattner70c2a612006-03-31 02:06:56 +00003347 SDOperand Root = SDL.getRoot();
3348 for (unsigned i = 0; i != NE; ++i) {
3349 SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT,
Evan Chenga8441262006-06-15 08:11:54 +00003350 Op, DAG.getConstant(i, TLI.getPointerTy()));
Chris Lattner70c2a612006-03-31 02:06:56 +00003351 if (PTyElementVT == PTyLegalElementVT) {
3352 // Elements are legal.
3353 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3354 } else if (PTyLegalElementVT > PTyElementVT) {
3355 // Elements are promoted.
3356 if (MVT::isFloatingPoint(PTyLegalElementVT))
3357 Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt);
3358 else
3359 Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt);
3360 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3361 } else {
3362 // Elements are expanded.
3363 // The src value is expanded into multiple registers.
3364 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
Evan Chenga8441262006-06-15 08:11:54 +00003365 Elt, DAG.getConstant(0, TLI.getPointerTy()));
Chris Lattner70c2a612006-03-31 02:06:56 +00003366 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
Evan Chenga8441262006-06-15 08:11:54 +00003367 Elt, DAG.getConstant(1, TLI.getPointerTy()));
Chris Lattner70c2a612006-03-31 02:06:56 +00003368 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo));
3369 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi));
3370 }
Chris Lattner1c6191f2006-03-21 19:20:37 +00003371 }
Chris Lattnerbd564bf2006-08-08 02:23:42 +00003372 return DAG.getNode(ISD::TokenFactor, MVT::Other,
3373 &OutChains[0], OutChains.size());
Chris Lattnerd5d0f9b2005-08-16 21:55:35 +00003374 } else if (SrcVT < DestVT) {
3375 // The src value is promoted to the register.
Chris Lattnerfae59b92005-08-17 06:06:25 +00003376 if (MVT::isFloatingPoint(SrcVT))
3377 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op);
3378 else
Chris Lattnerfab08872005-09-02 00:19:37 +00003379 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op);
Chris Lattnerd5d0f9b2005-08-16 21:55:35 +00003380 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
3381 } else {
3382 // The src value is expanded into multiple registers.
3383 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
Evan Chenga8441262006-06-15 08:11:54 +00003384 Op, DAG.getConstant(0, TLI.getPointerTy()));
Chris Lattnerd5d0f9b2005-08-16 21:55:35 +00003385 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
Evan Chenga8441262006-06-15 08:11:54 +00003386 Op, DAG.getConstant(1, TLI.getPointerTy()));
Chris Lattnerd5d0f9b2005-08-16 21:55:35 +00003387 Op = DAG.getCopyToReg(SDL.getRoot(), Reg, Lo);
3388 return DAG.getCopyToReg(Op, Reg+1, Hi);
3389 }
Chris Lattner1c08c712005-01-07 07:47:53 +00003390}
3391
Chris Lattner068a81e2005-01-17 17:15:02 +00003392void SelectionDAGISel::
3393LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
3394 std::vector<SDOperand> &UnorderedChains) {
3395 // If this is the entry block, emit arguments.
3396 Function &F = *BB->getParent();
Chris Lattner0afa8e32005-01-17 17:55:19 +00003397 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
Chris Lattnerbf209482005-10-30 19:42:35 +00003398 SDOperand OldRoot = SDL.DAG.getRoot();
3399 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
Chris Lattner068a81e2005-01-17 17:15:02 +00003400
Chris Lattnerbf209482005-10-30 19:42:35 +00003401 unsigned a = 0;
3402 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
3403 AI != E; ++AI, ++a)
3404 if (!AI->use_empty()) {
3405 SDL.setValue(AI, Args[a]);
Evan Chengf7179bb2006-04-27 08:29:42 +00003406
Chris Lattnerbf209482005-10-30 19:42:35 +00003407 // If this argument is live outside of the entry block, insert a copy from
3408 // whereever we got it to the vreg that other BB's will reference it as.
3409 if (FuncInfo.ValueMap.count(AI)) {
3410 SDOperand Copy =
3411 CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
3412 UnorderedChains.push_back(Copy);
3413 }
Chris Lattner0afa8e32005-01-17 17:55:19 +00003414 }
Chris Lattnerbf209482005-10-30 19:42:35 +00003415
Chris Lattnerbf209482005-10-30 19:42:35 +00003416 // Finally, if the target has anything special to do, allow it to do so.
Chris Lattner96645412006-05-16 06:10:58 +00003417 // FIXME: this should insert code into the DAG!
Chris Lattnerbf209482005-10-30 19:42:35 +00003418 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
Chris Lattner068a81e2005-01-17 17:15:02 +00003419}
3420
Chris Lattner1c08c712005-01-07 07:47:53 +00003421void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
3422 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
Nate Begemanf15485a2006-03-27 01:32:24 +00003423 FunctionLoweringInfo &FuncInfo) {
Chris Lattner1c08c712005-01-07 07:47:53 +00003424 SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
Chris Lattnerddb870b2005-01-13 17:59:43 +00003425
3426 std::vector<SDOperand> UnorderedChains;
Misha Brukmanedf128a2005-04-21 22:36:52 +00003427
Chris Lattnerbf209482005-10-30 19:42:35 +00003428 // Lower any arguments needed in this block if this is the entry block.
3429 if (LLVMBB == &LLVMBB->getParent()->front())
3430 LowerArguments(LLVMBB, SDL, UnorderedChains);
Chris Lattner1c08c712005-01-07 07:47:53 +00003431
3432 BB = FuncInfo.MBBMap[LLVMBB];
3433 SDL.setCurrentBasicBlock(BB);
3434
3435 // Lower all of the non-terminator instructions.
3436 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
3437 I != E; ++I)
3438 SDL.visit(*I);
Nate Begemanf15485a2006-03-27 01:32:24 +00003439
Chris Lattner1c08c712005-01-07 07:47:53 +00003440 // Ensure that all instructions which are used outside of their defining
3441 // blocks are available as virtual registers.
3442 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
Chris Lattnerf1fdaca2005-01-11 22:03:46 +00003443 if (!I->use_empty() && !isa<PHINode>(I)) {
Chris Lattneree749d72005-01-09 01:16:24 +00003444 std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
Chris Lattner1c08c712005-01-07 07:47:53 +00003445 if (VMI != FuncInfo.ValueMap.end())
Chris Lattnerddb870b2005-01-13 17:59:43 +00003446 UnorderedChains.push_back(
3447 CopyValueToVirtualRegister(SDL, I, VMI->second));
Chris Lattner1c08c712005-01-07 07:47:53 +00003448 }
3449
3450 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
3451 // ensure constants are generated when needed. Remember the virtual registers
3452 // that need to be added to the Machine PHI nodes as input. We cannot just
3453 // directly add them, because expansion might result in multiple MBB's for one
3454 // BB. As such, the start of the BB might correspond to a different MBB than
3455 // the end.
Misha Brukmanedf128a2005-04-21 22:36:52 +00003456 //
Chris Lattner1c08c712005-01-07 07:47:53 +00003457
3458 // Emit constants only once even if used by multiple PHI nodes.
3459 std::map<Constant*, unsigned> ConstantsOut;
Chris Lattnerd5e93c02006-09-07 01:59:34 +00003460
Chris Lattner1c08c712005-01-07 07:47:53 +00003461 // Check successor nodes PHI nodes that expect a constant to be available from
3462 // this block.
3463 TerminatorInst *TI = LLVMBB->getTerminator();
3464 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
3465 BasicBlock *SuccBB = TI->getSuccessor(succ);
Chris Lattnerd5e93c02006-09-07 01:59:34 +00003466 if (!isa<PHINode>(SuccBB->begin())) continue;
3467
Chris Lattner1c08c712005-01-07 07:47:53 +00003468 MachineBasicBlock::iterator MBBI = FuncInfo.MBBMap[SuccBB]->begin();
3469 PHINode *PN;
3470
3471 // At this point we know that there is a 1-1 correspondence between LLVM PHI
3472 // nodes and Machine PHI nodes, but the incoming operands have not been
3473 // emitted yet.
3474 for (BasicBlock::iterator I = SuccBB->begin();
Chris Lattnerf44fd882005-01-07 21:34:19 +00003475 (PN = dyn_cast<PHINode>(I)); ++I)
3476 if (!PN->use_empty()) {
3477 unsigned Reg;
3478 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
3479 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
3480 unsigned &RegOut = ConstantsOut[C];
3481 if (RegOut == 0) {
3482 RegOut = FuncInfo.CreateRegForValue(C);
Chris Lattnerddb870b2005-01-13 17:59:43 +00003483 UnorderedChains.push_back(
3484 CopyValueToVirtualRegister(SDL, C, RegOut));
Chris Lattnerf44fd882005-01-07 21:34:19 +00003485 }
3486 Reg = RegOut;
3487 } else {
3488 Reg = FuncInfo.ValueMap[PHIOp];
Chris Lattneree749d72005-01-09 01:16:24 +00003489 if (Reg == 0) {
Misha Brukmanedf128a2005-04-21 22:36:52 +00003490 assert(isa<AllocaInst>(PHIOp) &&
Chris Lattneree749d72005-01-09 01:16:24 +00003491 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
3492 "Didn't codegen value into a register!??");
3493 Reg = FuncInfo.CreateRegForValue(PHIOp);
Chris Lattnerddb870b2005-01-13 17:59:43 +00003494 UnorderedChains.push_back(
3495 CopyValueToVirtualRegister(SDL, PHIOp, Reg));
Chris Lattneree749d72005-01-09 01:16:24 +00003496 }
Chris Lattner1c08c712005-01-07 07:47:53 +00003497 }
Misha Brukmanedf128a2005-04-21 22:36:52 +00003498
Chris Lattnerf44fd882005-01-07 21:34:19 +00003499 // Remember that this register needs to added to the machine PHI node as
3500 // the input for this MBB.
Chris Lattner7e021512006-03-31 02:12:18 +00003501 MVT::ValueType VT = TLI.getValueType(PN->getType());
3502 unsigned NumElements;
3503 if (VT != MVT::Vector)
3504 NumElements = TLI.getNumElements(VT);
3505 else {
3506 MVT::ValueType VT1,VT2;
3507 NumElements =
3508 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
3509 VT1, VT2);
3510 }
Chris Lattnerf44fd882005-01-07 21:34:19 +00003511 for (unsigned i = 0, e = NumElements; i != e; ++i)
3512 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
Chris Lattner1c08c712005-01-07 07:47:53 +00003513 }
Chris Lattner1c08c712005-01-07 07:47:53 +00003514 }
3515 ConstantsOut.clear();
3516
Chris Lattnerddb870b2005-01-13 17:59:43 +00003517 // Turn all of the unordered chains into one factored node.
Chris Lattner5a6c6d92005-01-13 19:53:14 +00003518 if (!UnorderedChains.empty()) {
Chris Lattner7436b572005-11-09 05:03:03 +00003519 SDOperand Root = SDL.getRoot();
3520 if (Root.getOpcode() != ISD::EntryToken) {
3521 unsigned i = 0, e = UnorderedChains.size();
3522 for (; i != e; ++i) {
3523 assert(UnorderedChains[i].Val->getNumOperands() > 1);
3524 if (UnorderedChains[i].Val->getOperand(0) == Root)
3525 break; // Don't add the root if we already indirectly depend on it.
3526 }
3527
3528 if (i == e)
3529 UnorderedChains.push_back(Root);
3530 }
Chris Lattnerbd564bf2006-08-08 02:23:42 +00003531 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
3532 &UnorderedChains[0], UnorderedChains.size()));
Chris Lattnerddb870b2005-01-13 17:59:43 +00003533 }
3534
Chris Lattner1c08c712005-01-07 07:47:53 +00003535 // Lower the terminator after the copies are emitted.
3536 SDL.visit(*LLVMBB->getTerminator());
Chris Lattnera651cf62005-01-17 19:43:36 +00003537
Nate Begemanf15485a2006-03-27 01:32:24 +00003538 // Copy over any CaseBlock records that may now exist due to SwitchInst
Nate Begeman37efe672006-04-22 18:53:45 +00003539 // lowering, as well as any jump table information.
Nate Begemanf15485a2006-03-27 01:32:24 +00003540 SwitchCases.clear();
3541 SwitchCases = SDL.SwitchCases;
Nate Begeman37efe672006-04-22 18:53:45 +00003542 JT = SDL.JT;
Nate Begemanf15485a2006-03-27 01:32:24 +00003543
Chris Lattnera651cf62005-01-17 19:43:36 +00003544 // Make sure the root of the DAG is up-to-date.
3545 DAG.setRoot(SDL.getRoot());
Chris Lattner1c08c712005-01-07 07:47:53 +00003546}
3547
Nate Begemanf15485a2006-03-27 01:32:24 +00003548void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
Chris Lattneraf21d552005-10-10 16:47:10 +00003549 // Run the DAG combiner in pre-legalize mode.
3550 DAG.Combine(false);
Nate Begeman2300f552005-09-07 00:15:36 +00003551
Chris Lattner1c08c712005-01-07 07:47:53 +00003552 DEBUG(std::cerr << "Lowered selection DAG:\n");
3553 DEBUG(DAG.dump());
Nate Begemanf15485a2006-03-27 01:32:24 +00003554
Chris Lattner1c08c712005-01-07 07:47:53 +00003555 // Second step, hack on the DAG until it only uses operations and types that
3556 // the target supports.
Chris Lattnerac9dc082005-01-23 04:36:26 +00003557 DAG.Legalize();
Nate Begemanf15485a2006-03-27 01:32:24 +00003558
Chris Lattner1c08c712005-01-07 07:47:53 +00003559 DEBUG(std::cerr << "Legalized selection DAG:\n");
3560 DEBUG(DAG.dump());
Nate Begemanf15485a2006-03-27 01:32:24 +00003561
Chris Lattneraf21d552005-10-10 16:47:10 +00003562 // Run the DAG combiner in post-legalize mode.
3563 DAG.Combine(true);
Nate Begeman2300f552005-09-07 00:15:36 +00003564
Evan Chenga9c20912006-01-21 02:32:06 +00003565 if (ViewISelDAGs) DAG.viewGraph();
Evan Cheng552c4a82006-04-28 02:09:19 +00003566
Chris Lattnera33ef482005-03-30 01:10:47 +00003567 // Third, instruction select all of the operations to machine code, adding the
3568 // code to the MachineBasicBlock.
Chris Lattner1c08c712005-01-07 07:47:53 +00003569 InstructionSelectBasicBlock(DAG);
Nate Begemanf15485a2006-03-27 01:32:24 +00003570
Chris Lattner1c08c712005-01-07 07:47:53 +00003571 DEBUG(std::cerr << "Selected machine code:\n");
3572 DEBUG(BB->dump());
Nate Begemanf15485a2006-03-27 01:32:24 +00003573}
Chris Lattner1c08c712005-01-07 07:47:53 +00003574
Nate Begemanf15485a2006-03-27 01:32:24 +00003575void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
3576 FunctionLoweringInfo &FuncInfo) {
3577 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
3578 {
3579 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3580 CurDAG = &DAG;
3581
3582 // First step, lower LLVM code to some DAG. This DAG may use operations and
3583 // types that are not supported by the target.
3584 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
3585
3586 // Second step, emit the lowered DAG as machine code.
3587 CodeGenAndEmitDAG(DAG);
3588 }
3589
Chris Lattnera33ef482005-03-30 01:10:47 +00003590 // Next, now that we know what the last MBB the LLVM BB expanded is, update
Chris Lattner1c08c712005-01-07 07:47:53 +00003591 // PHI nodes in successors.
Nate Begeman37efe672006-04-22 18:53:45 +00003592 if (SwitchCases.empty() && JT.Reg == 0) {
Nate Begemanf15485a2006-03-27 01:32:24 +00003593 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
3594 MachineInstr *PHI = PHINodesToUpdate[i].first;
3595 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3596 "This is not a machine PHI node that we are updating!");
Chris Lattner09e46062006-09-05 02:31:13 +00003597 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
Nate Begemanf15485a2006-03-27 01:32:24 +00003598 PHI->addMachineBasicBlockOperand(BB);
3599 }
3600 return;
Chris Lattner1c08c712005-01-07 07:47:53 +00003601 }
Nate Begemanf15485a2006-03-27 01:32:24 +00003602
Nate Begeman9453eea2006-04-23 06:26:20 +00003603 // If the JumpTable record is filled in, then we need to emit a jump table.
3604 // Updating the PHI nodes is tricky in this case, since we need to determine
3605 // whether the PHI is a successor of the range check MBB or the jump table MBB
Nate Begeman37efe672006-04-22 18:53:45 +00003606 if (JT.Reg) {
3607 assert(SwitchCases.empty() && "Cannot have jump table and lowered switch");
3608 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3609 CurDAG = &SDAG;
3610 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
Nate Begeman9453eea2006-04-23 06:26:20 +00003611 MachineBasicBlock *RangeBB = BB;
Nate Begeman37efe672006-04-22 18:53:45 +00003612 // Set the current basic block to the mbb we wish to insert the code into
3613 BB = JT.MBB;
3614 SDL.setCurrentBasicBlock(BB);
3615 // Emit the code
3616 SDL.visitJumpTable(JT);
3617 SDAG.setRoot(SDL.getRoot());
3618 CodeGenAndEmitDAG(SDAG);
3619 // Update PHI Nodes
3620 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
3621 MachineInstr *PHI = PHINodesToUpdate[pi].first;
3622 MachineBasicBlock *PHIBB = PHI->getParent();
3623 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3624 "This is not a machine PHI node that we are updating!");
Nate Begemanf4360a42006-05-03 03:48:02 +00003625 if (PHIBB == JT.Default) {
Chris Lattner09e46062006-09-05 02:31:13 +00003626 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
Nate Begemanf4360a42006-05-03 03:48:02 +00003627 PHI->addMachineBasicBlockOperand(RangeBB);
3628 }
3629 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
Chris Lattner09e46062006-09-05 02:31:13 +00003630 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
Nate Begemanf4360a42006-05-03 03:48:02 +00003631 PHI->addMachineBasicBlockOperand(BB);
Nate Begeman37efe672006-04-22 18:53:45 +00003632 }
3633 }
3634 return;
3635 }
3636
Nate Begemanf15485a2006-03-27 01:32:24 +00003637 // If we generated any switch lowering information, build and codegen any
3638 // additional DAGs necessary.
Chris Lattnerd5e93c02006-09-07 01:59:34 +00003639 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
Nate Begemanf15485a2006-03-27 01:32:24 +00003640 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3641 CurDAG = &SDAG;
3642 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
Chris Lattnerd5e93c02006-09-07 01:59:34 +00003643
Nate Begemanf15485a2006-03-27 01:32:24 +00003644 // Set the current basic block to the mbb we wish to insert the code into
3645 BB = SwitchCases[i].ThisBB;
3646 SDL.setCurrentBasicBlock(BB);
Chris Lattnerd5e93c02006-09-07 01:59:34 +00003647
Nate Begemanf15485a2006-03-27 01:32:24 +00003648 // Emit the code
3649 SDL.visitSwitchCase(SwitchCases[i]);
3650 SDAG.setRoot(SDL.getRoot());
3651 CodeGenAndEmitDAG(SDAG);
Chris Lattnerd5e93c02006-09-07 01:59:34 +00003652
3653 // Handle any PHI nodes in successors of this chunk, as if we were coming
3654 // from the original BB before switch expansion. Note that PHI nodes can
3655 // occur multiple times in PHINodesToUpdate. We have to be very careful to
3656 // handle them the right number of times.
3657 while ((BB = SwitchCases[i].LHSBB)) { // Handle LHS and RHS.
3658 for (MachineBasicBlock::iterator Phi = BB->begin();
3659 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
3660 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
3661 for (unsigned pn = 0; ; ++pn) {
3662 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
3663 if (PHINodesToUpdate[pn].first == Phi) {
3664 Phi->addRegOperand(PHINodesToUpdate[pn].second, false);
3665 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB);
3666 break;
3667 }
3668 }
Nate Begemanf15485a2006-03-27 01:32:24 +00003669 }
Chris Lattnerd5e93c02006-09-07 01:59:34 +00003670
3671 // Don't process RHS if same block as LHS.
3672 if (BB == SwitchCases[i].RHSBB)
3673 SwitchCases[i].RHSBB = 0;
3674
3675 // If we haven't handled the RHS, do so now. Otherwise, we're done.
3676 SwitchCases[i].LHSBB = SwitchCases[i].RHSBB;
3677 SwitchCases[i].RHSBB = 0;
Nate Begemanf15485a2006-03-27 01:32:24 +00003678 }
Chris Lattnerd5e93c02006-09-07 01:59:34 +00003679 assert(SwitchCases[i].LHSBB == 0 && SwitchCases[i].RHSBB == 0);
Chris Lattnera33ef482005-03-30 01:10:47 +00003680 }
Chris Lattner1c08c712005-01-07 07:47:53 +00003681}
Evan Chenga9c20912006-01-21 02:32:06 +00003682
Jim Laskey13ec7022006-08-01 14:21:23 +00003683
Evan Chenga9c20912006-01-21 02:32:06 +00003684//===----------------------------------------------------------------------===//
3685/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
3686/// target node in the graph.
3687void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
3688 if (ViewSchedDAGs) DAG.viewGraph();
Evan Cheng4ef10862006-01-23 07:01:07 +00003689
Jim Laskeyeb577ba2006-08-02 12:30:23 +00003690 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
Jim Laskey13ec7022006-08-01 14:21:23 +00003691
3692 if (!Ctor) {
Jim Laskeyeb577ba2006-08-02 12:30:23 +00003693 Ctor = ISHeuristic;
Jim Laskey9373beb2006-08-01 19:14:14 +00003694 RegisterScheduler::setDefault(Ctor);
Evan Cheng4ef10862006-01-23 07:01:07 +00003695 }
Jim Laskey13ec7022006-08-01 14:21:23 +00003696
Jim Laskey9ff542f2006-08-01 18:29:48 +00003697 ScheduleDAG *SL = Ctor(this, &DAG, BB);
Chris Lattnera3818e62006-01-21 19:12:11 +00003698 BB = SL->Run();
Evan Chengcccf1232006-02-04 06:49:00 +00003699 delete SL;
Evan Chenga9c20912006-01-21 02:32:06 +00003700}
Chris Lattner0e43f2b2006-02-24 02:13:54 +00003701
Chris Lattner03fc53c2006-03-06 00:22:00 +00003702
Jim Laskey9ff542f2006-08-01 18:29:48 +00003703HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
3704 return new HazardRecognizer();
3705}
3706
Chris Lattner75548062006-10-11 03:58:02 +00003707//===----------------------------------------------------------------------===//
3708// Helper functions used by the generated instruction selector.
3709//===----------------------------------------------------------------------===//
3710// Calls to these methods are generated by tblgen.
3711
3712/// CheckAndMask - The isel is trying to match something like (and X, 255). If
3713/// the dag combiner simplified the 255, we still want to match. RHS is the
3714/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
3715/// specified in the .td file (e.g. 255).
3716bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
3717 int64_t DesiredMaskS) {
3718 uint64_t ActualMask = RHS->getValue();
3719 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
3720
3721 // If the actual mask exactly matches, success!
3722 if (ActualMask == DesiredMask)
3723 return true;
3724
3725 // If the actual AND mask is allowing unallowed bits, this doesn't match.
3726 if (ActualMask & ~DesiredMask)
3727 return false;
3728
3729 // Otherwise, the DAG Combiner may have proven that the value coming in is
3730 // either already zero or is not demanded. Check for known zero input bits.
3731 uint64_t NeededMask = DesiredMask & ~ActualMask;
3732 if (getTargetLowering().MaskedValueIsZero(LHS, NeededMask))
3733 return true;
3734
3735 // TODO: check to see if missing bits are just not demanded.
3736
3737 // Otherwise, this pattern doesn't match.
3738 return false;
3739}
3740
3741/// CheckOrMask - The isel is trying to match something like (or X, 255). If
3742/// the dag combiner simplified the 255, we still want to match. RHS is the
3743/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
3744/// specified in the .td file (e.g. 255).
3745bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
3746 int64_t DesiredMaskS) {
3747 uint64_t ActualMask = RHS->getValue();
3748 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
3749
3750 // If the actual mask exactly matches, success!
3751 if (ActualMask == DesiredMask)
3752 return true;
3753
3754 // If the actual AND mask is allowing unallowed bits, this doesn't match.
3755 if (ActualMask & ~DesiredMask)
3756 return false;
3757
3758 // Otherwise, the DAG Combiner may have proven that the value coming in is
3759 // either already zero or is not demanded. Check for known zero input bits.
3760 uint64_t NeededMask = DesiredMask & ~ActualMask;
3761
3762 uint64_t KnownZero, KnownOne;
3763 getTargetLowering().ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
3764
3765 // If all the missing bits in the or are already known to be set, match!
3766 if ((NeededMask & KnownOne) == NeededMask)
3767 return true;
3768
3769 // TODO: check to see if missing bits are just not demanded.
3770
3771 // Otherwise, this pattern doesn't match.
3772 return false;
3773}
3774
Jim Laskey9ff542f2006-08-01 18:29:48 +00003775
Chris Lattner0e43f2b2006-02-24 02:13:54 +00003776/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
3777/// by tblgen. Others should not call it.
3778void SelectionDAGISel::
3779SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
3780 std::vector<SDOperand> InOps;
3781 std::swap(InOps, Ops);
3782
3783 Ops.push_back(InOps[0]); // input chain.
3784 Ops.push_back(InOps[1]); // input asm string.
3785
Chris Lattner0e43f2b2006-02-24 02:13:54 +00003786 unsigned i = 2, e = InOps.size();
3787 if (InOps[e-1].getValueType() == MVT::Flag)
3788 --e; // Don't process a flag operand if it is here.
3789
3790 while (i != e) {
3791 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
3792 if ((Flags & 7) != 4 /*MEM*/) {
3793 // Just skip over this operand, copying the operands verbatim.
3794 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
3795 i += (Flags >> 3) + 1;
3796 } else {
3797 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
3798 // Otherwise, this is a memory operand. Ask the target to select it.
3799 std::vector<SDOperand> SelOps;
3800 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
3801 std::cerr << "Could not match memory address. Inline asm failure!\n";
3802 exit(1);
3803 }
3804
3805 // Add this to the output node.
3806 Ops.push_back(DAG.getConstant(4/*MEM*/ | (SelOps.size() << 3), MVT::i32));
3807 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
3808 i += 2;
3809 }
3810 }
3811
3812 // Add the flag input back if present.
3813 if (e != InOps.size())
3814 Ops.push_back(InOps.back());
3815}