Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1 | //===- ARMRegisterInfo.td - ARM Register defs -------------------*- C++ -*-===// |
Rafael Espindola | 7bc59bc | 2006-05-14 22:18:28 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame^] | 5 | // This file is distributed under the University of Illinois Open Source |
Rafael Espindola | 7bc59bc | 2006-05-14 22:18:28 +0000 | [diff] [blame] | 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | |
| 10 | //===----------------------------------------------------------------------===// |
| 11 | // Declarations that describe the ARM register file |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | // Registers are identified with 4-bit ID numbers. |
Evan Cheng | ba647be | 2007-04-20 21:20:10 +0000 | [diff] [blame] | 15 | class ARMReg<bits<4> num, string n, list<Register> subregs = []> : Register<n> { |
Rafael Espindola | 2718519 | 2006-09-29 21:20:16 +0000 | [diff] [blame] | 16 | field bits<4> Num; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 17 | let Namespace = "ARM"; |
Evan Cheng | ba647be | 2007-04-20 21:20:10 +0000 | [diff] [blame] | 18 | let SubRegs = subregs; |
Rafael Espindola | 2718519 | 2006-09-29 21:20:16 +0000 | [diff] [blame] | 19 | } |
| 20 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 21 | class ARMFReg<bits<5> num, string n> : Register<n> { |
| 22 | field bits<5> Num; |
| 23 | let Namespace = "ARM"; |
| 24 | } |
| 25 | |
Rafael Espindola | 7bc59bc | 2006-05-14 22:18:28 +0000 | [diff] [blame] | 26 | // Integer registers |
Anton Korobeynikov | f191c80 | 2007-11-11 19:50:10 +0000 | [diff] [blame] | 27 | def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>; |
| 28 | def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>; |
| 29 | def R2 : ARMReg< 2, "r2">, DwarfRegNum<[2]>; |
| 30 | def R3 : ARMReg< 3, "r3">, DwarfRegNum<[3]>; |
| 31 | def R4 : ARMReg< 4, "r4">, DwarfRegNum<[4]>; |
| 32 | def R5 : ARMReg< 5, "r5">, DwarfRegNum<[5]>; |
| 33 | def R6 : ARMReg< 6, "r6">, DwarfRegNum<[6]>; |
| 34 | def R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>; |
| 35 | def R8 : ARMReg< 8, "r8">, DwarfRegNum<[8]>; |
| 36 | def R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>; |
| 37 | def R10 : ARMReg<10, "r10">, DwarfRegNum<[10]>; |
| 38 | def R11 : ARMReg<11, "r11">, DwarfRegNum<[11]>; |
| 39 | def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>; |
| 40 | def SP : ARMReg<13, "sp">, DwarfRegNum<[13]>; |
| 41 | def LR : ARMReg<14, "lr">, DwarfRegNum<[14]>; |
| 42 | def PC : ARMReg<15, "pc">, DwarfRegNum<[15]>; |
Rafael Espindola | 2718519 | 2006-09-29 21:20:16 +0000 | [diff] [blame] | 43 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 44 | // Float registers |
| 45 | def S0 : ARMFReg< 0, "s0">; def S1 : ARMFReg< 1, "s1">; |
| 46 | def S2 : ARMFReg< 2, "s2">; def S3 : ARMFReg< 3, "s3">; |
| 47 | def S4 : ARMFReg< 4, "s4">; def S5 : ARMFReg< 5, "s5">; |
| 48 | def S6 : ARMFReg< 6, "s6">; def S7 : ARMFReg< 7, "s7">; |
| 49 | def S8 : ARMFReg< 8, "s8">; def S9 : ARMFReg< 9, "s9">; |
| 50 | def S10 : ARMFReg<10, "s10">; def S11 : ARMFReg<11, "s11">; |
| 51 | def S12 : ARMFReg<12, "s12">; def S13 : ARMFReg<13, "s13">; |
| 52 | def S14 : ARMFReg<14, "s14">; def S15 : ARMFReg<15, "s15">; |
| 53 | def S16 : ARMFReg<16, "s16">; def S17 : ARMFReg<17, "s17">; |
| 54 | def S18 : ARMFReg<18, "s18">; def S19 : ARMFReg<19, "s19">; |
| 55 | def S20 : ARMFReg<20, "s20">; def S21 : ARMFReg<21, "s21">; |
| 56 | def S22 : ARMFReg<22, "s22">; def S23 : ARMFReg<23, "s23">; |
| 57 | def S24 : ARMFReg<24, "s24">; def S25 : ARMFReg<25, "s25">; |
| 58 | def S26 : ARMFReg<26, "s26">; def S27 : ARMFReg<27, "s27">; |
| 59 | def S28 : ARMFReg<28, "s28">; def S29 : ARMFReg<29, "s29">; |
| 60 | def S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">; |
Rafael Espindola | 2718519 | 2006-09-29 21:20:16 +0000 | [diff] [blame] | 61 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 62 | // Aliases of the F* registers used to hold 64-bit fp values (doubles) |
| 63 | def D0 : ARMReg< 0, "d0", [S0, S1]>; |
| 64 | def D1 : ARMReg< 1, "d1", [S2, S3]>; |
| 65 | def D2 : ARMReg< 2, "d2", [S4, S5]>; |
| 66 | def D3 : ARMReg< 3, "d3", [S6, S7]>; |
| 67 | def D4 : ARMReg< 4, "d4", [S8, S9]>; |
| 68 | def D5 : ARMReg< 5, "d5", [S10, S11]>; |
| 69 | def D6 : ARMReg< 6, "d6", [S12, S13]>; |
| 70 | def D7 : ARMReg< 7, "d7", [S14, S15]>; |
| 71 | def D8 : ARMReg< 8, "d8", [S16, S17]>; |
| 72 | def D9 : ARMReg< 9, "d9", [S18, S19]>; |
| 73 | def D10 : ARMReg<10, "d10", [S20, S21]>; |
| 74 | def D11 : ARMReg<11, "d11", [S22, S23]>; |
| 75 | def D12 : ARMReg<12, "d12", [S24, S25]>; |
| 76 | def D13 : ARMReg<13, "d13", [S26, S27]>; |
| 77 | def D14 : ARMReg<14, "d14", [S28, S29]>; |
| 78 | def D15 : ARMReg<15, "d15", [S30, S31]>; |
Rafael Espindola | 7bc59bc | 2006-05-14 22:18:28 +0000 | [diff] [blame] | 79 | |
Evan Cheng | 16b6598 | 2007-07-05 07:17:13 +0000 | [diff] [blame] | 80 | // Current Program Status Register. |
| 81 | def CPSR : ARMReg<0, "cpsr">; |
| 82 | |
Rafael Espindola | 7bc59bc | 2006-05-14 22:18:28 +0000 | [diff] [blame] | 83 | // Register classes. |
| 84 | // |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 85 | // pc == Program Counter |
| 86 | // lr == Link Register |
| 87 | // sp == Stack Pointer |
| 88 | // r12 == ip (scratch) |
| 89 | // r7 == Frame Pointer (thumb-style backtraces) |
| 90 | // r11 == Frame Pointer (arm-style backtraces) |
| 91 | // r10 == Stack Limit |
Rafael Espindola | 7bc59bc | 2006-05-14 22:18:28 +0000 | [diff] [blame] | 92 | // |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 93 | def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, |
| 94 | R7, R8, R9, R10, R12, R11, |
| 95 | LR, SP, PC]> { |
Rafael Espindola | 7bc59bc | 2006-05-14 22:18:28 +0000 | [diff] [blame] | 96 | let MethodProtos = [{ |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 97 | iterator allocation_order_begin(const MachineFunction &MF) const; |
Chris Lattner | 5ea64fd | 2006-08-17 22:00:08 +0000 | [diff] [blame] | 98 | iterator allocation_order_end(const MachineFunction &MF) const; |
Rafael Espindola | 7bc59bc | 2006-05-14 22:18:28 +0000 | [diff] [blame] | 99 | }]; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 100 | // FIXME: We are reserving r12 in case the PEI needs to use it to |
| 101 | // generate large stack offset. Make it available once we have register |
Evan Cheng | 24f7fb3 | 2007-01-29 22:23:02 +0000 | [diff] [blame] | 102 | // scavenging. Similarly r3 is reserved in Thumb mode for now. |
Rafael Espindola | 7bc59bc | 2006-05-14 22:18:28 +0000 | [diff] [blame] | 103 | let MethodBodies = [{ |
Evan Cheng | bf822eb | 2007-03-08 02:56:40 +0000 | [diff] [blame] | 104 | // FP is R11, R9 is available. |
Evan Cheng | cb20998 | 2007-03-07 02:46:23 +0000 | [diff] [blame] | 105 | static const unsigned ARM_GPR_AO_1[] = { |
Evan Cheng | 41a4d56 | 2007-02-28 00:22:44 +0000 | [diff] [blame] | 106 | ARM::R3, ARM::R2, ARM::R1, ARM::R0, |
Evan Cheng | bf822eb | 2007-03-08 02:56:40 +0000 | [diff] [blame] | 107 | ARM::R12,ARM::LR, |
Evan Cheng | 41a4d56 | 2007-02-28 00:22:44 +0000 | [diff] [blame] | 108 | ARM::R4, ARM::R5, ARM::R6, ARM::R7, |
Evan Cheng | bf822eb | 2007-03-08 02:56:40 +0000 | [diff] [blame] | 109 | ARM::R8, ARM::R9, ARM::R10, |
| 110 | ARM::R11 }; |
| 111 | // FP is R11, R9 is not available. |
Evan Cheng | cb20998 | 2007-03-07 02:46:23 +0000 | [diff] [blame] | 112 | static const unsigned ARM_GPR_AO_2[] = { |
Evan Cheng | 41a4d56 | 2007-02-28 00:22:44 +0000 | [diff] [blame] | 113 | ARM::R3, ARM::R2, ARM::R1, ARM::R0, |
Evan Cheng | bf822eb | 2007-03-08 02:56:40 +0000 | [diff] [blame] | 114 | ARM::R12,ARM::LR, |
Evan Cheng | 41a4d56 | 2007-02-28 00:22:44 +0000 | [diff] [blame] | 115 | ARM::R4, ARM::R5, ARM::R6, ARM::R7, |
Evan Cheng | bf822eb | 2007-03-08 02:56:40 +0000 | [diff] [blame] | 116 | ARM::R8, ARM::R10, |
| 117 | ARM::R11 }; |
| 118 | // FP is R7, R9 is available. |
Evan Cheng | cb20998 | 2007-03-07 02:46:23 +0000 | [diff] [blame] | 119 | static const unsigned ARM_GPR_AO_3[] = { |
Evan Cheng | 41a4d56 | 2007-02-28 00:22:44 +0000 | [diff] [blame] | 120 | ARM::R3, ARM::R2, ARM::R1, ARM::R0, |
Evan Cheng | bf822eb | 2007-03-08 02:56:40 +0000 | [diff] [blame] | 121 | ARM::R12,ARM::LR, |
| 122 | ARM::R4, ARM::R5, ARM::R6, |
| 123 | ARM::R8, ARM::R9, ARM::R10,ARM::R11, |
| 124 | ARM::R7 }; |
| 125 | // FP is R7, R9 is not available. |
Evan Cheng | cb20998 | 2007-03-07 02:46:23 +0000 | [diff] [blame] | 126 | static const unsigned ARM_GPR_AO_4[] = { |
Evan Cheng | 41a4d56 | 2007-02-28 00:22:44 +0000 | [diff] [blame] | 127 | ARM::R3, ARM::R2, ARM::R1, ARM::R0, |
Evan Cheng | bf822eb | 2007-03-08 02:56:40 +0000 | [diff] [blame] | 128 | ARM::R12,ARM::LR, |
| 129 | ARM::R4, ARM::R5, ARM::R6, |
| 130 | ARM::R8, ARM::R10,ARM::R11, |
| 131 | ARM::R7 }; |
Evan Cheng | 41a4d56 | 2007-02-28 00:22:44 +0000 | [diff] [blame] | 132 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 133 | // FP is R7, only low registers available. |
| 134 | static const unsigned THUMB_GPR_AO[] = { |
Evan Cheng | 15991bf | 2007-02-27 23:03:55 +0000 | [diff] [blame] | 135 | ARM::R2, ARM::R1, ARM::R0, |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 136 | ARM::R4, ARM::R5, ARM::R6, ARM::R7 }; |
| 137 | |
| 138 | GPRClass::iterator |
| 139 | GPRClass::allocation_order_begin(const MachineFunction &MF) const { |
| 140 | const TargetMachine &TM = MF.getTarget(); |
| 141 | const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>(); |
| 142 | if (Subtarget.isThumb()) |
| 143 | return THUMB_GPR_AO; |
| 144 | if (Subtarget.useThumbBacktraces()) { |
| 145 | if (Subtarget.isR9Reserved()) |
Evan Cheng | cb20998 | 2007-03-07 02:46:23 +0000 | [diff] [blame] | 146 | return ARM_GPR_AO_4; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 147 | else |
Evan Cheng | cb20998 | 2007-03-07 02:46:23 +0000 | [diff] [blame] | 148 | return ARM_GPR_AO_3; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 149 | } else { |
| 150 | if (Subtarget.isR9Reserved()) |
Evan Cheng | cb20998 | 2007-03-07 02:46:23 +0000 | [diff] [blame] | 151 | return ARM_GPR_AO_2; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 152 | else |
Evan Cheng | cb20998 | 2007-03-07 02:46:23 +0000 | [diff] [blame] | 153 | return ARM_GPR_AO_1; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 154 | } |
| 155 | } |
| 156 | |
| 157 | GPRClass::iterator |
| 158 | GPRClass::allocation_order_end(const MachineFunction &MF) const { |
| 159 | const TargetMachine &TM = MF.getTarget(); |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 160 | const MRegisterInfo *RI = TM.getRegisterInfo(); |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 161 | const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>(); |
| 162 | GPRClass::iterator I; |
| 163 | if (Subtarget.isThumb()) |
| 164 | I = THUMB_GPR_AO + (sizeof(THUMB_GPR_AO)/sizeof(unsigned)); |
| 165 | else if (Subtarget.useThumbBacktraces()) { |
Evan Cheng | 41a4d56 | 2007-02-28 00:22:44 +0000 | [diff] [blame] | 166 | if (Subtarget.isR9Reserved()) { |
Evan Cheng | cb20998 | 2007-03-07 02:46:23 +0000 | [diff] [blame] | 167 | I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned)); |
Evan Cheng | 41a4d56 | 2007-02-28 00:22:44 +0000 | [diff] [blame] | 168 | } else { |
Evan Cheng | cb20998 | 2007-03-07 02:46:23 +0000 | [diff] [blame] | 169 | I = ARM_GPR_AO_3 + (sizeof(ARM_GPR_AO_3)/sizeof(unsigned)); |
Evan Cheng | 41a4d56 | 2007-02-28 00:22:44 +0000 | [diff] [blame] | 170 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 171 | } else { |
Evan Cheng | 41a4d56 | 2007-02-28 00:22:44 +0000 | [diff] [blame] | 172 | if (Subtarget.isR9Reserved()) { |
Evan Cheng | cb20998 | 2007-03-07 02:46:23 +0000 | [diff] [blame] | 173 | I = ARM_GPR_AO_2 + (sizeof(ARM_GPR_AO_2)/sizeof(unsigned)); |
Evan Cheng | 41a4d56 | 2007-02-28 00:22:44 +0000 | [diff] [blame] | 174 | } else { |
Evan Cheng | cb20998 | 2007-03-07 02:46:23 +0000 | [diff] [blame] | 175 | I = ARM_GPR_AO_1 + (sizeof(ARM_GPR_AO_1)/sizeof(unsigned)); |
Evan Cheng | 41a4d56 | 2007-02-28 00:22:44 +0000 | [diff] [blame] | 176 | } |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 177 | } |
| 178 | |
Evan Cheng | 75e18c4 | 2007-01-20 02:09:25 +0000 | [diff] [blame] | 179 | // Mac OS X requires FP not to be clobbered for backtracing purpose. |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 180 | return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I; |
Rafael Espindola | 7bc59bc | 2006-05-14 22:18:28 +0000 | [diff] [blame] | 181 | } |
| 182 | }]; |
| 183 | } |
Rafael Espindola | 2718519 | 2006-09-29 21:20:16 +0000 | [diff] [blame] | 184 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 185 | def SPR : RegisterClass<"ARM", [f32], 32, [S0, S1, S2, S3, S4, S5, S6, S7, S8, |
Rafael Espindola | 2718519 | 2006-09-29 21:20:16 +0000 | [diff] [blame] | 186 | S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, |
| 187 | S23, S24, S25, S26, S27, S28, S29, S30, S31]>; |
| 188 | |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 189 | // ARM requires only word alignment for double. It's more performant if it |
| 190 | // is double-word alignment though. |
| 191 | def DPR : RegisterClass<"ARM", [f64], 64, [D0, D1, D2, D3, D4, D5, D6, D7, D8, |
| 192 | D9, D10, D11, D12, D13, D14, D15]>; |
Evan Cheng | 16b6598 | 2007-07-05 07:17:13 +0000 | [diff] [blame] | 193 | |
| 194 | // Condition code registers. |
| 195 | def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>; |