Misha Brukman | 2a8350a | 2005-02-05 02:24:26 +0000 | [diff] [blame] | 1 | //===- AlphaRegisterInfo.h - Alpha Register Information Impl ----*- C++ -*-===// |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 2 | // |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame^] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 7 | // |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file contains the Alpha implementation of the MRegisterInfo class. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #ifndef ALPHAREGISTERINFO_H |
| 15 | #define ALPHAREGISTERINFO_H |
| 16 | |
| 17 | #include "llvm/Target/MRegisterInfo.h" |
| 18 | #include "AlphaGenRegisterInfo.h.inc" |
| 19 | |
| 20 | namespace llvm { |
| 21 | |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 22 | class TargetInstrInfo; |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 23 | class Type; |
| 24 | |
| 25 | struct AlphaRegisterInfo : public AlphaGenRegisterInfo { |
Evan Cheng | 7ce4578 | 2006-11-13 23:36:35 +0000 | [diff] [blame] | 26 | const TargetInstrInfo &TII; |
| 27 | |
| 28 | AlphaRegisterInfo(const TargetInstrInfo &tii); |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 29 | |
| 30 | /// Code Generation virtual methods... |
| 31 | void storeRegToStackSlot(MachineBasicBlock &MBB, |
| 32 | MachineBasicBlock::iterator MBBI, |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 33 | unsigned SrcReg, bool isKill, int FrameIndex, |
Chris Lattner | 97d5e64 | 2005-09-30 01:29:42 +0000 | [diff] [blame] | 34 | const TargetRegisterClass *RC) const; |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 35 | |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 36 | void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, |
Evan Cheng | f0a0cdd | 2007-10-18 22:40:57 +0000 | [diff] [blame] | 37 | SmallVectorImpl<MachineOperand> &Addr, |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 38 | const TargetRegisterClass *RC, |
Evan Cheng | 58184e6 | 2007-10-18 21:29:24 +0000 | [diff] [blame] | 39 | SmallVectorImpl<MachineInstr*> &NewMIs) const; |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 40 | |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 41 | void loadRegFromStackSlot(MachineBasicBlock &MBB, |
| 42 | MachineBasicBlock::iterator MBBI, |
Chris Lattner | 97d5e64 | 2005-09-30 01:29:42 +0000 | [diff] [blame] | 43 | unsigned DestReg, int FrameIndex, |
| 44 | const TargetRegisterClass *RC) const; |
Andrew Lenharth | fa08fb2 | 2005-10-09 20:11:35 +0000 | [diff] [blame] | 45 | |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 46 | void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, |
Evan Cheng | f0a0cdd | 2007-10-18 22:40:57 +0000 | [diff] [blame] | 47 | SmallVectorImpl<MachineOperand> &Addr, |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 48 | const TargetRegisterClass *RC, |
Evan Cheng | 58184e6 | 2007-10-18 21:29:24 +0000 | [diff] [blame] | 49 | SmallVectorImpl<MachineInstr*> &NewMIs) const; |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 50 | |
Evan Cheng | aee4af6 | 2007-12-02 08:30:39 +0000 | [diff] [blame] | 51 | MachineInstr* foldMemoryOperand(MachineInstr* MI, |
| 52 | SmallVectorImpl<unsigned> &Ops, |
Andrew Lenharth | 5cefc5e | 2005-11-09 19:17:08 +0000 | [diff] [blame] | 53 | int FrameIndex) const; |
| 54 | |
Evan Cheng | e62f97c | 2007-12-01 02:07:52 +0000 | [diff] [blame] | 55 | MachineInstr* foldMemoryOperand(MachineInstr* MI, |
Evan Cheng | aee4af6 | 2007-12-02 08:30:39 +0000 | [diff] [blame] | 56 | SmallVectorImpl<unsigned> &Ops, |
Evan Cheng | e62f97c | 2007-12-01 02:07:52 +0000 | [diff] [blame] | 57 | MachineInstr* LoadMI) const { |
| 58 | return 0; |
| 59 | } |
| 60 | |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 61 | void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, |
| 62 | unsigned DestReg, unsigned SrcReg, |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 63 | const TargetRegisterClass *DestRC, |
| 64 | const TargetRegisterClass *SrcRC) const; |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 65 | |
Evan Cheng | bf2c8b3 | 2007-03-20 08:09:38 +0000 | [diff] [blame] | 66 | void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, |
| 67 | unsigned DestReg, const MachineInstr *Orig) const; |
| 68 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 69 | const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const; |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 70 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 71 | const TargetRegisterClass* const* getCalleeSavedRegClasses( |
| 72 | const MachineFunction *MF = 0) const; |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 73 | |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 74 | BitVector getReservedRegs(const MachineFunction &MF) const; |
| 75 | |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 76 | bool hasFP(const MachineFunction &MF) const; |
| 77 | |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 78 | void eliminateCallFramePseudoInstr(MachineFunction &MF, |
| 79 | MachineBasicBlock &MBB, |
| 80 | MachineBasicBlock::iterator I) const; |
| 81 | |
Evan Cheng | 5e6df46 | 2007-02-28 00:21:17 +0000 | [diff] [blame] | 82 | void eliminateFrameIndex(MachineBasicBlock::iterator II, |
Evan Cheng | 97de913 | 2007-05-01 09:13:03 +0000 | [diff] [blame] | 83 | int SPAdj, RegScavenger *RS = NULL) const; |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 84 | |
| 85 | //void processFunctionBeforeFrameFinalized(MachineFunction &MF) const; |
| 86 | |
| 87 | void emitPrologue(MachineFunction &MF) const; |
| 88 | void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; |
| 89 | |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 90 | // Debug information queries. |
| 91 | unsigned getRARegister() const; |
Jim Laskey | a997918 | 2006-03-28 13:48:33 +0000 | [diff] [blame] | 92 | unsigned getFrameRegister(MachineFunction &MF) const; |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 93 | |
Jim Laskey | 62819f3 | 2007-02-21 22:54:50 +0000 | [diff] [blame] | 94 | // Exception handling queries. |
| 95 | unsigned getEHExceptionRegister() const; |
| 96 | unsigned getEHHandlerRegister() const; |
| 97 | |
Dale Johannesen | b97aec6 | 2007-11-13 19:13:01 +0000 | [diff] [blame] | 98 | int getDwarfRegNum(unsigned RegNum, bool isEH) const; |
Anton Korobeynikov | f191c80 | 2007-11-11 19:50:10 +0000 | [diff] [blame] | 99 | |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 100 | static std::string getPrettyName(unsigned reg); |
| 101 | }; |
| 102 | |
| 103 | } // end namespace llvm |
| 104 | |
| 105 | #endif |