Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 1 | //===- IA64RegisterInfo.cpp - IA64 Register Information ---------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame^] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file contains the IA64 implementation of the MRegisterInfo class. This |
| 11 | // file is responsible for the frame pointer elimination optimization on IA64. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
| 15 | #include "IA64.h" |
| 16 | #include "IA64RegisterInfo.h" |
| 17 | #include "IA64InstrBuilder.h" |
| 18 | #include "IA64MachineFunctionInfo.h" |
| 19 | #include "llvm/Constants.h" |
| 20 | #include "llvm/Type.h" |
| 21 | #include "llvm/CodeGen/ValueTypes.h" |
| 22 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
| 23 | #include "llvm/CodeGen/MachineFunction.h" |
| 24 | #include "llvm/CodeGen/MachineFrameInfo.h" |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 25 | #include "llvm/CodeGen/MachineLocation.h" |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 26 | #include "llvm/Target/TargetFrameInfo.h" |
| 27 | #include "llvm/Target/TargetMachine.h" |
| 28 | #include "llvm/Target/TargetOptions.h" |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 29 | #include "llvm/Target/TargetInstrInfo.h" |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 30 | #include "llvm/Support/CommandLine.h" |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 31 | #include "llvm/ADT/BitVector.h" |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 32 | #include "llvm/ADT/STLExtras.h" |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 33 | using namespace llvm; |
| 34 | |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 35 | IA64RegisterInfo::IA64RegisterInfo(const TargetInstrInfo &tii) |
| 36 | : IA64GenRegisterInfo(IA64::ADJUSTCALLSTACKDOWN, IA64::ADJUSTCALLSTACKUP), |
| 37 | TII(tii) {} |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 38 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 39 | void IA64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, |
Chris Lattner | 0ffb1a5 | 2005-09-30 01:30:55 +0000 | [diff] [blame] | 40 | MachineBasicBlock::iterator MI, |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 41 | unsigned SrcReg, bool isKill, |
| 42 | int FrameIdx, |
Chris Lattner | 0ffb1a5 | 2005-09-30 01:30:55 +0000 | [diff] [blame] | 43 | const TargetRegisterClass *RC) const{ |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 44 | |
Chris Lattner | a411bef | 2005-10-28 04:57:11 +0000 | [diff] [blame] | 45 | if (RC == IA64::FPRegisterClass) { |
Evan Cheng | 0fa1b6d | 2007-02-23 01:10:04 +0000 | [diff] [blame] | 46 | BuildMI(MBB, MI, TII.get(IA64::STF_SPILL)).addFrameIndex(FrameIdx) |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 47 | .addReg(SrcReg, false, false, isKill); |
Chris Lattner | a411bef | 2005-10-28 04:57:11 +0000 | [diff] [blame] | 48 | } else if (RC == IA64::GRRegisterClass) { |
Evan Cheng | 0fa1b6d | 2007-02-23 01:10:04 +0000 | [diff] [blame] | 49 | BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx) |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 50 | .addReg(SrcReg, false, false, isKill); |
Evan Cheng | 0fa1b6d | 2007-02-23 01:10:04 +0000 | [diff] [blame] | 51 | } else if (RC == IA64::PRRegisterClass) { |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 52 | /* we use IA64::r2 as a temporary register for doing this hackery. */ |
| 53 | // first we load 0: |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 54 | BuildMI(MBB, MI, TII.get(IA64::MOV), IA64::r2).addReg(IA64::r0); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 55 | // then conditionally add 1: |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 56 | BuildMI(MBB, MI, TII.get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2) |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 57 | .addImm(1).addReg(SrcReg, false, false, isKill); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 58 | // and then store it to the stack |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 59 | BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(IA64::r2); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 60 | } else assert(0 && |
| 61 | "sorry, I don't know how to store this sort of reg in the stack\n"); |
| 62 | } |
| 63 | |
Evan Cheng | e203ae9 | 2007-10-05 01:33:45 +0000 | [diff] [blame] | 64 | void IA64RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 65 | bool isKill, |
Evan Cheng | f0a0cdd | 2007-10-18 22:40:57 +0000 | [diff] [blame] | 66 | SmallVectorImpl<MachineOperand> &Addr, |
Evan Cheng | e203ae9 | 2007-10-05 01:33:45 +0000 | [diff] [blame] | 67 | const TargetRegisterClass *RC, |
Evan Cheng | 58184e6 | 2007-10-18 21:29:24 +0000 | [diff] [blame] | 68 | SmallVectorImpl<MachineInstr*> &NewMIs) const { |
Evan Cheng | e203ae9 | 2007-10-05 01:33:45 +0000 | [diff] [blame] | 69 | unsigned Opc = 0; |
| 70 | if (RC == IA64::FPRegisterClass) { |
| 71 | Opc = IA64::STF8; |
| 72 | } else if (RC == IA64::GRRegisterClass) { |
| 73 | Opc = IA64::ST8; |
| 74 | } else if (RC == IA64::PRRegisterClass) { |
| 75 | Opc = IA64::ST1; |
| 76 | } else { |
| 77 | assert(0 && |
| 78 | "sorry, I don't know how to store this sort of reg\n"); |
| 79 | } |
| 80 | |
| 81 | MachineInstrBuilder MIB = BuildMI(TII.get(Opc)); |
| 82 | for (unsigned i = 0, e = Addr.size(); i != e; ++i) { |
| 83 | MachineOperand &MO = Addr[i]; |
| 84 | if (MO.isRegister()) |
| 85 | MIB.addReg(MO.getReg()); |
| 86 | else if (MO.isImmediate()) |
| 87 | MIB.addImm(MO.getImmedValue()); |
| 88 | else |
| 89 | MIB.addFrameIndex(MO.getFrameIndex()); |
| 90 | } |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 91 | MIB.addReg(SrcReg, false, false, isKill); |
Evan Cheng | e203ae9 | 2007-10-05 01:33:45 +0000 | [diff] [blame] | 92 | NewMIs.push_back(MIB); |
| 93 | return; |
| 94 | |
| 95 | } |
| 96 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 97 | void IA64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, |
Chris Lattner | 0ffb1a5 | 2005-09-30 01:30:55 +0000 | [diff] [blame] | 98 | MachineBasicBlock::iterator MI, |
| 99 | unsigned DestReg, int FrameIdx, |
| 100 | const TargetRegisterClass *RC)const{ |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 101 | |
Chris Lattner | a411bef | 2005-10-28 04:57:11 +0000 | [diff] [blame] | 102 | if (RC == IA64::FPRegisterClass) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 103 | BuildMI(MBB, MI, TII.get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx); |
Chris Lattner | a411bef | 2005-10-28 04:57:11 +0000 | [diff] [blame] | 104 | } else if (RC == IA64::GRRegisterClass) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 105 | BuildMI(MBB, MI, TII.get(IA64::LD8), DestReg).addFrameIndex(FrameIdx); |
Chris Lattner | a411bef | 2005-10-28 04:57:11 +0000 | [diff] [blame] | 106 | } else if (RC == IA64::PRRegisterClass) { |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 107 | // first we load a byte from the stack into r2, our 'predicate hackery' |
| 108 | // scratch reg |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 109 | BuildMI(MBB, MI, TII.get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 110 | // then we compare it to zero. If it _is_ zero, compare-not-equal to |
| 111 | // r0 gives us 0, which is what we want, so that's nice. |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 112 | BuildMI(MBB, MI, TII.get(IA64::CMPNE), DestReg).addReg(IA64::r2).addReg(IA64::r0); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 113 | } else assert(0 && |
| 114 | "sorry, I don't know how to load this sort of reg from the stack\n"); |
| 115 | } |
| 116 | |
Evan Cheng | e203ae9 | 2007-10-05 01:33:45 +0000 | [diff] [blame] | 117 | void IA64RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, |
Evan Cheng | f0a0cdd | 2007-10-18 22:40:57 +0000 | [diff] [blame] | 118 | SmallVectorImpl<MachineOperand> &Addr, |
Evan Cheng | e203ae9 | 2007-10-05 01:33:45 +0000 | [diff] [blame] | 119 | const TargetRegisterClass *RC, |
Evan Cheng | 58184e6 | 2007-10-18 21:29:24 +0000 | [diff] [blame] | 120 | SmallVectorImpl<MachineInstr*> &NewMIs) const { |
Evan Cheng | e203ae9 | 2007-10-05 01:33:45 +0000 | [diff] [blame] | 121 | unsigned Opc = 0; |
| 122 | if (RC == IA64::FPRegisterClass) { |
| 123 | Opc = IA64::LDF8; |
| 124 | } else if (RC == IA64::GRRegisterClass) { |
| 125 | Opc = IA64::LD8; |
| 126 | } else if (RC == IA64::PRRegisterClass) { |
| 127 | Opc = IA64::LD1; |
| 128 | } else { |
| 129 | assert(0 && |
| 130 | "sorry, I don't know how to store this sort of reg\n"); |
| 131 | } |
| 132 | |
| 133 | MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg); |
| 134 | for (unsigned i = 0, e = Addr.size(); i != e; ++i) { |
| 135 | MachineOperand &MO = Addr[i]; |
| 136 | if (MO.isRegister()) |
| 137 | MIB.addReg(MO.getReg()); |
| 138 | else if (MO.isImmediate()) |
| 139 | MIB.addImm(MO.getImmedValue()); |
| 140 | else |
| 141 | MIB.addFrameIndex(MO.getFrameIndex()); |
| 142 | } |
| 143 | NewMIs.push_back(MIB); |
| 144 | return; |
| 145 | } |
| 146 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 147 | void IA64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, |
| 148 | MachineBasicBlock::iterator MI, |
| 149 | unsigned DestReg, unsigned SrcReg, |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 150 | const TargetRegisterClass *DestRC, |
| 151 | const TargetRegisterClass *SrcRC) const { |
| 152 | if (DestRC != SrcRC) { |
| 153 | cerr << "Not yet supported!"; |
| 154 | abort(); |
| 155 | } |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 156 | |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 157 | if(DestRC == IA64::PRRegisterClass ) // if a bool, we use pseudocode |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 158 | // (SrcReg) DestReg = cmp.eq.unc(r0, r0) |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 159 | BuildMI(MBB, MI, TII.get(IA64::PCMPEQUNC), DestReg) |
Chris Lattner | 09e4606 | 2006-09-05 02:31:13 +0000 | [diff] [blame] | 160 | .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 161 | else // otherwise, MOV works (for both gen. regs and FP regs) |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 162 | BuildMI(MBB, MI, TII.get(IA64::MOV), DestReg).addReg(SrcReg); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 163 | } |
| 164 | |
Evan Cheng | bf2c8b3 | 2007-03-20 08:09:38 +0000 | [diff] [blame] | 165 | void IA64RegisterInfo::reMaterialize(MachineBasicBlock &MBB, |
| 166 | MachineBasicBlock::iterator I, |
| 167 | unsigned DestReg, |
| 168 | const MachineInstr *Orig) const { |
| 169 | MachineInstr *MI = Orig->clone(); |
| 170 | MI->getOperand(0).setReg(DestReg); |
| 171 | MBB.insert(I, MI); |
| 172 | } |
| 173 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 174 | const unsigned* IA64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) |
| 175 | const { |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 176 | static const unsigned CalleeSavedRegs[] = { |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 177 | IA64::r5, 0 |
| 178 | }; |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 179 | return CalleeSavedRegs; |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 180 | } |
| 181 | |
| 182 | const TargetRegisterClass* const* |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 183 | IA64RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 184 | static const TargetRegisterClass * const CalleeSavedRegClasses[] = { |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 185 | &IA64::GRRegClass, 0 |
| 186 | }; |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 187 | return CalleeSavedRegClasses; |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 188 | } |
| 189 | |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 190 | BitVector IA64RegisterInfo::getReservedRegs(const MachineFunction &MF) const { |
| 191 | BitVector Reserved(getNumRegs()); |
| 192 | Reserved.set(IA64::r0); |
| 193 | Reserved.set(IA64::r1); |
| 194 | Reserved.set(IA64::r2); |
| 195 | Reserved.set(IA64::r5); |
| 196 | Reserved.set(IA64::r12); |
| 197 | Reserved.set(IA64::r13); |
| 198 | Reserved.set(IA64::r22); |
| 199 | Reserved.set(IA64::rp); |
| 200 | return Reserved; |
| 201 | } |
| 202 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 203 | //===----------------------------------------------------------------------===// |
| 204 | // Stack Frame Processing methods |
| 205 | //===----------------------------------------------------------------------===// |
| 206 | |
| 207 | // hasFP - Return true if the specified function should have a dedicated frame |
| 208 | // pointer register. This is true if the function has variable sized allocas or |
| 209 | // if frame pointer elimination is disabled. |
| 210 | // |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 211 | bool IA64RegisterInfo::hasFP(const MachineFunction &MF) const { |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 212 | return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); |
| 213 | } |
| 214 | |
| 215 | void IA64RegisterInfo:: |
| 216 | eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, |
| 217 | MachineBasicBlock::iterator I) const { |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 218 | if (hasFP(MF)) { |
| 219 | // If we have a frame pointer, turn the adjcallstackup instruction into a |
| 220 | // 'sub SP, <amt>' and the adjcallstackdown instruction into 'add SP, |
| 221 | // <amt>' |
| 222 | MachineInstr *Old = I; |
| 223 | unsigned Amount = Old->getOperand(0).getImmedValue(); |
| 224 | if (Amount != 0) { |
| 225 | // We need to keep the stack aligned properly. To do this, we round the |
| 226 | // amount of space needed for the outgoing arguments up to the next |
| 227 | // alignment boundary. |
| 228 | unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 229 | Amount = (Amount+Align-1)/Align*Align; |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 230 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 231 | MachineInstr *New; |
| 232 | if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 233 | New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12) |
Chris Lattner | 63b3d71 | 2006-05-04 17:21:20 +0000 | [diff] [blame] | 234 | .addImm(-Amount); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 235 | } else { |
Misha Brukman | 7847fca | 2005-04-22 17:54:37 +0000 | [diff] [blame] | 236 | assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 237 | New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12) |
Chris Lattner | 63b3d71 | 2006-05-04 17:21:20 +0000 | [diff] [blame] | 238 | .addImm(Amount); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 239 | } |
| 240 | |
| 241 | // Replace the pseudo instruction with a new instruction... |
| 242 | MBB.insert(I, New); |
| 243 | } |
| 244 | } |
| 245 | |
| 246 | MBB.erase(I); |
| 247 | } |
| 248 | |
Evan Cheng | 5e6df46 | 2007-02-28 00:21:17 +0000 | [diff] [blame] | 249 | void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, |
Evan Cheng | 97de913 | 2007-05-01 09:13:03 +0000 | [diff] [blame] | 250 | int SPAdj, RegScavenger *RS)const{ |
| 251 | assert(SPAdj == 0 && "Unexpected"); |
| 252 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 253 | unsigned i = 0; |
| 254 | MachineInstr &MI = *II; |
| 255 | MachineBasicBlock &MBB = *MI.getParent(); |
| 256 | MachineFunction &MF = *MBB.getParent(); |
| 257 | |
| 258 | bool FP = hasFP(MF); |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 259 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 260 | while (!MI.getOperand(i).isFrameIndex()) { |
| 261 | ++i; |
| 262 | assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); |
| 263 | } |
| 264 | |
| 265 | int FrameIndex = MI.getOperand(i).getFrameIndex(); |
| 266 | |
| 267 | // choose a base register: ( hasFP? framepointer : stack pointer ) |
Duraid Madina | b9bcd18 | 2006-01-23 06:08:46 +0000 | [diff] [blame] | 268 | unsigned BaseRegister = FP ? IA64::r5 : IA64::r12; |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 269 | // Add the base register |
Chris Lattner | 09e4606 | 2006-09-05 02:31:13 +0000 | [diff] [blame] | 270 | MI.getOperand(i).ChangeToRegister(BaseRegister, false); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 271 | |
| 272 | // Now add the frame object offset to the offset from r1. |
| 273 | int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); |
| 274 | |
| 275 | // If we're not using a Frame Pointer that has been set to the value of the |
| 276 | // SP before having the stack size subtracted from it, then add the stack size |
| 277 | // to Offset to get the correct offset. |
| 278 | Offset += MF.getFrameInfo()->getStackSize(); |
| 279 | |
| 280 | // XXX: we use 'r22' as another hack+slash temporary register here :( |
Chris Lattner | 09e4606 | 2006-09-05 02:31:13 +0000 | [diff] [blame] | 281 | if (Offset <= 8191 && Offset >= -8192) { // smallish offset |
| 282 | // Fix up the old: |
| 283 | MI.getOperand(i).ChangeToRegister(IA64::r22, false); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 284 | //insert the new |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 285 | MachineInstr* nMI=BuildMI(TII.get(IA64::ADDIMM22), IA64::r22) |
Chris Lattner | 63b3d71 | 2006-05-04 17:21:20 +0000 | [diff] [blame] | 286 | .addReg(BaseRegister).addImm(Offset); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 287 | MBB.insert(II, nMI); |
| 288 | } else { // it's big |
| 289 | //fix up the old: |
Chris Lattner | 09e4606 | 2006-09-05 02:31:13 +0000 | [diff] [blame] | 290 | MI.getOperand(i).ChangeToRegister(IA64::r22, false); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 291 | MachineInstr* nMI; |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 292 | nMI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(Offset); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 293 | MBB.insert(II, nMI); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 294 | nMI=BuildMI(TII.get(IA64::ADD), IA64::r22).addReg(BaseRegister) |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 295 | .addReg(IA64::r22); |
| 296 | MBB.insert(II, nMI); |
| 297 | } |
| 298 | |
| 299 | } |
| 300 | |
| 301 | void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const { |
| 302 | MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB |
| 303 | MachineBasicBlock::iterator MBBI = MBB.begin(); |
| 304 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 305 | MachineInstr *MI; |
| 306 | bool FP = hasFP(MF); |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 307 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 308 | // first, we handle the 'alloc' instruction, that should be right up the |
| 309 | // top of any function |
| 310 | static const unsigned RegsInOrder[96] = { // there are 96 GPRs the |
| 311 | // RSE worries about |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 312 | IA64::r32, IA64::r33, IA64::r34, IA64::r35, |
| 313 | IA64::r36, IA64::r37, IA64::r38, IA64::r39, IA64::r40, IA64::r41, |
| 314 | IA64::r42, IA64::r43, IA64::r44, IA64::r45, IA64::r46, IA64::r47, |
| 315 | IA64::r48, IA64::r49, IA64::r50, IA64::r51, IA64::r52, IA64::r53, |
| 316 | IA64::r54, IA64::r55, IA64::r56, IA64::r57, IA64::r58, IA64::r59, |
| 317 | IA64::r60, IA64::r61, IA64::r62, IA64::r63, IA64::r64, IA64::r65, |
| 318 | IA64::r66, IA64::r67, IA64::r68, IA64::r69, IA64::r70, IA64::r71, |
| 319 | IA64::r72, IA64::r73, IA64::r74, IA64::r75, IA64::r76, IA64::r77, |
| 320 | IA64::r78, IA64::r79, IA64::r80, IA64::r81, IA64::r82, IA64::r83, |
| 321 | IA64::r84, IA64::r85, IA64::r86, IA64::r87, IA64::r88, IA64::r89, |
| 322 | IA64::r90, IA64::r91, IA64::r92, IA64::r93, IA64::r94, IA64::r95, |
| 323 | IA64::r96, IA64::r97, IA64::r98, IA64::r99, IA64::r100, IA64::r101, |
| 324 | IA64::r102, IA64::r103, IA64::r104, IA64::r105, IA64::r106, IA64::r107, |
| 325 | IA64::r108, IA64::r109, IA64::r110, IA64::r111, IA64::r112, IA64::r113, |
| 326 | IA64::r114, IA64::r115, IA64::r116, IA64::r117, IA64::r118, IA64::r119, |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 327 | IA64::r120, IA64::r121, IA64::r122, IA64::r123, IA64::r124, IA64::r125, |
Misha Brukman | 7847fca | 2005-04-22 17:54:37 +0000 | [diff] [blame] | 328 | IA64::r126, IA64::r127 }; |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 329 | |
| 330 | unsigned numStackedGPRsUsed=0; |
| 331 | for(int i=0; i<96; i++) { |
| 332 | if(MF.isPhysRegUsed(RegsInOrder[i])) |
| 333 | numStackedGPRsUsed=i+1; // (i+1 and not ++ - consider fn(fp, fp, int) |
| 334 | } |
| 335 | |
| 336 | unsigned numOutRegsUsed=MF.getInfo<IA64FunctionInfo>()->outRegsUsed; |
| 337 | |
Chris Lattner | 09e4606 | 2006-09-05 02:31:13 +0000 | [diff] [blame] | 338 | // XXX FIXME : this code should be a bit more reliable (in case there _isn't_ |
| 339 | // a pseudo_alloc in the MBB) |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 340 | unsigned dstRegOfPseudoAlloc; |
| 341 | for(MBBI = MBB.begin(); /*MBBI->getOpcode() != IA64::PSEUDO_ALLOC*/; ++MBBI) { |
| 342 | assert(MBBI != MBB.end()); |
| 343 | if(MBBI->getOpcode() == IA64::PSEUDO_ALLOC) { |
| 344 | dstRegOfPseudoAlloc=MBBI->getOperand(0).getReg(); |
| 345 | break; |
| 346 | } |
| 347 | } |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 348 | |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 349 | MI=BuildMI(TII.get(IA64::ALLOC)).addReg(dstRegOfPseudoAlloc).addImm(0). \ |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 350 | addImm(numStackedGPRsUsed).addImm(numOutRegsUsed).addImm(0); |
| 351 | MBB.insert(MBBI, MI); |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 352 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 353 | // Get the number of bytes to allocate from the FrameInfo |
| 354 | unsigned NumBytes = MFI->getStackSize(); |
| 355 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 356 | if(FP) |
| 357 | NumBytes += 8; // reserve space for the old FP |
| 358 | |
| 359 | // Do we need to allocate space on the stack? |
| 360 | if (NumBytes == 0) |
| 361 | return; |
| 362 | |
| 363 | // Add 16 bytes at the bottom of the stack (scratch area) |
| 364 | // and round the size to a multiple of the alignment. |
| 365 | unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 366 | unsigned Size = 16 + (FP ? 8 : 0); |
| 367 | NumBytes = (NumBytes+Size+Align-1)/Align*Align; |
| 368 | |
| 369 | // Update frame info to pretend that this is part of the stack... |
| 370 | MFI->setStackSize(NumBytes); |
| 371 | |
| 372 | // adjust stack pointer: r12 -= numbytes |
| 373 | if (NumBytes <= 8191) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 374 | MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12). |
Evan Cheng | 7ce4578 | 2006-11-13 23:36:35 +0000 | [diff] [blame] | 375 | addImm(-NumBytes); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 376 | MBB.insert(MBBI, MI); |
| 377 | } else { // we use r22 as a scratch register here |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 378 | MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(-NumBytes); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 379 | // FIXME: MOVLSI32 expects a _u_32imm |
| 380 | MBB.insert(MBBI, MI); // first load the decrement into r22 |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 381 | MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).addReg(IA64::r22); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 382 | MBB.insert(MBBI, MI); // then add (subtract) it to r12 (stack ptr) |
| 383 | } |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 384 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 385 | // now if we need to, save the old FP and set the new |
| 386 | if (FP) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 387 | MI = BuildMI(TII.get(IA64::ST8)).addReg(IA64::r12).addReg(IA64::r5); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 388 | MBB.insert(MBBI, MI); |
| 389 | // this must be the last instr in the prolog ? (XXX: why??) |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 390 | MI = BuildMI(TII.get(IA64::MOV), IA64::r5).addReg(IA64::r12); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 391 | MBB.insert(MBBI, MI); |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 392 | } |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 393 | |
| 394 | } |
| 395 | |
| 396 | void IA64RegisterInfo::emitEpilogue(MachineFunction &MF, |
| 397 | MachineBasicBlock &MBB) const { |
| 398 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 399 | MachineBasicBlock::iterator MBBI = prior(MBB.end()); |
| 400 | MachineInstr *MI; |
| 401 | assert(MBBI->getOpcode() == IA64::RET && |
| 402 | "Can only insert epilog into returning blocks"); |
| 403 | |
| 404 | bool FP = hasFP(MF); |
| 405 | |
| 406 | // Get the number of bytes allocated from the FrameInfo... |
| 407 | unsigned NumBytes = MFI->getStackSize(); |
| 408 | |
| 409 | //now if we need to, restore the old FP |
| 410 | if (FP) |
| 411 | { |
| 412 | //copy the FP into the SP (discards allocas) |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 413 | MI=BuildMI(TII.get(IA64::MOV), IA64::r12).addReg(IA64::r5); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 414 | MBB.insert(MBBI, MI); |
| 415 | //restore the FP |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 416 | MI=BuildMI(TII.get(IA64::LD8), IA64::r5).addReg(IA64::r5); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 417 | MBB.insert(MBBI, MI); |
| 418 | } |
| 419 | |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 420 | if (NumBytes != 0) |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 421 | { |
| 422 | if (NumBytes <= 8191) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 423 | MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12). |
Evan Cheng | 7ce4578 | 2006-11-13 23:36:35 +0000 | [diff] [blame] | 424 | addImm(NumBytes); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 425 | MBB.insert(MBBI, MI); |
| 426 | } else { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 427 | MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(NumBytes); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 428 | MBB.insert(MBBI, MI); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 429 | MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12). |
Evan Cheng | 7ce4578 | 2006-11-13 23:36:35 +0000 | [diff] [blame] | 430 | addReg(IA64::r22); |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 431 | MBB.insert(MBBI, MI); |
| 432 | } |
| 433 | } |
| 434 | |
| 435 | } |
| 436 | |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 437 | unsigned IA64RegisterInfo::getRARegister() const { |
| 438 | assert(0 && "What is the return address register"); |
| 439 | return 0; |
| 440 | } |
| 441 | |
Jim Laskey | a997918 | 2006-03-28 13:48:33 +0000 | [diff] [blame] | 442 | unsigned IA64RegisterInfo::getFrameRegister(MachineFunction &MF) const { |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 443 | return hasFP(MF) ? IA64::r5 : IA64::r12; |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 444 | } |
| 445 | |
Jim Laskey | 62819f3 | 2007-02-21 22:54:50 +0000 | [diff] [blame] | 446 | unsigned IA64RegisterInfo::getEHExceptionRegister() const { |
| 447 | assert(0 && "What is the exception register"); |
| 448 | return 0; |
| 449 | } |
| 450 | |
| 451 | unsigned IA64RegisterInfo::getEHHandlerRegister() const { |
| 452 | assert(0 && "What is the exception handler register"); |
| 453 | return 0; |
| 454 | } |
| 455 | |
Dale Johannesen | b97aec6 | 2007-11-13 19:13:01 +0000 | [diff] [blame] | 456 | int IA64RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { |
Anton Korobeynikov | f191c80 | 2007-11-11 19:50:10 +0000 | [diff] [blame] | 457 | assert(0 && "What is the dwarf register number"); |
| 458 | return -1; |
| 459 | } |
| 460 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 461 | #include "IA64GenRegisterInfo.inc" |
| 462 | |