Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 1 | //===- SparcRegisterInfo.td - Sparc Register defs ----------*- tablegen -*-===// |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame^] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
Misha Brukman | c95759c | 2004-09-22 21:48:50 +0000 | [diff] [blame] | 9 | |
| 10 | //===----------------------------------------------------------------------===// |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 11 | // Declarations that describe the Sparc register file |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 12 | //===----------------------------------------------------------------------===// |
| 13 | |
Misha Brukman | c95759c | 2004-09-22 21:48:50 +0000 | [diff] [blame] | 14 | class SparcReg<string n> : Register<n> { |
| 15 | field bits<5> Num; |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 16 | let Namespace = "SP"; |
Brian Gaeke | 59e04e4 | 2004-04-07 04:01:11 +0000 | [diff] [blame] | 17 | } |
| 18 | |
Brian Gaeke | 8fe429d | 2004-12-10 04:46:30 +0000 | [diff] [blame] | 19 | // Registers are identified with 5-bit ID numbers. |
| 20 | // Ri - 32-bit integer registers |
| 21 | class Ri<bits<5> num, string n> : SparcReg<n> { |
| 22 | let Num = num; |
| 23 | } |
| 24 | // Rf - 32-bit floating-point registers |
| 25 | class Rf<bits<5> num, string n> : SparcReg<n> { |
| 26 | let Num = num; |
| 27 | } |
| 28 | // Rd - Slots in the FP register file for 64-bit floating-point values. |
Evan Cheng | 03494d7 | 2007-07-13 23:55:50 +0000 | [diff] [blame] | 29 | class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> { |
Brian Gaeke | 8fe429d | 2004-12-10 04:46:30 +0000 | [diff] [blame] | 30 | let Num = num; |
Evan Cheng | 03494d7 | 2007-07-13 23:55:50 +0000 | [diff] [blame] | 31 | let SubRegs = subregs; |
Brian Gaeke | 8fe429d | 2004-12-10 04:46:30 +0000 | [diff] [blame] | 32 | } |
Brian Gaeke | 8fe429d | 2004-12-10 04:46:30 +0000 | [diff] [blame] | 33 | |
| 34 | // Integer registers |
Anton Korobeynikov | f191c80 | 2007-11-11 19:50:10 +0000 | [diff] [blame] | 35 | def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>; |
| 36 | def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>; |
| 37 | def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>; |
| 38 | def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>; |
| 39 | def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>; |
| 40 | def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>; |
| 41 | def G6 : Ri< 6, "G6">, DwarfRegNum<[6]>; |
| 42 | def G7 : Ri< 7, "G7">, DwarfRegNum<[7]>; |
| 43 | def O0 : Ri< 8, "O0">, DwarfRegNum<[8]>; |
| 44 | def O1 : Ri< 9, "O1">, DwarfRegNum<[9]>; |
| 45 | def O2 : Ri<10, "O2">, DwarfRegNum<[10]>; |
| 46 | def O3 : Ri<11, "O3">, DwarfRegNum<[11]>; |
| 47 | def O4 : Ri<12, "O4">, DwarfRegNum<[12]>; |
| 48 | def O5 : Ri<13, "O5">, DwarfRegNum<[13]>; |
| 49 | def O6 : Ri<14, "O6">, DwarfRegNum<[14]>; |
| 50 | def O7 : Ri<15, "O7">, DwarfRegNum<[15]>; |
| 51 | def L0 : Ri<16, "L0">, DwarfRegNum<[16]>; |
| 52 | def L1 : Ri<17, "L1">, DwarfRegNum<[17]>; |
| 53 | def L2 : Ri<18, "L2">, DwarfRegNum<[18]>; |
| 54 | def L3 : Ri<19, "L3">, DwarfRegNum<[19]>; |
| 55 | def L4 : Ri<20, "L4">, DwarfRegNum<[20]>; |
| 56 | def L5 : Ri<21, "L5">, DwarfRegNum<[21]>; |
| 57 | def L6 : Ri<22, "L6">, DwarfRegNum<[22]>; |
| 58 | def L7 : Ri<23, "L7">, DwarfRegNum<[23]>; |
| 59 | def I0 : Ri<24, "I0">, DwarfRegNum<[24]>; |
| 60 | def I1 : Ri<25, "I1">, DwarfRegNum<[25]>; |
| 61 | def I2 : Ri<26, "I2">, DwarfRegNum<[26]>; |
| 62 | def I3 : Ri<27, "I3">, DwarfRegNum<[27]>; |
| 63 | def I4 : Ri<28, "I4">, DwarfRegNum<[28]>; |
| 64 | def I5 : Ri<29, "I5">, DwarfRegNum<[29]>; |
| 65 | def I6 : Ri<30, "I6">, DwarfRegNum<[30]>; |
| 66 | def I7 : Ri<31, "I7">, DwarfRegNum<[31]>; |
Brian Gaeke | 8fe429d | 2004-12-10 04:46:30 +0000 | [diff] [blame] | 67 | |
Brian Gaeke | 8fe429d | 2004-12-10 04:46:30 +0000 | [diff] [blame] | 68 | // Floating-point registers |
Anton Korobeynikov | f191c80 | 2007-11-11 19:50:10 +0000 | [diff] [blame] | 69 | def F0 : Rf< 0, "F0">, DwarfRegNum<[32]>; |
| 70 | def F1 : Rf< 1, "F1">, DwarfRegNum<[33]>; |
| 71 | def F2 : Rf< 2, "F2">, DwarfRegNum<[34]>; |
| 72 | def F3 : Rf< 3, "F3">, DwarfRegNum<[35]>; |
| 73 | def F4 : Rf< 4, "F4">, DwarfRegNum<[36]>; |
| 74 | def F5 : Rf< 5, "F5">, DwarfRegNum<[37]>; |
| 75 | def F6 : Rf< 6, "F6">, DwarfRegNum<[38]>; |
| 76 | def F7 : Rf< 7, "F7">, DwarfRegNum<[39]>; |
| 77 | def F8 : Rf< 8, "F8">, DwarfRegNum<[40]>; |
| 78 | def F9 : Rf< 9, "F9">, DwarfRegNum<[41]>; |
| 79 | def F10 : Rf<10, "F10">, DwarfRegNum<[42]>; |
| 80 | def F11 : Rf<11, "F11">, DwarfRegNum<[43]>; |
| 81 | def F12 : Rf<12, "F12">, DwarfRegNum<[44]>; |
| 82 | def F13 : Rf<13, "F13">, DwarfRegNum<[45]>; |
| 83 | def F14 : Rf<14, "F14">, DwarfRegNum<[46]>; |
| 84 | def F15 : Rf<15, "F15">, DwarfRegNum<[47]>; |
| 85 | def F16 : Rf<16, "F16">, DwarfRegNum<[48]>; |
| 86 | def F17 : Rf<17, "F17">, DwarfRegNum<[49]>; |
| 87 | def F18 : Rf<18, "F18">, DwarfRegNum<[50]>; |
| 88 | def F19 : Rf<19, "F19">, DwarfRegNum<[51]>; |
| 89 | def F20 : Rf<20, "F20">, DwarfRegNum<[52]>; |
| 90 | def F21 : Rf<21, "F21">, DwarfRegNum<[53]>; |
| 91 | def F22 : Rf<22, "F22">, DwarfRegNum<[54]>; |
| 92 | def F23 : Rf<23, "F23">, DwarfRegNum<[55]>; |
| 93 | def F24 : Rf<24, "F24">, DwarfRegNum<[56]>; |
| 94 | def F25 : Rf<25, "F25">, DwarfRegNum<[57]>; |
| 95 | def F26 : Rf<26, "F26">, DwarfRegNum<[58]>; |
| 96 | def F27 : Rf<27, "F27">, DwarfRegNum<[59]>; |
| 97 | def F28 : Rf<28, "F28">, DwarfRegNum<[60]>; |
| 98 | def F29 : Rf<29, "F29">, DwarfRegNum<[61]>; |
| 99 | def F30 : Rf<30, "F30">, DwarfRegNum<[62]>; |
| 100 | def F31 : Rf<31, "F31">, DwarfRegNum<[63]>; |
Brian Gaeke | 8fe429d | 2004-12-10 04:46:30 +0000 | [diff] [blame] | 101 | |
| 102 | // Aliases of the F* registers used to hold 64-bit fp values (doubles) |
Anton Korobeynikov | f191c80 | 2007-11-11 19:50:10 +0000 | [diff] [blame] | 103 | def D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<[32]>; |
| 104 | def D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<[34]>; |
| 105 | def D2 : Rd< 4, "F4", [F4, F5]>, DwarfRegNum<[36]>; |
| 106 | def D3 : Rd< 6, "F6", [F6, F7]>, DwarfRegNum<[38]>; |
| 107 | def D4 : Rd< 8, "F8", [F8, F9]>, DwarfRegNum<[40]>; |
| 108 | def D5 : Rd<10, "F10", [F10, F11]>, DwarfRegNum<[42]>; |
| 109 | def D6 : Rd<12, "F12", [F12, F13]>, DwarfRegNum<[44]>; |
| 110 | def D7 : Rd<14, "F14", [F14, F15]>, DwarfRegNum<[46]>; |
| 111 | def D8 : Rd<16, "F16", [F16, F17]>, DwarfRegNum<[48]>; |
| 112 | def D9 : Rd<18, "F18", [F18, F19]>, DwarfRegNum<[50]>; |
| 113 | def D10 : Rd<20, "F20", [F20, F21]>, DwarfRegNum<[52]>; |
| 114 | def D11 : Rd<22, "F22", [F22, F23]>, DwarfRegNum<[54]>; |
| 115 | def D12 : Rd<24, "F24", [F24, F25]>, DwarfRegNum<[56]>; |
| 116 | def D13 : Rd<26, "F26", [F26, F27]>, DwarfRegNum<[58]>; |
| 117 | def D14 : Rd<28, "F28", [F28, F29]>, DwarfRegNum<[60]>; |
| 118 | def D15 : Rd<30, "F30", [F30, F31]>, DwarfRegNum<[62]>; |
Brian Gaeke | 8fe429d | 2004-12-10 04:46:30 +0000 | [diff] [blame] | 119 | |
Brian Gaeke | da69e7d | 2004-03-04 05:15:03 +0000 | [diff] [blame] | 120 | // Register classes. |
Misha Brukman | 5914bf6 | 2004-02-25 21:00:05 +0000 | [diff] [blame] | 121 | // |
| 122 | // FIXME: the register order should be defined in terms of the preferred |
| 123 | // allocation order... |
| 124 | // |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 125 | def IntRegs : RegisterClass<"SP", [i32], 32, [L0, L1, L2, L3, L4, L5, L6, L7, |
Chris Lattner | 9b3c702 | 2004-03-08 03:48:07 +0000 | [diff] [blame] | 126 | I0, I1, I2, I3, I4, I5, |
Brian Gaeke | 4f217fd | 2004-06-18 08:19:08 +0000 | [diff] [blame] | 127 | O0, O1, O2, O3, O4, O5, O7, |
Chris Lattner | 85e42b4 | 2005-12-20 07:56:31 +0000 | [diff] [blame] | 128 | |
| 129 | // FIXME: G1 reserved for now for large imm generation by frame code. |
| 130 | G1, |
Brian Gaeke | 4b92ed6 | 2004-11-18 00:25:20 +0000 | [diff] [blame] | 131 | // Non-allocatable regs: |
| 132 | G2, G3, G4, // FIXME: OK for use only in |
| 133 | // applications, not libraries. |
| 134 | O6, // stack ptr |
| 135 | I6, // frame ptr |
| 136 | I7, // return address |
| 137 | G0, // constant zero |
| 138 | G5, G6, G7 // reserved for kernel |
| 139 | ]> { |
Chris Lattner | ecbce61 | 2005-08-19 19:13:20 +0000 | [diff] [blame] | 140 | let MethodProtos = [{ |
Chris Lattner | 5ea64fd | 2006-08-17 22:00:08 +0000 | [diff] [blame] | 141 | iterator allocation_order_end(const MachineFunction &MF) const; |
Chris Lattner | ecbce61 | 2005-08-19 19:13:20 +0000 | [diff] [blame] | 142 | }]; |
| 143 | let MethodBodies = [{ |
| 144 | IntRegsClass::iterator |
Chris Lattner | 5ea64fd | 2006-08-17 22:00:08 +0000 | [diff] [blame] | 145 | IntRegsClass::allocation_order_end(const MachineFunction &MF) const { |
Chris Lattner | ecbce61 | 2005-08-19 19:13:20 +0000 | [diff] [blame] | 146 | // FIXME: These special regs should be taken out of the regclass! |
Chris Lattner | 85e42b4 | 2005-12-20 07:56:31 +0000 | [diff] [blame] | 147 | return end()-10 // Don't allocate special registers |
| 148 | -1; // FIXME: G1 reserved for large imm generation by frame code. |
Chris Lattner | 9b3c702 | 2004-03-08 03:48:07 +0000 | [diff] [blame] | 149 | } |
| 150 | }]; |
| 151 | } |
Brian Gaeke | e7173b7 | 2004-03-04 04:37:22 +0000 | [diff] [blame] | 152 | |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 153 | def FPRegs : RegisterClass<"SP", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8, |
Brian Gaeke | e7173b7 | 2004-03-04 04:37:22 +0000 | [diff] [blame] | 154 | F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22, |
| 155 | F23, F24, F25, F26, F27, F28, F29, F30, F31]>; |
Brian Gaeke | da69e7d | 2004-03-04 05:15:03 +0000 | [diff] [blame] | 156 | |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 157 | def DFPRegs : RegisterClass<"SP", [f64], 64, [D0, D1, D2, D3, D4, D5, D6, D7, |
Brian Gaeke | da69e7d | 2004-03-04 05:15:03 +0000 | [diff] [blame] | 158 | D8, D9, D10, D11, D12, D13, D14, D15]>; |