Arnold Schwaighofer | 48abc5c | 2007-10-12 21:30:57 +0000 | [diff] [blame] | 1 | //===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===// |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame^] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | 762fb5f | 2003-08-03 15:47:49 +0000 | [diff] [blame] | 9 | // |
| 10 | // This is a target description file for the Intel i386 architecture, refered to |
| 11 | // here as the "X86" architecture. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 15 | // Get the target-independent interfaces which we are implementing... |
Chris Lattner | 762fb5f | 2003-08-03 15:47:49 +0000 | [diff] [blame] | 16 | // |
| 17 | include "../Target.td" |
| 18 | |
| 19 | //===----------------------------------------------------------------------===// |
Evan Cheng | a26eb5e | 2006-10-06 09:17:41 +0000 | [diff] [blame] | 20 | // X86 Subtarget features. |
Bill Wendling | 4222d80 | 2007-05-04 20:38:40 +0000 | [diff] [blame] | 21 | //===----------------------------------------------------------------------===// |
Evan Cheng | a26eb5e | 2006-10-06 09:17:41 +0000 | [diff] [blame] | 22 | |
Bill Wendling | 4222d80 | 2007-05-04 20:38:40 +0000 | [diff] [blame] | 23 | def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX", |
| 24 | "Enable MMX instructions">; |
| 25 | def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1", |
| 26 | "Enable SSE instructions", |
| 27 | [FeatureMMX]>; |
| 28 | def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2", |
| 29 | "Enable SSE2 instructions", |
| 30 | [FeatureSSE1]>; |
| 31 | def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3", |
| 32 | "Enable SSE3 instructions", |
| 33 | [FeatureSSE2]>; |
| 34 | def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3", |
| 35 | "Enable SSSE3 instructions", |
| 36 | [FeatureSSE3]>; |
| 37 | def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow", |
| 38 | "Enable 3DNow! instructions">; |
| 39 | def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA", |
Bill Wendling | 11d8fda | 2007-05-06 07:56:19 +0000 | [diff] [blame] | 40 | "Enable 3DNow! Athlon instructions", |
| 41 | [Feature3DNow]>; |
| 42 | def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", |
| 43 | "Support 64-bit instructions", |
Bill Wendling | cd6cea0 | 2007-05-22 05:15:37 +0000 | [diff] [blame] | 44 | [FeatureSSE2]>; |
Evan Cheng | a26eb5e | 2006-10-06 09:17:41 +0000 | [diff] [blame] | 45 | |
| 46 | //===----------------------------------------------------------------------===// |
| 47 | // X86 processors supported. |
| 48 | //===----------------------------------------------------------------------===// |
| 49 | |
| 50 | class Proc<string Name, list<SubtargetFeature> Features> |
| 51 | : Processor<Name, NoItineraries, Features>; |
| 52 | |
| 53 | def : Proc<"generic", []>; |
| 54 | def : Proc<"i386", []>; |
| 55 | def : Proc<"i486", []>; |
| 56 | def : Proc<"pentium", []>; |
| 57 | def : Proc<"pentium-mmx", [FeatureMMX]>; |
| 58 | def : Proc<"i686", []>; |
| 59 | def : Proc<"pentiumpro", []>; |
| 60 | def : Proc<"pentium2", [FeatureMMX]>; |
Bill Wendling | cd6cea0 | 2007-05-22 05:15:37 +0000 | [diff] [blame] | 61 | def : Proc<"pentium3", [FeatureSSE1]>; |
| 62 | def : Proc<"pentium-m", [FeatureSSE2]>; |
| 63 | def : Proc<"pentium4", [FeatureSSE2]>; |
| 64 | def : Proc<"x86-64", [Feature64Bit]>; |
| 65 | def : Proc<"yonah", [FeatureSSE3]>; |
| 66 | def : Proc<"prescott", [FeatureSSE3]>; |
| 67 | def : Proc<"nocona", [FeatureSSE3]>; |
| 68 | def : Proc<"core2", [FeatureSSSE3]>; |
Evan Cheng | a26eb5e | 2006-10-06 09:17:41 +0000 | [diff] [blame] | 69 | |
| 70 | def : Proc<"k6", [FeatureMMX]>; |
Bill Wendling | cd6cea0 | 2007-05-22 05:15:37 +0000 | [diff] [blame] | 71 | def : Proc<"k6-2", [FeatureMMX, Feature3DNow]>; |
| 72 | def : Proc<"k6-3", [FeatureMMX, Feature3DNow]>; |
| 73 | def : Proc<"athlon", [FeatureMMX, Feature3DNowA]>; |
| 74 | def : Proc<"athlon-tbird", [FeatureMMX, Feature3DNowA]>; |
| 75 | def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA]>; |
| 76 | def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA]>; |
| 77 | def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA]>; |
| 78 | def : Proc<"k8", [Feature3DNowA, Feature64Bit]>; |
| 79 | def : Proc<"opteron", [Feature3DNowA, Feature64Bit]>; |
| 80 | def : Proc<"athlon64", [Feature3DNowA, Feature64Bit]>; |
| 81 | def : Proc<"athlon-fx", [Feature3DNowA, Feature64Bit]>; |
Evan Cheng | a26eb5e | 2006-10-06 09:17:41 +0000 | [diff] [blame] | 82 | |
| 83 | def : Proc<"winchip-c6", [FeatureMMX]>; |
| 84 | def : Proc<"winchip2", [FeatureMMX, Feature3DNow]>; |
| 85 | def : Proc<"c3", [FeatureMMX, Feature3DNow]>; |
Bill Wendling | cd6cea0 | 2007-05-22 05:15:37 +0000 | [diff] [blame] | 86 | def : Proc<"c3-2", [FeatureSSE1]>; |
Evan Cheng | a26eb5e | 2006-10-06 09:17:41 +0000 | [diff] [blame] | 87 | |
| 88 | //===----------------------------------------------------------------------===// |
Chris Lattner | 762fb5f | 2003-08-03 15:47:49 +0000 | [diff] [blame] | 89 | // Register File Description |
| 90 | //===----------------------------------------------------------------------===// |
| 91 | |
| 92 | include "X86RegisterInfo.td" |
| 93 | |
Chris Lattner | b77eb78 | 2003-08-03 18:19:37 +0000 | [diff] [blame] | 94 | //===----------------------------------------------------------------------===// |
| 95 | // Instruction Descriptions |
| 96 | //===----------------------------------------------------------------------===// |
| 97 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 98 | include "X86InstrInfo.td" |
| 99 | |
Chris Lattner | b77eb78 | 2003-08-03 18:19:37 +0000 | [diff] [blame] | 100 | def X86InstrInfo : InstrInfo { |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 101 | |
| 102 | // Define how we want to layout our TargetSpecific information field... This |
| 103 | // should be kept up-to-date with the fields in the X86InstrInfo.h file. |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 104 | let TSFlagsFields = ["FormBits", |
| 105 | "hasOpSizePrefix", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 106 | "hasAdSizePrefix", |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 107 | "Prefix", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 108 | "hasREX_WPrefix", |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 109 | "ImmTypeBits", |
| 110 | "FPFormBits", |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 111 | "Opcode"]; |
| 112 | let TSFlagsShifts = [0, |
John Criswell | 4ffff9e | 2004-04-08 20:31:47 +0000 | [diff] [blame] | 113 | 6, |
Evan Cheng | 3c55c54 | 2006-02-01 06:13:50 +0000 | [diff] [blame] | 114 | 7, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 115 | 8, |
| 116 | 12, |
Evan Cheng | 3c55c54 | 2006-02-01 06:13:50 +0000 | [diff] [blame] | 117 | 13, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 118 | 16, |
| 119 | 24]; |
Chris Lattner | b77eb78 | 2003-08-03 18:19:37 +0000 | [diff] [blame] | 120 | } |
| 121 | |
Chris Lattner | 31c8a6d | 2007-02-26 18:17:14 +0000 | [diff] [blame] | 122 | //===----------------------------------------------------------------------===// |
| 123 | // Calling Conventions |
| 124 | //===----------------------------------------------------------------------===// |
| 125 | |
| 126 | include "X86CallingConv.td" |
| 127 | |
| 128 | |
| 129 | //===----------------------------------------------------------------------===// |
| 130 | // Assembly Printers |
| 131 | //===----------------------------------------------------------------------===// |
| 132 | |
Chris Lattner | 9a3e49a | 2004-10-03 20:36:57 +0000 | [diff] [blame] | 133 | // The X86 target supports two different syntaxes for emitting machine code. |
| 134 | // This is controlled by the -x86-asm-syntax={att|intel} |
| 135 | def ATTAsmWriter : AsmWriter { |
| 136 | string AsmWriterClassName = "ATTAsmPrinter"; |
| 137 | int Variant = 0; |
| 138 | } |
| 139 | def IntelAsmWriter : AsmWriter { |
| 140 | string AsmWriterClassName = "IntelAsmPrinter"; |
| 141 | int Variant = 1; |
| 142 | } |
| 143 | |
| 144 | |
Chris Lattner | b77eb78 | 2003-08-03 18:19:37 +0000 | [diff] [blame] | 145 | def X86 : Target { |
Chris Lattner | b77eb78 | 2003-08-03 18:19:37 +0000 | [diff] [blame] | 146 | // Information about the instructions... |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 147 | let InstructionSet = X86InstrInfo; |
Chris Lattner | 9a3e49a | 2004-10-03 20:36:57 +0000 | [diff] [blame] | 148 | |
| 149 | let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter]; |
Chris Lattner | b77eb78 | 2003-08-03 18:19:37 +0000 | [diff] [blame] | 150 | } |