Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 1 | //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame^] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file defines the interfaces that X86 uses to lower LLVM code into a |
| 11 | // selection DAG. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
| 15 | #ifndef X86ISELLOWERING_H |
| 16 | #define X86ISELLOWERING_H |
| 17 | |
Evan Cheng | 559806f | 2006-01-27 08:10:46 +0000 | [diff] [blame] | 18 | #include "X86Subtarget.h" |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 19 | #include "X86RegisterInfo.h" |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 20 | #include "llvm/Target/TargetLowering.h" |
| 21 | #include "llvm/CodeGen/SelectionDAG.h" |
Rafael Espindola | 1b5dcc3 | 2007-08-31 15:06:30 +0000 | [diff] [blame] | 22 | #include "llvm/CodeGen/CallingConvLower.h" |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 23 | |
| 24 | namespace llvm { |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 25 | namespace X86ISD { |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 26 | // X86 Specific DAG Nodes |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 27 | enum NodeType { |
| 28 | // Start the numbering where the builtin ops leave off. |
Evan Cheng | 7df96d6 | 2005-12-17 01:21:05 +0000 | [diff] [blame] | 29 | FIRST_NUMBER = ISD::BUILTIN_OP_END+X86::INSTRUCTION_LIST_END, |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 30 | |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 31 | /// BSF - Bit scan forward. |
| 32 | /// BSR - Bit scan reverse. |
| 33 | BSF, |
| 34 | BSR, |
| 35 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 36 | /// SHLD, SHRD - Double shift instructions. These correspond to |
| 37 | /// X86::SHLDxx and X86::SHRDxx instructions. |
| 38 | SHLD, |
| 39 | SHRD, |
| 40 | |
Evan Cheng | ef6ffb1 | 2006-01-31 03:14:29 +0000 | [diff] [blame] | 41 | /// FAND - Bitwise logical AND of floating point values. This corresponds |
| 42 | /// to X86::ANDPS or X86::ANDPD. |
| 43 | FAND, |
| 44 | |
Evan Cheng | 68c47cb | 2007-01-05 07:55:56 +0000 | [diff] [blame] | 45 | /// FOR - Bitwise logical OR of floating point values. This corresponds |
| 46 | /// to X86::ORPS or X86::ORPD. |
| 47 | FOR, |
| 48 | |
Evan Cheng | 223547a | 2006-01-31 22:28:30 +0000 | [diff] [blame] | 49 | /// FXOR - Bitwise logical XOR of floating point values. This corresponds |
| 50 | /// to X86::XORPS or X86::XORPD. |
| 51 | FXOR, |
| 52 | |
Evan Cheng | 73d6cf1 | 2007-01-05 21:37:56 +0000 | [diff] [blame] | 53 | /// FSRL - Bitwise logical right shift of floating point values. These |
| 54 | /// corresponds to X86::PSRLDQ. |
Evan Cheng | 68c47cb | 2007-01-05 07:55:56 +0000 | [diff] [blame] | 55 | FSRL, |
| 56 | |
Evan Cheng | e3de85b | 2006-02-04 02:20:30 +0000 | [diff] [blame] | 57 | /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the |
| 58 | /// integer source in memory and FP reg result. This corresponds to the |
| 59 | /// X86::FILD*m instructions. It has three inputs (token chain, address, |
| 60 | /// and source type) and two outputs (FP value and token chain). FILD_FLAG |
| 61 | /// also produces a flag). |
Evan Cheng | a3195e8 | 2006-01-12 22:54:21 +0000 | [diff] [blame] | 62 | FILD, |
Evan Cheng | e3de85b | 2006-02-04 02:20:30 +0000 | [diff] [blame] | 63 | FILD_FLAG, |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 64 | |
| 65 | /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the |
| 66 | /// integer destination in memory and a FP reg source. This corresponds |
| 67 | /// to the X86::FIST*m instructions and the rounding mode change stuff. It |
Chris Lattner | 9189777 | 2006-10-18 18:26:48 +0000 | [diff] [blame] | 68 | /// has two inputs (token chain and address) and two outputs (int value |
| 69 | /// and token chain). |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 70 | FP_TO_INT16_IN_MEM, |
| 71 | FP_TO_INT32_IN_MEM, |
| 72 | FP_TO_INT64_IN_MEM, |
| 73 | |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 74 | /// FLD - This instruction implements an extending load to FP stack slots. |
| 75 | /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain |
Evan Cheng | 38bcbaf | 2005-12-23 07:31:11 +0000 | [diff] [blame] | 76 | /// operand, ptr to load from, and a ValueType node indicating the type |
| 77 | /// to load to. |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 78 | FLD, |
| 79 | |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 80 | /// FST - This instruction implements a truncating store to FP stack |
| 81 | /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a |
| 82 | /// chain operand, value to store, address, and a ValueType to store it |
| 83 | /// as. |
| 84 | FST, |
| 85 | |
Chris Lattner | cb18656 | 2007-02-25 08:15:11 +0000 | [diff] [blame] | 86 | /// FP_GET_RESULT - This corresponds to FpGETRESULT pseudo instruction |
| 87 | /// which copies from ST(0) to the destination. It takes a chain and |
| 88 | /// writes a RFP result and a chain. |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 89 | FP_GET_RESULT, |
| 90 | |
Chris Lattner | cb18656 | 2007-02-25 08:15:11 +0000 | [diff] [blame] | 91 | /// FP_SET_RESULT - This corresponds to FpSETRESULT pseudo instruction |
| 92 | /// which copies the source operand to ST(0). It takes a chain+value and |
| 93 | /// returns a chain and a flag. |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 94 | FP_SET_RESULT, |
| 95 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 96 | /// CALL/TAILCALL - These operations represent an abstract X86 call |
| 97 | /// instruction, which includes a bunch of information. In particular the |
| 98 | /// operands of these node are: |
| 99 | /// |
| 100 | /// #0 - The incoming token chain |
| 101 | /// #1 - The callee |
| 102 | /// #2 - The number of arg bytes the caller pushes on the stack. |
| 103 | /// #3 - The number of arg bytes the callee pops off the stack. |
| 104 | /// #4 - The value to pass in AL/AX/EAX (optional) |
| 105 | /// #5 - The value to pass in DL/DX/EDX (optional) |
| 106 | /// |
| 107 | /// The result values of these nodes are: |
| 108 | /// |
| 109 | /// #0 - The outgoing token chain |
| 110 | /// #1 - The first register result value (optional) |
| 111 | /// #2 - The second register result value (optional) |
| 112 | /// |
| 113 | /// The CALL vs TAILCALL distinction boils down to whether the callee is |
| 114 | /// known not to modify the caller's stack frame, as is standard with |
| 115 | /// LLVM. |
| 116 | CALL, |
| 117 | TAILCALL, |
Andrew Lenharth | b873ff3 | 2005-11-20 21:41:10 +0000 | [diff] [blame] | 118 | |
| 119 | /// RDTSC_DAG - This operation implements the lowering for |
| 120 | /// readcyclecounter |
| 121 | RDTSC_DAG, |
Evan Cheng | 7df96d6 | 2005-12-17 01:21:05 +0000 | [diff] [blame] | 122 | |
| 123 | /// X86 compare and logical compare instructions. |
Evan Cheng | 7d6ff3a | 2007-09-17 17:42:53 +0000 | [diff] [blame] | 124 | CMP, COMI, UCOMI, |
Evan Cheng | 7df96d6 | 2005-12-17 01:21:05 +0000 | [diff] [blame] | 125 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 126 | /// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag |
| 127 | /// operand produced by a CMP instruction. |
| 128 | SETCC, |
| 129 | |
| 130 | /// X86 conditional moves. Operand 1 and operand 2 are the two values |
Chris Lattner | 9189777 | 2006-10-18 18:26:48 +0000 | [diff] [blame] | 131 | /// to select from (operand 1 is a R/W operand). Operand 3 is the |
| 132 | /// condition code, and operand 4 is the flag operand produced by a CMP |
| 133 | /// or TEST instruction. It also writes a flag result. |
Evan Cheng | 7df96d6 | 2005-12-17 01:21:05 +0000 | [diff] [blame] | 134 | CMOV, |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 135 | |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 136 | /// X86 conditional branches. Operand 1 is the chain operand, operand 2 |
| 137 | /// is the block to branch if condition is true, operand 3 is the |
| 138 | /// condition code, and operand 4 is the flag operand produced by a CMP |
| 139 | /// or TEST instruction. |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 140 | BRCOND, |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 141 | |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 142 | /// Return with a flag operand. Operand 1 is the chain operand, operand |
| 143 | /// 2 is the number of bytes of stack to pop. |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 144 | RET_FLAG, |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 145 | |
| 146 | /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx. |
| 147 | REP_STOS, |
| 148 | |
| 149 | /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx. |
| 150 | REP_MOVS, |
Evan Cheng | 223547a | 2006-01-31 22:28:30 +0000 | [diff] [blame] | 151 | |
Evan Cheng | 7ccced6 | 2006-02-18 00:15:05 +0000 | [diff] [blame] | 152 | /// GlobalBaseReg - On Darwin, this node represents the result of the popl |
| 153 | /// at function entry, used for PIC code. |
| 154 | GlobalBaseReg, |
Evan Cheng | a0ea053 | 2006-02-23 02:43:52 +0000 | [diff] [blame] | 155 | |
Chris Lattner | 6458f18 | 2006-09-28 23:33:12 +0000 | [diff] [blame] | 156 | /// Wrapper - A wrapper node for TargetConstantPool, |
Evan Cheng | 020d2e8 | 2006-02-23 20:41:18 +0000 | [diff] [blame] | 157 | /// TargetExternalSymbol, and TargetGlobalAddress. |
| 158 | Wrapper, |
Evan Cheng | 48090aa | 2006-03-21 23:01:21 +0000 | [diff] [blame] | 159 | |
Evan Cheng | 0085a28 | 2006-11-30 21:55:46 +0000 | [diff] [blame] | 160 | /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP |
| 161 | /// relative displacements. |
| 162 | WrapperRIP, |
| 163 | |
Evan Cheng | bc4832b | 2006-03-24 23:15:12 +0000 | [diff] [blame] | 164 | /// S2VEC - X86 version of SCALAR_TO_VECTOR. The destination base does not |
| 165 | /// have to match the operand type. |
| 166 | S2VEC, |
Evan Cheng | b9df0ca | 2006-03-22 02:53:00 +0000 | [diff] [blame] | 167 | |
Evan Cheng | b067a1e | 2006-03-31 19:22:53 +0000 | [diff] [blame] | 168 | /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to |
Evan Cheng | 653159f | 2006-03-31 21:55:24 +0000 | [diff] [blame] | 169 | /// i32, corresponds to X86::PEXTRW. |
Evan Cheng | b067a1e | 2006-03-31 19:22:53 +0000 | [diff] [blame] | 170 | PEXTRW, |
Evan Cheng | 653159f | 2006-03-31 21:55:24 +0000 | [diff] [blame] | 171 | |
| 172 | /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector, |
| 173 | /// corresponds to X86::PINSRW. |
Evan Cheng | 8ca2932 | 2006-11-10 21:43:37 +0000 | [diff] [blame] | 174 | PINSRW, |
| 175 | |
| 176 | /// FMAX, FMIN - Floating point max and min. |
| 177 | /// |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 178 | FMAX, FMIN, |
Dan Gohman | 2038252 | 2007-07-10 00:05:58 +0000 | [diff] [blame] | 179 | |
| 180 | /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal |
| 181 | /// approximation. Note that these typically require refinement |
| 182 | /// in order to obtain suitable precision. |
| 183 | FRSQRT, FRCP, |
| 184 | |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 185 | // Thread Local Storage |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 186 | TLSADDR, THREAD_POINTER, |
| 187 | |
| 188 | // Exception Handling helpers |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 189 | EH_RETURN, |
| 190 | |
| 191 | // tail call return |
| 192 | // oeprand #0 chain |
| 193 | // operand #1 callee (register or absolute) |
| 194 | // operand #2 stack adjustment |
| 195 | // operand #3 optional in flag |
Anton Korobeynikov | 45b22fa | 2007-11-16 01:31:51 +0000 | [diff] [blame] | 196 | TC_RETURN, |
| 197 | |
| 198 | // Store FP control world into i16 memory |
| 199 | FNSTCW16m |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 200 | }; |
| 201 | } |
| 202 | |
Evan Cheng | b9df0ca | 2006-03-22 02:53:00 +0000 | [diff] [blame] | 203 | /// Define some predicates that are used for node matching. |
| 204 | namespace X86 { |
Evan Cheng | 0188ecb | 2006-03-22 18:59:22 +0000 | [diff] [blame] | 205 | /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand |
| 206 | /// specifies a shuffle of elements that is suitable for input to PSHUFD. |
| 207 | bool isPSHUFDMask(SDNode *N); |
| 208 | |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 209 | /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand |
| 210 | /// specifies a shuffle of elements that is suitable for input to PSHUFD. |
| 211 | bool isPSHUFHWMask(SDNode *N); |
| 212 | |
| 213 | /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand |
| 214 | /// specifies a shuffle of elements that is suitable for input to PSHUFD. |
| 215 | bool isPSHUFLWMask(SDNode *N); |
| 216 | |
Evan Cheng | 14aed5e | 2006-03-24 01:18:28 +0000 | [diff] [blame] | 217 | /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand |
| 218 | /// specifies a shuffle of elements that is suitable for input to SHUFP*. |
| 219 | bool isSHUFPMask(SDNode *N); |
| 220 | |
Evan Cheng | 2c0dbd0 | 2006-03-24 02:58:06 +0000 | [diff] [blame] | 221 | /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand |
| 222 | /// specifies a shuffle of elements that is suitable for input to MOVHLPS. |
| 223 | bool isMOVHLPSMask(SDNode *N); |
| 224 | |
Evan Cheng | 6e56e2c | 2006-11-07 22:14:24 +0000 | [diff] [blame] | 225 | /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form |
| 226 | /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, |
| 227 | /// <2, 3, 2, 3> |
| 228 | bool isMOVHLPS_v_undef_Mask(SDNode *N); |
| 229 | |
Evan Cheng | 5ced1d8 | 2006-04-06 23:23:56 +0000 | [diff] [blame] | 230 | /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand |
| 231 | /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. |
| 232 | bool isMOVLPMask(SDNode *N); |
| 233 | |
| 234 | /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand |
Evan Cheng | 533a0aa | 2006-04-19 20:35:22 +0000 | [diff] [blame] | 235 | /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D} |
| 236 | /// as well as MOVLHPS. |
Evan Cheng | 5ced1d8 | 2006-04-06 23:23:56 +0000 | [diff] [blame] | 237 | bool isMOVHPMask(SDNode *N); |
| 238 | |
Evan Cheng | 0038e59 | 2006-03-28 00:39:58 +0000 | [diff] [blame] | 239 | /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand |
| 240 | /// specifies a shuffle of elements that is suitable for input to UNPCKL. |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 241 | bool isUNPCKLMask(SDNode *N, bool V2IsSplat = false); |
Evan Cheng | 0038e59 | 2006-03-28 00:39:58 +0000 | [diff] [blame] | 242 | |
Evan Cheng | 4fcb922 | 2006-03-28 02:43:26 +0000 | [diff] [blame] | 243 | /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand |
| 244 | /// specifies a shuffle of elements that is suitable for input to UNPCKH. |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 245 | bool isUNPCKHMask(SDNode *N, bool V2IsSplat = false); |
Evan Cheng | 4fcb922 | 2006-03-28 02:43:26 +0000 | [diff] [blame] | 246 | |
Evan Cheng | 1d5a8cc | 2006-04-05 07:20:06 +0000 | [diff] [blame] | 247 | /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form |
| 248 | /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, |
| 249 | /// <0, 0, 1, 1> |
| 250 | bool isUNPCKL_v_undef_Mask(SDNode *N); |
| 251 | |
Bill Wendling | 2f9bb1a | 2007-04-24 21:16:55 +0000 | [diff] [blame] | 252 | /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form |
| 253 | /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, |
| 254 | /// <2, 2, 3, 3> |
| 255 | bool isUNPCKH_v_undef_Mask(SDNode *N); |
| 256 | |
Evan Cheng | 017dcc6 | 2006-04-21 01:05:10 +0000 | [diff] [blame] | 257 | /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand |
| 258 | /// specifies a shuffle of elements that is suitable for input to MOVSS, |
| 259 | /// MOVSD, and MOVD, i.e. setting the lowest element. |
| 260 | bool isMOVLMask(SDNode *N); |
Evan Cheng | d6d1cbd | 2006-04-11 00:19:04 +0000 | [diff] [blame] | 261 | |
Evan Cheng | d953947 | 2006-04-14 21:59:03 +0000 | [diff] [blame] | 262 | /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand |
| 263 | /// specifies a shuffle of elements that is suitable for input to MOVSHDUP. |
| 264 | bool isMOVSHDUPMask(SDNode *N); |
| 265 | |
| 266 | /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand |
| 267 | /// specifies a shuffle of elements that is suitable for input to MOVSLDUP. |
| 268 | bool isMOVSLDUPMask(SDNode *N); |
| 269 | |
Evan Cheng | b9df0ca | 2006-03-22 02:53:00 +0000 | [diff] [blame] | 270 | /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand |
| 271 | /// specifies a splat of a single element. |
| 272 | bool isSplatMask(SDNode *N); |
| 273 | |
Evan Cheng | f686d9b | 2006-10-27 21:08:32 +0000 | [diff] [blame] | 274 | /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand |
| 275 | /// specifies a splat of zero element. |
| 276 | bool isSplatLoMask(SDNode *N); |
| 277 | |
Evan Cheng | 63d3300 | 2006-03-22 08:01:21 +0000 | [diff] [blame] | 278 | /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle |
| 279 | /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP* |
| 280 | /// instructions. |
| 281 | unsigned getShuffleSHUFImmediate(SDNode *N); |
Evan Cheng | 506d3df | 2006-03-29 23:07:14 +0000 | [diff] [blame] | 282 | |
| 283 | /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle |
| 284 | /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW |
| 285 | /// instructions. |
| 286 | unsigned getShufflePSHUFHWImmediate(SDNode *N); |
| 287 | |
| 288 | /// getShufflePSHUFKWImmediate - Return the appropriate immediate to shuffle |
| 289 | /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW |
| 290 | /// instructions. |
| 291 | unsigned getShufflePSHUFLWImmediate(SDNode *N); |
Evan Cheng | b9df0ca | 2006-03-22 02:53:00 +0000 | [diff] [blame] | 292 | } |
| 293 | |
Chris Lattner | 9189777 | 2006-10-18 18:26:48 +0000 | [diff] [blame] | 294 | //===--------------------------------------------------------------------===// |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 295 | // X86TargetLowering - X86 Implementation of the TargetLowering interface |
| 296 | class X86TargetLowering : public TargetLowering { |
| 297 | int VarArgsFrameIndex; // FrameIndex for start of varargs area. |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 298 | int RegSaveFrameIndex; // X86-64 vararg func register save area. |
| 299 | unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset. |
| 300 | unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset. |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 301 | int BytesToPopOnReturn; // Number of arg bytes ret should pop. |
| 302 | int BytesCallerReserves; // Number of arg bytes caller makes. |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 303 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 304 | public: |
Dan Gohman | 61e729e | 2007-08-02 21:21:54 +0000 | [diff] [blame] | 305 | explicit X86TargetLowering(TargetMachine &TM); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 306 | |
Evan Cheng | cc41586 | 2007-11-09 01:32:10 +0000 | [diff] [blame] | 307 | /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC |
| 308 | /// jumptable. |
| 309 | SDOperand getPICJumpTableRelocBase(SDOperand Table, |
| 310 | SelectionDAG &DAG) const; |
| 311 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 312 | // Return the number of bytes that a function should pop when it returns (in |
| 313 | // addition to the space used by the return address). |
| 314 | // |
| 315 | unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; } |
| 316 | |
| 317 | // Return the number of bytes that the caller reserves for arguments passed |
| 318 | // to this function. |
| 319 | unsigned getBytesCallerReserves() const { return BytesCallerReserves; } |
| 320 | |
Chris Lattner | 54e3efd | 2007-02-26 04:01:25 +0000 | [diff] [blame] | 321 | /// getStackPtrReg - Return the stack pointer register we are using: either |
| 322 | /// ESP or RSP. |
| 323 | unsigned getStackPtrReg() const { return X86StackPtr; } |
| 324 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 325 | /// LowerOperation - Provide custom lowering hooks for some operations. |
| 326 | /// |
| 327 | virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); |
| 328 | |
Chris Lattner | 27a6c73 | 2007-11-24 07:07:01 +0000 | [diff] [blame] | 329 | /// ExpandOperation - Custom lower the specified operation, splitting the |
| 330 | /// value into two pieces. |
| 331 | /// |
| 332 | virtual SDNode *ExpandOperationResult(SDNode *N, SelectionDAG &DAG); |
| 333 | |
| 334 | |
Evan Cheng | 206ee9d | 2006-07-07 08:33:52 +0000 | [diff] [blame] | 335 | virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; |
| 336 | |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 337 | virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, |
| 338 | MachineBasicBlock *MBB); |
| 339 | |
Evan Cheng | 7226158 | 2005-12-20 06:22:03 +0000 | [diff] [blame] | 340 | /// getTargetNodeName - This method returns the name of a target specific |
| 341 | /// DAG node. |
| 342 | virtual const char *getTargetNodeName(unsigned Opcode) const; |
| 343 | |
Nate Begeman | 368e18d | 2006-02-16 21:11:51 +0000 | [diff] [blame] | 344 | /// computeMaskedBitsForTargetNode - Determine which of the bits specified |
| 345 | /// in Mask are known to be either zero or one and return them in the |
| 346 | /// KnownZero/KnownOne bitsets. |
| 347 | virtual void computeMaskedBitsForTargetNode(const SDOperand Op, |
| 348 | uint64_t Mask, |
| 349 | uint64_t &KnownZero, |
| 350 | uint64_t &KnownOne, |
Dan Gohman | ea859be | 2007-06-22 14:59:07 +0000 | [diff] [blame] | 351 | const SelectionDAG &DAG, |
Nate Begeman | 368e18d | 2006-02-16 21:11:51 +0000 | [diff] [blame] | 352 | unsigned Depth = 0) const; |
| 353 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 354 | SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG); |
| 355 | |
Chris Lattner | 4234f57 | 2007-03-25 02:14:49 +0000 | [diff] [blame] | 356 | ConstraintType getConstraintType(const std::string &Constraint) const; |
Chris Lattner | f4dff84 | 2006-07-11 02:54:03 +0000 | [diff] [blame] | 357 | |
Chris Lattner | 259e97c | 2006-01-31 19:43:35 +0000 | [diff] [blame] | 358 | std::vector<unsigned> |
Chris Lattner | 1efa40f | 2006-02-22 00:56:39 +0000 | [diff] [blame] | 359 | getRegClassForInlineAsmConstraint(const std::string &Constraint, |
| 360 | MVT::ValueType VT) const; |
Chris Lattner | 48884cd | 2007-08-25 00:47:38 +0000 | [diff] [blame] | 361 | |
| 362 | /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops |
| 363 | /// vector. If it is invalid, don't add anything to Ops. |
| 364 | virtual void LowerAsmOperandForConstraint(SDOperand Op, |
| 365 | char ConstraintLetter, |
| 366 | std::vector<SDOperand> &Ops, |
| 367 | SelectionDAG &DAG); |
Chris Lattner | 22aaf1d | 2006-10-31 20:13:11 +0000 | [diff] [blame] | 368 | |
Chris Lattner | 9189777 | 2006-10-18 18:26:48 +0000 | [diff] [blame] | 369 | /// getRegForInlineAsmConstraint - Given a physical register constraint |
| 370 | /// (e.g. {edx}), return the register number and the register class for the |
| 371 | /// register. This should only be used for C_Register constraints. On |
| 372 | /// error, this returns a register number of 0. |
Chris Lattner | f76d180 | 2006-07-31 23:26:50 +0000 | [diff] [blame] | 373 | std::pair<unsigned, const TargetRegisterClass*> |
| 374 | getRegForInlineAsmConstraint(const std::string &Constraint, |
| 375 | MVT::ValueType VT) const; |
| 376 | |
Chris Lattner | c9addb7 | 2007-03-30 23:15:24 +0000 | [diff] [blame] | 377 | /// isLegalAddressingMode - Return true if the addressing mode represented |
| 378 | /// by AM is legal for this target, for a load/store of the specified type. |
| 379 | virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; |
| 380 | |
Evan Cheng | 2bd122c | 2007-10-26 01:56:11 +0000 | [diff] [blame] | 381 | /// isTruncateFree - Return true if it's free to truncate a value of |
| 382 | /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in |
| 383 | /// register EAX to i16 by referencing its sub-register AX. |
| 384 | virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const; |
Evan Cheng | 3c3ddb3 | 2007-10-29 19:58:20 +0000 | [diff] [blame] | 385 | virtual bool isTruncateFree(MVT::ValueType VT1, MVT::ValueType VT2) const; |
Evan Cheng | 2bd122c | 2007-10-26 01:56:11 +0000 | [diff] [blame] | 386 | |
Evan Cheng | 0188ecb | 2006-03-22 18:59:22 +0000 | [diff] [blame] | 387 | /// isShuffleMaskLegal - Targets can use this to indicate that they only |
| 388 | /// support *some* VECTOR_SHUFFLE operations, those with specific masks. |
Chris Lattner | 9189777 | 2006-10-18 18:26:48 +0000 | [diff] [blame] | 389 | /// By default, if a target supports the VECTOR_SHUFFLE node, all mask |
| 390 | /// values are assumed to be legal. |
Evan Cheng | ca6e8ea | 2006-03-22 22:07:06 +0000 | [diff] [blame] | 391 | virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const; |
Evan Cheng | 39623da | 2006-04-20 08:58:49 +0000 | [diff] [blame] | 392 | |
| 393 | /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is |
| 394 | /// used by Targets can use this to indicate if there is a suitable |
| 395 | /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant |
| 396 | /// pool entry. |
| 397 | virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps, |
| 398 | MVT::ValueType EVT, |
| 399 | SelectionDAG &DAG) const; |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 400 | |
| 401 | /// IsEligibleForTailCallOptimization - Check whether the call is eligible |
| 402 | /// for tail call optimization. Target which want to do tail call |
| 403 | /// optimization should implement this function. |
| 404 | virtual bool IsEligibleForTailCallOptimization(SDOperand Call, |
| 405 | SDOperand Ret, |
| 406 | SelectionDAG &DAG) const; |
| 407 | |
Rafael Espindola | f1ba1ca | 2007-11-05 23:12:20 +0000 | [diff] [blame] | 408 | virtual const TargetSubtarget* getSubtarget() { |
| 409 | return static_cast<const TargetSubtarget*>(Subtarget); |
| 410 | } |
| 411 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 412 | private: |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 413 | /// Subtarget - Keep a pointer to the X86Subtarget around so that we can |
| 414 | /// make the right decision when generating code for different targets. |
| 415 | const X86Subtarget *Subtarget; |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 416 | const MRegisterInfo *RegInfo; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 417 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 418 | /// X86StackPtr - X86 physical register used as stack ptr. |
| 419 | unsigned X86StackPtr; |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 420 | |
Dale Johannesen | f1fc3a8 | 2007-09-23 14:52:20 +0000 | [diff] [blame] | 421 | /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 |
| 422 | /// floating point ops. |
| 423 | /// When SSE is available, use it for f32 operations. |
| 424 | /// When SSE2 is available, use it for f64 operations. |
| 425 | bool X86ScalarSSEf32; |
| 426 | bool X86ScalarSSEf64; |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 427 | |
Chris Lattner | 3085e15 | 2007-02-25 08:59:22 +0000 | [diff] [blame] | 428 | SDNode *LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode*TheCall, |
| 429 | unsigned CallingConv, SelectionDAG &DAG); |
| 430 | |
Rafael Espindola | 1b5dcc3 | 2007-08-31 15:06:30 +0000 | [diff] [blame] | 431 | |
Rafael Espindola | 7effac5 | 2007-09-14 15:48:13 +0000 | [diff] [blame] | 432 | SDOperand LowerMemArgument(SDOperand Op, SelectionDAG &DAG, |
| 433 | const CCValAssign &VA, MachineFrameInfo *MFI, |
| 434 | SDOperand Root, unsigned i); |
| 435 | |
Rafael Espindola | 1b5dcc3 | 2007-08-31 15:06:30 +0000 | [diff] [blame] | 436 | SDOperand LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG, |
| 437 | const SDOperand &StackPtr, |
| 438 | const CCValAssign &VA, SDOperand Chain, |
| 439 | SDOperand Arg); |
| 440 | |
Anton Korobeynikov | b10308e | 2007-01-28 13:31:35 +0000 | [diff] [blame] | 441 | // C and StdCall Calling Convention implementation. |
| 442 | SDOperand LowerCCCArguments(SDOperand Op, SelectionDAG &DAG, |
| 443 | bool isStdCall = false); |
Chris Lattner | 09c75a4 | 2007-02-25 09:06:15 +0000 | [diff] [blame] | 444 | SDOperand LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 445 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 446 | // X86-64 C Calling Convention implementation. |
| 447 | SDOperand LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG); |
Chris Lattner | 09c75a4 | 2007-02-25 09:06:15 +0000 | [diff] [blame] | 448 | SDOperand LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,unsigned CC); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 449 | |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 450 | // fast calling convention (tail call) implementation for 32/64bit |
| 451 | SDOperand LowerX86_TailCallTo(SDOperand Op, |
| 452 | SelectionDAG & DAG, unsigned CC); |
| 453 | unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG); |
Anton Korobeynikov | b10308e | 2007-01-28 13:31:35 +0000 | [diff] [blame] | 454 | // Fast and FastCall Calling Convention implementation. |
Chris Lattner | 2db39b8 | 2007-02-28 06:05:16 +0000 | [diff] [blame] | 455 | SDOperand LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG); |
Chris Lattner | 09c75a4 | 2007-02-25 09:06:15 +0000 | [diff] [blame] | 456 | SDOperand LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC); |
Evan Cheng | 559806f | 2006-01-27 08:10:46 +0000 | [diff] [blame] | 457 | |
Chris Lattner | 27a6c73 | 2007-11-24 07:07:01 +0000 | [diff] [blame] | 458 | std::pair<SDOperand,SDOperand> FP_TO_SINTHelper(SDOperand Op, |
| 459 | SelectionDAG &DAG); |
| 460 | |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 461 | SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG); |
| 462 | SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG); |
| 463 | SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG); |
| 464 | SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG); |
| 465 | SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG); |
| 466 | SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG); |
| 467 | SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG); |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 468 | SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 469 | SDOperand LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG); |
| 470 | SDOperand LowerShift(SDOperand Op, SelectionDAG &DAG); |
| 471 | SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG); |
| 472 | SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG); |
| 473 | SDOperand LowerFABS(SDOperand Op, SelectionDAG &DAG); |
| 474 | SDOperand LowerFNEG(SDOperand Op, SelectionDAG &DAG); |
Evan Cheng | 68c47cb | 2007-01-05 07:55:56 +0000 | [diff] [blame] | 475 | SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG); |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 476 | SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 477 | SDOperand LowerSELECT(SDOperand Op, SelectionDAG &DAG); |
| 478 | SDOperand LowerBRCOND(SDOperand Op, SelectionDAG &DAG); |
| 479 | SDOperand LowerMEMSET(SDOperand Op, SelectionDAG &DAG); |
Rafael Espindola | 068317b | 2007-09-28 12:53:01 +0000 | [diff] [blame] | 480 | SDOperand LowerMEMCPYInline(SDOperand Dest, SDOperand Source, |
| 481 | SDOperand Chain, unsigned Size, unsigned Align, |
| 482 | SelectionDAG &DAG); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 483 | SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG); |
Evan Cheng | 32fe103 | 2006-05-25 00:59:30 +0000 | [diff] [blame] | 484 | SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 485 | SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG); |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 486 | SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG); |
Evan Cheng | 1bc7804 | 2006-04-26 01:20:17 +0000 | [diff] [blame] | 487 | SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 488 | SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG); |
Evan Cheng | ae64219 | 2007-03-02 23:16:35 +0000 | [diff] [blame] | 489 | SDOperand LowerVACOPY(SDOperand Op, SelectionDAG &DAG); |
Evan Cheng | 0db9fe6 | 2006-04-25 20:13:52 +0000 | [diff] [blame] | 490 | SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG); |
Nate Begeman | bcc5f36 | 2007-01-29 22:58:52 +0000 | [diff] [blame] | 491 | SDOperand LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG); |
| 492 | SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG); |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 493 | SDOperand LowerFRAME_TO_ARGS_OFFSET(SDOperand Op, SelectionDAG &DAG); |
| 494 | SDOperand LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG); |
Duncan Sands | b116fac | 2007-07-27 20:02:49 +0000 | [diff] [blame] | 495 | SDOperand LowerTRAMPOLINE(SDOperand Op, SelectionDAG &DAG); |
Anton Korobeynikov | 45b22fa | 2007-11-16 01:31:51 +0000 | [diff] [blame] | 496 | SDOperand LowerFLT_ROUNDS(SDOperand Op, SelectionDAG &DAG); |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 497 | SDOperand LowerCTLZ(SDOperand Op, SelectionDAG &DAG); |
| 498 | SDOperand LowerCTTZ(SDOperand Op, SelectionDAG &DAG); |
Chris Lattner | 27a6c73 | 2007-11-24 07:07:01 +0000 | [diff] [blame] | 499 | SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG); |
| 500 | SDNode *ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG); |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 501 | }; |
| 502 | } |
| 503 | |
Chris Lattner | dbdbf0c | 2005-11-15 00:40:23 +0000 | [diff] [blame] | 504 | #endif // X86ISELLOWERING_H |